Semiconductor device

Abstract

According to one embodiment, a semiconductor device includes a silicon carbide layer, a first electrode, a plurality of second electrodes, a third electrode, a conductive layer, a first conductive member, a second conductive member, and a recess. The first electrode is provided on the first main surface of the silicon carbide layer, and the plurality of second electrodes are provided on the second main surface of the silicon carbide layer. The third electrode faces the second silicon carbide region of the silicon carbide layer with the first insulating region therebetween. The conductive layer is electrically connected to the plurality of second electrodes, and has a first connection position and a second connection position on the upper surface. The first conductive member is connected to the first connection position and electrically connected to the conductive layer. The second conductive member is connected to the second connection position and electrically connected to the third electrode and the conductive layer. The recess is provided on the upper surface side of the conductive layer, and is located on the opposite side of the first connection position with the second connection position therebetween.

Description

[0001] [Related Application]

[0002] This application claims priority to Japanese Patent Application No. 2024-150893 (Filing Date: September 2, 2024). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments of the present application generally relate to a semiconductor device. BACKGROUND

[0004] It is known that in a semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) using silicon carbide, the gate-source voltage decreases, and thus the on-resistance increases. In a semiconductor device, an increase in on-resistance is not preferable. SUMMARY

[0005] The semiconductor device of the embodiment includes a silicon carbide layer, a first electrode, a plurality of second electrodes, a third electrode, a conductive layer, a first conduction member, a second conduction member, and a recess. The silicon carbide layer has a first main surface and a second main surface. The silicon carbide layer has a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type disposed between the second main surface and the first silicon carbide region, and a third silicon carbide region of the first conductivity type disposed between the second main surface and the second silicon carbide region. The first electrode is disposed on the first main surface. The plurality of second electrodes are disposed on the second main surface. The third electrode opposes the second silicon carbide region with a first insulating region interposed therebetween. The conductive layer is electrically connected to the plurality of second electrodes and has a first connection position and a second connection position on an upper surface. The first conduction member is connected to the first connection position and electrically connected to the conductive layer. The second conduction member is connected to the second connection position and electrically connected to the third electrode and the conductive layer. The recess is disposed on the upper surface side of the conductive layer and is located on an opposite side of the first connection position from the second connection position with the second connection position interposed therebetween.

[0006] According to the embodiment, it is possible to provide a semiconductor device capable of reducing on-resistance. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a plan view of a semiconductor device of a first embodiment.

[0008] Figure 2 is a sectional view of the semiconductor device of the first embodiment along line A-A of Figure 1 .

[0009] Figure 3 is a schematic plan view of a semiconductor device of the first embodiment.

[0010] Figure 4 is a plan view for explaining the flow of current in the semiconductor device of the first embodiment.

[0011] Figure 5 is a sectional view for explaining the flow of current in the semiconductor device of the first embodiment.

[0012] Figure 6 is an equivalent circuit diagram of the semiconductor device of the first embodiment.

[0013] Figure 7A is a sectional view for explaining an example of a manufacturing process of the semiconductor device of the first embodiment.

[0014] Figure 7B is a sectional view for explaining an example of a manufacturing process of the semiconductor device of the first embodiment. Figure 7A

[0015] Figure 7C is a sectional view for explaining an example of a manufacturing process of the semiconductor device of the first embodiment. Figure 7B

[0016] Figure 8 is a schematic plan view of a semiconductor device of the first embodiment modification 1.

[0017] Figure 9 is a schematic plan view of a semiconductor device of the first embodiment modification 2.

[0018] Figure 10 is a schematic plan view of a semiconductor device of the first embodiment modification 3.

[0019] Figure 11 is a sectional view of a semiconductor device of the second embodiment along the A-A line of Figure 1 .

[0020] Figure 12 is a sectional view of a semiconductor device of the third embodiment along the A-A line of Figure 1 .

[0021] Figure 13 is a sectional view of a semiconductor device of the third embodiment modification along the A-A line of Figure 1 .

[0022] Figure 14 is a schematic plan view of a semiconductor device of the fourth embodiment. DETAILED DESCRIPTION​​

[0023] Hereinafter, an embodiment of the present application will be described with reference to the drawings. The embodiment is not intended to limit the present application. The drawings are schematic or conceptual, and the ratio of each part, etc. is not necessarily the same as that in reality. In the description and the drawings, the same elements as those described previously with reference to the drawings are denoted by the same reference numerals, and detailed description will be appropriately omitted.

[0024] Further, for convenience of explanation, the source electrode side is also referred to as "upper", and the drain electrode side is also referred to as "lower". However, the expression is for convenience, and is not related to the direction of gravity.

[0025] Further, in the following description, in order to express the relative levels of impurity concentrations in each conductivity type, the expressions of n + , n - , and p + , p - are sometimes used. That is, n + indicates that the n-type impurity concentration is relatively higher than n, and n - indicates that the n-type impurity concentration is relatively lower than n. Further, p + indicates that the p-type impurity concentration is relatively higher than p, and p - indicates that the p-type impurity concentration is relatively lower than p. These expressions indicate the relative levels of the substantial impurity concentrations after the compensation of both the p-type impurity and the n-type impurity in each region. The n-type, n + -type, and n - -type are examples of the first conductivity type in the claims. The p-type, p + -type, and p - -type are examples of the second conductivity type in the claims. Further, in the following description, the n-type and the p-type can be reversed. That is, the first conductivity type can be the p-type.

[0026] Further, the impurity concentration of the semiconductor region can be measured by Secondary Ion Mass Spectrometry (SIMS), for example. Further, the relative levels of the impurity concentrations can be determined from the levels of the carrier concentrations calculated by Scanning Capacitance Microscopy (SCM), for example.

[0027] Further, the planar shape, the depth, and the like of the recessed portion can be determined, for example, by analyzing the surface and the cross section of the semiconductor device using an optical microscope, a Transmission Electron Microscope (TEM), an Energy dispersive X-ray spectroscopy (EDX), a Scanning Electron Microscope (SEM), or the like.

[0028] Further, the terms such as "same", "identical", and the like, the dimensions, the values of physical properties, and the like, used in the present specification are not bound by strict meanings, and are to be interpreted within a range in which the same functions can be expected.

[0029] (First Embodiment)

[0030] Reference Figure 1 and Figure 2 The semiconductor device 1 of the first embodiment will be described. Figure 1 is a plan view of the semiconductor device 1 of the first embodiment. Figure 2 is a cross-sectional view of the semiconductor device 1 of the first embodiment along the A-A line of Figure 1 Further, in Figure 1 , the conduction member 41 and the conduction member 42 are illustrated as contacting the upper surface of the conductive layer 30.

[0031] The semiconductor device 1 is, for example, a MOSFET. In the present embodiment, a case where the semiconductor device 1 is a vertical MOSFET having a planar gate structure will be described. Further, the semiconductor device 1 can also be a vertical MOSFET having a trench gate structure, or the like.

[0032] As shown in Figure 2 , the semiconductor device 1 of the present embodiment includes a silicon carbide layer 2, a drain electrode 11, a plurality of source electrodes 12, a gate electrode 13, a conductive layer 30, a conduction member 41, a conduction member 42, a recessed portion 51, a plurality of barrier metals 60, and an insulating region (first insulating region) 70.

[0033] The silicon carbide layer 2 includes a lower surface (first main surface) and an upper surface (second main surface). A drift region (first silicon carbide region) 21, a drain region (first silicon carbide region) 22, a base region (second silicon carbide region) 23, and a source region (third silicon carbide region) 24 are provided within the silicon carbide layer 2. Details of each region will be described later.

[0034] The silicon carbide layer 2 can be an epitaxial layer, a semiconductor substrate, or a semiconductor substrate and an epitaxial layer disposed thereon. The silicon carbide layer 2 is single-crystal silicon carbide (SiC). In this case, nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb) are used as n-type impurities, and aluminum (Al) or boron (B) are used as p-type impurities.

[0035] The drain electrode 11 functions as the drain electrode of the MOSFET. The drain electrode 11 is disposed on the lower surface of the silicon carbide layer 2, in contact with and electrically connected to the drain region 22. The drain electrode 11 is an example of the first electrode in the claim. The drain electrode 11 is, for example, made of a material comprising at least one of nickel (Ni), titanium (Ti), aluminum (Al), etc.

[0036] The source electrode 12 functions as the source electrode of the MOSFET. The source electrode 12 is disposed on the upper surface of the silicon carbide layer 2, contacting and electrically connecting with the substrate region 23 and the source region 24. The source electrode 12 is an example of the second electrode described in the claims. In this embodiment, a plurality of source electrodes 12 are disposed on the upper surface of the silicon carbide layer 2. The source electrode 12 is, for example, made of a material comprising at least one of nickel (Ni), titanium (Ti), aluminum (Al), etc.

[0037] A barrier metal 60 is disposed on the source electrode 12. In this embodiment, multiple barrier metals 60 are disposed on multiple source electrodes 12. The barrier metal 60 is, for example, made of a material comprising at least one of titanium (Ti), tungsten (W), tantalum (Ta), titanium nitride, tungsten nitride, or tantalum nitride.

[0038] In addition, in this embodiment, such as Figure 1 As shown, the plurality of source electrodes 12 are respectively positioned in a direction orthogonal to the thickness direction of the silicon carbide layer 2. Figure 1 Extending upwards (in the vertical direction). That is, the plurality of source electrodes 12 have a striped planar shape. Furthermore, the planar shape of the plurality of source electrodes 12 is not limited to... Figure 1 The shape shown. For example, at least a portion of the multiple source electrodes 12 may also have a point-like planar shape.

[0039] like Figure 2 As shown, an insulating region 70 is disposed on the upper surface of the silicon carbide layer 2. The insulating region 70 is configured to be sandwiched by the source electrode 12. In this embodiment, the insulating region 70 is disposed in a two-layer structure consisting of the source electrode 12 and the barrier metal 60 thereon. The insulating region 70 is embedded in the conductive layer 30. The insulating region 70 is, for example, an insulating film comprising silicon oxide or silicon nitride.

[0040] The gate electrode 13 functions as the gate electrode of the MOSFET. The gate electrode 13 is disposed within the insulating region 70, and is electrically insulated from the silicon carbide layer 2 through the insulating region 70. The gate electrode 13 controls the current I flowing between the drain electrode 11 and the source electrode 12. DS (Drain-source current). Gate electrode 13 is an example of the third electrode in the claim. Gate electrode 13 is, for example, made of polysilicon containing p-type or n-type impurities. When a voltage is applied to gate electrode 13, a channel is formed in substrate region 23, and charge carriers flow between drift region 21 and source region 24. Thus, the MOSFET becomes in the on state.

[0041] The conductive layer 30 is provided in such a way that a plurality of source electrodes 12 are embedded therein, and is electrically connected to the plurality of source electrodes 12. In this embodiment, the conductive layer 30 embeds the plurality of source electrodes 12 via a plurality of barrier metals 60. In other words, the plurality of barrier metals 60 are respectively disposed between the plurality of source electrodes 12 and the conductive layer 30. The conductive layer 30 is made of, for example, a material comprising at least one of aluminum (Al), copper (Cu), titanium (Ti), and tungsten (W). The conductive layer 30 is also referred to as source metal. Furthermore, the conductive layer 30 may be made of the same material as the barrier metals 60, or it may be made of a different material.

[0042] like Figure 1 and Figure 2 As shown, the conductive layer 30 has a connection position P1 for connecting the conductive member 41 and a connection position P2 for connecting the conductive member 42 on its upper surface. That is, the conductive member 41 and the conductive member 42 are connected to the same conductive layer 30. Connection position P1 is an example of a first connection position in the claims. Connection position P2 is an example of a second connection position in the claims. Furthermore, connection position P1 is the center of the portion of the upper surface of the conductive layer 30 that contacts the conductive member 41 (hereinafter also referred to as "the contact portion of the conductive member 41"), for example, the geometric center of that portion. Similarly, connection position P2 is the center of the portion of the upper surface of the conductive layer 30 that contacts the conductive member 42 (hereinafter also referred to as "the contact portion of the conductive member 42"), for example, the geometric center of that portion. Furthermore, the shapes of the contact portions of the conductive member 41 and the conductive member 42 are not limited to... Figure 1 The shape shown.

[0043] The conductive components 41 and 42 are wires or metal sheets, etc. When they are wires, the constituent material is, for example, aluminum or an aluminum alloy. When they are metal sheets, the constituent material is, for example, copper or a copper alloy. Furthermore, at least one of the conductive components 41 and 42 may also be a component obtained by bundling multiple wires together.

[0044] The conductive component 41 is electrically connected to the conductive layer 30. A current I flows through the conductive component 41 between the drain electrode 11 and the source electrode 12. DS For example, current flowing from drain electrode 11 to source electrode 12 flows through conductive layer 30 and then into conductive member 41. Conversely, current flowing from conductive member 41 to conductive layer 30 then flows from source electrode 12 to drain electrode 11. Conductive member 41 is an example of the first conductive member in the claims. Conductive member 41 is also referred to as source line or source wire.

[0045] The conducting component 42 is electrically connected to the gate electrode 13 and the conductive layer 30. A control current I is applied between the conducting component 42 and the gate electrode 13. DS Drive voltage V DRV By connecting such a conductive component 42, and by not connecting the conductive component 42, a driving voltage V is applied to the conductive component 41. DRV Compared to the case where the resistance of the conducting component 41 and the current I flowing through the conducting component 41 are different... DS It can suppress the voltage actually applied between the source electrode 12 and the gate electrode 13, i.e., the gate-source voltage V. GS Ratio of driving voltage V DRV Reduced. The conducting component 42 is an example of the second conducting component in the claims. The conducting component 42 is also referred to as the source induction line. Furthermore, as... Figure 2 As shown, the diameter of the conductive component 42 can also be smaller than the diameter of the conductive component 41.

[0046] A recess 51 is provided on the upper surface side of the conductive layer 30, located opposite the connection position P1, separated by the connection position P2. The recess 51 is, for example, a portion of the conductive layer 30 that has been removed. Figure 1 As shown, in this embodiment, the planar shape of the recess 51 is a slit, i.e., a straight line. Furthermore, the planar shape of the recess 51 is not limited to a straight line; it can also be any shape such as a dot shape, a wavy shape, or a sawtooth shape.

[0047] like Figure 2 As shown, in this embodiment, the upper surface of a portion of the blocking metals 60a is exposed at the bottom surface of the recess 51. Alternatively, the bottom surface of the recess 51 may not reach the blocking metal 60.

[0048] Furthermore, although not shown, a portion of the sealing material of the semiconductor device 1 may also flow into the recess 51. That is, at least a portion of the recess 51 may also be filled with the sealing material that seals the conductive layer 30, the conductive member 41, and the conductive member 42.

[0049] In addition, Figure 2In the example, the recess 51 is located on the blocking metal 60. However, it is not limited to this; the recess 51 can be located on the insulating region 70, or on both the blocking metal 60 and the insulating region 70. That is, the positional relationship between the recess 51 and the blocking metal 60 and the insulating region 70 is arbitrary. Furthermore, in Figure 1 In this example, the length direction of the recess 51 is consistent with the extension direction of the source electrode 12. However, it is not limited to this; the direction of the long side of the recess 51 may also be different from the extension direction of the source electrode 12.

[0050] Here, refer to Figure 3 The shape of the recess 51 will be described in more detail. Figure 3 This is a schematic top view of the semiconductor device 1 according to the first embodiment. Furthermore, in Figure 3 In this design, the direction from connection position P2 towards connection position P1 on the upper surface of the conductive layer 30 is defined as the U-axis direction, and the direction orthogonal to the U-axis direction on the upper surface of the conductive layer 30 is defined as the V-axis direction. The U-axis direction is an example of the first direction in the claims. The V-axis direction is an example of the second direction in the claims. Furthermore, in Figure 1 as well as Figure 3 In the example, the U-axis direction from connection position P2 towards connection position P1 is orthogonal to the extension direction of source electrode 12. However, this is not a limitation; the U-axis direction may also differ from the extension direction of source electrode 12. For example, the U-axis direction may be parallel to or oblique to the extension direction of source electrode 12.

[0051] like Figure 3 As shown, the recess 51 in this embodiment is symmetrical about the straight line L1 passing through the connecting positions P1 and P2. The straight line L1 is an example of the first straight line in the claims. That is, in Figure 3 In the recess 51, the portion above and below the line L1 have symmetrical shapes. Alternatively, the recess 51 may not be symmetrical about the line L1 passing through the connecting positions P1 and P2.

[0052] Furthermore, the length of the recess 51 in the long side direction is greater than or equal to the width of the conductive member 42 connected to the upper surface of the conductive layer 30. More specifically, the length W1 of the recess 51 in the V-axis direction is greater than or equal to the length W2 of the portion of the conductive member 42 that contacts the upper surface of the conductive layer 30. In other words, the length of the recess 51 in the long side direction is greater than or equal to the width of the contact portion of the conductive member 42.

[0053] The following is for reference Figure 2 An example of the internal structure of silicon carbide layer 2 will be described below. However, the internal structure of silicon carbide layer 2 is not limited to the structure described below. Furthermore, the internal structure of silicon carbide layer 2 will be appropriately omitted in the following figures.

[0054] likeFigure 2 As shown, a drift region 21, a drain region 22, a substrate region 23, and a source region 24 are provided in the silicon carbide layer 2, for example.

[0055] Drift region 21 functions as the drift region of the MOSFET. Drift region 21 is positioned above drain region 22 (above drain electrode 11). Drift region 21 is, for example, n - The n-type semiconductor region. The n-type impurity concentration in drift region 21 is, for example, 4 × 10⁻⁶. 14 cm -3 Above and 1×10 17 cm -3 the following.

[0056] Drain region 22 functions as the drain region of the MOSFET. Drain region 22 is positioned between drift region 21 and drain electrode 11. Drain region 22 is in contact with drain electrode 11, making an ohmic contact with drain electrode 11. Drain region 22 is, for example, n + The n-type semiconductor region. The n-type impurity concentration in the drain region 22 is, for example, 1 × 10⁻⁶. 18 cm -3 Above and 1×10 21 cm -3 the following.

[0057] The substrate region 23 functions as the substrate region of the MOSFET. The substrate region 23 is disposed above the drift region 21. The substrate region 23 is, for example, a p-type semiconductor region. The p-type impurity concentration of the substrate region 23 is, for example, 1 × 10⁻⁶. 16 cm -3 Above and 1×10 21 cm -3 Below. Figure 2 In this example, the substrate region 23 has: a first portion located below the source region 24; a second portion extending from the first portion toward the upper surface of the silicon carbide layer 2 and contacting the source electrode 12; and a third portion extending from the first portion toward the upper surface of the silicon carbide layer 2 and contacting the insulating region 70 below the gate electrode 13. Furthermore, the second portion can also be p + The second part can have a higher p-type impurity concentration than the first and third parts.

[0058] Source region 24 functions as the source region of the MOSFET. Source region 24 is located between the substrate region 23 and the source electrode 12. Source region 24 is in contact with source electrode 12, making an ohmic contact with source electrode 12. Source region 24 is, for example, n + The source region 24 is a semiconductor region of type n. The n-type impurity concentration is, for example, 1 × 10⁻⁶. 18cm -3 Above and 1×10 21 cm -3 the following.

[0059] Furthermore, the semiconductor device 1 may also include a field plate electrode (FP electrode) disposed within the silicon carbide layer 2 through an insulating region. The FP electrode is electrically insulated from the silicon carbide layer 2 through the insulating region and is electrically connected to the source electrode 12. By providing such an FP electrode, when the MOSFET is in the off state, by applying a voltage between the drain electrode 11 and the source electrode 12, the depletion layer extends from the FP electrode to the surrounding drift region 21. By connecting this depletion layer to the depletion layer of the adjacent FP electrode, the breakdown voltage of the semiconductor device 1 can be improved.

[0060] As described above, the semiconductor device 1 according to this embodiment includes a silicon carbide layer 2, a drain electrode 11, a plurality of source electrodes 12, a gate electrode 13, a conductive layer 30, and a recess 51. The silicon carbide layer 2 has a lower surface and an upper surface. The drain electrode 11 is disposed on the lower surface of the silicon carbide layer 2. The plurality of source electrodes 12 are disposed on the upper surface of the silicon carbide layer 2. The gate electrode 13 is electrically insulated from the silicon carbide layer 2 through an insulating region 70, and the current I flowing between the drain electrode 11 and the plurality of source electrodes 12 is controlled. DS The conductive layer 30 is disposed with multiple source electrodes 12 embedded therein and is electrically connected to the multiple source electrodes 12. The conductive layer 30 has connection positions P1 for connecting to the conductive component 41 and P2 for connecting to the conductive component 42 on its upper surface. Current I DS Conducting component 41. A driving voltage V is applied between conducting component 42 and gate electrode 13. DRV The recess 51 is provided on the upper surface side of the conductive layer 30, and is located on the opposite side of the connection position P1, separated by the connection position P2.

[0061] According to this embodiment, compared to the case where the recess 51 is not provided, the on-resistance of the semiconductor device 1 can be reduced. Hereinafter, refer to... Figures 4-6 The effects of this embodiment will be explained in detail. Figure 4 This is a top view used to illustrate the flow of current in the semiconductor device 1 of the first embodiment. Figure 5 This is a cross-sectional view used to illustrate the flow of current in the semiconductor device 1 of the first embodiment, along... Figure 1 A cross-sectional view along line AA. Figure 6 This is an equivalent circuit diagram of the semiconductor device 1 according to the first embodiment. Furthermore, in Figure 4 as well as Figure 5 In the accompanying drawings, reference numeral I schematically indicates the path of current flowing from the drain electrode 11 through the source electrode 12, the blocking metal 60, and the conductive layer 30 to the conducting member 41. Additionally, in... Figure 6In the middle, R M R represents the resistance caused by the conductive layer 30 between the source electrode 12 and the conducting component 41. F This indicates the resistance of the conducting component 41.

[0062] like Figure 5 As shown, when the semiconductor device 1, which functions as a MOSFET, is in the ON state, current I first flows from the drain electrode 11 towards the source electrode 12 within the silicon carbide layer 2. Then, as... Figure 4 as well as Figure 5 As shown, the current I passing through the source electrode 12 and the blocking metal 60 flows from the blocking metal 60 to the connection position P1 of the conducting component 41 within the conductive layer 30.

[0063] In this embodiment, by providing a recess 51, such as Figure 4 As shown, the current I flowing from each source electrode 12 and within the conductive layer 30, specifically the current flowing to connection position P1 from the side opposite to connection position P1 across connection position P2, does not pass through connection position P2 but instead flows to connection position P1 by bypassing connection position P2. That is, the contact portion of the conducting member 42 is separated from at least a portion of the multiple currents I. Therefore, compared to the case where the recess 51 is not provided, the current flowing through the contact portion of the conducting member 42 can be reduced. As a result, voltage drop at the contact portion of the conducting member 42 can be suppressed. That is, as... Figure 6 As shown, the conducting component 42 is substantially connected to the source electrode 12 and the resistor R. M The state between the source electrode 12 and the gate electrode 13. Therefore, according to this embodiment, the gate-source voltage V actually applied between the source electrode 12 and the gate electrode 13 can be suppressed. GS Ratio of driving voltage V DRV reduce.

[0064] Generally speaking, in semiconductor devices with a silicon carbide layer, the gate-source voltage V is known to be... GS This reduces the on-resistance of the semiconductor device, thereby increasing its resistance. Therefore, according to this embodiment, compared to the case where the recess 51 is not provided, the gate-source voltage V can be suppressed. GS This reduces the on-resistance of semiconductor device 1.

[0065] Furthermore, the current density within the conductive layer 30 increases as it approaches the conducting member 41. Therefore, when the conducting member 42 approaches the conducting member 41, the voltage drop at the contact portion of the conducting member 42 increases. According to this embodiment, by providing the recess 51, the on-resistance of the semiconductor device 1 can be effectively reduced when the conducting member 42 approaches the conducting member 41.

[0066] Furthermore, according to this embodiment, the recess 51 is symmetrical about the straight line L1 passing through the connection position P1 and the connection position P2. Thus, for example, in... Figure 4 In this process, the current flowing through the upper side of the recess 51 toward the connection position P2 and the current flowing through the lower side of the recess 51 toward the connection position P2 cancel each other out in their vertical direction components. Therefore, the current flowing through the contact portion of the conducting member 42 can be further reduced.

[0067] Furthermore, in this embodiment, the length of the long side of the recess 51 is greater than or equal to the width of the conductive member 42 connected to the upper surface of the conductive layer 30. This further reduces the current flowing through the contact portion of the conductive member 42.

[0068] Furthermore, in this embodiment, both the conductive member 41 and the conductive member 42 are connected to the same conductive layer 30. Therefore, for example, compared to the case where the conductive member 41 is connected to the first conductive layer and the conductive member 42 is connected to a second conductive layer that is physically separated from the first conductive layer, the reduction in the area of ​​the conductive layer 30 that facilitates the conduction of current I can be suppressed. Thus, the on-resistance of the semiconductor device 1 can be further reduced.

[0069] <Manufacturing Method of Semiconductor Device 1>

[0070] Next, refer to Figures 7A-7C An example of the manufacturing method of the semiconductor device 1 of this embodiment will be described. Figures 7A-7C This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1 according to the first embodiment, along... Figure 1 A cross-sectional view along line AA.

[0071] First, such as Figure 7A As shown, a semiconductor device component comprising a silicon carbide layer 2, a source electrode 12, a gate electrode 13, a barrier metal 60, and an insulating region 70 is prepared. Although not shown, a semiconductor region such as a drift region 21 is formed within the silicon carbide layer 2.

[0072] Next, as Figure 7B As shown, a conductive layer 30 is formed on the upper surface of the silicon carbide layer 2 by embedding a barrier metal 60 and an insulating region 70. Then, although not shown, a drain electrode 11 is formed on the lower surface of the silicon carbide layer 2. Furthermore, the drain electrode 11 may be formed before the conductive layer 30.

[0073] Next, as Figure 7C As shown, the portion of the conductive layer 30 above the barrier metal 60a is removed by methods such as Reactive Ion Etching (RIE). This forms a recess 51 on the upper surface of the conductive layer 30. The upper surface of the barrier metal 60a is exposed at the bottom surface of the recess 51.

[0074] Then, although not shown in the diagram, one end of conductive component 41 and conductive component 42 are connected to the upper surface of conductive layer 30 using bonding materials such as solder, and the other end of conductive component 41 and conductive component 42 are connected to the inner lead of the lead frame. Then, conductive layer 30, conductive component 41 and conductive component 42 are sealed with sealing material.

[0075] Through the above processes, the semiconductor device 1 of this embodiment is manufactured.

[0076] Furthermore, in the manufacturing method of the semiconductor device 1 of this embodiment, the conductive layer 30 may also be made of a material different from the blocking metal 60. Therefore, in use... Figure 7C In the described process, the formation of the recess 51 becomes easier. Specifically, in the RIE used to remove a portion of the conductive layer 30, it is possible to prevent the removal of the barrier metal 60.

[0077] Hereinafter, several variations of the first embodiment, in which the planar shape of the recess 51 is changed, will be described, focusing on the differences from the first embodiment. According to each of the variations described below, similar to the first embodiment described above, the on-resistance of the semiconductor device can also be reduced compared to the case where the recess is not provided.

[0078] (Modification 1 of the first embodiment)

[0079] Reference Figure 8 The semiconductor device of the modified example 1 of the first embodiment will be described. Figure 8 This is a schematic top view of a semiconductor device according to a variation of the first embodiment 1.

[0080] like Figure 8 As shown, the semiconductor device of this modified example has a U-shaped recess, that is, a rectangular shape with one side removed. More specifically, in this modified example, the recess 51 has one end ( Figure 8 The upper end) and the other end on the opposite side of one end ( Figure 8 (Lower end of the middle). Additionally, the semiconductor device of this modified example further includes: a recess 52 disposed on the upper surface side of the conductive layer 30 and connected to one end of the recess 51; and a recess 53 disposed on the upper surface side of the conductive layer 30 and connected to the other end of the recess 51. Recess 52 is an example of a second recess in the claims. Recess 53 is an example of a third recess in the claims. Furthermore, the recess 51 of this modified example has a […]. Figure 3 The recesses 52 and 53 have the same shape as the recess 51 in the first embodiment described herein. In addition, the recesses 52 and 53 are straight lines with their length directions orthogonal to the length direction (V-axis direction) of the recess 51.

[0081] The recess 53, together with the recess 52, clamps the connection position P2. That is, the recess 53 is located on the opposite side of the recess 52, separated from the connection position P2. As a result, the current through the contact portion of the conducting member 42 can be further reduced.

[0082] Furthermore, the length W1 of the recesses formed by recesses 51, 52, and 53 in the V-axis direction is longer than the length W2 of the conducting member 42 in the V-axis direction. This further reduces the current flowing through the contacts of the conducting member 42.

[0083] Furthermore, the recesses formed by recesses 51, 52, and 53 are symmetrical about the straight line L1 passing through connection position P1 and connection position P2. This further reduces the current flowing through the contact portion of the conducting member 42.

[0084] Furthermore, recesses 52 and 53 extend further towards the conducting member 41 than straight line L2, which is perpendicular to straight line L1 and passes through connection point P2. This further reduces the current flowing through the contact portion of the conducting member 42. Straight line L2 is an example of the second straight line described in the claims.

[0085] Alternatively, recesses 51 and 52 may be discontinuous, with a conductive layer 30 provided between them. Similarly, recesses 51 and 53 may be discontinuous, with a conductive layer 30 provided between them.

[0086] (Modification 2 of the first embodiment)

[0087] Reference Figure 9 The semiconductor device of the modified example 2 of the first embodiment will be described. Figure 9 This is a schematic top view of a semiconductor device according to a variation of the first embodiment, Example 2.

[0088] like Figure 9 As shown, the semiconductor device of this modified example has a U-shaped recess. More specifically, in this modified example, the recess 51 has one end ( Figure 9 The upper end) and the other end on the opposite side of one end ( Figure 9(Lower end of the middle). In addition, the semiconductor device of this modified embodiment further includes: a recess 52 disposed on the upper surface side of the conductive layer 30 and connected to one end of the recess 51; and a recess 53 disposed on the upper surface side of the conductive layer 30 and connected to the other end of the recess 51. More specifically, the semiconductor device of this modified embodiment further includes: a recess 52 connected to one end of the recess 51 via a connecting recess 54; and a recess 53 connected to the other end of the recess 51 via a connecting recess 55. The connecting recess 54 extends from one end of the recess 51 toward the connection position P1 side, connecting the recess 51 and the recess 52. The connecting recess 55 extends from the other end of the recess 51 toward the connection position P1 side, connecting the recess 51 and the recess 53. Furthermore, the recess 51 and the recess 52 are continuous via the connecting recess 54, and the recess 51 and the recess 53 are continuous via the connecting recess 55. The connecting recess 54 is an example of the first connecting recess in the claims. The connecting recess 55 is an example of the second connecting recess in the claims. Furthermore, the recess 51 in this modified example is consistent with... Figure 3 The recess 51 in the first embodiment described herein has the same straight-line shape. However, the length of the recess 51A in this modified example is shorter in the longitudinal direction than the length W1 of the recess 51 in the first embodiment. In addition, the recesses 52 and 53 are straight-line shapes whose longitudinal direction is orthogonal to the longitudinal direction (V-axis direction) of the recess 51.

[0089] In addition, Figure 9 In the example, both connecting recesses 54 and 55 are straight lines. Furthermore, the length directions of connecting recesses 54 and 55 are inclined at approximately 45° relative to the length direction (V-axis direction) of recess 51. However, this is not a limitation; connecting recess 54 can also be a curved shape, such as an arc, that smoothly connects recesses 51 and 52. Similarly, connecting recess 55 can also be a curved shape that smoothly connects recesses 51 and 53.

[0090] Furthermore, the recesses formed by recesses 51, 52, 53 and connecting recesses 54, 55 are symmetrical about the straight line L1 passing through the connecting position P1 and the connecting position P2. This further reduces the current flowing through the contact portion of the conducting member 42.

[0091] (Modification 3 of the first embodiment)

[0092] Reference Figure 10 The semiconductor device of the modified example 3 of the first embodiment will be described. Figure 10 This is a schematic top view of a semiconductor device according to a variation of the first embodiment, Example 3.

[0093] like Figure 10As shown, the semiconductor device of this modified example has an II-shaped recess. More specifically, in addition to the recess 51, the semiconductor device of this modified example also has a recess 56.

[0094] Recess 56 is disposed on the conductive layer 30, located on the opposite side to recess 51, i.e., the side of connection position P1, across connection position P2. However, recess 56 is located between connection position P2 and connection position P1. Recess 56 is an example of the fourth recess in the claims. Figure 10 In the example, recess 56 is parallel to recess 51 and has the same shape as recess 51. That is, the length of recess 56 in the longitudinal direction is equal to the length W1 of recess 51 in the longitudinal direction.

[0095] In this modified example, both recesses 51 and 56 are symmetrical about the straight line L1 passing through connection positions P1 and P2. This further reduces the current flowing through the contacts of the conducting member 42.

[0096] (Second Implementation)

[0097] Reference Figure 11 The semiconductor device 1A of the second embodiment will be described. Figure 11 Along the semiconductor device 1A of the second embodiment Figure 1 A cross-sectional view along line AA. One difference between the first embodiment described above and this embodiment is the depth of the recess. Hereinafter, this embodiment will be described focusing on the differences from the first embodiment.

[0098] like Figure 11 As shown, the semiconductor device 1A of this embodiment includes a recess 51A instead of a recess 51. The recess 51A extends through the blocking metal 60a. The upper surface of a portion of the source electrodes 12a of the plurality of source electrodes 12 is exposed on the bottom surface of the recess 51A. In addition, the planar shape of the recess 51A is the same as the planar shape of the recess 51 in the first embodiment.

[0099] According to this embodiment, since the resistance below the recess 51A increases the amount of blocking metal 60a removed, the current through the contact portion of the conducting member 42 can be further reduced.

[0100] The semiconductor device 1A of this embodiment can be manufactured by, for example, using the semiconductor device 1 of the first embodiment described above in the manufacturing method. Figure 7C The manufacturing process involves changing the conditions of the RIE. Furthermore, in this embodiment, the conductive layer 30 can also be made of a different material than the plurality of source electrodes 12. This facilitates the formation of the recess 51A.

[0101] (Third Implementation)

[0102] Reference Figure 12 The semiconductor device 1B of the third embodiment will be described. Figure 12 The semiconductor device of the third embodiment is along Figure 1 A cross-sectional view of line AA. One difference between the first embodiment described above and this embodiment is the positional relationship between the recess and the insulating region 70. Hereinafter, this embodiment will be described focusing on the differences from the first embodiment.

[0103] like Figure 12 As shown, the semiconductor device 1B of this embodiment includes a recess 51B instead of a recess 51. The upper surface of a portion of the plurality of insulating regions 70, insulating region 70A, is exposed on the bottom surface of the recess 51B. Insulating region 70A is an example of the second insulating region described in the claims. Figure 12 In the example, the width of the insulating region 70A ( Figure 12 The length of the recess 70A in the left-right direction is the same as the width of the other insulating regions 70. Alternatively, the width of the insulating region 70A may differ from the width of the other insulating regions 70. Furthermore, the planar shape of the recess 51B is the same as the planar shape of the recess 51 in the first embodiment.

[0104] The gate electrode 13 is not provided below the recess 51B. In this embodiment, the gate electrode 13 is not provided within the insulating region 70A.

[0105] According to this embodiment, since the resistance of the bottom surface of the recess 51B increases, the current through the contact portion of the conducting member 42 can be further reduced.

[0106] The semiconductor device 1B of this embodiment can be manufactured by, for example, using the semiconductor device 1 of the first embodiment described above in the manufacturing method. Figure 7C The process described involves changing the location where the conductive layer 30 is removed during manufacturing.

[0107] According to the manufacturing method of the semiconductor device 1B of this embodiment, by not providing the gate electrode 13 below the recess 51B, the risk of short circuit between the conductive layer 30 and the gate electrode 13 can be reduced.

[0108] In addition, Figure 12 In this example, the insulating region 70A has the same height as the other insulating regions 70. Therefore, it can be formed together with the other insulating regions 70 to form the insulating region 70A.

[0109] (A variation of the third embodiment)

[0110] Reference Figure 13 The semiconductor device 1C of the modified example of the third embodiment will be described. Figure 13In the semiconductor device 1C of the third embodiment, along Figure 1 A cross-sectional view along line AA. One difference between the third embodiment described above and this modified example is the structure of the insulating region exposed on the bottom surface of the recess 51B. Hereinafter, this modified example will be described focusing on the differences from the third embodiment.

[0111] like Figure 13 As shown, in this modified example, the upper surface of a portion of the insulating regions 70B, one of the plurality of insulating regions 70, is exposed on the bottom surface of the recess 51B. Insulating region 70B is an example of the second insulating region described in the claims.

[0112] No gate electrode 13 is provided below the recess 51B. More specifically, although two gate electrodes 13a are provided within the insulating region 70B, neither of the two gate electrodes 13a is located below the recess 51B.

[0113] According to this modified example, since the resistance below the recess 51B increases, the current through the contact portion of the conducting member 42 can be further reduced.

[0114] According to the manufacturing method of the semiconductor device 1C of this modified example, by not providing the gate electrode 13a below the recess 51B, the risk of short circuit between the conductive layer 30 and the gate electrode 13a can be reduced.

[0115] (Fourth Implementation)

[0116] Reference Figure 14 The semiconductor device 1D of the fourth embodiment will be described. Figure 14 This is a schematic top view of the semiconductor device 1D according to the fourth embodiment. One of the differences between the first embodiment described above and this embodiment is the number of recesses 51. Hereinafter, this embodiment will be described focusing on the differences from the first embodiment.

[0117] like Figure 14 As shown, in the semiconductor device 1D of this embodiment, the conductive layer 30A has regions capable of connecting to the conductive components 41 and 42. Specifically, the conductive layer 30A has a connection region A1 on its upper surface capable of connecting to the conductive component 41 and multiple connection regions A2 capable of connecting to the conductive component 42. Connection region A1 is an example of a first connection region in the claims. Connection region A2 is an example of a second connection region in the claims.

[0118] Connect the conductive component 41 at any position within the connection area A1. Similarly, connect the conductive component 42 at any position within the connection area A2.

[0119] exist Figure 14In this example, the conductive layer 30A has one connection region A1 and multiple connection regions A2 on its upper surface. The connection region A1 has a larger area than each of the connection regions A2. In this case, for example, one or more conductive components 41 are connected at any position within the connection region A1. On the other hand, a conductive component 42 is connected at any position within one of the multiple connection regions A2.

[0120] On the upper surface of the conductive layer 30A, a plurality of recesses 51 are provided on the side opposite to the connection region A1, separated by a plurality of connection regions A2. Alternatively, the recesses of the modifications 1 to 3 of the first embodiment may be provided instead of at least one of the plurality of recesses 51.

[0121] According to this embodiment, the degree of freedom in the connection positions of the conducting members 41 and 42 in the semiconductor device 1D can be increased. Furthermore, when multiple conducting members 41 are connected, the increase in resistance of the semiconductor device 1D due to the conducting members 41 can be suppressed.

[0122] Furthermore, in the embodiments described above, the case where the semiconductor device is a vertically oriented MOSFET has been described. However, it is not limited to this; the semiconductor device may also be a vertically oriented transistor such as an IGBT (Insulated Gate Bipolar Transistor).

[0123] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising: a silicon carbide layer having a first main surface and a second main surface, a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type provided between the second main surface and the first silicon carbide region, and a third silicon carbide region of the first conductivity type provided between the second main surface and the second silicon carbide region; a first electrode provided on the first main surface; a plurality of second electrodes provided on the second main surface; a third electrode facing the second silicon carbide region with a first insulating region interposed therebetween; a conductive layer electrically connected to the plurality of second electrodes, having a first connection position and a second connection position on an upper surface; a first conduction member connected to the first connection position and electrically connected to the conductive layer; a second conduction member connected to the second connection position and electrically connected to the third electrode and the conductive layer; and a recess provided on the upper surface side of the conductive layer and located on an opposite side of the first connection position from the second connection position with the second connection position interposed therebetween.

2. The semiconductor device according to claim 1, further comprising a barrier metal provided between at least some of the plurality of second electrodes and the conductive layer, wherein an upper surface of the barrier metal is exposed on a bottom surface of the recess.

3. The semiconductor device according to claim 2, wherein the conductive layer is composed of a material containing at least one of aluminum, copper, titanium, and tungsten, and the barrier metal is composed of a material containing at least one of titanium, tungsten, tantalum, titanium nitride, tungsten nitride, and tantalum nitride.

4. The semiconductor device according to claim 2, wherein the conductive layer is composed of a material different from the barrier metal.

5. The semiconductor device according to claim 1, wherein an upper surface of some of the plurality of second electrodes is exposed on a bottom surface of the recess.

6. The semiconductor device according to claim 1, further comprising a second insulating region provided on an upper surface of the silicon carbide layer, wherein an upper surface of the second insulating region is exposed on a bottom surface of the recess.

7. The semiconductor device according to claim 6, wherein the third electrode is not provided below the recess.

8. The semiconductor device according to claim 6, wherein the third electrode is not provided in the second insulating region.

9. The semiconductor device according to claim 6, wherein the second insulating region has the same height as the first insulating region.

10. The semiconductor device according to claim 1, wherein the recess has one end and another end, the semiconductor device further comprising: a second recess provided on the upper surface side of the conductive layer and connected to the one end of the recess; and a third recess provided on the upper surface side of the conductive layer and connected to the another end of the recess, the second recess and the third recess sandwiching the second connection position.

11. The semiconductor device according to claim 10, wherein the second recess is connected to the one end of the recess via a first connection recess, and the third recess is connected to the another end of the recess via a second connection recess. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 12. The semiconductor device according to claim 10, wherein the second recess and the third recess extend more to the first conduction member side than a first straight line that is perpendicular to the first straight line passing through the second connection position and passing through the second connection position.

13. The semiconductor device according to claim 1, wherein a fourth recess is further provided on a side opposite to the recess with respect to the second connection position.

14. The semiconductor device according to claim 1, wherein the recess is symmetrical with respect to a first straight line passing through the first connection position and the second connection position.

15. The semiconductor device according to claim 1, wherein a length of the recess in a second direction orthogonal to a first direction from the second connection position toward the first connection position is equal to or greater than a length of a portion of the second conduction member that contacts the upper surface of the conductive layer in the second direction.

16. The semiconductor device according to claim 1, wherein the conductive layer has a first connection region capable of connecting the first conduction member and a plurality of second connection regions capable of connecting the second conduction member, respectively, on the upper surface, a plurality of the recesses are provided on a side opposite to the first connection region with respect to the plurality of second connection regions on the upper surface side of the conductive layer.

17. The semiconductor device according to claim 16, wherein a plurality of the first conduction members are connected within the first connection region.

18. The semiconductor device according to claim 1, wherein at least a portion of the recess is filled with a sealing material that seals the conductive layer, the first conduction member, and the second conduction member.

19. The semiconductor device according to claim 1, wherein the first conduction member is a wire or a metal sheet, the second conduction member is a wire or a metal sheet.

20. The semiconductor device according to claim 1, wherein the semiconductor device is a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

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