Thin film transistor based on channel edge electric field enhancement
By designing a microstructure that increases the P/W ratio and utilizing the channel edge effect to form a high-conductivity channel, the problem of limited on-state current enhancement in thin-film transistors is solved, achieving a doubling of driving capability and performance decoupling, making it suitable for highly integrated circuits.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-10
- Publication Date
- 2026-03-10
AI Technical Summary
Existing thin-film transistor technology fails to effectively utilize the channel edge effect, resulting in limited improvement in on-state current, and traditional designs have limited performance improvement when the macroscopic W/L ratio is fixed.
By designing a two-dimensional microstructure with an increased P/W ratio, a high-conductivity conductive channel is formed at the channel edge. The edge effect is used as a performance gain mechanism, and the total current is formed by combining the bulk conduction current and the edge conduction current.
Under the same floor space and macro W/L ratio, the on-state current is increased by 60%~150%, achieving performance decoupling, suitable for highly integrated circuits and highly compatible with existing production lines.
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Figure CN121645959A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and more specifically, to a thin-film transistor (TFT) that improves carrier transport efficiency by regulating the electric field distribution within the channel. Background Technology
[0002] Thin-film transistors (TFTs) are the cornerstone of modern electronics industries such as flat panel displays and flexible electronics. Their on-state current (I_on), as a core indicator of driving capability, directly determines circuit performance. According to classical TFT theory, the on-state current is mainly determined by the channel width-to-length ratio (W / L), carrier mobility, and gate capacitance.
[0003] To improve the on-state current, those skilled in the art typically follow two technical paths: First, optimize the device geometry at the macroscopic level. For example, use comb / interdigital structures or simple serpentine structures to increase the aspect ratio (W / L). The essence of this type of design is still to treat the channel as a uniform "bulk conductance" region, and its performance improvement is limited by the device footprint.
[0004] Second, addressing and suppressing parasitic effects at the channel edges at the microscopic level. In patterned semiconductor channels, electric fields concentrate at edges and corners, a phenomenon known as the "edge effect." This is generally considered detrimental, leading to threshold voltage drift and decreased device reliability. Therefore, numerous technologies have focused on reducing or shielding edge electric fields through methods such as channel rounding and adding guard rings, clearly demonstrating that edge effects should be avoided rather than utilized in this field.
[0005] In addition, a technique has recently emerged that achieves macroscopic stretchability of devices by introducing microstructures within the channel. This technique aims to address the mechanical stretchability problem of rigid semiconductor materials. Its core principle is to utilize mechanical structural design to dissipate macroscopic strain through geometric deformations of the structure (such as buckling and rotation), thereby protecting the material from damage. However, this technique focuses on maintaining mechanical properties and does not reveal or utilize the intrinsic enhancing effect of these microstructures on electrical drive capability.
[0006] In summary, existing technologies either focus on improving the macroscopic W / L ratio, suppressing edge effects (considered a negative factor), or addressing mechanical issues. No technology has yet proposed a method to actively and controllably utilize and maximize channel edge effects by designing the channel's micro-geometry to enhance edge conductivity, thereby achieving a significant increase in on-state current while maintaining a fixed macroscopic W / L ratio. There is an urgent need in this field for a technology that can overcome the physical limitations of traditional devices and open up new dimensions for performance improvement. Summary of the Invention
[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a thin-film transistor that can significantly improve the on-state current by utilizing and enhancing the channel edge electric field effect within a limited footprint.
[0008] To achieve the above objectives, the present invention provides a thin-film transistor, comprising a substrate, a gate, a gate insulating layer, a source, a drain, and a semiconductor active layer located between the source and the drain. Its core feature is that the conductive channel formed by the semiconductor active layer is patterned as a predetermined two-dimensional microstructure. The microstructure is increased such that the ratio (P / W) of the total edge length (P) of the channel to the macroscopic width (W) of the channel is increased, thereby forming an edge conductive channel with a higher conductivity than the central body region of the channel when a gate voltage is applied.
[0009] The core idea of this invention lies in its revolutionary transformation of the "edge effect," which traditionally needs to be suppressed, into a performance-gain mechanism that can be actively utilized. This invention reveals that the total current of a transistor is composed of both "bulk current (I_bulk)" and "edge current (I_edge)" (I_total = I_bulk + I_edge). Because the gate electric field lines are distorted and concentrated at the sharp edges and corners of the channel, the carrier surface density in the edge region is significantly higher than that in the central bulk region of the channel, thus forming a parallel conductive path with higher conductivity, i.e., the "edge conductive channel."
[0010] This invention achieves successful decoupling of driving capability and macroscopic geometric W / L ratio by carefully designing a microstructure with an increased P / W ratio, so that the current contributed by edge effect (I_edge) in the total current changes from a negligible parasitic part to the main source of gain.
[0011] Compared with the prior art, the present invention has the following beneficial technical effects: Increased driving capability: Under the same device footprint and macro W / L ratio, the on-state current of the TFT of the present invention is increased by 60% to 150% compared with conventional smooth channel TFT.
[0012] Achieving performance decoupling: This invention introduces "edge length" as a new degree of freedom for performance regulation at the electrical design level, breaking the traditional limitation that the on-state current depends only on the macroscopic W / L ratio.
[0013] High integration and compatibility: This invention improves performance by optimizing the internal geometry of the channel without changing the overall size of the device. It is easy to integrate in high-density circuits and can be fabricated using standard micro-nano processes, making it highly compatible with existing production lines. Attached Figure Description
[0014] Figure 1 This is a schematic diagram of the cross-sectional structure of a thin-film transistor according to the present invention.
[0015] Figure 2 This is a schematic diagram of a conventional smooth-edge serpentine channel in the prior art (Example 1).
[0016] Figure 3 This is a schematic diagram of a serpentine channel structure with periodic concave and convex edge structure in Embodiment 2 of the present invention.
[0017] Figure 4 for Figure 3 An enlarged schematic diagram of part A in the middle.
[0018] Figure 5 This is a schematic diagram of a serpentine channel structure with an arrayed hole structure in Embodiment 3 of the present invention.
[0019] Figure 6 This is a schematic diagram of a serpentine channel structure with a three-level fractal structure in Embodiment 4 of the present invention.
[0020] Figure 7 for Figure 6 Enlarged diagram of part B.
[0021] Figure 8 This is a comparison graph of the transfer characteristic curves of the devices prepared in Example 1 and other examples.
[0022] Figure 9 This is a comparison chart of the output characteristic curves of the devices prepared in Example 1 and other examples. Detailed Implementation
[0023] The embodiments of the present invention will now be clearly and completely described in conjunction with the accompanying drawings.
[0024] See Figure 1 A thin-film transistor based on channel edge electric field enhancement is disclosed, including a substrate (101), a gate (102), a gate insulating layer (103), a source (105), a drain (106), and a semiconductor active layer (104) located between the source and the drain.
[0025] Preparation of Examples 1, 2, 3, and 4 Four sets of devices were fabricated using the same materials and process steps, with the core difference being the pattern of the semiconductor active layer (104). The macroscopic width W of the channel in all devices was uniformly 20 μm, the macroscopic length L was uniformly 200 μm, and the macroscopic L / W ratio was 10.
[0026] Example 1: Conventional smooth serpentine channel ( Figure 2 (As shown).
[0027] Example 2: A serpentine channel with a periodic U-shaped groove edge (e.g.) Figure 3 , Figure 4 As shown), the groove depth (d / 2) is 2μm and the period (p) is 5μm.
[0028] Example 3: A serpentine channel with an internal array of circular holes (e.g.) Figure 5 As shown in the figure, the hole radius is 1μm and the spacing is 3μm.
[0029] Example 4: A three-level fractal serpentine channel composed of microscopic serpentine paths (e.g.) Figure 6 As shown in the figure, the widths of the secondary and tertiary micropaths are 2 μm and 0.3 μm, respectively.
[0030] Core technology feature analysis To clarify the underlying mechanism of the present invention, the total edge length / macro width ratio (P / W) of each embodiment is first quantitatively analyzed. The total edge length P of the channel includes the outer edge and the edges of all internal holes.
[0031] Table 1: Macroscopic L / W ratio and P / W ratio for each embodiment
[0032] Note: The P / W value is estimated based on geometric parameters.
[0033] Performance Testing and Results Analysis The electrical performance of the above-mentioned devices was tested, and the results are as follows: Figure 7 and Figure 8 As shown.
[0034] from Figure 7 The transfer characteristic curves and the data in the table above can be compared as follows: Example 1 (P / W ≈ 20.2): The on-state current I_on is approximately 5.2μA.
[0035] Example 2 (P / W ≈ 26.5): The on-state current I_on reached 8.5μA, an improvement of 63%.
[0036] Example 3 (P / W ≈ 45.8): The on-state current I_on reached 7.9μA, an improvement of 52%.
[0037] Example 4 (P / W ≈ 82.0): On-state current I_on is up to 12.8μA, an improvement of 146%.
[0038] Experimental results clearly demonstrate a strong and definite positive correlation between the on-state current gain and the P / W ratio. The fractal structure (Example 4), due to its highest P / W ratio, exhibits excellent current enhancement, confirming the core technical concept of this invention: by maximizing the channel edge length, the "edge conductive channel" effect can be effectively utilized to achieve a multiplication of the on-state current. Simultaneously, the negative shift in the threshold voltage of each embodiment also confirms the physical phenomenon that edge field enhancement enables the channel to open earlier.
[0039] The basic principles, main features, and advantages of this invention in the explored field have been described in detail above, and some usage examples have been detailed. Finally, it should be noted that the examples given above are only for illustrative purposes and are not intended to limit the invention. Although we have described this invention in detail with reference to the examples, those skilled in the art can still modify the described examples and solutions, or replace related technical parts. Therefore, any modifications or equivalent substitutions made within the spirit and principles of this invention are within the protection scope of the claims of this patent.
Claims
1. A thin film transistor based on channel edge electric field enhancement, comprising: a substrate (101) and a gate (102), a gate insulating layer (103), a source (105), a drain (106) and a semiconductor active layer (104) located above the substrate (101); the source (105) and the drain (106) are located on both sides of the semiconductor active layer (104); the gate insulating layer (103) is located between the semiconductor active layer (104) and the gate (102); characterized in that: the channel formed by the semiconductor active layer (104) is a thin film with a preset two-dimensional microstructure, the two-dimensional microstructure makes the ratio (P / W) of the total edge length (P) of the channel to the macroscopic width (W) of the channel greater than the ratio (L / W) of the macroscopic length (L) of the channel to the macroscopic width (W), so that the gate electric field is concentrated in the edge region of the two-dimensional microstructure, resulting in a higher carrier surface density in the edge region than in the central bulk region of the channel, forming an edge conduction channel with higher conductivity than the central bulk region of the channel in the edge region of the channel.
2. The channel- edge electric field enhancement based thin film transistor according to claim 1, wherein, The ratio of the ratio (P / W) of the total edge length (P) of the channel to the macroscopic width (W) to the ratio (L / W) of the macroscopic length (L) to the macroscopic width (W) is greater than 1.
2.
3. The channel- edge electric field enhancement based thin film transistor according to claim 1, wherein, The two-dimensional microstructure is a periodic concave-convex structure provided on at least one side wall of the macroscopic path of the channel.
4. The channel- edge electric field enhancement based thin film transistor according to claim 1, wherein, The two-dimensional microstructure is an arrayed hole formed inside the region defined by the macroscopic path of the channel.
5. The channel- edge electric field enhancement based thin film transistor according to claim 1, wherein The two-dimensional microstructure is a fractal structure, wherein the macroscopic path of the channel itself is composed of a plurality of microscopic paths with smaller geometric parameters.
6. The channel- edge electric field enhancement based thin film transistor according to any one of claims 1 to 5, wherein The semiconductor active layer is an organic semiconductor thin film or an oxide semiconductor thin film.
7. The channel- edge electric field enhanced thin film transistor according to claim 6, wherein The semiconductor active layer is a two-dimensional material.
8. A method of manufacturing a channel- edge electric field enhancement-based thin film transistor according to any one of claims 1 to 7, characterized by, The step of forming the two-dimensional microstructure on the semiconductor active layer by a micro-nano processing process to construct the edge conduction channel. 9.The application of the thin film transistor based on channel edge electric field enhancement in an organic light emitting diode (OLED) display driving circuit, a logic operation circuit or a sensor array according to any one of claims 1-7.