Integrated groove type silicon carbide transistor and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductors, and discloses an integrated groove type silicon carbide transistor and a preparation method thereof, the integrated groove type silicon carbide transistor structurally comprises a silicon carbide MOSFET cellular structure, and the MOSFET cellular structure comprises a silicon carbide semiconductor film, an MOSFET structure and at least one diode integrated structure; the silicon carbide semiconductor film sequentially comprises a silicon carbide substrate, a silicon carbide buffer layer and a silicon carbide epitaxial film from bottom to top; and the MOSFET structure and the diode integrated structure are arranged in a row and are arranged on the silicon carbide semiconductor film. The device is good in structural stability and reliability and high in practicability, and the effect of continuous transmission of circuit current can be guaranteed. The preparation method comprises the steps of dividing a region, forming a source region doped region, forming a source trench, forming a base region doped region, forming a gate trench, forming a gate conductive film, forming an isolation dielectric film, forming ohmic contact and forming a pressure welding electrode. The method is high in process adaptability, good in compatibility and suitable for large-scale production.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an integrated trench silicon carbide transistor and its fabrication method. Background Technology

[0002] Silicon carbide MOSFETs, as third-generation semiconductor devices, possess advantages such as high breakdown voltage, fast switching speed, and high temperature resistance, making them widely used in high-voltage, high-current applications such as electric vehicles, aerospace, and new energy power generation. In typical bridge circuit applications such as half-bridge or full-bridge circuits, a freewheeling path is required when the switching transistor is turned off. However, silicon carbide MOSFETs naturally possess a body diode (i.e., a parasitic diode) composed of P-doped regions and N-drift regions. Silicon carbide MOSFET devices are often forced to act as freewheeling diodes, which may lead to a series of performance and reliability issues, mainly including the following: 1. The typical forward voltage drop of silicon carbide bulk diodes is 2.5V to 4V. In high-current freewheeling scenarios, it will generate huge conduction losses, which will severely limit system efficiency and generate a lot of heat. 2. The body diode is a bipolar conductor. During the reverse recovery process, there are reverse recovery current and reverse recovery charge, which cause significant current spikes, voltage spikes and switching losses, posing a serious challenge to circuit stability and electromagnetic compatibility. 3. The unique defects of silicon carbide materials make it easy for holes injected during the conduction of the body diode to be captured by crystal defects. The energy released by carrier recombination during the reverse recovery stage will exacerbate the expansion of lattice defects, causing the on-resistance of the MOSFET to gradually increase with the number of switching cycles, which may eventually lead to device overheating failure. This is especially fatal in applications with high reliability requirements.

[0003] To address the aforementioned problems with silicon carbide MOSFET devices, some researchers have attempted to solve these issues by connecting an external parallel freewheeling diode. However, this additional device increases circuit size, cost, and parasitic parameters, affecting system integration and switching performance. Other solutions attempt to optimize the body diode structure, but these cannot fundamentally eliminate the reverse recovery problem and long-term reliability risks caused by bipolar conductivity. Summary of the Invention

[0004] The purpose of this invention is to provide an integrated trench silicon carbide transistor with good structural stability and reliability, strong practicality, and the ability to ensure continuous current transmission in the circuit.

[0005] The technical solution adopted to achieve the purpose of this invention is: An integrated trench silicon carbide transistor includes a silicon carbide MOSFET cell structure, wherein the MOSFET cell structure includes a silicon carbide semiconductor thin film, a MOSFET structure, and at least one integrated diode structure. The silicon carbide semiconductor thin film comprises, from bottom to top, a silicon carbide substrate, a silicon carbide buffer layer, and a silicon carbide epitaxial thin film; The MOSFET structure and the diode integrated structure are arranged in a row on a silicon carbide semiconductor thin film.

[0006] Furthermore, a gate trench is formed on the top of the silicon carbide epitaxial film, penetrating the MOSFET structure region and the diode integrated structure region. Bottom insulating dielectric film and sidewall insulating dielectric film are respectively provided on the bottom and sidewall of the gate trench. The gate trench is also filled with a gate conductive film. Source trenches are also formed on the top of the silicon carbide epitaxial films on both sides of the gate trench. Base doped regions are also provided inside the source trenches. Source doped regions are also provided on the top of the base doped regions.

[0007] Furthermore, a front bonding electrode is provided on the top of both the base doped region and the source doped region; a front ohmic contact layer and an isolation dielectric film are respectively provided between the front bonding electrode and the base doped region and the source doped region; a back bonding electrode is also provided on the back side of the silicon carbide substrate, and a back ohmic contact is formed between the back bonding electrode and the silicon carbide substrate.

[0008] Furthermore, the width of the gate trench in the diode integrated structure region is greater than the width in the MOSFET structure region; the distance d1 between the gate trench and the source trench in the diode structure region is less than the distance d2 in the MOSFET structure region.

[0009] Furthermore, when the integrated trench silicon carbide transistor is a silicon carbide MOSFET device, the silicon carbide substrate, silicon carbide buffer layer, silicon carbide epitaxial film and source region doped region are of the first conductivity type, and the base region doped region is of the second conductivity type. When the integrated trench silicon carbide transistor is a silicon carbide IGBT device, the silicon carbide buffer layer, the silicon carbide epitaxial film, and the source region doped region are of the first conductivity type, and the silicon carbide substrate and the base region doped region are of the second conductivity type. The first conductivity type and the second conductivity type have opposite doping types, and the doping types include N-type or P-type. The N-type doping impurity is nitrogen or phosphorus, and the P-type doping impurity is aluminum or boron.

[0010] Furthermore, the front bonding electrode, the back bonding electrode, and the front ohmic contact layer are composed of a single-layer thin film or multiple composite thin films of Ti, Ni, Al, Cu, Au, Ag, Mo, W, TiW, TiC, Fe, and Cr, with a film thickness of 0.001 μm to 10 μm.

[0011] Another objective of this invention is to provide a method for fabricating integrated trench silicon carbide transistors, which has high process adaptability, good compatibility, and is suitable for large-scale production.

[0012] The technical solution adopted to achieve another objective of the present invention is: A method for fabricating an integrated trench silicon carbide transistor specifically includes the following steps: Step S1, Divide the region: Divide the silicon carbide semiconductor thin film, which includes a silicon carbide substrate, a silicon carbide buffer layer and a silicon carbide epitaxial thin film from bottom to top, into a MOSFET structure region and a diode integrated structure region. Step S2, forming the source doped region: forming the source doped region on the top of the silicon carbide epitaxial film; Step S3, forming source trench: A source trench is formed on both sides of the source doped region, penetrating the MOSFET structure region and the diode integrated structure region, and the source trench extends downward to the silicon carbide epitaxial film, so that the silicon carbide epitaxial film has a "convex" shaped structure. Step S4, forming the base region doped region: doping is performed on the top of the silicon carbide epitaxial film of the source trench wall and the MOSFET structure region to form the base region doped region; Step S5, forming a gate trench: A gate trench is formed in the middle of the source region doped region, penetrating the MOSFET structure region and the diode integrated structure region, and the gate trench extends downward to the silicon carbide epitaxial film. Step S6, forming a gate conductive film: a bottom insulating dielectric film and a sidewall insulating dielectric film are formed at the bottom and sidewall of the gate trench, respectively, and then the gate conductive film is filled in the gate trench; Step S7, forming an isolation dielectric film: depositing an isolation dielectric film on the source doped region and the upper surface of the gate conductive film; Step S8, forming an ohmic contact: forming a front ohmic contact layer on the surface of the base doped region within the source trench; Step S9, forming a bonding electrode: A front bonding electrode covering a front ohmic contact layer, a gate conductive film and an isolation dielectric film is deposited on top of a silicon carbide semiconductor thin film, and a back bonding electrode is deposited on the back side of the silicon carbide substrate, and a back ohmic contact is formed between the back bonding electrode and the silicon carbide substrate.

[0013] Furthermore, in step S2, the source region doped is formed by secondary epitaxy or ion implantation.

[0014] Further, in step S4, the base region doped is formed by ion implantation, with the ion implantation energy being 10 keV~15 MeV, the implantation temperature being 22℃~1000℃, and the implantation dose being 1×10⁻⁶. 10 ~5×10 16 cm -2 .

[0015] The beneficial effects of this invention are as follows: 1. The MOSFET structure and diode integrated structure of the present invention rely on the same silicon carbide substrate and epitaxial layer, which ensures the structural stability and reliability of the device of the present invention; and there is no need for an external independent freewheeling diode, which can reduce the number of devices and the circuit space occupied, reduce parasitic parameters such as parasitic inductance and parasitic capacitance, and has strong practicality. 2. The device using the present invention can achieve the effect of the diode integrated structure not conducting and not interfering when the MOSFET structure is working normally, and the diode integrated structure automatically forming a freewheeling channel to replace the traditional body diode when the switching transistor is turned off, thus ensuring the continuous transmission of circuit current. 3. The process of the present invention does not require the development of special equipment and is highly compatible with existing silicon carbide device mass production lines, which can reduce equipment investment and process debugging costs. Furthermore, the process of the present invention can simultaneously process the MOSFET structure and diode integrated structure in the integrated trench silicon carbide transistor, avoiding alignment deviations caused by multiple etching in different regions. It has high process matching degree, good compatibility, and is suitable for large-scale production. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Figure 1 This is a top view schematic diagram of an integrated trench silicon carbide transistor of the present invention; Figure 2 This is a schematic diagram of a longitudinal section of a silicon carbide semiconductor thin film at different positions in the structure of this invention; Figure 3 This is a schematic diagram of a structure after step S4 in Example 2 is completed; Figure 4 This is a schematic diagram of a processing procedure in steps S5 to S6 of Example 2; Figure 5 This is a schematic diagram of an overall longitudinal section at different locations in the structure of this invention.

[0017] exist Figures 2 to 5 In the diagram, (a), (b), and (c) represent the directions along... Figure 1 Schematic diagrams of the corresponding structures at the cross-sectional views of positions A-A', B-B', and C-C'.

[0018] In the figure: 1. Silicon carbide semiconductor thin film; 2. MOSFET structure; 3. Diode integrated structure; 4. Gate trench; 5. Bottom insulating dielectric film; 6. Sidewall insulating dielectric film; 7. Gate conductive film; 8. Source trench; 9. Base doped region; 10. Source doped region; 11. Front bonding electrode; 12. Front ohmic contact layer; 13. Isolation dielectric film; 14. Back bonding electrode; 101. Silicon carbide substrate; 102. Silicon carbide buffer layer; 103. Silicon carbide epitaxial thin film; 131. Lower epitaxial layer; 132. Upper epitaxial layer; 301. Integrated diode structure I; 302. Integrated diode structure II. Detailed Implementation

[0019] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0020] Example 1 like Figures 1 to 5 As shown, an integrated trench silicon carbide transistor includes a silicon carbide MOSFET cell structure, wherein the MOSFET cell structure includes a silicon carbide semiconductor thin film 1, a MOSFET structure 2 and at least one diode integrated structure 3. The silicon carbide semiconductor thin film 1 includes, from bottom to top, a silicon carbide substrate 101, a silicon carbide buffer layer 102, and a silicon carbide epitaxial thin film 103; The MOSFET structure 2 and the diode integrated structure 3 are arranged in a row on the silicon carbide semiconductor thin film 1.

[0021] The silicon carbide semiconductor thin film 1 of the present invention is made of 4H-SiC. The silicon carbide epitaxial thin film 103 is a single-layer silicon carbide epitaxial thin film 103 or a multi-layer silicon carbide epitaxial thin film 103. The present invention is described using a two-layer epitaxial film as an example. Specifically, in one embodiment of the present invention, the silicon carbide epitaxial thin film 103 comprises two layers of silicon carbide epitaxial thin films 103, namely, a lower epitaxial layer 131 and an upper epitaxial layer 132 from bottom to top. Furthermore, in the present invention, the trenching and doping of the silicon carbide epitaxial thin film 103 are all performed on the upper epitaxial layer 132.

[0022] The device of this invention uses a silicon carbide semiconductor thin film 1 as the base carrier, and arranges the MOSFET structure 2 and the diode integrated structure 3 in a row within the same MOSFET cell, achieving tight integration of two core functional structures. Furthermore, the MOSFET structure 2 and the diode integrated structure 3 rely on the same silicon carbide substrate 101 and epitaxial layer, ensuring the structural stability and reliability of the device. Simultaneously, integrating the MOSFET switching function and the freewheeling diode function into the same cell structure eliminates the need for an external independent freewheeling diode, reducing the number of devices and circuit space, and lowering parasitic parameters such as parasitic inductance and capacitance, thus enhancing its practicality.

[0023] The present invention provides at least one diode integrated structure 3 that can meet multiple requirements in high voltage and high current scenarios. It achieves balanced distribution of freewheeling current through multi-channel parallelism, reducing local heat generation and electrical stress concentration. It can also improve the fault tolerance of the device with functional redundancy, avoiding system paralysis caused by the failure of a single structure. At the same time, it compensates for process deviations in mass production by leveraging the complementary performance of multiple structures, and ultimately comprehensively optimizes the working stability, reliability and applicability of the device.

[0024] In this invention, a gate trench 4 penetrating the MOSFET structure 2 region and the diode integrated structure 3 region is formed on the top of the silicon carbide epitaxial film 103. A bottom insulating dielectric film 5 and a sidewall insulating dielectric film 6 are respectively provided on the bottom and sidewall of the gate trench 4. A gate conductive film 7 is also filled inside the gate trench 4. Source trenches 8 are also formed on the top of the silicon carbide epitaxial films 103 on both sides of the gate trench 4. A base doped region 9 is also provided inside the source trench 8. A source doped region 10 is also provided on the top of the base doped region 9. The width of the gate trench 4 in the diode integrated structure 3 region is greater than the width in the MOSFET structure 2 region. The distance d1 between the gate trench 4 and the source trench 8 in the diode structure region is less than the distance d2 in the MOSFET structure 2 region.

[0025] In this invention, a front bonding electrode 11 is provided on the top of both the base doped region 9 and the source doped region 10; a front ohmic contact layer 12 and an isolation dielectric film 13 are respectively provided between the front bonding electrode 11 and the base doped region 9 and the source doped region 10; a back bonding electrode 14 is also provided on the back side of the silicon carbide substrate 101, and a back ohmic contact is formed between the back bonding electrode 14 and the silicon carbide substrate 101. In this invention, the front bonding electrode 11, the back bonding electrode 14, and the front ohmic contact layer 12 are composed of a single-layer film or multiple composite films of Ti, Ni, Al, Cu, Au, Ag, Mo, W, TiW, TiC, Fe, and Cr, and the film thickness is 0.001 μm to 10 μm.

[0026] In this invention, the gate trench 4 penetrates the regions of the MOSFET structure 2 and the diode integrated structure 3. The insulating dielectric film on its bottom and sidewalls provides electrical isolation between the gate conductive film 7 and the silicon carbide semiconductor film 1. The gate conductive film 7 regulates the operating states of the two structures through voltage control. Functional partitioning is constructed by differentiating the width of the gate trench 4 and the spacing between the gate trench 4 and the source trench 8. The size design of the MOSFET structure 2 region meets its normal switching control requirements, while the size design of the diode integrated structure 3 region provides the structural conditions for the freewheeling function to start. The base-doped region 9 forms a PN junction with the silicon carbide epitaxial film 103, and its conductivity is jointly regulated by voltage changes and the aforementioned size design.

[0027] When the device of the present invention is operating normally, the MOSFET structure 2 is turned on and off under the control of the gate voltage. At this time, when a forward voltage is applied to the gate, the MOSFET structure 2 forms a conductive channel, and the current flows through the front bonding electrode 11, the front ohmic contact layer 12, the source doped region 10, the silicon carbide epitaxial film 103, the silicon carbide substrate 101, and the back bonding electrode 14 to form a circuit. At this time, the PN junction in the region of the diode integrated structure 3 is in a reverse bias or depletion region blocking state due to the gate voltage regulation and the design of the spacing d1. The isolation dielectric film 13 further ensures the insulation between the electrodes, ensuring that the diode integrated structure 3 does not conduct and does not interfere with the normal operation of the MOSFET structure 2.

[0028] When the device is used in a bridge circuit and the switching transistor is off, the circuit requires a freewheeling path. At this time, the freewheeling current causes a voltage change in the region of the diode integrated structure 3, forward biasing the PN junction formed by the base doped region 9 and the silicon carbide epitaxial film 103. This causes the junction to automatically conduct and form a freewheeling channel. The current completes the loop transmission through the diode integrated structure 3, replacing the body diode of a traditional MOSFET to perform the freewheeling function and ensuring continuous current transmission in the circuit. Simultaneously, due to the wider gate trench 4 and smaller spacing d1 in the diode region, the width of the PN junction depletion region is significantly reduced, forming a conduction channel. The current completes the freewheeling through the front bonding electrode 11, the base doped region 9, the silicon carbide epitaxial film 103, the silicon carbide substrate 101, and the back bonding electrode 14, replacing the traditional body diode to perform the freewheeling function.

[0029] The following uses data examples to illustrate a specific embodiment of the present invention.

[0030] In this embodiment, the base doped region 9 has a depth in the vertical direction and a width in the horizontal direction of 0.5 μm. The base doped region 9 is P. + Region, doping concentration of 1e18cm -3 The silicon carbide epitaxial thin film 103 is N - Region, doping concentration of 1e16cm -3The P-type base doped region 9 and the silicon carbide epitaxial film 103 form a P-type base doped region 9. + -N - The depletion region is mainly in N. - On one side, the width of the depletion layer at 0V is approximately 0.567 μm.

[0031] In the MOSFET structure 2 of this embodiment, the gate trench 4 has a width of 1 μm, and the distance between the gate trench 4 and the source trenches 8 on its corresponding two sides is 1.2 μm; the distance between the gate trench 4 and the base doped region 9 is 0.7 μm (>0.567 μm), and it will not be pinched off under natural conditions.

[0032] In the diode integrated structure 3 of this embodiment, the width of the gate trench 4 can be increased to 1.5 μm during layout design, and the spacing between the gate trench 4 and the source trenches 8 on its corresponding two sides is reduced to 0.95 μm. The distance between the gate trench 4 and the base doped region 9 is 0.45 μm (<0.567 μm), and it is pinched off in its natural state.

[0033] When the switching transistor is turned off, the voltage of the base doped region 9 in the diode integrated structure 3 relative to the silicon carbide epitaxial film 103 increases under the action of the freewheeling current. + -N - When the junction forward bias voltage is 1.5V and 2V, N - The widths of the depletion layer on one side of the region decreased to 0.4 μm and 0.327 μm (both < 0.45 μm), respectively, and the follow current channel opened.

[0034] In this embodiment, there are two diode integrated structures 3. The MOSFET structure 2 and the two diode integrated structures 3 are arranged in a row on the silicon carbide semiconductor thin film 1, and the positions of the MOSFET structure 2 and the two diode integrated structures 3 can be arbitrarily interchanged.

[0035] For ease of understanding, the two MOSFET structures 2 are respectively named diode integrated structure I 301 and diode integrated structure II 302. The MOSFET structure 2 is located at the outermost edge, and diode integrated structure I 301 and diode integrated structure II 302 are sequentially located on the same side of the MOSFET structure 2. That is, diode integrated structure I 301 is located in the middle, and MOSFET structure 2 and diode integrated structure II 302 are located on opposite sides of diode integrated structure I 301. In this embodiment, diode integrated structure I 301 and diode integrated structure II 302 can be completely identical, and diode integrated structure II 302 may also omit the isolation dielectric film 13 between the front bonding electrode 11 and the source doped region 10. In other embodiments, the MOSFET structure 2 can also be located between diode integrated structure I 301 and diode integrated structure II 302, depending on the processing habits.

[0036] Both diode integrated structure I 301 and diode integrated structure II 302 have the same effect at the turn-off moment. In actual design, the choice can be made based on the actual fabrication process. However, diode integrated structure I 301 has a better process matching with MOSFET structure II. When MOSFET structure II is operating normally, a positive voltage is applied to the gate, and the gate conductive film 7, the sidewall insulating dielectric film 6, and the silicon carbide epitaxial film 103 form a MOS capacitor that enters a depletion or strong inversion mode. This capacitor, along with the base doped region 9 and the silicon carbide epitaxial film 103, forms a P-type capacitor. + -N - The natural depletion regions of the single-sided abrupt junction are connected, enhancing the effect of the current blocking region under normal operating conditions. Therefore, in practical design, the diode integrated structure 3 is preferably designed as the structure of diode integrated structure I 301, that is, diode integrated structure I 301 and diode integrated structure II 302 can be completely identical, and an isolation dielectric film 13 is provided between the front bonding electrode 11 and the source doped region 10.

[0037] In this invention, when the integrated trench silicon carbide transistor is a silicon carbide MOSFET device, the silicon carbide substrate 101, the silicon carbide buffer layer 102, the silicon carbide epitaxial film 103 and the source doped region 10 are of the first conductivity type, and the base doped region 9 is of the second conductivity type. When the integrated trench silicon carbide transistor is a silicon carbide IGBT device, the silicon carbide buffer layer 102, the silicon carbide epitaxial thin film 103 and the source region doped region 10 are of the first conductivity type, and the silicon carbide substrate 101 and the base region doped region 9 are of the second conductivity type. The first conductivity type and the second conductivity type have opposite doping types, and the doping types include N-type or P-type. The N-type doping impurity is nitrogen or phosphorus, and the P-type doping impurity is aluminum or boron.

[0038] The structure of this invention can be flexibly adapted to the conductivity type of each region according to the device type. In MOSFET devices, the silicon carbide substrate 101, silicon carbide buffer layer 102, silicon carbide epitaxial film 103, and source doped region 10 have the same conductivity type, while the base doped region 9 has the opposite type. In IGBT devices, the silicon carbide buffer layer 102, silicon carbide epitaxial film 103, and source doped region 10 have the same conductivity type, while the silicon carbide substrate 101 and base doped region 9 have opposite types. This invention, through differentiated configuration of conductivity types, lays the foundation for the independent functions and collaborative operation of the two core structures.

[0039] Example 2 This embodiment describes the preparation method of the structure in Example 1. The specific scheme of this embodiment will be described in detail below.

[0040] A method for fabricating an integrated trench silicon carbide transistor specifically includes the following steps: Step S1, Divide the region: The silicon carbide semiconductor thin film 1, which includes a silicon carbide substrate 101, a silicon carbide buffer layer 102 and a silicon carbide epitaxial thin film 103 from bottom to top, is divided into a MOSFET structure 2 region and a diode integrated structure 3 region.

[0041] Step S2, forming source doped region 10: a source doped region 10 is formed on the top of silicon carbide epitaxial film 103.

[0042] In this step, a source doped region 10 is formed on top of the silicon carbide epitaxial film 103 through a secondary epitaxy or ion implantation process. The implanted ions are either N-type or P-type. If it is N-type doping, the dopant is nitrogen or phosphorus; if it is P-type doping, the dopant is aluminum or boron. In a MOSFET device, the silicon carbide substrate 101, silicon carbide buffer layer 102, silicon carbide epitaxial film 103, and source doped region 10 in this step have the same conductivity type, while the base doped region 9 has the opposite conductivity type. In an IGBT device, the silicon carbide buffer layer 102, silicon carbide epitaxial film 103, and source doped region 10 in this step have the same conductivity type, while the silicon carbide substrate 101 and base doped region 9 have the opposite conductivity type.

[0043] Secondary epitaxy and ion implantation are both common processes in this field. If secondary epitaxy is used, the silicon carbide epitaxial film 103 is used as the silicon carbide substrate 101, and the source region epitaxial layer is grown by vapor phase epitaxy. If ion implantation is used, an implantation mask is first deposited and patterned to expose the predetermined area of ​​the source region. The implanted ions are selected to match the doping type of the impurities. After implantation, a subsequent annealing activation step needs to be reserved to ensure that the doped atoms are effectively activated.

[0044] Step S3, forming source trench 8: A source trench 8 is formed on both sides of the source doped region 10, penetrating the MOSFET structure 2 region and the diode integrated structure 3 region, and the source trench 8 extends downward to the silicon carbide epitaxial film 103, so that the silicon carbide epitaxial film 103 has a "convex" shaped structure.

[0045] In this step, a dielectric mask is first deposited on the surface of the source doped region 10. The mask is then patterned using photolithography to define the position and size of the source trench 8. Next, trench etching is performed. A specialized gas suitable for silicon carbide, such as CF4, is used for etching. The etching depth is precisely controlled to penetrate the silicon carbide epitaxial film 103, causing the remaining silicon carbide epitaxial film 103 to form a "convex" shaped structure. After etching, the residual mask is removed, and the surface is cleaned.

[0046] In the above process, the dielectric mask is silicon dioxide, silicon nitride, polycrystalline silicon, amorphous silicon or common metal, and the common metal is a single-layer thin film or a composite layer thin film formed by Ni, Al, W, Ti or any alloy compound thereof, and the thickness of the dielectric mask is 0.01um to 10um.

[0047] In the above process, the photolithography technique used for trench etching is either wet or dry etching. The patterned mask is an interdigitated structure, a parallel strip, a polygonal mesa, or a combination thereof. The width of the window area is 0.1μm to 5μm, the etching depth is 0.1μm to 100μm, and the width of the mesa area is 0.1μm to 10μm.

[0048] Step S4, forming base region doped region 9: doping is performed on the walls of the source trench 8 and the top of the silicon carbide epitaxial film 103 in the region of MOSFET structure 2 to form base region doped region 9.

[0049] In this step, the base doped region 9 is formed via ion implantation. First, the area to be doped is covered with a carbon film for protection and then subjected to high-temperature annealing to activate the implanted impurities. The carbon film can be formed by photoresist spin coating followed by carbonization, or by carbon thin film sputtering. The ion implanted material is N, P, B, or Al; the ion implantation energy is 10 keV–15 MeV; the implantation temperature is 22℃–1000℃; and the implantation dose is 1 × 10⁻⁶. 10 ~5×10 16 cm -2 The annealing atmosphere is a vacuum, nitrogen, or argon atmosphere, the annealing temperature is 300℃~3000℃, and the annealing time is 0.1min~1000h. The carbon film must be completely removed after annealing.

[0050] Step S5, forming gate trench 4: A gate trench 4 is formed in the middle of the source region doped region 10, penetrating the region of MOSFET structure 2 and diode integrated structure 3, and the gate trench 4 extends downward to the silicon carbide epitaxial film 103.

[0051] In this step, the gate trench 4 process is a common process in the art, such as the gate trench 4 process disclosed in patents with publication numbers CN113506826A or CN113299748A.

[0052] In practice, this step requires a photolithography process compatible with the source trench 8 fabrication. A gate trench 4 pattern is defined in the middle of the source doped region 10, with the width of the gate trench 4 pattern in the diode integrated structure 3 region designed to be greater than that in the MOSFET structure region. Then, a dry etching process is used to form the gate trench 4, penetrating both the MOSFET structure 2 region and the diode integrated structure 3 region. The etching depth must match the device's withstand voltage design, ensuring the bottom of the trench extends to a predetermined depth on the silicon carbide epitaxial film 103. After etching, plasma cleaning is performed to remove the etching damage layer from the trench sidewalls and bottom.

[0053] Step S6, forming gate conductive film 7: forming bottom insulating dielectric film 5 and sidewall insulating dielectric film 6 at the bottom and sidewall of gate trench 4 respectively, and then filling gate conductive film 7 in gate trench 4.

[0054] In this step, an insulating dielectric film is first formed on the bottom and sidewalls of the gate trench 4 using thermal oxidation or chemical vapor deposition (CVD) processes. The film thickness is controlled to be uniform and free of pinhole defects. Then, conductive material is filled using CVD or sputtering processes to form the gate conductive film 7. Finally, excess conductive material outside the trench is removed using chemical mechanical polishing (CMP) or etching processes, making the gate conductive film 7 flush with the trench surface. The bottom insulating dielectric film 5 and the sidewall insulating dielectric film 6 are both single-layer or multi-layer composite films of insulating silicon dioxide, silicon nitride, polycrystalline silicon, amorphous silicon, phosphosilicate glass, borosilicate glass, TEOS, etc. The gate conductive film 7 is a single-layer film of highly doped polycrystalline silicon or common metals (Al, Ni, Ti, W, Ag, and Au, etc.) or a composite film of any combination thereof.

[0055] Step S7, forming an isolation dielectric film 13: depositing an isolation dielectric film 13 on the upper surface of the source region doped region 10 and the gate conductive film 7.

[0056] In this step, a chemical vapor deposition process is used to deposit an isolation dielectric film 13 on the upper surface of the source region doped region 10 and the gate conductive film 7. The material of the isolation dielectric film 13 is selected from single-layer or multi-layer composite films such as silicon dioxide, silicon nitride, phosphosilicate glass or TEOS.

[0057] Step S8, forming an ohmic contact: forming a front ohmic contact layer 12 on the surface of the base region doped region 9 within the source trench 8.

[0058] In this step, a metal thin film is deposited on the surface of the base doped region 9 within the source trench 8 as the front ohmic contact layer 12 by sputtering or evaporation.

[0059] Step S9, forming a bonding electrode: depositing a front bonding electrode 11 covering the front ohmic contact layer 12, the gate conductive film 7 and the isolation dielectric film 13 on the silicon carbide semiconductor thin film 1; first performing a grinding and thinning process on the back side of the silicon carbide substrate 101, and then depositing the corresponding front bonding electrode 11 metal thin film.

[0060] In this step, a front bonding electrode 11 is deposited on the silicon carbide semiconductor thin film 1 using sputtering, evaporation, or electroplating processes. During deposition, it is ensured that the electrode covers the reserved area of ​​the front ohmic contact layer 12 and the gate conductive film 7. A back bonding electrode 14 is deposited on the back side of the silicon carbide substrate 101. After deposition, the electrode is patterned using photolithography and etching processes to form a preset electrode morphology and size, ensuring reliable connection between the electrode and the external circuit. In the above process, the ohmic contact can be achieved through a high-temperature processing process, including rapid thermal annealing (RTA), laser annealing (LA), or other high-temperature furnaces. During the processing, the gas atmosphere is a vacuum environment or an inert gas atmosphere such as nitrogen or argon.

[0061] In steps S8 and S9, the metals of the ohmic contact layer and the welding electrode are both metals or other conductive materials. When it is a metal, it is specifically composed of a single-layer thin film or multiple composite thin films such as Ti, Ni, Al, Cu, Au, Ag, Mo, W, TiW, TiC, Fe, Cr, etc., with a film thickness of 0.01um to 10um.

[0062] The present invention does not require the development of special equipment and is highly compatible with existing silicon carbide device mass production lines, which can reduce equipment investment and process debugging costs. At the same time, the process of the present invention can simultaneously process the MOSFET structure 2 and diode integrated structure 3 in the trench silicon carbide transistor, avoiding alignment deviations caused by multiple etching in different regions, with high process matching and good compatibility.

[0063] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the scope of the present invention should be included within the protection scope of the present invention.

Claims

1. An integrated trench silicon carbide transistor, comprising: The application relates to a silicon carbide MOSFET cell structure, which comprises a silicon carbide semiconductor film (1), a MOSFET structure (2) and at least one diode integrated structure (3). The silicon carbide semiconductor film (1) comprises, from bottom to top, a silicon carbide substrate (101), a silicon carbide buffer layer (102) and a silicon carbide epitaxial film (103). The MOSFET structure (2) and the diode integrated structure (3) are arranged in a row on the silicon carbide semiconductor film (1).

2. The integrated trench silicon carbide transistor of claim 1, wherein, The top of the silicon carbide epitaxial film (103) is provided with a gate trench (4) penetrating the MOSFET structure (2) region and the diode integrated structure (3) region, the bottom and the sidewall of the gate trench (4) are respectively provided with a bottom insulating medium film (5) and a sidewall insulating medium film (6), and the gate trench (4) is further filled with a gate conductive film (7); the top of the silicon carbide epitaxial film (103) on both sides of the gate trench (4) is further provided with a source trench (8), the inner side of the source trench (8) is further provided with a base region doped area (9), and the top of the base region doped area (9) is further provided with a source region doped area (10).

3. The integrated trench silicon carbide transistor of claim 2, wherein, The top of the base region doped area (9) and the source region doped area (10) is provided with a front surface press welding electrode (11); the front surface press welding electrode (11) is further provided with a front surface ohmic contact layer (12) and an isolation medium film (13) between the base region doped area (9) and the source region doped area (10); the back surface of the silicon carbide substrate (101) is further provided with a back surface press welding electrode (14), and the back surface ohmic contact is formed between the back surface press welding electrode (14) and the silicon carbide substrate (101).

4. The integrated trench silicon carbide transistor of claim 2 or 3, wherein, The width of the gate trench (4) in the diode integrated structure (3) region is greater than that in the MOSFET structure (2) region; the distance d1 between the gate trench (4) and the source trench (8) in the diode structure region is less than the distance d2 in the MOSFET structure (2) region.

5. The integrated trench silicon carbide transistor of claim 2 or 3, wherein, When the integrated trench type silicon carbide transistor is a silicon carbide MOSFET device, the silicon carbide substrate (101), the silicon carbide buffer layer (102), the silicon carbide epitaxial film (103) and the source region doped area (10) are of a first conductive type, and the base region doped area (9) is of a second conductive type; When the integrated trench type silicon carbide transistor is a silicon carbide IGBT device, the silicon carbide buffer layer (102), the silicon carbide epitaxial film (103) and the source region doped area (10) are of a first conductive type, and the silicon carbide substrate (101) and the base region doped area (9) are of a second conductive type; The first conductive type and the second conductive type are opposite in doping type, and the doping type comprises N type or P type; the impurities doped in the N type are nitrogen or phosphorus, and the impurities doped in the P type are aluminum or boron.

6. The integrated trench silicon carbide transistor of claim 4, wherein, When the integrated trench type silicon carbide transistor is a silicon carbide MOSFET device, the silicon carbide substrate (101), the silicon carbide buffer layer (102), the silicon carbide epitaxial film (103) and the source region doped area (10) are of a first conductive type, and the base region doped area (9) is of a second conductive type; When the integrated trench silicon carbide transistor is a silicon carbide IGBT device, the silicon carbide buffer layer (102), the silicon carbide epitaxial film (103) and the source region doped region (10) are of a first conductive type, and the silicon carbide substrate (101) and the base region doped region (9) are of a second conductive type; The first conductive type and the second conductive type are opposite in doping type, and the doping type includes N type or P type, the N type doped impurity is nitrogen or phosphorus, and the P type doped impurity is aluminum or boron.

7. The integrated trench silicon carbide transistor of claim 3 or 6, wherein, The front surface pressure welding electrode (11), the back surface pressure welding electrode (14) and the front surface ohmic contact layer (12) are single-layer thin films or multiple composite thin films composed of Ti, Ni, Al, Cu, Au, Ag, Mo, W, TiW, TiC, Fe or Cr, and the thickness of the thin film is 0.001 um to 10 um.

8. A method of fabricating an integrated trench silicon carbide transistor as claimed in any one of claims 1 to 7, characterised by, Specifically, the method comprises the following steps: Step S1, region division: dividing a silicon carbide semiconductor film (1) sequentially comprising a silicon carbide substrate (101), a silicon carbide buffer layer (102) and a silicon carbide epitaxial film (103) from bottom to top into a MOSFET structure (2) region and a diode integrated structure (3) region; Step S2, forming a source region doped region (10): forming the source region doped region (10) on the top of the silicon carbide epitaxial film (103); Step S3, forming a source electrode trench (8): forming the source electrode trench (8) on both sides of the source region doped region (10) and extending through the MOSFET structure (2) region and the diode integrated structure (3) region, and the source electrode trench (8) extends downward to the silicon carbide epitaxial film (103), so that the silicon carbide epitaxial film (103) is in a "convex" shape; Step S4, forming a base region doped region (9): doping the wall of the source electrode trench (8) and the top of the silicon carbide epitaxial film (103) in the MOSFET structure (2) region to form the base region doped region (9); Step S5, forming a gate trench (4): forming the gate trench (4) in the middle of the source region doped region (10) and extending through the MOSFET structure (2) region and the diode integrated structure (3) region, and the gate trench (4) extends downward to the silicon carbide epitaxial film (103); Step S6, forming a gate electrode conductive film (7): forming a bottom insulating dielectric thin film (5) and a sidewall insulating dielectric thin film (6) on the bottom and the sidewall of the gate trench (4), and then filling the gate electrode conductive film (7) in the gate trench (4); Step S7, forming an isolation dielectric thin film (13): depositing the isolation dielectric thin film (13) on the source region doped region (10) and the upper surface of the gate electrode conductive film (7); Step S8, forming an ohmic contact: forming the front surface ohmic contact layer (12) on the surface of the base region doped region (9) in the source electrode trench (8); Step S9, forming a pressure welding electrode: depositing the front surface pressure welding electrode (11) on the silicon carbide semiconductor film (1) to cover the front surface ohmic contact layer (12), the gate electrode conductive film (7) and the isolation dielectric thin film (13), and depositing the back surface pressure welding electrode (14) on the back surface of the silicon carbide substrate (101), and forming a back surface ohmic contact between the back surface pressure welding electrode (14) and the silicon carbide substrate (101).

9. The method of fabricating an integrated trench silicon carbide transistor of claim 8, wherein, In step S2, the source region doped region (10) is formed by a secondary epitaxy or ion implantation process.

10. The method of fabricating an integrated trench silicon carbide transistor of claim 8, wherein, In step S4, the base region doped region (9) is formed by an ion implantation process, and the energy of ion implantation is 10 kev~15 Mev, the temperature of implantation is 22℃~1000℃, the dose of implantation is 1×10 10 ~5×10 16 cm -2 .

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