Semiconductor device

Abstract

An example semiconductor device may include: a first semiconductor pattern and a second semiconductor pattern overlapping each other; a gate electrode including an electrode portion between the first semiconductor pattern and the second semiconductor pattern; an inner spacer contacting a top surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern; a two-dimensional layer contacting the first semiconductor pattern, the second semiconductor pattern, and the inner spacer; and a source / drain pattern, the source / drain pattern being located on the two-dimensional layer.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor device having improved electrical characteristics and reliability characteristics. BACKGROUND

[0002] Semiconductor devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOS-FETs). To meet increasing demands for semiconductor devices having small pattern sizes and reduced design rules, MOS-FETs are scaled down. Scaling down of MOS-FETs can cause deterioration of operating characteristics of semiconductor devices. Accordingly, various studies are conducted to overcome technical limitations associated with scaling down of semiconductor devices and to provide high-performance semiconductor devices. SUMMARY

[0003] In general, according to some aspects, a semiconductor device can include a first semiconductor pattern and a second semiconductor pattern that overlap each other, a gate electrode including an electrode portion located between the first semiconductor pattern and the second semiconductor pattern, an inner spacer in contact with a top surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern, a two-dimensional layer in contact with the first semiconductor pattern, the second semiconductor pattern, and the inner spacer, and a source / drain pattern located on the two-dimensional layer.

[0004] In general, according to some aspects, a semiconductor device can include a first semiconductor pattern and a second semiconductor pattern that overlap each other, a gate electrode including an electrode portion located between the first semiconductor pattern and the second semiconductor pattern, a two-dimensional layer in contact with the first semiconductor pattern and the second semiconductor pattern, an inner spacer located between the two-dimensional layer and the electrode portion, and a source / drain pattern located on the two-dimensional layer. The inner spacer can include a first side surface in contact with the two-dimensional layer and a second side surface opposite the first side surface. An area of the first side surface of the inner spacer can be less than an area of the second side surface of the inner spacer.

[0005] Generally, according to some aspects, a semiconductor device can include: a first semiconductor pattern and a second semiconductor pattern that overlap each other; a gate electrode including an electrode portion located between the first semiconductor pattern and the second semiconductor pattern; an inner spacer in contact with a top surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern; a gate insulating layer located between the inner spacer and the electrode portion; a two-dimensional layer in contact with a side surface of the first semiconductor pattern, a side surface of the second semiconductor pattern, and a first side surface of the inner spacer; a source / drain pattern located on the two-dimensional layer; and an active contact electrically connected to the source / drain pattern. The side surface of the first semiconductor pattern, the side surface of the second semiconductor pattern, and the first side surface of the inner spacer can be coplanar with each other. BRIEF DESCRIPTION OF DRAWINGS

[0006] FIG. 1A is a top view showing an example of a semiconductor device.

[0007] FIG. 1B is an example cross-sectional view taken along line A-A' of FIG. 1A .

[0008] FIG. 1C is an example cross-sectional view taken along line B-B' of FIG. 1A .

[0009] FIG. 1D is an example cross-sectional view taken along line C-C' of FIG. 1A .

[0010] FIG. 1E is an example cross-sectional view taken along line D-D' of FIG. 1A .

[0011] FIG. 1F is an example enlarged view showing a portion "Q1" of FIG. 1B .

[0012] FIG. 2A , FIG. 2B , FIG. 2C , FIG. 3A , FIG. 3B , FIG. 4A , FIG. 4B , FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B ,FIG. 10A 、 FIG. 10B 、 FIG. 11A 、 FIG. 11B 、 FIG. 12A 、 FIG. 12B 、 FIG. 13A 、 FIG. 13B 、 FIG. 14A 、 FIG. 14B 、 FIG. 15A 、 FIG. 15B 、 FIG. 16 、 FIG. 17 、 FIG. 18A 、 FIG. 18B 、 FIG. 19A 、 FIG. 19B 、 FIG. 20A 、 FIG. 20B 、 FIG. 21A and FIG. 21B are diagrams showing an example of a method of manufacturing a semiconductor device. FIGS. 1A-1F

[0013] FIG. 22 is a cross-sectional view showing an example of a semiconductor device. DETAILED DESCRIPTION

[0014] FIG. 1A is a plan view showing an example of a semiconductor device. FIG. 1B is an example cross-sectional view taken along line A-A' of FIG. 1A . FIG. 1C is an example cross-sectional view taken along line B-B' of FIG. 1A . FIG. 1D is an example cross-sectional view taken along line C-C' of FIG. 1A . FIG. 1E is an example cross-sectional view taken along line D-D' of FIG. 1A . FIG. 1F is an example enlarged view of a portion "Q1" of FIG. 1B .

[0015] Referring to FIG. 1A 、 FIG. 1B 、 FIG. 1C 、 FIG. 1D and FIG. 1E , the semiconductor device can include a substrate 10. A logic unit can be provided over the substrate 10. In the present specification, the logic unit can mean a logic device (e.g., AND, OR, XOR, XNOR, inverter, etc.) configured to perform a specific function. The logic unit can include a transistor constituting the logic device.

[0016] ​The substrate 10 can be a semiconductor substrate, an insulating substrate, or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate can be formed of or include, for example, silicon, germanium, silicon-germanium, GaP, or GaAs. The substrate 10 can be a plate-like structure extending in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 can be non-parallel to each other. For example, the first direction D1 and the second direction D2 can be horizontal directions orthogonal to each other.

[0017] The substrate 10 can include a fin pattern FP. The fin pattern FP can extend in the first direction D1. The fin pattern FP can be arranged to be spaced apart from each other in the second direction D2. The fin pattern FP can be an upper portion of the substrate 10 protruding in a third direction D3. The third direction D3 can be non-parallel to the first direction D1 and the second direction D2. For example, the third direction D3 can be a vertical direction orthogonal to the first direction D1 and the second direction D2.

[0018] In some embodiments, a lower portion of the substrate 10 can be omitted, and the fin patterns FP can be spaced apart from each other. In some embodiments, the fin patterns FP spaced apart from each other can include an insulating material.

[0019] A device isolation layer 11 can be provided on the substrate 10. The device isolation layer 11 can be provided to surround the fin pattern FP. The device isolation layer 11 can fill a space between the fin patterns FP. The device isolation layer 11 can include an insulating material. For example, the device isolation layer 11 can include an oxide material. In some embodiments, the device isolation layer 11 can be a multi-layer structure including a plurality of insulating layers.

[0020] A channel structure CH can be provided. The channel structure CH can overlap the fin pattern FP in the third direction D3. A plurality of channel structures CH overlapping one fin pattern FP in the third direction D3 can be arranged to be spaced apart from each other in the first direction D1. The channel structure CH can include semiconductor patterns SP overlapping each other in the third direction D3. The semiconductor pattern SP can include a crystalline semiconductor material. The semiconductor pattern SP can include, for example, silicon or silicon-germanium. The number of semiconductor patterns SP in the channel structure CH can not be limited to the illustrated example. In some embodiments, the channel structure CH can include two semiconductor patterns SP or four or more semiconductor patterns SP.

[0021] A source / drain pattern SD can be provided. The source / drain pattern SD can overlap the fin pattern FP in the third direction D3. A plurality of source / drain patterns SD overlapping one fin pattern FP in the third direction D3 can be arranged to be spaced apart from each other in the first direction D1. The source / drain pattern SD can be provided between the channel structures CH. The channel structure CH can be provided between the source / drain patterns SD.

[0022] The source / drain pattern SD can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. The source / drain pattern SD can be formed of, or include, silicon or silicon-germanium. The source / drain pattern SD can be doped with an impurity. In a case where the source / drain pattern SD includes silicon-germanium, the germanium concentration in the source / drain pattern SD can be uniform throughout the entire region.

[0023] A lower pattern LP can be provided. The lower pattern LP can be disposed between the fin pattern FP and the source / drain pattern SD. The lower pattern LP can overlap the fin pattern FP and the source / drain pattern SD in the third direction D3. A plurality of lower patterns LP overlapping one fin pattern FP in the third direction D3 can be arranged to be spaced apart from each other in the first direction D1. The lower pattern LP can include a semiconductor material. In some embodiments, the lower pattern LP can include an insulating material. In some embodiments, the lower pattern LP can be omitted.

[0024] A two-dimensional layer 20 can be provided. The two-dimensional layer 20 can be disposed on the fin pattern FP. A plurality of two-dimensional layers 20 overlapping one fin pattern FP in the third direction D3 can be arranged to be spaced apart from each other in the first direction D1. The two-dimensional layer 20 can be disposed between the channel structures CH. The two-dimensional layer 20 can contact the fin pattern FP, the lower pattern LP, the source / drain pattern SD, the semiconductor pattern SP, and an inner spacer IG1 to be described below. The two-dimensional layer 20 can be disposed between the lower pattern LP and the fin pattern FP. The two-dimensional layer 20 can be disposed between the semiconductor pattern SP and the source / drain pattern SD. The two-dimensional layer 20 can be disposed between the inner spacer IG1 and the source / drain pattern SD. The lower pattern LP and the source / drain pattern SD can be disposed on the two-dimensional layer 20.

[0025] The two-dimensional layer 20 can include a two-dimensional material. The two-dimensional layer 20 can include a material that electrically connects the semiconductor patterns SP and the source / drain pattern SD located on both sides of the two-dimensional layer 20 and electrically isolates the semiconductor patterns SP overlapping each other in the third direction D3. In some embodiments, the two-dimensional layer 20 can include a two-dimensional insulating material (e.g., h-BN, MnO, MoO, GaSe, GaN, or AsS).

[0026] The two-dimensional layer 20 can be a monoatomic layer or a multiatomic layer.

[0027] An inner spacer IG1 can be provided. The inner spacer IG1 can overlap the fin pattern FP and the semiconductor pattern SP in the third direction D3. The inner spacer IG1 can include inner spacers IG1 overlapping each other in the third direction D3. The semiconductor pattern SP can be disposed between the inner spacers IG1 overlapping each other in the third direction D3. The inner spacer IG1 can be in contact with the two-dimensional layer 20, the semiconductor pattern SP, and a gate insulating layer GI to be described below. The lowermost inner spacer IG1 can be in contact with the fin pattern FP. The inner spacer IG1 can be disposed between the gate insulating layer GI and the two-dimensional layer 20.

[0028] The inner spacer IG1 can include an insulating material. In some embodiments, the inner spacer IG1 can include a low-k dielectric material.

[0029] An interlayer insulating structure 40 can be provided. The interlayer insulating structure 40 can be disposed on the device isolation layer 11, the lower pattern LP, and the source / drain pattern SD. The interlayer insulating structure 40 can include an interlayer liner 41 disposed on the device isolation layer 11, the lower pattern LP, and the source / drain pattern SD, and an interlayer insulating layer 42 disposed on the interlayer liner 41. The interlayer liner 41 and the interlayer insulating layer 42 can include an insulating material. In some embodiments, the interlayer liner 41 can include a nitride material, and the interlayer insulating layer 42 can include an oxide material.

[0030] An upper channel structure UCH can be provided. The upper channel structure UCH can overlap the channel structure CH in the third direction D3. The upper channel structure UCH can include upper semiconductor patterns USP overlapping each other in the third direction D3. The upper semiconductor patterns USP can include a crystalline semiconductor material. The upper semiconductor patterns USP can include, for example, silicon or silicon-germanium. The number of the upper semiconductor patterns USP in the upper channel structure UCH can not be limited to the illustrated example.

[0031] An intermediate insulating structure 50 can be provided. The intermediate insulating structure 50 can be disposed between the upper channel structure UCH and the channel structure CH. The intermediate insulating structure 50 and the interlayer insulating structure 40 can be alternately arranged in the first direction D1.

[0032] The intermediate insulating structure 50 can include a first intermediate insulating pattern 51, a second intermediate insulating pattern 52 located on the first intermediate insulating pattern 51, and a third intermediate insulating pattern 53 located on the second intermediate insulating pattern 52. The first intermediate insulating pattern 51, the second intermediate insulating pattern 52, and the third intermediate insulating pattern 53 can include an insulating material. In some embodiments, the first intermediate insulating pattern 51, the second intermediate insulating pattern 52, and the third intermediate insulating pattern 53 can include a nitride material. In some embodiments, the intermediate insulating structure 50 can include one insulating pattern.

[0033] An upper source / drain pattern USD can be provided. The upper source / drain pattern USD can overlap with the fin pattern FP in the third direction D3. A plurality of upper source / drain patterns USD overlapping with one fin pattern FP in the third direction D3 can be arranged to be spaced apart from each other in the first direction D1. A pair of upper source / drain patterns USD can overlap with the source / drain pattern SD in the third direction D3. In some embodiments, the source / drain pattern SD can be disposed between the pair of upper source / drain patterns USD, and the source / drain pattern SD can not overlap with the pair of upper source / drain patterns USD in the third direction D3.

[0034] A pair of upper source / drain patterns USD can be disposed between upper channel structures UCH adjacent to each other in the first direction D1. A pair of upper source / drain patterns USD can be disposed between upper semiconductor patterns USP adjacent to each other in the first direction D1. The upper channel structure UCH can be disposed between the upper source / drain patterns USD.

[0035] The upper source / drain pattern USD can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. The upper source / drain pattern USD can include silicon or silicon-germanium. The upper source / drain pattern USD can be doped with an impurity. In case that the upper source / drain pattern USD includes silicon-germanium, a germanium concentration in the upper source / drain pattern USD can be uniform throughout the entire area.

[0036] An upper two-dimensional layer 30 can be provided. The upper two-dimensional layer 30 can be disposed on the interlayer insulating structure 40. The upper two-dimensional layer 30 can overlap with the fin pattern FP in the third direction D3. A plurality of upper two-dimensional layers 30 overlapping with one fin pattern FP in the third direction D3 can be arranged to be spaced apart from each other in the first direction D1. The upper two-dimensional layer 30 can overlap with the two-dimensional layer 20 in the third direction D3. The upper two-dimensional layer 30 can be disposed between the upper channel structures UCH. The upper two-dimensional layer 30 can contact the interlayer insulating structure 40, the upper source / drain pattern USD, the upper semiconductor pattern USP, an active contact AC to be described below, and an upper inner spacer IG2 to be described below. The upper two-dimensional layer 30 can be disposed between the interlayer insulating structure 40 and the upper source / drain pattern USD. The upper two-dimensional layer 30 can be disposed between the upper semiconductor pattern USP and the upper source / drain pattern USD. The upper two-dimensional layer 30 can be disposed between the upper inner spacer IG2 and the upper source / drain pattern USD.

[0037] The upper two-dimensional layer 30 can include a two-dimensional material. The upper two-dimensional layer 30 can include a material that electrically connects the upper semiconductor patterns USP and the upper source / drain patterns USD that are to be located on both sides of the upper two-dimensional layer 30 and electrically isolates the upper semiconductor patterns USP that overlap each other in the third direction D3. In some embodiments, the upper two-dimensional layer 30 can include a two-dimensional insulating material (e.g., h-BN, MnO, MoO, GaSe, GaN, or AsS). The upper two-dimensional layer 30 can be a single-atom layer or a multi-atom layer.

[0038] The two-dimensional layer 20 and the upper two-dimensional layer 30 can include the same two-dimensional material, or can include different two-dimensional materials from each other.

[0039] An upper inner spacer IG2 can be provided. The upper inner spacer IG2 can overlap the fin pattern FP and the upper semiconductor pattern USP in the third direction D3. The upper inner spacer IG2 can include upper inner spacers IG2 that overlap each other in the third direction D3. The upper semiconductor pattern USP can be disposed between the upper inner spacers IG2 that overlap each other in the third direction D3. The upper inner spacer IG2 can be in contact with the upper two-dimensional layer 30, the upper semiconductor pattern USP, and the gate insulating layer GI. The lowermost upper inner spacer IG2 can be in contact with the intermediate insulating structure 50. The upper inner spacer IG2 can be disposed between the gate insulating layer GI and the upper two-dimensional layer 30.

[0040] The upper inner spacer IG2 can include an insulating material. In some embodiments, the upper inner spacer IG2 can include a low-k dielectric material.

[0041] A gate electrode GE can be provided to extend in the second direction D2. The gate electrode GE can be disposed to cross the channel structure CH and the upper channel structure UCH. The gate electrode GE can overlap the channel structure CH and the upper channel structure UCH in the third direction D3. The gate electrode GE can be arranged to be spaced apart from each other in the first direction D1. The source / drain pattern SD can be disposed between the gate electrode GE. The upper source / drain pattern USD can be disposed between the gate electrode GE.

[0042] The gate electrode GE can include a first electrode portion IN1 and a second electrode portion IN2. The first electrode portion IN1 can be disposed between the semiconductor patterns SP, between the semiconductor patterns SP and the fin pattern FP, or between the semiconductor patterns SP and the intermediate insulating structure 50. The second electrode portion IN2 can be disposed between the upper semiconductor patterns USP, or between the upper semiconductor patterns USP and the intermediate insulating structure 50. The inner spacer IG1 can be disposed between the first electrode portion IN1 and the two-dimensional layer 20. The upper inner spacer IG2 can be disposed between the second electrode portion IN2 and the upper two-dimensional layer 30.

[0043] The gate electrode GE can comprise an electrically conductive material. The gate electrode GE can be disposed to surround the semiconductor pattern SP and the upper semiconductor pattern USP (e.g., as viewed in a cross-sectional view of FIG. 1E The gate electrode GE, the semiconductor pattern SP, and the upper semiconductor pattern USP can constitute a three-dimensional field effect transistor (e.g., a MBCFET or a GAAFET).

[0044] A gate insulating layer GI can be provided. The gate insulating layer GI can be in contact with the gate electrode GE. The gate insulating layer GI can separate the gate electrode GE from the semiconductor pattern SP and the upper semiconductor pattern USP. The gate insulating layer GI can be disposed to surround the semiconductor pattern SP, the upper semiconductor pattern USP, and the intermediate insulating structure 50 (e.g., as viewed in a cross-sectional view of FIG. 1E The gate insulating layer GI can be in contact with the inner spacers GI1 and the upper inner spacers IG2. The gate insulating layer GI can comprise an insulating material. In some embodiments, the gate insulating layer GI can comprise an oxide material.

[0045] A gate spacer GS can be provided. A pair of gate spacers GS can be disposed on both sides of the gate electrode GE. The gate spacer GS can extend in the second direction D2. The gate spacer GS can comprise an insulating material.

[0046] A gate cap pattern GP can be provided. The gate cap pattern GP can be disposed on the gate electrode GE. The gate cap pattern GP can extend in the second direction D2. The gate cap pattern GP can be disposed between the gate spacers GS. The gate cap pattern GP can comprise an insulating material.

[0047] A cap liner 70 can be provided. The cap liner 70 can be disposed on the gate spacer GS and the upper source / drain pattern USD. The cap liner 70 can comprise an insulating material.

[0048] A cap insulating layer 60 can be disposed on the cap liner 70. The cap insulating layer 60 can comprise an insulating material.

[0049] An active contact AC can be provided. The active contact AC can be electrically connected to two upper source / drain patterns USD and one source / drain pattern SD. The active contact AC can be in contact with the two upper source / drain patterns USD and the one source / drain pattern SD. The active contact AC can be disposed to penetrate the cap insulating layer 60, the cap liner 70, and the interlayer insulating structure 40. The active contact AC can comprise an electrically conductive material.

[0050] A gate contact can be provided. The gate contact can be electrically connected to the gate electrode GE. The gate contact can comprise an electrically conductive material.

[0051] A gate separation layer 65 can be provided. The gate separation layer 65 can be provided on the device isolation layer 11. A gate electrode GE can be provided between the gate separation layers 65. The gate electrodes GE can be spaced apart from each other by the gate separation layers 65. The gate separation layer 65 can include an insulating material.

[0052] Referring to FIG. 1F The semiconductor pattern SP can include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 that overlap each other in the third direction D3, and a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 that overlap each other in the third direction D3. The second semiconductor pattern SP2 and the fourth semiconductor pattern SP4 can be provided at a higher height (e.g., a vertical height from a top surface of the substrate 10) than the first semiconductor pattern SP1 and the third semiconductor pattern SP3. The first semiconductor pattern SP1 and the third semiconductor pattern SP3 can be adjacent to each other in the first direction D1. The second semiconductor pattern SP2 and the fourth semiconductor pattern SP4 can be adjacent to each other in the first direction D1.

[0053] The first electrode portion IN1 can be provided between the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The inner spacer IG1 can include a first inner spacer IG1a provided between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a second inner spacer IG1b provided between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4.

[0054] The first inner spacer IG1a can be in contact with a top surface SP1_U of the first semiconductor pattern SP1 and a bottom surface SP2_L of the second semiconductor pattern SP2. A top surface of the first inner spacer IG1a can be in contact with the bottom surface SP2_L of the second semiconductor pattern SP2. A bottom surface of the first inner spacer IG1a can be in contact with the top surface SP1_U of the first semiconductor pattern SP1.

[0055] The second inner spacer IG1b can be in contact with a top surface of the third semiconductor pattern SP3 and a bottom surface of the fourth semiconductor pattern SP4. A top surface of the second inner spacer IG1b can be in contact with the bottom surface of the fourth semiconductor pattern SP4. A bottom surface of the second inner spacer IG1b can be in contact with the top surface of the third semiconductor pattern SP3.

[0056] The two-dimensional layer 20 can include a first two-dimensional layer 21 located between the first semiconductor pattern SP1 and the third semiconductor pattern SP3, and located between the second semiconductor pattern SP2 and the fourth semiconductor pattern SP4. The first two-dimensional layer 21 can include a first portion 21a in contact with the first semiconductor pattern SP1, the first inner spacer IG1a, and the second semiconductor pattern SP2, and a second portion 21b in contact with the third semiconductor pattern SP3, the second inner spacer IG1b, and the fourth semiconductor pattern SP4.

[0057] The outer side surface 21a_S1 of the first portion 21a of the first two-dimensional layer 21 can include a first portion P1 in contact with the side surface SP1_S of the first semiconductor pattern SP1, a second portion P2 in contact with the side surface SP2_S of the second semiconductor pattern SP2, and a third portion P3 in contact with the first side surface IG1a_S1 of the first inner spacer IG1a.

[0058] The inner side surface 21a_S2 of the first portion 21a of the first two-dimensional layer 21 can be in contact with the side surface SD_S of the source / drain pattern SD. The side surface SD_S of the source / drain pattern SD can be flat.

[0059] The first portion P1, the second portion P2, and the third portion P3 of the outer side surface 21a_S1 of the first portion 21a of the first two-dimensional layer 21 can be located on a straight line extending in the third direction D3. The first portion P1, the second portion P2, and the third portion P3 of the outer side surface 21a_S1 of the first portion 21a of the first two-dimensional layer 21 can overlap each other in the third direction D3. The first portion P1, the second portion P2, and the third portion P3 of the outer side surface 21a_S1 of the first portion 21a of the first two-dimensional layer 21 can be coplanar with each other. The first portion P1, the second portion P2, and the third portion P3 of the outer side surface 21a_S1 of the first portion 21a of the first two-dimensional layer 21 can be flat.

[0060] A thickness of the first portion 21a of the first two-dimensional layer 21 in the first direction D1 can be constant. In some embodiments, the thickness of the first portion 21a of the first two-dimensional layer 21 in the first direction D1 can be less than or equal to 9 Å. A distance between the inner side surface 21a_S2 and the outer side surface 21a_S1 of the first portion 21a of the first two-dimensional layer 21 in the first direction D1 can be constant. The inner side surface 21a_S2 and the outer side surface 21a_S1 of the first portion 21a of the first two-dimensional layer 21 can be flat.

[0061] The side surface SP1_S of the first semiconductor pattern SP1, the side surface SP2_S of the second semiconductor pattern SP2, and the first side surface IG1a_S1 of the first inner spacer IG1a can be located on a straight line extending in the third direction D3. The side surface SP1_S of the first semiconductor pattern SP1, the side surface SP2_S of the second semiconductor pattern SP2, and the first side surface IG1a_S1 of the first inner spacer IG1a can overlap each other in the third direction D3. The side surface SP1_S of the first semiconductor pattern SP1, the side surface SP2_S of the second semiconductor pattern SP2, and the first side surface IG1a_S1 of the first inner spacer IG1a can be coplanar with each other. The side surface SP1_S of the first semiconductor pattern SP1, the side surface SP2_S of the second semiconductor pattern SP2, and the first side surface IG1a_S1 of the first inner spacer IG1a can be flat.

[0062] The first inner spacer IG1a can include a second side surface IG1a_S2 opposite the first side surface IG1a_S1 of the first inner spacer IG1a. The second side surface IG1a_S2 of the first inner spacer IG1a can be curved (e.g., include a curved shape). The second side surface IG1a_S2 of the first inner spacer IG1a can be in contact with the gate insulating layer GI. The gate insulating layer GI can be disposed between the second side surface IG1a_S2 of the first inner spacer IG1a and the first electrode portion IN1.

[0063] Since the second side surface IG1a_S2 of the first inner spacer IG1a is curved and the first side surface IG1a_S1 of the first inner spacer IG1a is flat, an area of the first side surface IG1a_S1 of the first inner spacer IG1a can be smaller than an area of the second side surface IG1a_S2 of the first inner spacer IG1a. A length of the first side surface IG1a_S1 of the first inner spacer IG1a in the second direction D2 can be equal to a length of the second side surface IG1a_S2 of the first inner spacer IG1a in the second direction D2.

[0064] The upper semiconductor patterns USP can include a first upper semiconductor pattern USP1 and a second upper semiconductor pattern USP2 that overlap each other in the third direction D3, and a third upper semiconductor pattern USP3 and a fourth upper semiconductor pattern USP4 that overlap each other in the third direction D3. The second upper semiconductor pattern USP2 and the fourth upper semiconductor pattern USP4 can be located at a higher height than the first upper semiconductor pattern USP1 and the third upper semiconductor pattern USP3. The first upper semiconductor pattern USP1 and the third upper semiconductor pattern USP3 can be adjacent to each other in the first direction D1. The second upper semiconductor pattern USP2 and the fourth upper semiconductor pattern USP4 can be adjacent to each other in the first direction D1. The first upper semiconductor pattern USP1 and the second upper semiconductor pattern USP2 can overlap the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the third direction D3. The third upper semiconductor pattern USP3 and the fourth upper semiconductor pattern USP4 can overlap the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 in the third direction D3.

[0065] The second electrode portion IN2 can be disposed between the first upper semiconductor pattern USP1 and the second upper semiconductor pattern USP2. The upper inner spacer IG2 can be disposed between the first upper semiconductor pattern USP1 and the second upper semiconductor pattern USP2.

[0066] The upper two-dimensional layer 30 can include a first upper two-dimensional layer 31 located between the first upper semiconductor pattern USP1 and the third upper semiconductor pattern USP3, and located between the second upper semiconductor pattern USP2 and the fourth upper semiconductor pattern USP4. The first upper two-dimensional layer 31 can include a first portion 31a in contact with the first upper semiconductor pattern USP1, the upper inner spacer IG2, and the second upper semiconductor pattern USP2, and a second portion 31b in contact with the third upper semiconductor pattern USP3, the upper inner spacer IG2, and the fourth upper semiconductor pattern USP4.

[0067] The first active contact AC1 can be disposed between the first portion 31a and the second portion 31b of the first upper two-dimensional layer 31. The upper source / drain pattern USD can include a first upper source / drain pattern USD1 disposed between the first portion 31a of the first upper two-dimensional layer 31 and the first active contact AC1, and a second upper source / drain pattern USD2 disposed between the second portion 31b of the first upper two-dimensional layer 31 and the first active contact AC1.

[0068] The first active contact AC1 can include first and second side surfaces AC1_S1 and AC1_S2 opposite to each other. The first side surface AC1_S1 of the first active contact AC1 can be in contact with a side surface USD1_S of the first upper source / drain pattern USD1 and a surface 31a_S of the first portion 31a of the first upper two-dimensional layer 31. The second side surface AC1_S2 of the first active contact AC1 can be in contact with a side surface USD2_S of the second upper source / drain pattern USD2 and a surface 31b_S of the second portion 31b of the first upper two-dimensional layer 31. The first active contact AC1 can be disposed to penetrate the first upper two-dimensional layer 31. In some embodiments, the first and second portions 31a and 31b of the first upper two-dimensional layer 31 can be separated from each other by the first active contact AC1.

[0069] The side surface USD1_S of the first upper source / drain pattern USD1 and the surface 31a_S of the first portion 31a of the first upper two-dimensional layer 31 can be coplanar with each other. The side surface USD2_S of the second upper source / drain pattern USD2 and the surface 31b_S of the second portion 31b of the first upper two-dimensional layer 31 can be coplanar with each other.

[0070] A distance between the first and second portions 31a and 31b of the first upper two-dimensional layer 31 in the first direction D1 can be greater than a distance between the first and second portions 21a and 21b of the first two-dimensional layer 21 in the first direction D1.

[0071] A portion of the first upper source / drain pattern USD1 and a portion of the second upper source / drain pattern USD2 can overlap with the source / drain pattern SD in the third direction D3. In some embodiments, the first and second upper source / drain patterns USD1 and USD2 can not overlap with a portion of the source / drain pattern SD between the first and second upper source / drain patterns USD1 and USD2 in the third direction D3.

[0072] A side surface of the first upper semiconductor pattern USP1, a side surface of the second upper semiconductor pattern USP2, and a first side surface IG2_S1 of the upper inner spacer IG2 can be coplanar with each other. The side surface of the first upper semiconductor pattern USP1, the side surface of the second upper semiconductor pattern USP2, and the first side surface IG2_S1 of the upper inner spacer IG2 can be flat.

[0073] The upper inner spacer IG2 can include a second side surface IG2_S2 opposite the first side surface IG2_S1 of the upper inner spacer IG2. The second side surface IG2_S2 of the upper inner spacer IG2 can be curved. The second side surface IG2_S2 of the upper inner spacer IG2 can be in contact with the gate insulating layer GI. The gate insulating layer GI can be disposed between the second side surface IG2_S2 of the upper inner spacer IG2 and the second electrode portion IN2.

[0074] Since the second side surface IG2_S2 of the upper inner spacer IG2 is curved and the first side surface IG2_S1 of the upper inner spacer IG2 is flat, an area of the second side surface IG2_S2 of the upper inner spacer IG2 can be greater than an area of the first side surface IG2_S1 of the upper inner spacer IG2.

[0075] In some embodiments, since the semiconductor device includes the two-dimensional layer 20 and the upper two-dimensional layer 30, the inner spacer IG1 and the upper inner spacer IG2 can have flat side surfaces. Accordingly, the inner spacer IG1 and the upper inner spacer IG2 including the low-k dielectric material can be disposed to have a relatively large width, and thus, a capacitance between the gate electrode GE and the source / drain pattern SD, and between the gate electrode GE and the upper source / drain pattern USD can be reduced.

[0076] In the semiconductor device according to some embodiments, since the side surface of each of the inner spacer IG1 and the upper inner spacer IG2 has a relatively small area and a flat shape, a capacitance can be reduced.

[0077] In the semiconductor device according to some embodiments, since the two-dimensional layer 20 and the upper two-dimensional layer 30 are provided, it can not be necessary to provide a plurality of layers having different germanium concentrations in each of the source / drain pattern SD and the upper source / drain pattern USD. Accordingly, each of the source / drain pattern SD and the upper source / drain pattern USD can have a uniform germanium concentration throughout an entire area, and thus, a performance of the semiconductor device can be improved.

[0078] In the semiconductor device according to some embodiments, the germanium concentration in the source / drain pattern SD and the upper source / drain pattern USD can be relatively high, and this can increase a stress applied to the semiconductor pattern SP and the upper semiconductor pattern USP, thereby improving a mobility of electrons.

[0079] FIG. 2A 、 FIG. 2B 、 FIG. 2C 、 FIG. 3A 、 FIG. 3B 、 FIG. 4A 、 FIG. 4B 、FIG. 5A , FIG. 5B , FIG. 6A , FIG. 6B , FIG. 7A , FIG. 7B , FIG. 8A , FIG. 8B , FIG. 9A , FIG. 9B , FIG. 10A , FIG. 11A , FIG. 11B , FIG. 12A , FIG. 13A , FIG. 13B , FIG. 14A , FIG. 14B , FIG. 15A , FIG. 15B , FIG. 16 , FIG. 17 , FIG. 18A , FIG. 19A , FIG. 20A , FIG. 20B , FIG. 21A , FIG. 21B , FIGS. 1A-1E , FIG. 22 , FIG. 22 and FIGS. 1A-1F It shows the manufacturing process. FIG. 22 A diagram illustrating an example of a method for developing semiconductor devices.

[0080] refer to ​ , ​ and ​ A substrate 10 can be provided. A fin pattern FP, a first sacrificial layer 111, a first semiconductor layer 121, a first interlayer pattern 131, a second interlayer pattern 132, a third interlayer pattern 133, a second sacrificial layer 112, a second semiconductor layer 122, a third sacrificial layer 113, a sacrificial insulating layer 114, a sacrificial pattern 115, and a mask pattern 116 can be formed thereon.

[0081] In some embodiments, the fin pattern FP, the first sacrificial layer 111, the first semiconductor layer 121, the first interlayer pattern 131, the second interlayer pattern 132, the third interlayer pattern 133, the second sacrificial layer 112, the second semiconductor layer 122, the third sacrificial layer 113, the sacrificial insulating layer 114, and the sacrificial pattern 115 can be formed by an etching process that uses the mask pattern 116 as an etching mask.

[0082] The first sacrificial layer 111, the second sacrificial layer 112, and the third sacrificial layer 113 may include a first semiconductor material. The first semiconductor layer 121, the second semiconductor layer 122, and the second interlayer pattern 132 may include a second semiconductor material. The first interlayer pattern 131 and the third interlayer pattern 133 may include a third semiconductor material.

[0083] The first semiconductor material can have an etching selectivity with respect to the second semiconductor material and the third semiconductor material. The second semiconductor material can have an etching selectivity with respect to the third semiconductor material. In some embodiments, the second semiconductor material can include silicon, the first semiconductor material and the third semiconductor material can include silicon-germanium, and a germanium concentration of the first semiconductor material can be lower than a germanium concentration of the third semiconductor material.

[0084] The sacrificial insulating layer 114 and the mask pattern 116 can include an insulating material. The sacrificial pattern 115 can include, for example, polysilicon. The device isolation layer 11 can be formed.

[0085] Referring to ​ and ​ The first interlayer pattern 131 and the third interlayer pattern 133 can be selectively removed.

[0086] Referring to ​ and ​ The first preliminary insulating layer 141 can be formed. The first preliminary insulating layer 141 can be formed by, for example, a deposition process. The first preliminary insulating layer 141 can cover the first sacrificial layer 111, the first semiconductor layer 121, the second interlayer pattern 132, the second sacrificial layer 112, the second semiconductor layer 122, the third sacrificial layer 113, the sacrificial insulating layer 114, the sacrificial pattern 115, and the mask pattern 116. The first preliminary insulating layer 141 can fill empty spaces formed by removing the first interlayer pattern 131 and the third interlayer pattern 133. The first preliminary insulating layer 141 can include an insulating material. In some embodiments, the first preliminary insulating layer 141 can be formed of, or include, nitride.

[0087] Referring to ​ and ​ The first preliminary insulating layer 141, the second semiconductor layer 122, and the second sacrificial layer 112 can be etched. For example, the first preliminary insulating layer 141, the second semiconductor layer 122, and the second sacrificial layer 112 can be etched by an anisotropic etching process.

[0088] An upper semiconductor pattern USP can be formed by etching the second semiconductor layer 122. The second semiconductor layer 122 can be divided into the upper semiconductor pattern USP.

[0089] A first trench TR1 can be formed due to etching of the second semiconductor layer 122 and the second sacrificial layer 112. The first trench TR1 can be an empty space between the upper semiconductor pattern USP and between the second sacrificial layer 112.

[0090] Referring to ​ and ​A second preliminary insulating layer 142 can be formed. The second preliminary insulating layer 142 can include an insulating material. In some embodiments, the second preliminary insulating layer 142 can be formed of, or include, nitride. A portion of the second preliminary insulating layer 142 can be disposed in the first trench TR1. The second preliminary insulating layer 142 can cover the first preliminary insulating layer 141, the upper semiconductor pattern USP, and the second sacrificial layer 112.

[0091] The second preliminary insulating layer 142, the first preliminary insulating layer 141, and the second interlayer pattern 132 can be etched through the first trench TR1. In some embodiments, the second preliminary insulating layer 142, the first preliminary insulating layer 141, and the second interlayer pattern 132 can be etched through an anisotropic etching process. The first trench TR1 can be enlarged due to the etching of the second preliminary insulating layer 142, the first preliminary insulating layer 141, and the second interlayer pattern 132.

[0092] The second interlayer pattern 132 can be exposed through the first trench TR1 due to the etching of the first preliminary insulating layer 141.

[0093] Referring to ​ and ​ The second interlayer pattern 132 exposed through the first trench TR1 can be removed. A hollow space formed by the removal of the second interlayer pattern 132 can be defined as a first cavity CA1. The first cavity CA1 can be disposed between the first sacrificial layer 111 and the second sacrificial layer 112. The first cavity CA1 can be disposed between the first semiconductor layer 121 and the upper semiconductor pattern USP. The first cavity CA1 can be connected to the first trench TR1. The first trench TR1 can be enlarged due to the removal of the second interlayer pattern 132.

[0094] Referring to ​ and ​ The first preliminary insulating layer 141, the first sacrificial layer 111, the first semiconductor layer 121, and the fin pattern FP can be etched through the first trench TR1. For example, the first preliminary insulating layer 141, the first sacrificial layer 111, the first semiconductor layer 121, and the fin pattern FP can be formed through an anisotropic etching process.

[0095] The semiconductor pattern SP can be formed due to the etching of the first semiconductor layer 121. For example, the first semiconductor layer 121 can be divided into semiconductor patterns SP separated from each other.

[0096] The second trench TR2 can be formed due to the etching of the first semiconductor layer 121 and the first sacrificial layer 111. The second trench TR2 can be a hollow space between the semiconductor patterns SP and between the first sacrificial layers 111. The second trench TR2 can be connected to the first trench TR1. The second trench TR2 can overlap the first trench TR1 in the third direction D3.

[0097] A first intermediate insulating pattern 51 and a third intermediate insulating pattern 53 can be defined. The first intermediate insulating pattern 51 and the third intermediate insulating pattern 53 can be portions of the first preliminary insulating layer 141 that are separated from each other.

[0098] A third preliminary insulating layer 143 can be formed. The third preliminary insulating layer 143 can include an insulating material. In some embodiments, the third preliminary insulating layer 143 can include a nitride material. The third preliminary insulating layer 143 can cover the second preliminary insulating layer 142, the first sacrificial layer 111, the semiconductor pattern SP, the fin pattern FP, the first intermediate insulating pattern 51, and the third intermediate insulating pattern 53.

[0099] The third preliminary insulating layer 143 can fill the first cavity CA1. The third preliminary insulating layer 143 can include a portion located in the first trench TR1 and a portion located in the second trench TR2.

[0100] Referring to ​ and ​ The third preliminary insulating layer 143 can be etched. In some embodiments, the etching of the third preliminary insulating layer 143 can be performed to expose the fin pattern FP, the first sacrificial layer 111, the semiconductor pattern SP, the first intermediate insulating pattern 51, the third intermediate insulating pattern 53, and the second preliminary insulating layer 142.

[0101] A second intermediate insulating pattern 52 can be defined. The second intermediate insulating pattern 52 can be a portion of the third preliminary insulating layer 143 that remains in the first cavity CA1.

[0102] Referring to ​ and 10B A first preliminary two-dimensional layer p20 can be formed. For example, the first preliminary two-dimensional layer p20 can be formed by an atomic layer deposition (ALD) process. The first preliminary two-dimensional layer p20 can include a two-dimensional material.

[0103] The first preliminary two-dimensional layer p20 can include a portion formed in the first trench TR1 and a portion formed in the second trench TR2. The first preliminary two-dimensional layer p20 can be formed on the fin pattern FP, the first sacrificial layer 111, the semiconductor pattern SP, the first intermediate insulating pattern 51, the second intermediate insulating pattern 52, and the third intermediate insulating pattern 53, and the second preliminary insulating layer 142.

[0104] Referring to ​ and ​ A lower pattern LP and a source / drain pattern SD can be formed. For example, the lower pattern LP and the source / drain pattern SD can be formed by an epitaxial growth process using the semiconductor pattern SP and the first sacrificial layer 111 as seed layers.

[0105] In some embodiments, the first preliminary two-dimensional layer p20 can have a relatively small thickness, and in this case, the lower pattern LP and the source / drain pattern SD can be formed by a remote epitaxial growth process in which the semiconductor pattern SP and the first sacrificial layer 111 are used as seed layers. In some embodiments, the thickness of the first preliminary two-dimensional layer p20 can be less than or equal to 9 A.

[0106] The lower pattern LP and the source / drain pattern SD can fill the second trench TR2.

[0107] Referring to ​ and 12B The first preliminary two-dimensional layer p20 can be etched. In some embodiments, the first preliminary two-dimensional layer p20 can be etched by a selective etching process. Due to the etching of the first preliminary two-dimensional layer p20, a two-dimensional layer 20 can be formed. The portion of the first preliminary two-dimensional layer p20 remaining in the second trench TR2 can be defined as the two-dimensional layer 20.

[0108] Referring to ​ and ​ An interlayer insulating structure 40 can be formed. The formation of the interlayer insulating structure 40 can include forming an interlayer liner 41 on the device isolation layer 11, the lower pattern LP, and the source / drain pattern SD, and forming an interlayer insulating layer 42 on the interlayer liner 41.

[0109] Referring to ​ and ​ The second preliminary insulating layer 142 can be removed. For example, the second preliminary insulating layer 142 can be removed to expose the second sacrificial layer 112, the upper semiconductor pattern USP, and the first preliminary insulating layer 141.

[0110] A second preliminary two-dimensional layer p30 can be formed. The second preliminary two-dimensional layer p30 can be formed by, for example, an ALD process. The second preliminary two-dimensional layer p30 can include a two-dimensional material.

[0111] The second preliminary two-dimensional layer p30 can include a portion formed in the first trench TR1. The second preliminary two-dimensional layer p30 can be formed on the second sacrificial layer 112, the upper semiconductor pattern USP, the interlayer insulating layer 42, and the first preliminary insulating layer 141.

[0112] Referring to ​ and ​A sacrificial spacer 151 can be formed. The formation of the sacrificial spacer 151 can include forming a preliminary spacer layer on the second preliminary two-dimensional layer p30, and etching the preliminary spacer layer to form the sacrificial spacer 151. In some embodiments, the second preliminary two-dimensional layer p30 can be etched in the step of etching the preliminary spacer layer, and can be divided into a plurality of second preliminary two-dimensional layers p30.

[0113] The sacrificial spacer 151 can include a material having etch selectivity with respect to the second preliminary two-dimensional layer p30. In some embodiments, the sacrificial spacer 151 can include molybdenum (Mo).

[0114] The sacrificial spacer 151 can be disposed on the second preliminary two-dimensional layer p30. In the first trench TR1, two sacrificial spacers 151 can be spaced apart from each other in the first direction D1.

[0115] Referring to ​ A fill pattern 152 can be formed. The fill pattern 152 can be disposed between a pair of sacrificial spacers 151. The fill pattern 152 can fill the first trench TR1. The fill pattern 152 can be disposed on the second preliminary two-dimensional layer p30.

[0116] The fill pattern 152 can include a material having etch selectivity with respect to the sacrificial spacer 151 and the second preliminary two-dimensional layer p30. In some embodiments, the fill pattern 152 can include LaO.

[0117] Referring to ​ The fill pattern 152 can be etched. The fill pattern 152 can be etched by a selective etching process.

[0118] Referring to ​ And 18B The sacrificial spacer 151 can be removed. The sacrificial spacer 151 can be removed by a selective etching process. Due to the removal of the sacrificial spacer 151, a second cavity CA2 can be formed between the fill pattern 152 and the second preliminary two-dimensional layer p30. The second cavity CA2 can be an empty space between the fill pattern 152 and the second preliminary two-dimensional layer p30.

[0119] Referring to ​ And 19B An upper source / drain pattern USD can be formed. For example, the upper source / drain pattern USD can be formed by an epitaxial growth process using the upper semiconductor pattern USP and the second sacrificial layer 112 as a seed layer.

[0120] In some embodiments, the second preliminary two-dimensional layer p30 can have a relatively small thickness, and in this case, the upper source / drain pattern USD can be formed by a remote epitaxial growth process in which the upper semiconductor pattern USP and the second sacrificial layer 112 are used as seed layers. In this case, the thickness of the second preliminary two-dimensional layer p30 can be less than or equal to 9 Å.

[0121] The upper source / drain pattern USD can fill the second cavity CA2.

[0122] Referring to ​ and ​ The second preliminary two-dimensional layer p30 can be etched. In some embodiments, the second preliminary two-dimensional layer p30 can be etched by a selective etching process. Due to the etching of the second preliminary two-dimensional layer p30, the upper two-dimensional layer 30 can be formed.

[0123] Referring to ​ and ​ The cover pad 70 can be formed. The cover pad 70 can cover the upper source / drain pattern USD, the first preliminary insulating layer 141, the fill pattern 152, and the interlayer insulating layer 42.

[0124] Referring to ​ The preliminary cover insulating layer can be formed on the cover pad 70. The cover pad 70 and the first preliminary insulating layer 141 can be etched. In some embodiments, due to the etching of the first preliminary insulating layer 141, the first preliminary insulating layer 141 can be divided into gate spacers GS.

[0125] In some embodiments, the etching of the first preliminary insulating layer 141 can be performed to expose the mask pattern 116. The mask pattern 116, the sacrificial pattern 115, the sacrificial insulating layer 114, the third sacrificial layer 113, the second sacrificial layer 112, and the first sacrificial layer 111 can be removed. The third sacrificial layer 113, the second sacrificial layer 112, and the first sacrificial layer 111 can be removed by, for example, an etchant containing fluorine.

[0126] The inner spacer IG1, the upper inner spacer IG2, the gate insulating layer GI, the gate electrode GE, and the gate cover pattern GP can be formed. The inner spacer IG1, the upper inner spacer IG2, the gate insulating layer GI, the gate electrode GE, and the gate cover pattern GP can be formed in the empty space formed by removing the sacrificial pattern 115, the sacrificial insulating layer 114, the third sacrificial layer 113, the second sacrificial layer 112, and the first sacrificial layer 111. In some embodiments, the inner spacer IG1 and the upper inner spacer IG2 can be formed simultaneously.

[0127] The inner spacers IG1 can be formed on a surface of the two-dimensional layer 20 exposed by removing the first sacrificial layer 111. The upper inner spacers IG2 can be formed on a surface of the upper two-dimensional layer 30 exposed by removing the second sacrificial layer 112. The gate separation layer 65 can be formed.

[0128] The active contacts AC can be formed. In some embodiments, the formation of the active contacts AC can include etching the preliminary cover insulating layer, the cover liner 70, and the fill pattern 152; forming the cover insulating layer 60 in a hollow space formed by etching the preliminary cover insulating layer, the cover liner 70, and the fill pattern 152; etching the cover insulating layer 60 and the interlayer insulating structure 40; and forming the active contacts AC in a hollow space formed by etching the cover insulating layer 60 and the interlayer insulating structure 40.

[0129] In the method of manufacturing a semiconductor device according to some embodiments, the two-dimensional layer 20 and the upper two-dimensional layer 30 can have a relatively high etching selectivity with respect to an etchant for a process for removing the first sacrificial layer 111 and the second sacrificial layer 112. Thus, even when the two-dimensional layer 20 and the upper two-dimensional layer 30 are relatively thin, the two-dimensional layer 20 and the upper two-dimensional layer 30 can effectively protect the source / drain pattern SD and the upper source / drain pattern USD.

[0130] In the method of manufacturing a semiconductor device according to some embodiments, since the inner spacers IG1 and the upper inner spacers IG2 are formed on the two-dimensional layer 20 and the upper two-dimensional layer 30 having flat side surfaces, the inner spacers IG1 and the upper inner spacers IG2 can also have flat side surfaces.

[0131] ​ is a cross-sectional view illustrating an example of a semiconductor device. In addition to the features to be described below, ​ The semiconductor device of ​ The semiconductor device of

[0132] Referring to ​ A substrate 210 including a fin pattern FPa, a channel structure CHa including a semiconductor pattern SPa, a two-dimensional layer 220, a source / drain pattern SDa, an inner spacer IGa, a gate insulating layer GIa, a gate electrode GEa, a gate spacer GSa, and a gate cover pattern GPa can be provided.

[0133] A cover insulating layer 260 can be disposed on the two-dimensional layer 220 and the source / drain pattern SDa. An active contact ACa can be provided to penetrate the cover insulating layer 260. The active contact ACa can be electrically connected to the source / drain pattern SDa.

[0134] In the semiconductor device according to some embodiments, the inner spacer can have a relatively large width, and thus can reduce capacitance.

[0135] In the semiconductor device according to some embodiments, the inner spacer can have a flat side surface, and can be such that capacitance is reduced.

[0136] In the semiconductor device according to some embodiments, the germanium concentration in the source / drain pattern can be uniform throughout the entire region, and can improve the performance of the semiconductor device.

[0137] In the semiconductor device according to some embodiments, the germanium concentration in the source / drain pattern can be relatively high, and can improve the electron mobility of the semiconductor pattern.

[0138] Although this specification contains many specifics, these should not be construed as limiting the scope of any invention or the scope of what can be claimed, but as describing a particular implementation of features that can be used in a specific implementation of the inventions. The features described in this specification in separate embodiments contexts can also be implemented in combination. Conversely, various features described in the context of a single embodiment also can be implemented separately or in any suitable subcombination. Moreover, although features can be described above as acting in particular combinations, one or more features from a combination can in some cases be excised from the combination and the combination can be directed to a subcombination or variation of a subcombination.

[0139] While example embodiments of the present disclosure have been shown and described, it will be understood by those of ordinary skill in the art that changes can be made in form and details without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device comprising: a first semiconductor pattern and a second semiconductor pattern; a gate electrode including an electrode portion between the first semiconductor pattern and the second semiconductor pattern; an inner spacer contacting a top surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern; a two-dimensional layer contacting the first semiconductor pattern, the second semiconductor pattern, and the inner spacer; and a source / drain pattern on the two-dimensional layer. the two-dimensional layer contacts a side surface of the first semiconductor pattern, a side surface of the second semiconductor pattern, and a first side surface of the inner spacer, and 2. The semiconductor device of claim 1, wherein, wherein the side surface of the first semiconductor pattern, the side surface of the second semiconductor pattern, and the first side surface of the inner spacer are flat. the side surface of the first semiconductor pattern, the side surface of the second semiconductor pattern, and the first side surface of the inner spacer are coplanar with each other.

3. The semiconductor device of claim 2, wherein, the inner spacer includes a second side surface opposite to the first side surface of the inner spacer, and 4. The semiconductor device of claim 2, wherein, wherein the second side surface of the inner spacer includes a curved shape.

5. The semiconductor device of claim 1, further comprising: a first upper semiconductor pattern and a second upper semiconductor pattern overlapping the first semiconductor pattern and the second semiconductor pattern; an upper two-dimensional layer contacting the first upper semiconductor pattern and the second upper semiconductor pattern; and an upper source / drain pattern on the upper two-dimensional layer, wherein the upper two-dimensional layer overlaps the two-dimensional layer.

6. The semiconductor device of claim 5, further comprising an active contact electrically connected to the upper source / drain pattern and the source / drain pattern, a side surface of the active contact contacts a side surface of the upper source / drain pattern. the two-dimensional layer includes a two-dimensional insulating material. wherein the source / drain pattern includes a side surface contacting the two-dimensional layer, and 7. The semiconductor device of claim 1, wherein, wherein the side surface of the source / drain pattern is flat.

8. The semiconductor device of claim 1, wherein, 9. A semiconductor device comprising: a first semiconductor pattern and a second semiconductor pattern; a gate electrode including an electrode portion between the first semiconductor pattern and the second semiconductor pattern; a two-dimensional layer contacting the first semiconductor pattern and the second semiconductor pattern; an inner spacer between the two-dimensional layer and the electrode portion; and a source / drain pattern on the two-dimensional layer, wherein the inner spacer includes a first side surface contacting the two-dimensional layer and a second side surface opposite to the first side surface, and wherein an area of the first side surface of the inner spacer is smaller than an area of the second side surface of the inner spacer. the first side surface of the inner spacer is flat, and ​ ​ 10. The semiconductor device of claim 9, wherein, ​ The second side surface of the inner spacer includes a curved shape.

11. The semiconductor device of claim 9, wherein, The two-dimensional layer has a thickness less than or equal to 9 A.

12. The semiconductor device of claim 9, further comprising: a first upper semiconductor pattern and a second upper semiconductor pattern, the first upper semiconductor pattern and the second upper semiconductor pattern overlapping the first semiconductor pattern and the second semiconductor pattern; and an upper two-dimensional layer, the upper two-dimensional layer contacting the first upper semiconductor pattern and the second upper semiconductor pattern, wherein the upper two-dimensional layer overlaps the two-dimensional layer.

13. The semiconductor device of claim 12, further comprising: a third semiconductor pattern spaced apart from the first semiconductor pattern in a first direction; a fourth semiconductor pattern spaced apart from the second semiconductor pattern in the first direction; a third upper semiconductor pattern spaced apart from the first upper semiconductor pattern in the first direction; and a fourth upper semiconductor pattern spaced apart from the second upper semiconductor pattern in the first direction, wherein the two-dimensional layer includes a first portion and a second portion, the first portion of the two-dimensional layer contacting the first semiconductor pattern and the second semiconductor pattern, and the second portion of the two-dimensional layer contacting the third semiconductor pattern and the fourth semiconductor pattern, and wherein the upper two-dimensional layer includes a first portion and a second portion, the first portion of the upper two-dimensional layer contacting the first upper semiconductor pattern and the second upper semiconductor pattern, and the second portion of the upper two-dimensional layer contacting the third upper semiconductor pattern and the fourth upper semiconductor pattern.

14. The semiconductor device of claim 13, further comprising: an active contact between the first portion of the upper two-dimensional layer and the second portion of the upper two-dimensional layer, a first upper source / drain pattern between the first portion of the upper two-dimensional layer and the active contact; and a second upper source / drain pattern between the second portion of the upper two-dimensional layer and the active contact.

15. The semiconductor device of claim 14, wherein, The active contact includes first and second side surfaces opposite each other, wherein the first side surface of the active contact contacts a side surface of the first upper source / drain pattern and a surface of the first portion of the upper two-dimensional layer, wherein the second side surface of the active contact contacts a side surface of the second upper source / drain pattern and a surface of the second portion of the upper two-dimensional layer, wherein the side surface of the first upper source / drain pattern and the surface of the first portion of the upper two-dimensional layer are coplanar with each other, and wherein the side surface of the second upper source / drain pattern and the surface of the second portion of the upper two-dimensional layer are coplanar with each other. wherein the side surface of the second upper source / drain pattern and the surface of the second portion of the upper two-dimensional layer are coplanar with each other.

16. The semiconductor device of claim 13, wherein, a distance in the first direction between the first portion of the two-dimensional layer and the second portion of the two-dimensional layer is smaller than a distance in the first direction between the first portion of the upper two-dimensional layer and the second portion of the upper two-dimensional layer.

17. The semiconductor device of claim 9, wherein, the two-dimensional layer includes an outer side surface, the outer side surface of the two-dimensional layer contacting a side surface of the first semiconductor pattern, a side surface of the second semiconductor pattern, and the first side surface of the inner spacer, wherein the outer side surface of the two-dimensional layer includes a first portion contacting the side surface of the first semiconductor pattern, a second portion contacting the side surface of the second semiconductor pattern, and a third portion contacting the first side surface of the inner spacer, and wherein the first portion, the second portion, and the third portion of the outer side surface of the two-dimensional layer are coplanar with each other.

18. A semiconductor device, the semiconductor device comprising: a first semiconductor pattern and a second semiconductor pattern; a gate electrode including an electrode portion between the first semiconductor pattern and the second semiconductor pattern; an inner spacer contacting a top surface of the first semiconductor pattern and a bottom surface of the second semiconductor pattern; a gate insulating layer between the inner spacer and the electrode portion; a two-dimensional layer contacting a side surface of the first semiconductor pattern, a side surface of the second semiconductor pattern, and a first side surface of the inner spacer; a source / drain pattern on the two-dimensional layer; and an active contact electrically connected with the source / drain pattern, wherein the side surface of the first semiconductor pattern, the side surface of the second semiconductor pattern, and the first side surface of the inner spacer are coplanar with each other.

19. The semiconductor device of claim 18, further comprising an upper two-dimensional layer overlapping the two-dimensional layer, the active contact is configured to extend through the upper two-dimensional layer. wherein, 20. The semiconductor device of claim 19, further comprising a first upper source / drain pattern and a second upper source / drain pattern on the upper two-dimensional layer, the first upper source / drain pattern and the second upper source / drain pattern overlapping the source / drain pattern. wherein, ​

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