Self-aligned gate cuts with hybrid architecture

Abstract

The invention relates to a self-aligned gate cut with a hybrid architecture. Techniques are provided herein for forming a semiconductor device that includes one or more self-aligned gate cuts having a hybrid architecture between adjacent devices. In an example, a semiconductor device includes a gate structure surrounding or otherwise on a semiconductor region (also referred to as a channel region). The gate structure may be interrupted between two transistors having a gate cut-out extending through at least an entire thickness of the gate structure and including a dielectric material. The gate cut-out includes a hybrid design formed in two portions. A first portion of the gate cut-out is formed prior to any gate patterning and is self-aligned between adjacent fins of semiconductor material. A second portion of the gate cut-out is formed over the first portion of the gate cut-out and integrated with a spacer structure formed on sidewalls of the sacrificial gate extending over adjacent fins.

Description

Background Technology

[0001] As integrated circuits continue to shrink in size, numerous challenges arise. For example, reducing the size of memory and logic cells is becoming increasingly difficult because it reduces the spacing between devices at the device layers. As transistors are arranged more densely, forming certain device structures to isolate adjacent transistors becomes challenging. Therefore, many significant challenges remain regarding the fabrication of semiconductor devices. Attached Figure Description

[0002] Figure 1A and Figure 1B These are cross-sectional and plan views of some semiconductor devices having hybrid self-aligned gate cutouts between devices, according to embodiments of the present disclosure.

[0003] Figure 2A and Figure 2B These are cross-sectional and plan views illustrating a first stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0004] Figure 3A and Figure 3B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0005] Figure 4A and Figure 4B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0006] Figure 5A and Figure 5B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0007] Figure 5A' and Figure 5B' These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some other embodiments of the present disclosure.

[0008] Figure 6A and Figure 6B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0009] Figure 7A and Figure 7B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0010] Figure 8A and Figure 8B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0011] Figure 9A and Figure 9B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0012] Figure 10A and Figure 10B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0013] Figure 11A and Figure 11B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0014] Figure 12A and Figure 12B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0015] Figure 13A and Figure 13B These are cross-sectional and plan views illustrating another stage in an exemplary process for forming a semiconductor device with hybrid self-aligned gate cutouts between devices, according to some embodiments of the present disclosure.

[0016] Figure 14 This is a cross-sectional view showing a hybrid self-aligned gate cutout between devices that are spaced further apart than other devices according to some embodiments of the present disclosure.

[0017] Figure 15 A cross-sectional view of a chip package containing one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0018] Figure 16This is a flowchart of a manufacturing process for a semiconductor device having hybrid self-aligned gate cutouts between devices, according to embodiments of the present disclosure.

[0019] Figure 17 A computing system comprising one or more integrated circuits as described herein is illustrated according to embodiments of the present disclosure.

[0020] Although the following detailed description is based on illustrative embodiments, many alternatives, modifications, and variations will be apparent from this disclosure. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit this disclosure to the specific constructions shown. For example, while some drawings generally indicate perfect straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have imperfect straight lines, right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topologies, or otherwise be non-smooth, due to the given practical limitations of the processing equipment and techniques used. Detailed Implementation

[0021] This document provides techniques for forming semiconductor devices including one or more self-aligned gate cutouts with a hybrid architecture between adjacent devices. This technique can be used in any number of integrated circuit applications and is particularly useful for device-layer transistors (e.g., finFETs or all-around gate transistors (e.g., strip FETs and nanowire FETs) or forked-edge transistors (e.g., nanosheet FETs)). In examples, the semiconductor device includes a gate structure surrounding or otherwise formed on a semiconductor region (also called a channel region). The semiconductor region can be, for example, a fin of semiconductor material extending from a source region to a drain region, or one or more nanowires, nanoribbons, or nanosheets of semiconductor material extending from a source region to a drain region. The gate structure includes a gate dielectric (e.g., a high-k gate dielectric material) and a gate electrode (e.g., a conductive material such as a work function material and / or a gate-fill metal). The gate structure can, for example, be interrupted between two transistors having a gate cutout extending through at least the entire thickness of the gate structure, and includes a dielectric material to electrically isolate portions of the gate structure on either side of the gate cutout. According to some embodiments, the gate cutout includes a hybrid design formed in two parts. A first portion of the gate notch is formed prior to any gate patterning and is self-aligned between adjacent fins of the semiconductor material. A second portion of the gate notch is formed over the first portion of the gate notch and is integrated with a spacer body structure formed on the sidewall of a sacrificial gate extending over the adjacent fins. Numerous configurations and variations will be apparent according to this disclosure.

[0022] General Overview

[0023] As mentioned above, many significant challenges remain in integrated circuit manufacturing. More specifically, as devices become smaller and more densely packed, and as the critical dimension (CD) of the structure is pushed to the limits of current manufacturing technologies, the fabrication of many structures becomes increasingly challenging. Exemplary structures similar to gate nicks are used in integrated circuit design to isolate gate structures from each other. Such gate nicks can be formed in various ways, but existing techniques for forming gate nicks have drawbacks. Gate nicks are typically high aspect ratio structures that require deep etching through one or more materials between adjacent devices. However, it is difficult to maintain sufficient selectivity in these deep etchings while ensuring that the etched trenches extend throughout the entire thickness of the adjacent gate structures.

[0024] Therefore, and according to embodiments of this disclosure, this document provides techniques for forming hybrid self-aligned gate nicks between devices (e.g., at cell boundaries). The gate nick can have a hybrid structure formed by two segments. A first segment can be self-aligned between adjacent fins prior to any gate patterning, and a second segment can be formed on the first segment after a sacrificial gate is formed over the fins. In this way, the etching for forming the second segment of the gate nick only needs to fall on the top surface of the first segment of the gate nick, rather than on the bottom of the gate trench. The gate nick can be self-aligned between any type of transistor device (e.g., finFET, gate all-around (GAA) device, and fork-type device). In the case of fork-type devices, the self-aligned gate nick can be formed at a different time with the dielectric ridge between the nanosheet devices. According to some embodiments, the first segment of the gate nick may include a dielectric liner and a dielectric filler on the dielectric liner. The dielectric filler may include a low-k dielectric material (e.g., a dielectric with a dielectric constant of about 4.5 or less), while the dielectric liner may include a high-k dielectric material (e.g., a dielectric with a dielectric constant of about 5.5 or greater). According to some embodiments, a second segment of the gate notch may include the same dielectric material as the spacer structure used on the edge of the gate trench. For example, the second segment of the gate notch may include silicon nitride, silicon oxynitride, or silicon oxycarbide. In some embodiments, the second segment of the gate notch is seamlessly integrated with the spacer structure.

[0025] According to an embodiment, an integrated circuit includes: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction; a second semiconductor device having a second semiconductor region extending from a second source or drain region in the first direction; and a second gate structure extending over the second semiconductor region in a second direction; a first dielectric structure separating the first gate structure from the second gate structure between the first semiconductor device and the second semiconductor device and along the second direction; and a second dielectric structure on the top surface of the first dielectric structure, wherein the second dielectric structure further separates the first gate structure from the second gate structure along the second direction. The first dielectric structure extends along a third direction through a portion of the entire height of the first gate structure or the second gate structure, and the second dielectric structure extends along a third direction through the remaining portion of the entire height of the first gate structure or the second gate structure.

[0026] According to another embodiment, an integrated circuit includes: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction; a second semiconductor device having a second semiconductor region extending from a second source or drain region in a first direction and a second gate structure extending over the second semiconductor region in a second direction; a spacer structure extending along a second direction on the sidewalls of the first and second gate structures and together with the first and second gate structures; a first dielectric structure separating the first gate structure from the second gate structure along the second direction; and a second dielectric structure on the top surface of the first dielectric structure. The second dielectric structure also separates the first gate structure from the second gate structure along the second direction. The second dielectric structure and the spacer structure are a continuum of materials, such that there is no seam between the second dielectric structure and the spacer structure.

[0027] According to another embodiment, a method of forming an integrated circuit includes: forming at least two adjacent fins comprising semiconductor material, the fins extending over a substrate and each extending parallel to each other in a first direction; forming a spacer material on and between the at least two adjacent fins; forming a first dielectric structure on the spacer material between the at least two adjacent fins; recessing the spacer material between the at least two adjacent fins; forming a dielectric filler between the at least two adjacent fins and adjacent to the first dielectric structure; recessing the dielectric filler between the at least two adjacent fins; forming a sacrificial gate on the semiconductor material of the at least two adjacent fins and on the first dielectric structure in a second direction different from the first direction; forming a recess through the sacrificial gate on the first dielectric structure; forming a spacer structure on the sidewall of the sacrificial gate and within the recess on the first dielectric structure, such that the spacer structure within the recess forms a second dielectric structure; removing the sacrificial gate; and forming a gate structure on the semiconductor material of each of the adjacent fins.

[0028] To name just a few examples, this technique can be used with any type of nonplanar transistor, including finFETs (sometimes called dual-gate transistors), nanowire and nanoribbon transistors (sometimes called all-around gate transistors), or fork-plate transistors. The source and drain regions can be, for example, epitaxial regions deposited during etching and replacement source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented using a back-gate process (sometimes called a replacement metal gate or RMG process). Any number of semiconductor materials can be used to form the transistor, such as group IV materials (e.g., silicon, germanium, silicon-germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0029] The techniques and structures provided herein can be used with tools that can be detected, such as: electron microscopy including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); compositional mapping; X-ray crystallography or diffraction (XRD); energy-dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atomic probe imaging or tomography; local electrode atomic probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis, to name just a few suitable exemplary analytical tools. For example, in some exemplary embodiments, such a tool can be used to detect the presence of gate cutouts that are substantially equidistant (e.g., within 1-2 nm) between adjacent semiconductor devices. Furthermore, the tool can also be used to show that the gate cutout comprises two distinct segments, wherein a first segment is between adjacent devices, and a second segment is on the first segment. The second segment of the gate cutout can be seamlessly integrated with an adjacent spacer structure. Based on this disclosure, many constructions and variations will be apparent.

[0030] It should be readily understood that the meanings of “above” and “on top” in this disclosure should be interpreted in the broadest sense, such that “above” and “on top” not only mean “directly on” something, but also include the meaning of being above something with an intermediate feature or intervening layer. Furthermore, for ease of description, spatial relational terms such as “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” etc., may be used herein to describe the relationship between one element or feature shown in the figures and other elements or features. In addition to the orientations shown in the figures, spatial relational terms are also intended to cover different orientations of the device in use and operation. The device may be otherwise oriented (rotated 90 degrees or otherwise), and the spatial descriptive terms used herein may be interpreted accordingly.

[0031] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A monolayer is a layer composed of a single layer of atoms of a given material. A layer may extend over the entire upper or lower layer structure, or may have a range smaller than that of the upper or lower layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, wherein the layer has a thickness smaller than that of the continuous structure. For example, a layer may lie between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a conical surface. A layer may conform to a given surface (whether flat or curved), wherein it has a relatively uniform thickness throughout the layer.

[0032] As used herein, “compositionally different” or “compositionally dissimilar” materials refer to two materials with different chemical compositions. This compositional difference can be, for example, due to elements present in one material but not in the other (e.g., SiGe is compositionally different from silicon), or it can be by having one material with all the same elements as the second material, but at least one of those elements is intentionally provided in one material at a different concentration relative to the other (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to such chemical compositional diversity, materials can also have dissimilar dopants (e.g., gallium and magnesium) or the same dopants but at different concentrations. In yet another embodiment, compositionally dissimilar materials can also refer to two materials with different crystal orientations. For example, (110) silicon is compositionally different from (100) silicon. For example, uniform-thickness wafer layer transfer can be used to create stacks with different orientations. If the two materials are elementally different, one material has elements not present in the other.

[0033] Architecture

[0034] Figure 1A This is a cross-sectional view taken through a plurality of semiconductor devices 101 according to an embodiment of the present disclosure. Figure 1B This is a top cross-sectional view of semiconductor device 101, and Figure 1A It shows crossing Figure 1B The section depicted by the dashed line 1A-1A is shown. It should be noted that, to make the structure below visible, [the following text is missing]. Figure 1B Some material layers are omitted in the top view. Each semiconductor device in semiconductor device 101 may be a non-planar metal-oxide-semiconductor (MOS) transistor, such as a tri-gate (e.g., finFET) or gate-all-around (GAA) transistor or fork-plate transistor, but other transistor topologies and types may also benefit from the gate sizing techniques and structures provided herein. The exemplary embodiments shown herein use a GAA structure. Semiconductor device 101 represents a portion of an integrated circuit that may contain any number of similar semiconductor devices.

[0035] As can be seen, semiconductor device 101 is formed on substrate 102. Any number of semiconductor devices can be formed on substrate 102, but three are shown here as examples. Substrate 102 can be, for example, a bulk substrate comprising group IV semiconductor materials (e.g., silicon, germanium, or silicon-germanium), group III-V semiconductor materials (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Optionally, substrate 102 can be a semiconductor-on-insulator substrate (e.g., silicon on silicon dioxide) having a desired semiconductor layer over a buried insulating layer. Optionally, substrate 102 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some embodiments, the lower portion (or all) of substrate 102 is removed and replaced by one or more back-side interconnect layers to form back-side signal and power wiring.

[0036] Each semiconductor device in semiconductor device 101 includes a direction along the distance between the source region and the drain region (e.g., in...). Figure 1A One or more nanoribbons 104 extending parallel to each other (in the first direction of the page in the cross-sectional view). Nanoribbon 104 is an example of a semiconductor region or semiconductor body extending between source and drain regions. The term "nanoribbon" can also cover other similar shapes, such as nanowires or nanosheets. The semiconductor material of the nanoribbon 104 can be formed from a substrate 102. In some embodiments, the semiconductor device 101 may each include a fin-shaped semiconductor region, which may be native to the substrate 102 (formed by the substrate itself), for example, a silicon fin etched from a bulk silicon substrate. Alternatively, the fins may be formed from a material deposited on an underlying substrate. In one such exemplary case, a uniform-thickness layer of silicon germanium (SiGe) can be deposited onto a silicon substrate, then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, the non-native fins can be formed in a so-called aspect ratio-based trapping process, where the native fins are etched away to leave fin trenches, which can then be filled with an alternative semiconductor material (e.g., group IV or III-V materials). In other embodiments, the fins comprise alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of the nanoribbon 104 shown during the gate formation process (where one type of alternating layer is selectively etched away to release other types of alternating layers in the channel region), allowing a gate all-around (GAA) or fork-and-chip process to then be performed. Again, according to some examples, the alternating layers can be deposited at a uniform thickness and then etched into the fins or deposited within the fin trenches.

[0037] As can be further seen, adjacent semiconductor devices are separated by a dielectric layer 106 (which may include silicon dioxide). The dielectric layer 106 provides shallow trench isolation (STI) between any adjacent semiconductor device and the adjacent sub-fin region 108. The dielectric layer 106 may be any suitable dielectric material, such as silicon dioxide, alumina, or silicon oxycarbonate.

[0038] In this example, each of the semiconductor devices 101 includes a sub-fin region 108. According to some embodiments, the sub-fin region 108 comprises the same semiconductor material as the substrate 102 and is adjacent to the dielectric layer 106. According to some embodiments, a nanoribbon 104 (or other semiconductor body) extends in a first direction between the source and drain regions, thereby providing an active region for the transistor (e.g., the semiconductor region below the gate). The source and drain regions are... Figure 1A Not shown in the cross-section, but in Figure 1B As can be seen in the top view, each semiconductor device 101 has nanoribbons 104 extending between source or drain regions 110. Figure 1B It also shows the direction along the second direction (e.g., across). Figure 1A The dielectric filler 112 extends between the source or drain regions 110 of a given source / drain trench (as shown on the page). The dielectric filler 112 may comprise any suitable dielectric material, such as silicon dioxide. According to some embodiments, a spacer structure 114 surrounds the end of the nanoribbon 104 and extends along the sidewalls of the gate structure. The spacer structure 114 may comprise a dielectric material (e.g., silicon nitride) and may be deposited and etched to a desired thickness (e.g., 2 nm to 10 nm) using a conformal method or other suitable deposition process.

[0039] According to some embodiments, the source and drain regions 110 are epitaxial regions provided using etching and replacement processes. Any semiconductor material suitable for the source or drain regions (e.g., group IV and III-V semiconductor materials) can be used. The source and drain regions 110 may include multiple layers, such as a substrate and a cap layer, to improve contact resistance. In any such case, depending on the transistor polarity, the composition and doping of the source and drain regions 110 may be the same or different. In examples, phosphorus-doped silicon can be used for the n-type source or drain regions, while boron-doped silicon-germanium can be used for the p-type source or drain regions. Any number of source and drain configurations and materials can be used.

[0040] According to some embodiments, each semiconductor device 101 includes components along a transverse span Figure 1AThe second direction of the page extends over the nanoribbon 104 as a gate structure. The second direction may be orthogonal to the first direction. Each gate structure includes a corresponding gate dielectric 116 and a gate electrode 118. The gate dielectric 116 represents any number of dielectric layers present between the nanoribbon 104 and the gate electrode 118. The gate dielectric 116 may also be present on the surface of other structures within the gate trench, such as portions of the sub-fin region 108. The gate dielectric 116 may include any suitable gate dielectric material(s). In some embodiments, the gate dielectric 116 includes a native oxide material (e.g., silicon dioxide) layer on the nanoribbon or other semiconductor region constituting the channel region of the device, and a high-k dielectric material (e.g., hafnium oxide) layer on the native oxide.

[0041] Gate electrode 118 can represent any number of conductive layers, such as any metal, metal alloy, or doped polycrystalline silicon layer. In some embodiments, gate electrode 118 includes one or more work function metals surrounding nanoribbon 104. In some embodiments, one or more semiconductor devices in semiconductor device 101 are p-channel devices that include a work function metal of titanium surrounding their nanoribbon 104. In some embodiments, one or more semiconductor devices in semiconductor device 101 are n-channel devices that include a work function metal of tungsten surrounding their nanoribbon 104. Gate electrode 118 may also include filler metal or other conductive material (e.g., tungsten, ruthenium, molybdenum, cobalt) surrounding the work function metal to provide the overall gate electrode structure.

[0042] According to some embodiments, adjacent gate structures may be separated by gate cutouts along a second direction (e.g., across a page), the gate cutouts acting as dielectric barriers or walls between gate structures. The gate cutouts may include a first dielectric structure 120 and a second dielectric structure 122 on a first dielectric structure 120. The gate cutouts extend vertically (e.g., third-direction upward) through at least the entire thickness of the adjacent gate structure on either side of the gate cutout. Thus, the first dielectric structure 120 extends through a first portion of the thickness of the gate structure, and the second dielectric structure 122 extends through a second portion of the thickness of the gate structure. In some embodiments, the first dielectric structure 120 is disposed on the top surface of the dielectric layer 106. According to some embodiments, the first dielectric structure 120 includes a dielectric liner along the outer edge of the first dielectric structure 120 and a dielectric filler on the dielectric liner. According to some embodiments, the dielectric liner comprises a high-k dielectric material, such as silicon nitride, and the dielectric filler comprises a medium-k or low-k dielectric material (e.g., a dielectric having a dielectric constant of about 4.5 or less), such as silicon dioxide, porous silicon dioxide, or a flowable oxide.

[0043] According to some embodiments, the second dielectric structure 122 includes a different dielectric material compared to the first dielectric structure 120. In some examples, the second dielectric structure 122 includes silicon nitride, silicon oxynitride, or silicon oxycarbide. The second dielectric structure 122 may be offset from the first dielectric structure 120 along a second direction by up to 1 nm, up to 2 nm, or up to 3 nm. According to some embodiments, such as Figure 1B As shown more clearly in the top view, the second dielectric structure 122 is seamlessly integrated with the spacer structure 114. Therefore, as will be discussed in more detail herein, the second dielectric structure 122 and the spacer structure 114 can be formed from the same dielectric material deposited simultaneously. In this way, the second dielectric structure 122 and the spacer structure 114 can be monolithic and continuous material bodies, such that there are no seams between the second dielectric structure 122 and the spacer structure 114.

[0044] According to some embodiments, the gate notch is self-aligned within the gate trench between adjacent devices, such that the distance (d) between each edge of the gate notch and the corresponding nanoribbon 104 along the common plane is substantially the same (e.g., the deviation of distance d on one side from distance d on the other side is within 1 nm). The distance (d) can vary depending on the device density, but is typically between about 5 nm and about 20 nm. It should be noted that the gate notch can be used to separate any number of devices. Figure 1A and Figure 1B In the example shown, the gate cut separates individual devices from each other along the second direction. However, the gate cut can also be patterned to separate groups of two, three, four, or more devices from other groups of devices. As will be discussed in more detail herein, the gate cut is formed prior to the formation of the gate structure such that the gate dielectric 116 extends along the sidewalls of both the first dielectric structure 120 and the second dielectric structure 122.

[0045] Manufacturing method

[0046] Figures 2A-13A and Figures 2B-13B The images include cross-sectional and planar views, which together illustrate an exemplary process for forming an integrated circuit having semiconductor devices with hybrid self-aligned gate cutouts between devices, according to embodiments of the present disclosure. Figures 2A-13A This refers to a series of semiconductor devices and Figure 1A A cross-sectional view similar to the cross-sectional view, and Figures 2B-13B This represents the corresponding plan view at each stage of manufacturing. Each group of figures sharing the same letters shows an exemplary structure resulting from the process flow up to that point in time; therefore, the depicted structure evolves as the process continues, ending at... Figures 13A-13B The structure shown (which is similar to) Figure 1Aand Figure 1B The structure shown is an example of a structure that can be part of an entire integrated circuit (e.g., a processor or memory chip) that includes, for example, digital logic units and / or memory units and analog mixed-signal circuitry. Therefore, the integrated circuit structure shown can be part of a larger integrated circuit that includes other integrated circuits not shown. Exemplary material and process parameters are given, but other material and process parameters may be used as will be understood from this disclosure. Although the fabrication of two gate cutouts is shown in the foregoing figures, it should be understood that any number of similar gate cutouts can be fabricated on an integrated circuit using the same processes discussed herein.

[0047] Figure 2A and Figure 2B The illustration shows a cross-sectional view through substrate 201 and a plan view of the entire substrate 201 according to an embodiment of the present disclosure, the substrate 201 having a series of material layers formed thereon. Alternating material layers can be deposited on substrate 201, including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating semiconductor layers 204 and sacrificial layers 202 can be deposited on substrate 201. The above description of substrate 102 also applies to substrate 201. Figure 2B The plan view shows the top semiconductor layer 204 of the stacked layers.

[0048] According to some embodiments, the sacrificial layer 202 has a different material composition than the semiconductor layer 204. In some embodiments, the sacrificial layer 202 is silicon-germanium (SiGe), while the semiconductor layer 204 comprises a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or group III-V materials (such as indium phosphide (InP) or gallium arsenide (GaAs)). In each sacrificial layer in the sacrificial layer 202 and in the example where SiGe is used in the semiconductor layer 204, the germanium concentration differs between the sacrificial layer 202 and the semiconductor layer 204. For example, the sacrificial layer 202 may include a higher germanium content compared to the semiconductor layer 204. In some examples, the semiconductor layer 204 may be doped with an n-type dopant (to produce a p-channel transistor) or a p-type dopant (to produce an n-channel transistor).

[0049] While the dimensions of one exemplary embodiment may differ from those of the next exemplary embodiment, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm). The thickness of each semiconductor layer in semiconductor layer 204 may be substantially the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Each of the sacrificial layer 202 and semiconductor layer 204 may be deposited using any known or proprietary material deposition technique (e.g., chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)).

[0050] Figure 3A and Figure 3B The following are depictions, according to the embodiment, after the formation of the cap layer 302 and subsequently the formation of fins below the cap layer 302. Figure 2A and Figure 2B The diagram shows cross-sectional and planar views of the structure. The cap layer 302 can be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The cap layer 302 is patterned into rows to form corresponding rows of fins from the alternating stack of sacrificial layer 202 and semiconductor layer 204. The rows of fins extend longitudinally in a first direction (e.g., in and out). Figure 3A (See the page). According to some embodiments, an anisotropic etching process continues through the stacked layers into at least a portion of the substrate 201, thereby creating a sub-fin region 304. According to some embodiments, the sub-fin region 304 represents the remainder of the substrate 201 directly beneath the alternating layers of the sacrificial layer 202 and the semiconductor layer 204.

[0051] Figure 4A and Figure 4B The following are depictions according to some embodiments of the deposition of spacer material 402. Figure 3A and Figure 3B The diagram shows cross-sectional and planar views of the structure. Spacer material 402 can be conformally deposited on the fins using, for example, chemical vapor deposition (CVD) or atomic layer deposition (ALD). According to some embodiments, the conformal deposition will leave groove-shaped recesses 404 between fins spaced sufficiently far apart. If the fins are too close together, the spacer material 402 will essentially fill the space between the fins, and no recess will be created. In this way, the location of the recesses 404 can be determined based on the spacing between adjacent fins. According to some embodiments, the spacer material 402 comprises an oxide-based material, such as silicon dioxide. The spacer material 402 can have a conformal thickness on the fins between about 5 nm and about 30 nm.

[0052] Figure 5A and Figure 5B The following descriptions depict the formation of the first dielectric structure 502 within the recess 404 according to some embodiments. Figure 4A and Figure 4B The diagram shows cross-sectional and plan views of the structure. In the example shown, the dielectric structure 502 comprises a single dielectric material and is polished such that its top surface is substantially coplanar with the top surface of the cap layer 302 (or, in the example where the cap layer 302 is removed, the top surface of the topmost semiconductor layer 204). The first dielectric structure 502 can be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride.

[0053] Figure 5A' and Figure 5B' The alternative formation of a first dielectric structure 502, including a dielectric liner 502a and a dielectric filler 502b, according to some embodiments is depicted respectively. Figure 4A and Figure 4B The diagram shows cross-sectional and plan views of the structure. The dielectric liner may comprise a high-k dielectric material, such as hafnium oxide, and the dielectric filler 502b may comprise a low-k dielectric material, such as silicon dioxide. Other dielectric liners may comprise silicon nitride or silicon oxynitride. According to some embodiments, a dielectric liner 502a is first deposited on the sidewalls and bottom surface of the recess 404, followed by the formation of the dielectric filler 502b on the dielectric liner 502a within the recess 404. The dielectric filler 502b may then be recessed, and the remaining portion of the dielectric liner 502a is formed in the recessed region such that the dielectric liner 502a surrounds the dielectric filler 502b. In other words, the dielectric liner 502a is present on the bottom, side, and top surfaces of the dielectric filler 502b.

[0054] Figure 6A and Figure 6B The following are depictions, according to some embodiments, after the spacer material 402 is recessed and the dielectric layer 602 is further formed. Figure 5A and Figure 5BThe diagram shows cross-sectional and planar views of the structure. The spacer material 402 can be recessed using a suitable isotropic etching process. In some examples, the spacer material 402 is recessed such that the top surface of the spacer material 402 is at least below the top surface of the sub-fin region 304, or at least below the midpoint of the height along the sub-fin region 304. According to some embodiments, another dielectric material is deposited over the entire structure and subsequently recessed to form a dielectric layer 602 around the bottom of the first dielectric structure 502. The dielectric layer 602 can be formed with a top surface lower than the top surface of the sub-fin region 304. The spacer material 402 and the dielectric layer 602 together can serve as shallow trench isolation (STI) between adjacent fins. In some examples, the dielectric layer 602 is omitted, such that the spacer material 402 alone serves as the STI between adjacent fins. It should be noted that the dielectric materials of each of the spacer material 402 and the dielectric layer 602 have sufficient etch selectivity for the dielectric material of the first dielectric structure 502, such that the isotropic etching of both the spacer material 402 and the dielectric layer 602 will not significantly etch the first dielectric structure 502.

[0055] Figure 7A and Figure 7B The description depicts, according to some embodiments, a sacrificial gate 702 formed below a gate mask layer 704, extending over the entire fin in a second direction different from the first direction. Figure 6A and Figure 6B The diagram shows cross-sectional and planar views of the structure. Gate mask layer 704 may comprise any suitable hard mask material, such as a carbon hard mask (CHM), and is patterned into strips to form corresponding strips of sacrificial gate 702. Sacrificial gate 702 may extend over the entire fin in a second direction orthogonal to the first direction. According to some embodiments, the sacrificial gate material is formed as parallel strips over the entire integrated circuit and is removed in all areas not protected by gate mask layer 704 (e.g., using an etching process). Sacrificial gate 702 may be any suitable material capable of selective removal without damaging the semiconductor material of the fin. In some examples, sacrificial gate 702 comprises polysilicon.

[0056] Figure 8A and Figure 8B The following are depictions, according to some embodiments, after further patterning of the gate mask layer 704 to remove the portion of the gate mask layer 704 located above the first dielectric structure 502. Figure 7A and Figure 7BThe diagram shows a cross-section and a plan view of the structure. The gate mask layer 704 can be patterned using appropriate photolithography techniques to expose the portion of the underlying sacrificial gate 702 located above the first dielectric structure 502. Thus, the opening through the gate mask layer 704 can have a width similar to the width of the first dielectric structure 502 (e.g., along the second direction).

[0057] According to some embodiments, an etching process is performed to remove exposed portions of the sacrificial gate 702 that are not protected by the gate mask layer 704 to form an opening 802. At least a portion of the top surface of the first dielectric structure 502 is exposed at the bottom of the opening 802.

[0058] Figure 9A and Figure 9B The following are depictions, according to some embodiments, of forming a second dielectric structure 902 on a first dielectric structure 502 (e.g., within an opening 802) and forming a spacer structure 904 on the sidewalls of the sacrificial gate 702 and the gate mask layer 704. Figure 8A and Figure 8B The cross-sectional and plan views of the structure are shown. Figure 9B As shown, the second dielectric structure 902 and the spacer structure 904 can both be formed from the same material deposited simultaneously, resulting in seamless integration of the second dielectric structure 902 and the spacer structure 904. Note that the second dielectric structure 902 and the spacer structure 904 are a continuum of material, resulting in no seams between the second dielectric structure 902 and the spacer structure 904. The dielectric material can be deposited uniformly over the entire structure and etched back, thereby forming the spacer structure 904 on any structure extending above the substrate 201 and on the sidewalls of the second dielectric structure 902 within the opening 802. Figure 9B As shown, the spacer structure 904 extends along the sidewalls of the sacrificial gate 702 and the gate mask layer 704 in a second direction. In some embodiments, the spacer structure may also be formed on the sidewalls of the fin not below the sacrificial gate 702 or on the sidewalls of the first dielectric structure 502. In some examples, the second dielectric structure 902 and the spacer structure 904 comprise silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0059] Figure 10A and Figure 10B The following are depictions, according to some embodiments, after removing any exposed fins and subsequently forming source or drain regions 1002 at the ends of the fins. Figure 9A and Figure 9BThe diagram shows cross-sectional and planar views of the structure. Exposed fin portions (e.g., those not protected by the sacrificial gate 702 or spacer structure 904) can be removed using any anisotropic etching process (e.g., reactive ion etching (RIE)). According to some embodiments, removing the exposed fin portions creates source or drain trenches alternating with the gate trench (currently filled with the sacrificial gate 702) along a first direction.

[0060] According to some embodiments, the source or drain region 1002 may be formed from the exposed end of a fin within a source / drain trench. The source or drain region 1002 may be formed in a region previously occupied by exposed fins adjacent to the spacer structure 904. According to some embodiments, the source or drain region 1002 is epitaxially grown from exposed semiconductor material at the end of the semiconductor layer 204. In some exemplary embodiments, either the source or drain region 1002 may be an NMOS source or drain region (e.g., epitaxial silicon) or a PMOS source or drain region (e.g., epitaxial SiGe).

[0061] According to some embodiments, a dielectric filler is provided within the source / drain trench. In some examples, the dielectric filler occupies the remaining volume within the source / drain trench, surrounding and possibly above both the source or drain region 1002 and the first dielectric structure 502. The dielectric filler can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler extends upward to the top surface of the spacer structure 904 and is flush with the top surface of the spacer structure 404 (e.g., after a polishing process). Therefore, in Figure 10B The dielectric filler is not shown in the top view to avoid obscuring the features beneath it.

[0062] Figure 11A and Figure 11B The following are depictions, according to some embodiments, of the gate mask layer 704, the sacrificial gate 702, and the sacrificial layer 202 after removal. Figure 10A and Figure 10B The diagram shows a cross-sectional view and a plan view of the structure. Once the sacrificial gate 702 is removed, the fins that were located below the sacrificial gate 702 are exposed within the gate trench.

[0063] In examples where the fins comprise alternating semiconductor layers, the sacrificial layer 202 is selectively removed to release nanoribbons 1102 extending along a first direction between corresponding source or drain regions 1002. Each vertical group of nanoribbons 1102 represents a semiconductor region or channel region of a different semiconductor device. It should be understood that the nanoribbons 1102 may also be nanowires or nanosheets (e.g., from a forked arrangement) or fins (e.g., for a finFET arrangement). The same isotropic etching process or different isotropic etching processes can be used to remove the sacrificial gate 702 and the sacrificial layer 202. Furthermore, note that the source or drain regions 1002 are adjacent to or otherwise contact the corresponding ends of the nanoribbons 1102 beneath the spacer body structure 904 to provide a transistor conduction path from the source region to the drain region when the gate is properly biased. In some examples, a capping layer 302 is retained on the topmost nanoribbon 1102. In other examples, the capping layer 302 is removed at any time earlier in the fabrication process.

[0064] Figure 12A and Figure 12B The following descriptions depict the formation of the gate dielectric 1202 on any exposed surface within the gate trench, according to some embodiments. Figure 11A and Figure 11B The diagram shows cross-sectional and planar views of the structure. The gate dielectric 1202 may comprise any suitable dielectric material (e.g., silicon dioxide and / or a high-k dielectric material). Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, the gate dielectric 1202 comprises a hafnium oxide layer with a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 1202 may comprise one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some cases, the gate dielectric 1202 may comprise a first layer on nanoribbon 1102 and a second layer on the first layer. The first layer can be, for example, an oxide (e.g., silicon dioxide) of a semiconductor material with nanoribbons 1102, and the second layer can be a high-k dielectric material (e.g., hafnium oxide). More generally, the gate dielectric 1202 can comprise any number of dielectric layers. According to some embodiments, the gate dielectric 1202 is formed along all surfaces exposed within the gate trench, for example along the inner sidewalls of the spacer structure (e.g., Figure 7B(As seen in the diagram) and formed along the exposed surface of the sub-fin region 304. According to some embodiments, the gate dielectric 1202 is also formed along the sidewalls of both the first dielectric structure 502 and the second dielectric structure 902 within the gate trench. Since both the first dielectric structure 502 and the second dielectric structure 902 are formed prior to the formation of the gate dielectric 1202, the gate dielectric 1202 can seamlessly transition along the sidewalls across the boundary between the first dielectric structure 502 and the second dielectric structure 902.

[0065] Figure 13A and Figure 13B The following are depictions, according to some embodiments, of the formation of a gate electrode 1302 surrounding a nanoribbon 1102 within a gate trench and on a gate dielectric 1202. Figure 12A and Figure 12B The diagram shows cross-sectional and planar views of the structure. The gate electrode 1302 may include any number of conductive layers. As just a few examples, the conductive gate electrode 1302 may be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD. In some embodiments, the gate electrode 1302 comprises doped polysilicon, a metal, or a metal alloy. Exemplary suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. The gate electrode 1302 may include, for example, a metal filler material and one or more work function layers, resistance-reducing layers, and / or barrier layers. The work function layer may include, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate or an n-type work function material (e.g., aluminum titanium carbide) for an NMOS gate. After forming the gate structure, the entire structure may be polished or planarized such that the top surface of the gate structure (e.g., the top surface of the gate electrode 1302) is substantially coplanar with the top surfaces of other semiconductor elements (e.g., the spacer structure 904 defining the gate trench and the second dielectric structure 902). Therefore, the gate cut, composed of the first dielectric structure 502 and the second dielectric structure 902, separates the different gate structures along the second direction.

[0066] As discussed above, the techniques described in this article can be used to form gate cutouts that separate any number of transistors. Figure 14An exemplary portion of an integrated circuit is shown, comprising a substrate 1401 with GAA devices separated by gate cutouts 1402. In this example, a group of three transistors is separated by gate cutouts 1402, which consist of a first dielectric structure 1404 and a second dielectric structure 1406. Thus, a first gate structure 1408a may be formed around three devices between corresponding gate cutouts 1402, and a second gate structure 1408b may be formed around three other devices between corresponding gate cutouts 1402. According to some embodiments, the gate cutouts are self-aligned between devices further spaced apart along a first direction. (See above regarding...) Figure 4A As cited, since the spacer material 402 does not leave enough space between closer devices to form a gate cutout, no gate cutout is formed between closer devices.

[0067] Figure 15 An exemplary embodiment of a chip package 1500 according to embodiments of the present disclosure is shown. As can be seen, the chip package 1500 includes one or more dies 1502. The one or more dies 1502 may include at least one integrated circuit having a semiconductor device, such as any semiconductor device disclosed herein. In some exemplary configurations, the one or more dies 1502 may include any other circuitry for interfacing with other devices formed on the die or connected to other devices of the chip package 1500.

[0068] As can be further seen, the chip package 1500 includes a housing 1504 bonded to a package substrate 1506. The housing 1504 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for components of the chip package 1500. To name just a few examples, one or more dies 1502 may be electrically coupled to the package substrate 1506 using connectors 1708, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGAs), pins, or wire bonding. The package substrate 1506 can be any standard or proprietary package substrate, but in some cases includes a dielectric material having a dielectric material extending through the surfaces of the package substrate 1506 or conductive paths (e.g., including conductive vias and lines) between different locations on each surface. In some embodiments, the package substrate 1506 may have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), although any number of package geometries can be used. Additional conductive contacts 1512 may be disposed on the opposite side of the package substrate 1506 for conductive contact, such as a printed circuit board (PCB). One or more vias 1510 extend through the thickness of the package substrate 1506 to provide a conductive path between one or more connectors in the connectors 1508 and one or more contacts in the contacts 1512. For ease of illustration, the via 1510 is shown as a single straight post through the package substrate 1506, although other constructions may be used (e.g., damascene, dual damascene, through-silicon vias, or interconnect structures meandering through the thickness of the substrate 1506 to contact one or more intermediate locations therein). In other embodiments, the vias 1510 are made of a plurality of smaller stacked vias, or staggered at different locations throughout the package substrate 1506. In the illustrated embodiment, the contacts 1512 are solder balls (e.g., for bump-based connectors or ball grid array arrangements), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement, or pads in a pad grid array arrangement). In some embodiments, solder resist is disposed between contacts 1512 to suppress short circuits.

[0069] In some embodiments, molding material 1514 may be disposed around one or more dies 1502 included within housing 1504 (e.g., as an underfill material between die 1502 and encapsulation substrate 1506, and as an overflow material between die 1502 and housing 1504). Although the size and weight of molding material 1514 may differ between one embodiment and another, in some embodiments, the thickness of molding material 1514 is less than 1 mm. Exemplary materials that can be used for molding material 1514, if appropriate, include epoxy molding materials. In some cases, molding material 1514 is not only electrically insulating but also thermally conductive.

[0070] method

[0071] Figure 16 This is a flowchart of a method 1600 for forming at least a portion of an integrated circuit according to an embodiment. Various operations of method 1600 may be... Figures 2A-13A and Figures 2B-13B As shown in the figures. However, the relevance of the various operations of method 1600 to the specific components shown in the foregoing figures is not intended to imply any structural limitations and / or usage limitations. Rather, the foregoing figures provide an exemplary embodiment of method 1600. Other operations may be performed before, during, or after any operation of method 1600. For example, method 1600 does not explicitly describe all processes performed to form a common transistor structure. Some operations of method 1600 may be performed in a different order than that shown.

[0072] According to some embodiments, method 1600 begins at operation 1602, wherein any number of parallel semiconductor fins comprising at least two adjacent fins are formed. The semiconductor material in the fins can be formed from a substrate such that the fins are integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins can be formed from material deposited on an underlying substrate. In one such exemplary case, a uniform-thickness layer of silicon germanium (SiGe) can be deposited onto a silicon substrate, then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, the fins comprise alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons during a gate formation process, in which one type of alternating layer is selectively etched away to release other types of alternating layers in the channel region, allowing a gate all-around (GAA) process to then be performed. The alternating layers can be deposited uniformly and then etched into fins, or deposited into fin trenches. The fins may also include a cap structure on each fin, which defines the position of the fin during, for example, a RIE process. The cap structure may be a dielectric material, such as silicon nitride. In some embodiments, an anisotropic etching process forming the fins also etches into a portion of the substrate.

[0073] Method 1600 continues to operation 1604, wherein spacer material is formed on and between the fins. According to some embodiments, the spacer material is conformally deposited on the fins such that the spacer material has substantially the same thickness on the top and sidewall surfaces of the fins. The spacer material can be conformally deposited on the fins using, for example, CVD, PECVD, or ALD. According to some embodiments, if adjacent fins are spaced sufficiently far apart, the conformal deposition will leave groove-shaped recesses between adjacent fins. If the fins are too close to each other, the spacer material will substantially fill the space between the fins and will not create recesses. The spacer material may include an oxide-based material, such as silicon dioxide, and may have a conformal thickness on the fins between about 5 nm and about 30 nm.

[0074] Method 1600 continues to operation 1606, wherein a first dielectric structure is formed within a trench-shaped recess between adjacent fins. In some examples, the first dielectric structure comprises a single dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. In some examples, the first dielectric structure comprises a dielectric liner and a dielectric filler on the dielectric liner. The dielectric liner may comprise a high-k dielectric material, such as hafnium oxide, and the dielectric filler may comprise a low-k dielectric material, such as silicon dioxide. Other dielectric liners may comprise silicon nitride or silicon oxynitride. According to some embodiments, a first portion of the dielectric liner is formed on the sidewalls and bottom of the trench-shaped recess, followed by the formation of the dielectric filler on the dielectric liner, and then a second portion of the dielectric liner is formed over the top surface of the dielectric filler. In other words, the dielectric liner is present on the bottom, side, and top surfaces of the dielectric filler.

[0075] Method 1600 continues to operation 1608, wherein the spacer material is recessed. The spacer material can be recessed using a suitable isotropic etching process. In some examples, the spacer material is recessed such that the top surface of the spacer material is at least below the topmost surface of the substrate. According to some embodiments, another dielectric material is deposited over the entire structure and subsequently recessed to form a dielectric layer around the bottom of the first dielectric structure and on the top surface of the recessed spacer material. The spacer material and the dielectric layer together can be used as an STI between adjacent fins. In some examples, only the spacer material is provided to serve as an STI between adjacent fins.

[0076] Method 1600 continues to operation 1610, wherein a sacrificial gate is formed over adjacent fins. The sacrificial gate can be patterned using gate mask layers in strips extending orthogonally over the fins (a plurality of gate mask layers and corresponding sacrificial gates can be formed parallel to each other, e.g., forming a cross-shading pattern with respect to the fins). The sacrificial gate also spans a first dielectric structure extending parallel to and between adjacent fins. The gate mask layers can be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate itself can be formed of any suitable material capable of selective removal at subsequent times without damaging the semiconductor material of the fins. In one example, the sacrificial gate comprises polysilicon.

[0077] Method 1600 continues with operation 1612, wherein the portion of the sacrificial gate above the first dielectric structure is removed. The gate mask layer can be patterned using any suitable photolithography technique to expose the portion of the sacrificial gate above the first dielectric structure. The exposed portion can then be etched to form an opening through a portion of the sacrificial gate that exposes at least a portion of the top surface of the first dielectric structure.

[0078] Method 1600 continues with operation 1614, wherein a dielectric material is deposited to form a spacer structure on the sidewalls of the sacrificial gate, and a second dielectric structure is formed on the first dielectric structure within an opening in the portion passing through the sacrificial gate. The dielectric material may be deposited and then etched back, such that the spacer structure remains primarily on the sidewalls of any exposed structure, and the second dielectric structure remains within the opening. According to some embodiments, the dielectric material of the spacer structure and the second dielectric structure can be any suitable dielectric material, such as silicon nitride, silicon oxynitride, or silicon oxycarbide. Because the spacer structure and the second dielectric structure are formed together, there may be no visible seam between the structures that are in contact with each other.

[0079] Method 1600 continues with operation 1616, wherein the sacrificial gate is removed and a gate structure (separated by a combination of a first dielectric structure and a second dielectric structure) is formed over adjacent fins. The sacrificial gate can be removed using an isotropic etching process that selectively removes all material from it, thereby exposing the individual fins between a set of spacer structures. In the exemplary case of using a GAA transistor, any sacrificial layer within the exposed fins between the spacer structures can also be removed to release nanoribbons, nanosheets, or nanowires of semiconductor material.

[0080] The gate structure(s) formed on adjacent fins includes a gate dielectric and a gate electrode. The gate dielectric can be formed on exposed semiconductor regions between spacer structures. The gate dielectric can include any number of dielectric layers deposited using a CVD process (e.g., ALD). One or more annealing processes can also be used to influence the elemental composition of the gate dielectric. To name just a few examples, the gate electrode can include any number of conductive layers deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD. In some embodiments, the gate electrode includes a metal filler material and one or more work function layers, resistance-reducing layers, and / or barrier layers. The work function layers can include, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate or an n-type work function material (e.g., aluminum titanium carbide) for an NMOS gate. After forming the gate structure, the entire structure can be polished or planarized such that the top surface of the gate structure (e.g., the top surface of the gate electrode) is substantially coplanar with the top surfaces of other semiconductor elements (e.g., spacer structures defining the top surfaces of the gate trench and / or the second dielectric structure).

[0081] Exemplary System

[0082] Figure 17 This is an exemplary computing system implemented according to some embodiments of the present disclosure, employing one or more integrated circuit structures as disclosed herein. As can be seen, the computing system 1700 houses a motherboard 1702. The motherboard 1702 may include numerous components, including but not limited to a processor 1704 and at least one communication chip 1706, each of which may be physically and electrically coupled to the motherboard 1702 or otherwise integrated into the motherboard 1702. It should be understood that the motherboard 1702 may be, for example, any printed circuit board (PCB), whether it is a motherboard, a daughterboard mounted on a motherboard, or the sole board of system 1700, etc.

[0083] Depending on its application, the computing system 1700 may include one or more other components that may or may not be physically coupled and electrically coupled to the motherboard 1702. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (e.g., hard disk drive, optical disc (CD), digital versatile optical disc (DVD), etc.). Any component included in the computing system 1700 may include one or more integrated circuit structures or devices constructed according to exemplary embodiments, such as modules comprising integrated circuits on a substrate having semiconductor devices having one or more gate cutouts formed as described herein. In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that the communication chip 1706 may be part of processor 1704 or otherwise integrated into processor 1904).

[0084] Communication chip 1706 implements wireless communication for transmitting data to and from computing system 1700 and computing system 1900. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data via a non-solid-state medium using modulated electromagnetic radiation. This term does not imply that the associated device contains no wires, although in some embodiments it may contain no wires. Communication chip 1706 can implement any of a large number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and above. Computing system 1700 may include multiple communication chips 1706. For example, the first communication chip 1706 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 1706 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0085] The processor 1704 of the computing system 1700 includes an integrated circuit die packaged within the processor 1704. In some embodiments, the processor's integrated circuit die includes onboard circuitry implemented using one or more semiconductor devices as described herein. The term "processor" can refer to any device or part of a device that processes electronic data, for example, from registers and / or memory, to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0086] The communication chip 1706 may also include an integrated circuit die packaged within the communication chip 1706. According to some exemplary embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described in various descriptions herein. As will be understood from this disclosure, note that multi-standard wireless capabilities may be directly integrated into the processor 1704 (e.g., where the functionality of any chip 1706 is integrated into the processor 1704, rather than having a separate communication chip). Further note that the processor 1704 may be a chipset having such wireless capabilities. In short, any number of processors 1704 and / or communication chips 1706 can be used. Similarly, any chip or chipset may have multiple functions integrated therein.

[0087] In various embodiments, the computing system 1700 may be a laptop computer, netbook, notebook computer, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques as described herein.

[0088] It should be understood that, in some embodiments, various components of the computing system 1700 may be combined or integrated in a system-on-a-chip (SoC) architecture. In some embodiments, the component may be a hardware component, firmware component, software component, or any suitable combination of hardware, firmware, or software.

[0089] Further exemplary embodiments

[0090] The following examples relate to further embodiments, based on which many substitutions and constructions will be apparent.

[0091] Example 1 is an integrated circuit comprising: a first semiconductor device having a first semiconductor region extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor region in a second direction; a second semiconductor device having a second semiconductor region extending from a second source or drain region in a first direction and a second gate structure extending over the second semiconductor region in a second direction; a first dielectric structure separating the first gate structure from the second gate structure between the first semiconductor device and the second semiconductor device and along a second direction; and a second dielectric structure on the top surface of the first dielectric structure, wherein the second dielectric structure further separates the first gate structure from the second gate structure along a second direction. The first dielectric structure extends along a third direction through a portion of the entire height of the first gate structure or the second gate structure, and the second dielectric structure extends along a third direction through the remaining portion of the entire height of the first gate structure or the second gate structure.

[0092] Example 2 includes the integrated circuit of Example 1, wherein each of the first gate structure and the second gate structure has the same height.

[0093] Example 3 includes the integrated circuit of Example 1 or 2, wherein a first distance between the edge of the first dielectric structure and the edge of the first semiconductor region closest to the first dielectric structure along a second direction is substantially the same as a second distance between the edge of the first dielectric structure and the edge of the second semiconductor region closest to the first dielectric structure along a second direction.

[0094] Example 4 includes an integrated circuit of any one of Examples 1-3, and further includes a spacer structure on the sidewalls of the first gate structure and the second gate structure and extending along a second direction together with the first gate structure and the second gate structure, wherein the first dielectric structure extends beyond the spacer structure along the first direction.

[0095] Example 5 includes the integrated circuit of Example 4, wherein the second dielectric structure is seamlessly integrated with the spacer structure.

[0096] Example 6 includes an integrated circuit of Example 4 or 5, wherein the top surface of the second dielectric structure is substantially coplanar with the top surface of the spacer structure.

[0097] Example 7 includes an integrated circuit of any one of Examples 1-6, wherein a first dielectric structure comprises silicon and nitrogen, and / or a second dielectric structure comprises silicon and nitrogen.

[0098] Example 8 includes an integrated circuit of any one of Examples 1-7, wherein the first dielectric structure includes a dielectric filler and a dielectric substrate on the dielectric filler.

[0099] Example 9 includes the integrated circuit of Example 8, wherein the dielectric filler comprises a low-k dielectric material and the dielectric liner comprises a high-k dielectric material.

[0100] Example 10 includes an integrated circuit of any one of Examples 1-9, wherein the top surface of the first dielectric structure is substantially coplanar with the topmost surfaces of the first semiconductor region and the second semiconductor region.

[0101] Example 11 includes an integrated circuit of any one of Examples 1-10, wherein a first gate structure includes a first gate electrode on a first gate dielectric, and a second gate structure includes a second gate electrode on a second gate dielectric.

[0102] Example 12 includes the integrated circuit of Example 11, wherein a first gate dielectric extends along a first sidewall of a first dielectric structure and a first sidewall of a second dielectric structure, and a second gate dielectric extends along a second sidewall of a first dielectric structure and a second sidewall of a second dielectric structure.

[0103] Example 13 includes an integrated circuit of any one of Examples 1-12, wherein the first semiconductor region and the second semiconductor region each include a plurality of semiconductor nanoribbons.

[0104] Example 14 includes the integrated circuit of Example 13, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0105] Example 15 includes an integrated circuit of any of Examples 1-14, wherein, along a first direction, a first dielectric structure is longer than a second dielectric structure.

[0106] Example 16 is a die of an integrated circuit that includes any one of Examples 1-15.

[0107] Example 17 is an electronic device comprising a chip package having one or more dies. At least one of the one or more dies includes: a first semiconductor region extending from a first source or drain region in a first direction; a first gate structure extending over the first semiconductor region in a second direction, the second direction being different from the first direction; a second semiconductor region extending from a second source or drain region in the first direction; a second gate structure extending over the second semiconductor region in the second direction; a first dielectric structure separating the first gate structure from the second gate structure along the second direction; and a second dielectric structure on the top surface of the first dielectric structure. The first dielectric structure extends along a third direction through a first portion of the entire height of the first gate structure or the second gate structure. The second dielectric structure also separates the first gate structure from the second gate structure along the second direction. The second dielectric structure extends along a third direction through a second portion of the entire height of the first gate structure or the second gate structure. The first portion and the second portion together equal the entire height of the first gate structure or the second gate structure.

[0108] Example 18 includes the electronic device of Example 17, wherein the second dielectric structure comprises silicon and nitrogen.

[0109] Example 19 includes the electronic device of Example 17 or 18, wherein a first distance between the edge of the first dielectric structure and the edge of the first semiconductor region closest to the first dielectric structure along a second direction is substantially the same as a second distance between the edge of the first dielectric structure and the edge of the second semiconductor region closest to the first dielectric structure along a second direction.

[0110] Example 20 includes an electronic device comprising any one of Examples 17-19, and further includes a spacer structure on the sidewalls of the first gate structure and the second gate structure and extending along a second direction together with the first gate structure and the second gate structure, wherein the first dielectric structure extends beyond the spacer structure along the first direction.

[0111] Example 21 includes the electronic device of Example 20, wherein the second dielectric structure is seamlessly integrated with the spacer structure.

[0112] Example 22 includes the electronic device of Example 20 or 21, wherein the top surface of the second dielectric structure is substantially coplanar with the top surface of the spacer structure.

[0113] Example 23 includes an electronic device of any of Examples 17-22, wherein the first dielectric structure comprises silicon and nitrogen.

[0114] Example 24 includes an electronic device of any one of Examples 17-23, wherein the first dielectric structure includes a dielectric filler and a dielectric liner on the dielectric filler.

[0115] Example 25 includes the electronic device of Example 24, wherein the dielectric filler comprises a low-k dielectric material and the dielectric liner comprises a high-k dielectric material.

[0116] Example 26 includes an electronic device of any of Examples 17-25, wherein the top surface of the first dielectric structure is substantially coplanar with the topmost surfaces of the first semiconductor region and the second semiconductor region.

[0117] Example 27 includes an electronic device of any one of Examples 17-26, wherein a first gate structure includes a first gate electrode on a first gate dielectric, and a second gate structure includes a second gate electrode on a second gate dielectric.

[0118] Example 28 includes the electronic device of Example 27, wherein a first gate dielectric extends along a first sidewall of a first dielectric structure and a first sidewall of a second dielectric structure, and a second gate dielectric extends along a second sidewall of a first dielectric structure and a second sidewall of a second dielectric structure.

[0119] Example 29 includes an electronic device of any of Examples 17-28, wherein the first semiconductor region and the second semiconductor region each include a plurality of semiconductor nanoribbons.

[0120] Example 30 includes the electronic device of Example 29, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0121] Example 31 includes an electronic device of any of Examples 17-30, wherein, along a first direction, a first dielectric structure is longer than a second dielectric structure.

[0122] Example 32 includes an electronic device of any of Examples 17-31, and also includes a printed circuit board, wherein the chip package is coupled to the printed circuit board.

[0123] Example 33 is a method of forming an integrated circuit. The method includes: forming at least two adjacent fins comprising semiconductor material, the fins extending over a substrate and each extending parallel to each other in a first direction; forming a spacer material on and between the at least two adjacent fins; forming a first dielectric structure on the spacer material between the at least two adjacent fins; recessing the spacer material between the at least two adjacent fins; forming a dielectric filler between the at least two adjacent fins and adjacent to the first dielectric structure; recessing the dielectric filler between the at least two adjacent fins; forming a sacrificial gate extending over the semiconductor material of the at least two adjacent fins and over the first dielectric structure in a second direction different from the first direction; forming a recess through the sacrificial gate over the first dielectric structure; forming a spacer structure on the sidewall of the sacrificial gate and within the recess over the first dielectric structure, such that the spacer structure within the recess forms a second dielectric structure; removing the sacrificial gate; and forming a gate structure on the semiconductor material of each of the adjacent fins.

[0124] Example 34 includes the method of Example 33, wherein the spacer material comprises silicon and oxygen.

[0125] Example 35 includes the method of Example 33 or 34, wherein forming the first dielectric structure includes: forming a dielectric liner on a spacer material between at least two adjacent fins; and forming a dielectric filler on the dielectric liner.

[0126] Example 36 includes the method of Example 35, wherein the dielectric filler comprises a low-k dielectric material and the dielectric liner comprises a high-k dielectric material.

[0127] Example 37 is an integrated circuit comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate structure extending in a second direction over the first semiconductor region; a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate structure extending in the second direction over the second semiconductor region; a spacer structure extending along a second direction on the sidewalls of the first and second gate structures and together with the first and second gate structures; a first dielectric structure separating the first gate structure from the second gate structure along the second direction; and a second dielectric structure on the top surface of the first dielectric structure. The second dielectric structure also separates the first gate structure from the second gate structure along the second direction. The second dielectric structure and the spacer structure are a continuum of materials such that there is no seam between the second dielectric structure and the spacer structure.

[0128] Example 38 includes the integrated circuit of Example 37, wherein the second dielectric structure comprises silicon and nitrogen.

[0129] Example 39 includes the integrated circuit of Example 37 or 38, wherein a first distance between the edge of the first dielectric structure and the edge of the first semiconductor region closest to the first dielectric structure along a second direction is substantially the same as a second distance between the edge of the first dielectric structure and the edge of the second semiconductor region closest to the first dielectric structure along a second direction.

[0130] Example 40 includes an integrated circuit of any one of Examples 37-39, wherein a first dielectric structure extends along a third direction through a first portion of the entire height of the first gate structure and the second gate structure, and a second dielectric structure extends along a third direction through a second portion of the entire height of the first gate structure and the second gate structure, the first portion and the second portion together being equal to the entire height of the first gate structure and the second gate structure.

[0131] Example 41 includes an integrated circuit of any of Examples 37-40, wherein the top surface of the second dielectric structure is substantially coplanar with the top surface of the spacer structure.

[0132] Example 42 includes an integrated circuit of any of Examples 37-41, wherein the first dielectric structure comprises silicon and nitrogen.

[0133] Example 43 includes an integrated circuit of any one of Examples 37-42, wherein the first dielectric structure includes a dielectric filler and a dielectric substrate on the dielectric filler.

[0134] Example 44 includes the integrated circuit of Example 43, wherein the dielectric filler comprises a low-k dielectric material and the dielectric liner comprises a high-k dielectric material.

[0135] Example 45 includes an integrated circuit of any one of Examples 37-44, wherein the top surface of the first dielectric structure is substantially coplanar with the topmost surfaces of the first semiconductor region and the second semiconductor region.

[0136] Example 46 includes an integrated circuit of any one of Examples 37-45, wherein a first gate structure includes a first gate electrode on a first gate dielectric, and a second gate structure includes a second gate electrode on a second gate dielectric.

[0137] Example 47 includes the integrated circuit of Example 46, wherein a first gate dielectric extends along a first sidewall of a first dielectric structure and a first sidewall of a second dielectric structure, and a second gate dielectric extends along a second sidewall of a first dielectric structure and a second sidewall of a second dielectric structure.

[0138] Example 48 includes an integrated circuit of any of Examples 37-47, wherein the first semiconductor region and the second semiconductor region each include a plurality of semiconductor nanoribbons.

[0139] Example 49 includes an integrated circuit of Example 48, wherein the plurality of semiconductor nanoribbons include germanium, silicon, or a combination thereof.

[0140] Example 50 includes an integrated circuit of any of Examples 37-49, wherein, along a first direction, a first dielectric structure is longer than a second dielectric structure.

[0141] Example 51 is a die of an integrated circuit that includes any of Examples 37-50.

[0142] The foregoing description of embodiments of the present disclosure has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible according to the present disclosure. The scope of the disclosure is not limited by this detailed description, but rather by the appended claims.

Claims

1. An integrated circuit, comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate structure extending over the second semiconductor region in the second direction; a first dielectric structure between the first semiconductor device and the second semiconductor device and separating the first gate structure from the second gate structure along the second direction, the first dielectric structure extending along a third direction through a portion of an entire height of the first gate structure or the second gate structure; and a second dielectric structure on a top surface of the first dielectric structure, wherein the second dielectric structure also separates the first gate structure from the second gate structure along the second direction, and wherein the second dielectric structure extends along the third direction through a remaining portion of the entire height of the first gate structure or the second gate structure. Each of the first gate structure and the second gate structure has a same height.

2. The integrated circuit of claim 1, wherein, A first distance between the first dielectric structure and an edge of the first semiconductor region closest to the first dielectric structure along the second direction is substantially the same as a second distance between the first dielectric structure and an edge of the second semiconductor region closest to the first dielectric structure along the second direction.

3. The integrated circuit of claim 1, wherein, The first dielectric structure extends beyond the spacer structure along the first direction.

4. The integrated circuit of claim 1, further comprising a spacer structure on sidewalls of the first gate structure and the second gate structure and extending along the second direction with the first gate structure and the second gate structure, wherein, The second dielectric structure is seamlessly integrated with the spacer structure.

5. The integrated circuit of claim 4, wherein, A top surface of the second dielectric structure is substantially coplanar with a top surface of the spacer structure.

6. The integrated circuit of claim 4, wherein, The first dielectric structure includes silicon and nitrogen, and / or the second dielectric structure includes silicon and nitrogen.

7. The integrated circuit of claim 1, wherein, The first dielectric structure includes a dielectric fill and a dielectric liner on the dielectric fill.

8. The integrated circuit of claim 1, wherein, The dielectric fill includes a low-k dielectric material and the dielectric liner includes a high-k dielectric material.

9. The integrated circuit of claim 8, wherein, A top surface of the first dielectric structure is substantially coplanar with topmost surfaces of the first semiconductor region and the second semiconductor region.

10. The integrated circuit according to any one of claims 1 to 9, wherein, The first gate structure includes a first gate electrode on a first gate dielectric, and the second gate structure includes a second gate electrode on a second gate dielectric.

11. The integrated circuit of any one of claims 1 to 9, wherein, The first gate dielectric extends along first sidewalls of the first dielectric structure and the second dielectric structure, and the second gate dielectric extends along second sidewalls of the first dielectric structure and the second dielectric structure.

12. The integrated circuit of claim 11, wherein, The first semiconductor region and the second semiconductor region each include a plurality of semiconductor nanoribbons.

13. The integrated circuit of any one of claims 1 to 9, wherein, ​ 14. The integrated circuit of any one of claims 1 to 9, wherein, Along the first direction, the first dielectric structure is longer than the second dielectric structure.

15. A die comprising the integrated circuit of any one of claims 1-9.

16. An electronic device comprising: a chip package comprising one or more dies, at least one of the one or more dies comprising: a first semiconductor region extending in a first direction from a first source or drain region; a first gate structure extending over the first semiconductor region in a second direction different from the first direction; a second semiconductor region extending in the first direction from a second source or drain region; a second gate structure extending over the second semiconductor region in the second direction; a first dielectric structure separating the first gate structure from the second gate structure along the second direction, the first dielectric structure extending along a third direction through a first portion of an entire height of the first and second gate structures; and a second dielectric structure on a top surface of the first dielectric structure, wherein the second dielectric structure also separates the first gate structure from the second gate structure along the second direction, and wherein the second dielectric structure extends along the third direction through a second portion of the entire height of the first and second gate structures, the first and second portions together equaling the entire height of the first and second gate structures.

17. The electronic device of claim 16, wherein, a first distance between the first dielectric structure and an edge of the first semiconductor region closest to the first dielectric structure along the second direction is substantially the same as a second distance between the first dielectric structure and an edge of the second semiconductor region closest to the first dielectric structure along the second direction.

18. The electronic device according to claim 16 or 17, further comprising a spacer structure on sidewalls of the first and second gate structures and extending along the second direction together with the first and second gate structures, wherein, the first dielectric structure extends beyond the spacer structure along the first direction.

19. Electronic device according to claim 16 or 17, wherein, a top surface of the first dielectric structure is substantially coplanar with topmost surfaces of the first and second semiconductor regions.

20. An integrated circuit comprising: a first semiconductor device having a first semiconductor region extending in a first direction from a first source or drain region and a first gate structure extending over the first semiconductor region in a second direction different from the first direction; a second semiconductor device having a second semiconductor region extending in the first direction from a second source or drain region and a second gate structure extending over the second semiconductor region in the second direction; a spacer structure on sidewalls of the first and second gate structures and extending along the second direction with the first and second gate structures; a first dielectric structure separating the first gate structure and the second gate structure along the second direction; and a second dielectric structure on a top surface of the first dielectric structure, wherein the second dielectric structure also separates the first gate structure and the second gate structure along the second direction, and wherein the second dielectric structure and the spacer structure are a continuous body of material such that there is no seam between the second dielectric structure and the spacer structure.

21. The integrated circuit of claim 20, wherein, a first distance between the first dielectric structure and an edge of the first semiconductor region closest to the first dielectric structure along the second direction is substantially the same as a second distance between the first dielectric structure and an edge of the second semiconductor region closest to the first dielectric structure along the second direction.

22. The integrated circuit of claim 20, wherein, the first dielectric structure extends along a third direction through a first portion of an entire height of the first gate structure and the second gate structure, and the second dielectric structure extends along the third direction through a second portion of the entire height of the first gate structure and the second gate structure, the first portion and the second portion together equaling the entire height of the first gate structure and the second gate structure.

23. The integrated circuit of claim 20, wherein, a top surface of the first dielectric structure is substantially coplanar with topmost surfaces of the first semiconductor region and the second semiconductor region.

24. The integrated circuit of any one of claims 20-23, wherein, the first gate structure includes a first gate electrode on a first gate dielectric, and the second gate structure includes a second gate electrode on a second gate dielectric.

25. The integrated circuit of claim 24, wherein, the first gate dielectric extends along a first sidewall of the first dielectric structure and a first sidewall of the second dielectric structure, and the second gate dielectric extends along a second sidewall of the first dielectric structure and a second sidewall of the second dielectric structure.

Images