Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes: a stretchable lower substrate divided into a first area and a second area different from the first area; a pattern layer disposed on the lower substrate and including a plate pattern disposed in the first region and a line pattern disposed in the second region; a first metal layer disposed on the plate pattern and the line pattern; a circuit element layer disposed on the plate pattern and the first metal layer, and including at least one transistor; a light emitting element provided on the circuit element layer; and a connection line disposed on the line pattern and connected to the circuit element layer. Accordingly, tensile reliability of the display device may be improved.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0120290, filed on September 4, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices and methods of manufacturing the display device, and more particularly to extendable and stretchable display devices and methods of manufacturing the display device. Background Technology

[0004] As display devices used in computer monitors, televisions, mobile phones, etc., there are organic light-emitting displays (OLEDs) that are configured to emit light themselves and liquid crystal displays (LCDs) that require a separate light source.

[0005] The applications of display devices range from computer monitors and televisions to personal mobile devices, and research is being conducted on display devices with wide display areas and reduced size and weight.

[0006] Furthermore, display devices have recently been manufactured by forming display portions, lines, etc., on a flexible substrate made of flexible plastic material. These display devices are manufactured to be stretchable in a specific direction and capable of various shape changes, thus attracting attention as a next-generation display device. Summary of the Invention

[0007] The purpose of this disclosure is to provide a display device and a method for manufacturing the display device, wherein damage to the line pattern provided with connecting lines is suppressed.

[0008] Another objective of this disclosure is to provide a display device with improved tensile reliability and a method for manufacturing the display device.

[0009] Another objective of this disclosure is to provide a display device with improved resolution and a method for manufacturing the display device.

[0010] To achieve the aforementioned objectives, a display device according to embodiments of the present disclosure may include: a stretchable lower substrate divided into a first region and a second region different from the first region; a pattern layer disposed on the lower substrate and including a plate pattern disposed in the first region and a line pattern disposed in the second region; a first metal layer disposed on the plate pattern; a circuit element layer disposed on the plate pattern and the first metal layer and including at least one transistor; a light-emitting element disposed on the circuit element layer; and a connecting line disposed on the line pattern and connected to the circuit element layer, wherein the first metal layer is in an electrically floating state.

[0011] To achieve the aforementioned objectives, a display device according to embodiments of the present disclosure may include: a stretchable lower substrate divided into a first region and a second region different from the first region; a pattern layer disposed on the lower substrate and including a plate pattern disposed in the first region and a line pattern disposed in the second region; a first metal layer disposed on the plate pattern and the line pattern; a circuit element layer disposed on the plate pattern and the first metal layer and including at least one transistor; a light-emitting element disposed on the circuit element layer; and a connecting line disposed on the line pattern and connected to the circuit element layer.

[0012] To achieve the aforementioned objectives, a method for manufacturing a display device according to another embodiment of this disclosure may include: providing a lower substrate divided into a first region and a second region different from the first region; providing a pattern layer on the lower substrate, the pattern layer including a plate pattern configured to overlap with the first region and a line pattern configured to overlap with the second region; providing a first metal layer on the pattern layer, the first metal layer being configured to overlap with at least a portion of the first region and the second region; sequentially providing a first insulating material, a second insulating material, a third insulating material, a fourth insulating material, a fifth insulating material, a sixth insulating material, and a seventh insulating material on the pattern layer and the first metal layer; forming a seventh insulating layer, a sixth insulating layer, and a fifth insulating layer on the plate pattern by removing the seventh insulating material, the sixth insulating material, and the fifth insulating material provided in the second region; and forming a fourth insulating layer, a third insulating layer, a second insulating layer, and a first insulating layer on the plate pattern by removing the fourth insulating material, the third insulating material, the second insulating material, and the first insulating material provided in the second region.

[0013] The purpose of this disclosure is not limited to the purposes mentioned above, and other purposes not mentioned above will be clearly understood by those skilled in the art based on the following description.

[0014] According to the display device and the method of manufacturing the display device according to the embodiments of the present disclosure, when an insulating material disposed above the line pattern is etched while a metal layer is disposed above the line pattern, damage to the line pattern and the boundary between the line pattern and the board pattern by the metal layer can be suppressed during the etching of the insulating material. Therefore, the tensile reliability of the display device can be improved.

[0015] Furthermore, according to the display device and the method of manufacturing the display device according to the embodiments of the present disclosure, the damage to the metal layer above the line pattern and the boundary between the line pattern and the board pattern caused by etching the insulating material is suppressed. This allows the area where a planarization layer is provided on the board pattern to strengthen the boundary between the line pattern and the board pattern to be minimized, or the planarization layer may not be required. Therefore, the size and / or area of ​​the board pattern on which multiple pixels are provided can be reduced, and a high-resolution display device can be achieved.

[0016] The effects of this disclosure are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description other effects not mentioned above.

[0017] The objectives to be achieved by the present disclosure, the means to achieve those objectives, and the effects of the present disclosure do not specify the essential features of the claims, and therefore the scope of the claims is not limited to the contents of this disclosure. Attached Figure Description

[0018] The above and other aspects, features, and other advantages of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 This is a top plan view showing a display device according to an embodiment of the present disclosure;

[0020] Figure 2 It is shown Figure 1 Enlarged top view of example A in section A;

[0021] Figure 3 It shows along Figure 2 The cross-sectional view of the example intercepted by line III-III' shown;

[0022] Figures 4A to 4L This is a process diagram illustrating a method for manufacturing a display device according to an embodiment of the present disclosure;

[0023] Figure 5 It is used for explanation Figure 3 A view of an example of a protective pattern included in a display device;

[0024] Figure 6It is used for explanation Figure 3 A view of another example of a protective pattern included in a display device;

[0025] Figure 7 It shows along Figure 2 A cross-sectional view of another example taken from line III-III' shown;

[0026] Figure 8 This is a process diagram illustrating a method for manufacturing a display device according to an embodiment of the present disclosure;

[0027] Figure 9A It shows along Figure 2 A cross-sectional view of another example taken from line III-III' shown;

[0028] Figure 9B It is used for explanation Figure 9A A view of an example of a protective pattern included in a display device;

[0029] Figure 10A It shows along Figure 2 A cross-sectional view of another example taken from line III-III' shown;

[0030] Figure 10B It is used for explanation Figure 10A A view of an example of a protective pattern included in a display device;

[0031] Figure 11A It shows along Figure 2 A cross-sectional view of another example taken from line III-III' shown;

[0032] Figure 11B It is used for explanation Figure 11A A view of an example of a protective pattern included in a display device;

[0033] Figure 11C It is used for explanation Figure 11A A view of another example of a protective pattern included in a display device;

[0034] Figure 12A It shows along Figure 2 A cross-sectional view of another example taken from line III-III' shown;

[0035] Figure 12B It is used for explanation Figure 12A A view of an example of a protective pattern included in a display device;

[0036] Figures 13A to 13D This is a view used to illustrate a defective portion of a line pattern included in a display device according to a comparative example of this disclosure; and

[0037] Figure 14A and Figure 14B This is a view used to illustrate the line patterns included in a display device according to an embodiment of the present disclosure. Detailed Implementation

[0038] Please refer to the following and appendix. Figure 1 The advantages and features of this disclosure, as well as methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail herein. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided by way of example only so that those skilled in the art can fully understand the disclosure and scope of this disclosure.

[0039] The shapes, dimensions, ratios, angles, numbers, etc., shown in the accompanying drawings to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0040] Even if not explicitly stated, components are interpreted as including the normal tolerance range.

[0041] When using terms such as “on top of,” “above,” “below,” and “beside” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately adjacent” or “directly.”

[0042] When an element or layer is placed "on" another element or layer, the other layer or element can be placed directly on or between the other elements.

[0043] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, in the technical concept of this disclosure, the first component referred to below can be the second component.

[0044] Throughout the specification, similar reference numerals generally denote similar elements.

[0045] For ease of description, the dimensions and thickness of each component shown in the accompanying drawings are illustrated, and this disclosure is not limited to the dimensions and thickness of the components shown.

[0046] Features of various embodiments of this disclosure may be partially or completely adhered to or combined with each other and may be interlocked and operated in technically different ways, and the embodiments may be implemented independently of each other or in relation to each other.

[0047] In the following, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] Figure 1 This is a top plan view showing a display device according to an embodiment of the present disclosure.

[0049] Reference Figure 1 The display device 100 according to embodiments of the present disclosure may include a lower substrate 111, a pattern layer 120, a plurality of pixels PX, a gate driver GD, a data driver DD, and a power supply PS. In embodiments, the display device 100 may further include an upper substrate (e.g., Figure 3 (upper substrate 112 in the middle).

[0050] The lower substrate 111 can support several components of the display device 100, and the upper substrate (e.g., Figure 3 The upper substrate 112 can cover several components of the display device 100. In an embodiment, the lower substrate 111 and the upper substrate 112 can each be a flexible substrate containing a bendable or stretchable insulating material.

[0051] The lower substrate 111 and the upper substrate 112 may each have an elastic modulus ranging from several MPa to several hundred MPa. According to an embodiment, the ductile fracture rate of each of the lower substrate 111 and the upper substrate 112 may be 100% or higher. In this case, the ductile fracture rate refers to the elongation at the point in time when the tensile object breaks or fractures.

[0052] The lower substrate 111 may include a display area AA for displaying an image and a non-display area NA excluding the display area AA. For example, multiple pixels PX, each including display elements and circuit elements, may be provided in the display area AA, and a gate driver GD and a power supply PS configured to operate the multiple pixels PX provided in the display area AA may be provided in the non-display area NA.

[0053] A pattern layer 120 may be formed on the lower substrate 111. In an embodiment, the pattern layer 120 may include a plurality of first plate patterns 121 and a plurality of first line patterns 122 formed in the display area AA, and a plurality of second plate patterns 123 and a plurality of second line patterns 124 formed in the non-display area NA. For example, the plurality of first plate patterns 121 and the plurality of second plate patterns 123 may be arranged in an island-like configuration that is spaced apart from each other. The plurality of first line patterns 122 may connect adjacent first plate patterns 121, and the plurality of second line patterns 124 may connect adjacent first plate patterns 121 and second plate patterns 123, or connect multiple adjacent second plate patterns 123.

[0054] Multiple pixels (PX) can be formed on multiple first board patterns 121, and gate drivers (GD) and power supplies (PS) can be formed on multiple second board patterns 123. Meanwhile, Figure 1 A plurality of first plate patterns 121 and a plurality of second plate patterns 123 are shown, each having a quadrilateral shape. However, the present disclosure is not limited thereto.

[0055] The plurality of first line patterns 122 and the plurality of second line patterns 124 may each have a curved shape (e.g., a sine shape). However, this disclosure is not limited thereto. The plurality of first line patterns 122 and the plurality of second line patterns 124 may each extend in a zigzag shape or have various shapes, such as a shape in which a plurality of rhomboid substrates are connected at their vertices.

[0056] In this embodiment, each of the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 is a rigid pattern. For example, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 may be more rigid than the lower substrate 111 and the upper substrate 112. Therefore, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 may each have an elastic modulus and hardness higher than that of the lower substrate 111. For example, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, and the plurality of second line patterns 124 may each have an elastic modulus 1000 times or more than that of the lower substrate 111 and the upper substrate 112. However, this disclosure is not limited thereto.

[0057] The multiple first plate patterns 121, multiple first line patterns 122, multiple second plate patterns 123 and multiple second line patterns 124 can each be made of a plastic material with a lower flexibility than the lower substrate 111 and the upper substrate 112.

[0058] The gate driver GD can supply gate signals to multiple pixels PX disposed in the display area AA. The gate driver GD includes multiple stages formed on multiple second board patterns 123. Each stage of the gate driver GD can be electrically connected to each other through multiple gate connection lines. Therefore, the gate signal output from any stage can be transmitted to another stage. Each stage can sequentially supply gate voltage to the multiple pixels PX respectively connected to each stage.

[0059] The power supply PS can be connected to the gate driver GD and supply the gate drive voltage and gate clock voltage. Additionally, the power supply PS can be connected to multiple pixels PX and supply pixel drive voltages to them.

[0060] A printed circuit board (PCB) may include controllers such as IC chips and circuitry, memory, and / or processors, and transmits signals and voltages from the controllers to the display elements for operating them. The PCB may include stretchable and non-stretchable areas to ensure flexibility. For example, IC chips, circuitry, memory, and processors can be mounted in the non-stretchable areas. Lines electrically connected to the IC chips, circuitry, memory, and processor can be provided in the stretchable areas.

[0061] The data driver DD can supply data voltage to multiple pixels PX located in the display area AA. The data driver DD can be configured as an IC chip and is therefore called a data integrated circuit (D-IC).

[0062] Figure 2 It is shown Figure 1 An enlarged top view of part A in the diagram.

[0063] Figure 3 It shows along Figure 2 The example cross-sectional view taken by line III-III' is shown.

[0064] at the same time, Figure 3 This is a cross-sectional view showing an example of a display device 100 according to an embodiment of the present disclosure.

[0065] Reference Figures 1 to 3 Multiple first plate patterns 121 can be disposed in the display area AA of the lower substrate 111. Multiple first plate patterns 121 can be disposed on the lower substrate 111 and spaced apart from each other. For example, as... Figure 1 As shown, a plurality of first plate patterns 121 may be arranged in a matrix shape on the lower substrate 111. However, the present disclosure is not limited thereto.

[0066] A pixel PX comprising a plurality of sub-pixels SPX can be provided on the first plate pattern 121. Each of the plurality of sub-pixels SPX may include an LED (or light-emitting element) 170 as a display element and a circuit element, such as at least one transistor T configured to operate the LED 170. However, this is provided for illustrative purposes only. In the sub-pixel SPX, the display element is not limited to LEDs, but may be changed to an organic light-emitting diode.

[0067] Multiple subpixels (SPX) may include red, green, and blue subpixels. However, this disclosure is not limited to this. The colors of the multiple subpixels (SPX) may be changed differently as needed.

[0068] Multiple sub-pixels SPX can be connected to multiple connection lines CL1 and CL2. That is, multiple sub-pixels SPX can be electrically connected to a first connection line CL1 extending in a first direction X, and multiple sub-pixels SPX can be electrically connected to a second connection line CL2 extending in a second direction Y.

[0069] In the following text, reference will be made to Figure 3 The cross-sectional structure of the display area AA of the display device 100 according to an embodiment of the present disclosure is described in more detail.

[0070] First, refer to Figure 3 Multiple first plate patterns 121 can be provided in the display area AA of the lower substrate 111, and multiple first line patterns 122 connecting adjacent first plate patterns 121 can be provided in the display area AA of the lower substrate 111.

[0071] According to the implementation, the display area AA can be divided into multiple areas A1 and A2. For example, in the display area AA of the lower substrate 111 where the pattern layer 120 is provided, the area where multiple first board patterns 121 are provided can be defined as the first area A1, and the area where multiple first line patterns 122 are provided can be defined as the second area A2.

[0072] In one embodiment, a first metal layer 131 may be provided in a first region A1 having a plurality of first plate patterns 121.

[0073] The first metal layer 131 may include a protective pattern SLD. The protective pattern SLD may correspond to a portion of the first metal layer 131 formed above the portion of the first line pattern 122 adjacent to the first plate pattern 121, to suppress damage to the pattern layer 120 (e.g., the first line pattern 122) during the manufacturing process of the display device 100 caused by etching a plurality of insulating layers disposed in the second region A2 where the first line pattern 122 is disposed. More specifically, the protective pattern SLD may be formed by removing (e.g., etching) a portion of the first metal layer 131 disposed in the first region A1 and a portion disposed in the second region A2, to expose the first line pattern 122 after the etching of the plurality of insulating layers disposed in the second region A2.

[0074] According to an embodiment, the protective pattern SLD can be disposed in a portion of the first region A1, which is provided with a plurality of first plate patterns 121. For example, the protective pattern SLD can be disposed at a predetermined interval d between the boundary between the first region A1 and the second region A2. In other words, during the process of removing (e.g., etching) a portion of the first metal layer 131, the protective pattern SLD can be formed not only by removing the second region A2, which is provided with the first line pattern 122, but also by removing the first metal layer 131 disposed in the region adjacent to the boundary between the first region A1 and the second region A2.

[0075] Meanwhile, since the protective pattern SLD is formed by removing at least a portion of the first metal layer 131, the first metal layer 131 (e.g., the protective pattern SLD) can have an electrically floating state without contacting another metal (e.g., an electrode, a wire, etc.).

[0076] The first metal layer 131 (e.g., the protective pattern SLD) may include a transparent conductive material. For example, the first metal layer 131 (e.g., the protective pattern SLD) may include a transparent conductive oxide based on indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and tin oxide (TO). However, this disclosure is not limited thereto. As described above, since the first metal layer 131 (e.g., the protective pattern SLD) includes a transparent material, the display image quality will not degrade even if the first metal layer 131 for protecting the first line pattern 122 is additionally provided during the manufacturing process of the display device 100.

[0077] Reference Figures 4A to 4L The process of depositing the first metal layer 131 and the process of forming a protective pattern SLD by removing at least a portion of the first metal layer 131 are described in more detail.

[0078] A circuit element layer DCL configured to operate as a display element of an LED 170 can be disposed in a first region A1 having a plurality of first board patterns 121. For example, the circuit element layer DCL can be disposed on the plurality of first board patterns 121 and a first metal layer 131. The circuit element layer DCL may include at least one transistor T configured to operate as a display element of the LED 170.

[0079] The circuit element layer DCL may include a plurality of insulating layers disposed sequentially. For example, the plurality of insulating layers may include a first buffer layer 141 (e.g., a main buffer layer or a first insulating layer), a second buffer layer 142 (e.g., an active buffer layer or a second insulating layer), a gate insulating layer 143 (or a third insulating layer), a first interlayer insulating layer 144 (or a fourth insulating layer), a second interlayer insulating layer 145 (or a fifth insulating layer), a third interlayer insulating layer 146 (or a sixth insulating layer), and a passivation layer 147 (or a seventh insulating layer). However, this disclosure is not limited thereto. In addition to the insulating layers mentioned above, various insulating layers may be additionally disposed on the plurality of first board patterns 121, or at least one of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, or the passivation layer 147 may not be included.

[0080] According to an embodiment, the plurality of insulating layers disposed on the plurality of first plate patterns 121 may be disposed in a portion of the first region A1 on which the plurality of first plate patterns 121 are disposed. For example, the first buffer layer 141 at the lowermost end of the plurality of insulating layers disposed on the plurality of first plate patterns 121 may be disposed at a predetermined interval d from the boundary between the first region A1 and the second region A2. For example, the end of the first buffer layer 141 and the end of the protective pattern SLD may overlap.

[0081] Meanwhile, a planarization layer 148, which will be described below, can be provided in a region of the first region A1 where multiple insulating layers disposed on multiple first plate patterns 121 are not provided (e.g., a region where the first buffer layer 141 is disposed at a predetermined interval d between the boundary between the first region A1 and the second region A2).

[0082] At least one metal layer and at least one semiconductor layer constituting a circuit element (e.g., a transistor T) for operating the LED 170 may be included between a plurality of first plate patterns 121 and a plurality of insulating layers disposed on the plurality of first plate patterns 121. For example, at least one metal layer and at least one semiconductor layer may include a second metal layer 132, a semiconductor layer 133, a third metal layer 134, a fourth metal layer 135, a fifth metal layer 136, and a sixth metal layer 137. However, this disclosure is not limited thereto. In addition to the metal layers and semiconductor layers mentioned above, various metal layers and various semiconductor layers may be additionally disposed on the plurality of first plate patterns 121, or at least one of the second metal layer 132, semiconductor layer 133, third metal layer 134, fourth metal layer 135, fifth metal layer 136, or sixth metal layer 137 may not be included.

[0083] More specifically, a first buffer layer 141 (e.g., a main buffer layer) may be provided on the first plate pattern 121. For example, the first buffer layer 141 may be provided on the first plate pattern 121 and cover the first metal layer 131 (e.g., a protective pattern SLD).

[0084] The first buffer layer 141 may include an insulating material and is formed on a plurality of first plate patterns 121 to protect the various components of the display device 100 from the penetration of moisture (H2O) and oxygen (O2) from the lower substrate 111 and the plurality of first plate patterns 121. Depending on the structure or properties of the display device 100, the first buffer layer 141 may not be included.

[0085] In an embodiment, the first buffer layer 141 may be formed only in the region where the lower substrate 111 overlaps with the plurality of first plate patterns 121 and the plurality of second plate patterns 123. As described above, since the first buffer layer 141 may be made of an inorganic material, the display device 100 may be easily damaged or broken during the stretching process. Therefore, the first buffer layer 141 can be patterned in the shapes of the plurality of first plate patterns 121 and the plurality of second plate patterns 123 and formed only on the upper parts of the plurality of first plate patterns 121 and the plurality of second plate patterns 123, and not formed in the region between the plurality of first plate patterns 121 and the plurality of second plate patterns 123. Therefore, in the case of the display device 100 according to the embodiment of the present disclosure, the first buffer layer 141 is formed only in the region overlapping with the plurality of first plate patterns 121 and the plurality of second plate patterns 123, which are rigid patterns. Therefore, even if the display device 100 deforms due to bending or stretching, damage to the various components of the display device 100 can be suppressed. For example, as described above, the first buffer layer 141 may be disposed in at least a portion of the first region A1 and overlap therewith, but not in the second region A2 where the first line pattern 122 is disposed. For example, the first buffer layer 141 may not be disposed in the following region of the first region A1: the region corresponding to the portion spaced apart from the boundary between the first region A1 and the second region A2 by a predetermined interval d.

[0086] A second metal layer 132 may be disposed on the first buffer layer 141. The second metal layer 132 may include various metal materials. In an embodiment, the second metal layer 132 may include a barrier layer (barrier shielding metal (BSM)) and is disposed on a plurality of first plate patterns 121.

[0087] The barrier layer BSM can protect at least a portion of the semiconductor layer 133, such as the active layer ACT of the transistor T. For example, the barrier layer BSM can be disposed on the first buffer layer 141 and overlap with the active layer ACT of the transistor T. Furthermore, in a cross-sectional view, the width of the barrier layer BSM can be equal to or greater than the width of the active layer ACT. However, this disclosure is not limited thereto.

[0088] At the same time, such as Figure 3 As shown, the second metal layer 132 (e.g., the barrier layer BSM) can be connected to another metal layer (e.g., the third metal layer 134 or the fifth metal layer 136) and receive a constant voltage. However, this disclosure is not limited thereto. The barrier layer BSM can be in a floating state with no applied voltage.

[0089] A second buffer layer 142 (e.g., an active buffer layer) can be disposed on the first buffer layer 141. For example, the second buffer layer 142 can be disposed on the first buffer layer 141 and cover the second metal layer 132.

[0090] The second buffer layer 142 may include an insulating material and insulate the second metal layer 132 (e.g., a barrier layer BSM) from the active layer ACT of the transistor T.

[0091] At least one transistor T, comprising a gate electrode GE, an active layer ACT, a source electrode SE, and a drain electrode DE, may be disposed on the second buffer layer 142. However, this disclosure is not limited thereto. According to embodiments, at least one transistor T may also be defined as further comprising a barrier layer BSM.

[0092] A semiconductor layer 133 may be disposed on the second buffer layer 142. The semiconductor layer 133 may include the active layer ACT of the transistor T.

[0093] A gate insulating layer 143 may be disposed on the second buffer layer 142. For example, the gate insulating layer 143 may include an insulating material and be disposed on the second buffer layer 142 to cover the semiconductor layer 133. The gate insulating layer 143 may electrically insulate the gate electrode GE of the transistor T from the active layer ACT.

[0094] A third metal layer 134 may be disposed on the gate insulating layer 143. The third metal layer 134 may include various metal materials. The third metal layer 134 may include the gate electrode GE of the transistor T. Therefore, the gate electrode GE of the transistor T may be insulated from the active layer ACT through the gate insulating layer 143. In addition, the gate electrode GE of the transistor T may overlap with the active layer ACT.

[0095] A first interlayer insulating layer 144 may be disposed on the gate insulating layer 143. For example, the first interlayer insulating layer 144 may be disposed on the gate insulating layer 143 and cover the third metal layer 134.

[0096] The first interlayer insulating layer 144 may include an insulating material and insulate the third metal layer 134 (e.g., the gate electrode GE of transistor T) from the fourth metal layer 135. The fourth metal layer 135 may be disposed on the first interlayer insulating layer 144. The fourth metal layer 135 may include various metallic materials. The fourth metal layer 135 may include an intermediate metal layer IM and a pad electrode PE.

[0097] The intermediate metal layer IM can overlap with the gate electrode GE of the transistor T. Therefore, a capacitor can be formed in the region where the intermediate metal layer IM and the gate electrode GE of the transistor T overlap. For example, when the transistor T is a driving transistor, the gate electrode GE included in the third metal layer 134, the first interlayer insulating layer 144, and the intermediate metal layer IM included in the fourth metal layer 135 can form a storage capacitor. However, the arrangement area of ​​the intermediate metal layer IM is not limited to this. The capacitor can be formed such that the intermediate metal layer IM overlaps with another electrode.

[0098] The pad electrode PE can provide various signals and / or voltages. For example, the pad electrode PE can constitute at least one of the following: a data pad configured to transmit data voltages to a plurality of sub-pixels SPX, a gate pad configured to transmit gate signals to a plurality of sub-pixels SPX, or a voltage pad configured to transmit pixel drive voltages to a plurality of sub-pixels SPX. For this purpose, the pad electrode PE can be electrically connected via at least one contact hole to the connection line CL1 included in the seventh metal layer 138 through the first connection pad CNT1 included in the sixth metal layer 137. Figure 3 (not shown in the diagram) and CL2. Therefore, the data voltage, gate signal and / or pixel drive voltage supplied through the connection lines CL1 and CL2 can be transmitted to the pad electrode PE and provided to the sub-pixel SPX.

[0099] A second interlayer insulation layer 145 may be disposed on the first interlayer insulation layer 144. For example, the second interlayer insulation layer 145 may be disposed on the first interlayer insulation layer 144 and cover the fourth metal layer 135.

[0100] The second interlayer insulating layer 145 may include an insulating material and insulate the fourth metal layer 135 (e.g., the intermediate metal layer IM and the pad electrode PE) and the fifth metal layer 136 (e.g., the source electrode SE and drain electrode DE of transistor T). The fifth metal layer 136 may be disposed on the second interlayer insulating layer 145. The fifth metal layer 136 may include various metallic materials. The fifth metal layer 136 may include the source electrode SE and drain electrode DE of transistor T. The source electrode SE and drain electrode DE of transistor T may be disposed on the same layer and spaced apart from each other.

[0101] The source electrode SE and drain electrode DE of transistor T can be electrically connected to and adjacent to the active layer ACT. A third interlayer insulating layer 146 can be disposed on the second interlayer insulating layer 145. For example, the third interlayer insulating layer 146 can be disposed on the second interlayer insulating layer 145 and cover the fifth metal layer 136.

[0102] The third interlayer insulating layer 146 may include an insulating material and insulate the fifth metal layer 136 (e.g., the source electrode SE and drain electrode DE of transistor T) and the sixth metal layer 137 (e.g., the first connection pad CNT1). The sixth metal layer 137 may be disposed on the third interlayer insulating layer 146. The sixth metal layer 137 may include various metallic materials. The sixth metal layer 137 may include the first connection pad CNT1. The first connection pad CNT1 may be electrically connected to the pad electrode PE via a contact hole and to the connection lines CL1 and CL2 via another contact hole. Therefore, as described above, the data voltage, gate signal, and / or pixel drive voltage supplied through the connection lines CL1 and CL2 can be transmitted to the pad electrode PE and provided to the sub-pixel SPX. A passivation layer 147 may be disposed on the third interlayer insulating layer 146. For example, the passivation layer 147 may be disposed on the third interlayer insulating layer 146 and cover the sixth metal layer 137.

[0103] The passivation layer 147 may include an insulating material. The passivation layer 147 may be configured to cover various metal layers disposed beneath the passivation layer 147 and protect various components disposed beneath the passivation layer 147 (e.g., transistor T, etc.) from the penetration of moisture, oxygen, etc.

[0104] Meanwhile, the second buffer layer 142, gate insulating layer 143, first interlayer insulating layer 144, second interlayer insulating layer 145, third interlayer insulating layer 146, and passivation layer 147 can be patterned and formed only in the regions overlapping with the plurality of first plate patterns 121 (e.g., first region A1). For example, like the first buffer layer 141, the second buffer layer 142, gate insulating layer 143, first interlayer insulating layer 144, second interlayer insulating layer 145, third interlayer insulating layer 146, and passivation layer 147 can each be made of inorganic materials. Therefore, during the stretching process of the display device 100, the display device 100 may be prone to breakage and damage. Therefore, the second buffer layer 142, gate insulating layer 143, first interlayer insulating layer 144, second interlayer insulating layer 145, third interlayer insulating layer 146, and passivation layer 147 can be patterned in the shape of the plurality of first board patterns 121 and formed only above the plurality of first board patterns 121, but not in the region between the plurality of first board patterns 121. For example, the second buffer layer 142, gate insulating layer 143, first interlayer insulating layer 144, second interlayer insulating layer 145, third interlayer insulating layer 146, and passivation layer 147 can be disposed in at least a portion of the first region A1 and overlap therewith, but not in the second region A2 where the first line pattern 122 is disposed. For example, the second buffer layer 142, gate insulating layer 143, first interlayer insulating layer 144, second interlayer insulating layer 145, third interlayer insulating layer 146 and passivation layer 147 may not be provided in the following region of the first region A1: the region corresponds to the portion that is spaced apart from the boundary between the first region A1 and the second region A2 by a predetermined interval d.

[0105] A planarization layer 148 can be formed on the circuit element layer DCL. For example, the planarization layer 148 can be formed on the passivation layer 147. The planarization layer 148 can be disposed between the circuit element layer DCL (e.g., passivation layer 147) and the LED 170.

[0106] Planarization layer 148 can planarize the upper portion of circuit element layer DCL. For example, planarization layer 148 can planarize the upper portion of at least one transistor T included in circuit element layer DCL. Planarization layer 148 can be configured as a single layer or multiple layers and is made of organic material.

[0107] In the implementation method, refer to Figure 3The planarization layer 148 can be configured to cover the top surface of the uppermost insulating layer, the side surface of each of the multiple insulating layers included in the circuit element layer DCL on the plurality of first board patterns 121, and a portion of the top surface of the first board pattern 121. For example, the planarization layer 148 can be configured to cover the top and side surfaces of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147 on the plurality of first board patterns 121. Furthermore, the planarization layer 148 can be configured to surround the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147 together with the plurality of first board patterns 121. Specifically, the planarization layer 148 may be configured to cover the top and side surfaces of the passivation layer 147, the side surfaces of the third interlayer insulating layer 146, the side surfaces of the second interlayer insulating layer 145, the side surfaces of the first interlayer insulating layer 144, the side surfaces of the gate insulating layer 143, the side surfaces of the second buffer layer 142, the side surfaces of the first buffer layer 141, and a portion of the top surfaces of the plurality of first board patterns 121. For example, the planarization layer 148 may be configured to cover the portion corresponding to the area on the top surface of the plurality of first board patterns 121 and the boundary between the first region A1 and the second region A2, spaced apart by a predetermined interval d.

[0108] Therefore, the planarization layer 148 can compensate for the horizontal difference between the side surfaces of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147. Furthermore, the planarization layer 148 can increase the bonding strength with the connection lines CL1 and CL2 disposed on the side surface of the planarization layer 148.

[0109] Reference Figure 3The tilt angle of the side surface of the planarization layer 148 can be smaller than the tilt angle defined by the side surfaces of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147. For example, the side surface of the planarization layer 148 can have a gentler tilt than the tilt defined by the side surfaces of the passivation layer 147, the third interlayer insulating layer 146, the second interlayer insulating layer 145, the first interlayer insulating layer 144, the gate insulating layer 143, the second buffer layer 142, and the first buffer layer 141. Therefore, the connecting lines CL1 and CL2, which are configured to be adjacent to the side surfaces of the planarization layer 148, are configured to have a gentler tilt, such that the stress applied to the connecting lines CL1 and CL2 can be reduced when the display device 100 is stretched. Furthermore, the side surface of the planarization layer 148 may have a relatively gentle slope, thereby suppressing the connection lines CL1 and CL2 from breaking or separating from the side surface of the planarization layer 148.

[0110] Reference Figure 2 and Figure 3 A seventh metal layer 138 can be formed on the planarization layer 148. The seventh metal layer 138 may include multiple interconnect lines CL1 and CL2 and a second interconnect pad CNT2.

[0111] Connectors CL1 and CL2 can be connected to the circuit element layer DCL. For example, connectors CL1 and CL2 can electrically connect multiple pads (e.g., pad electrodes PE) on the first board pattern 121.

[0112] Connecting lines CL1 and CL2 can be disposed on multiple first line patterns 122. Furthermore, connecting lines CL1 and CL2 can even extend on multiple first board patterns 121 to electrically connect to pad electrodes PE on the multiple first board patterns 121. For example, for each of the multiple first line patterns 122, connecting lines CL1 and CL2 can be connected to the side and top surfaces of the planarization layer 148. Meanwhile, the first line patterns 122 may not be disposed in areas between the multiple first board patterns 121 where connecting lines CL1 and CL2 are not disposed.

[0113] The connecting lines CL1 and CL2 may include a first connecting line CL1 and a second connecting line CL2. The first connecting line CL1 and the second connecting line CL2 may be disposed among a plurality of first plate patterns 121. The first connecting line CL1 and the second connecting line CL2 may each comprise a metallic material.

[0114] More specifically, such as Figure 2As shown, the first connecting line CL1 can refer to the line that extends in the first direction X between the multiple first plate patterns 121, and the second connecting line CL2 can refer to the line that extends in the second direction Y between the multiple first plate patterns 121, and the first connecting line CL1 can refer to the line that extends in the second direction Y between the multiple first plate patterns 121.

[0115] Meanwhile, in a typical display device, various lines, such as multiple gate lines and multiple data lines, are arranged between multiple sub-pixels and extend in a straight line. Multiple sub-pixels are connected to a single signal line. Therefore, in a typical display device, various lines, such as gate lines, data lines, high-potential voltage lines, and reference voltage lines, extend on the substrate from one side to the other without interruption.

[0116] In contrast, in the case of the display device 100 according to the embodiments of the present disclosure, various lines such as gate lines, data lines, high-potential voltage lines, reference voltage lines, and initialization voltage lines (which can be considered as straight lines in a general display panel for a display device) can be provided only on the plurality of first plate patterns 121 and the plurality of second plate patterns 123. That is, in the display device 100 according to the embodiments of the present disclosure, straight lines can be provided only on the plurality of first plate patterns 121 and the plurality of second plate patterns 123.

[0117] In the display device 100 according to an embodiment of the present disclosure, pads (e.g., pad electrodes PE) on two adjacent first board patterns 121 can be connected by multiple connection lines CL1 and CL2. Therefore, connection lines CL1 and CL2 can electrically connect the pad electrodes PE on two adjacent first board patterns 121. Thus, the display device 100 according to an embodiment of the present disclosure may include multiple connection lines CL1 and CL2 to electrically connect various lines such as gate lines, data lines, high-potential voltage lines, and reference voltage lines between multiple first board patterns 121.

[0118] For example, gate lines can be disposed on a plurality of first board patterns 121 arranged adjacent to each other in the first direction X, and gate pads included in the pad electrodes PE can be disposed at two opposite ends of the gate lines. In this case, the plurality of gate pads on the plurality of first board patterns 121 arranged adjacent to each other in the first direction X can be interconnected by a first connecting line CL1 used as a gate line. Therefore, the gate lines disposed on the plurality of first board patterns 121 and the first connecting line CL1 disposed on the first line pattern 122 can be used as a single gate line. The gate line can be referred to as a scan signal line. In addition, among all the various lines that can be included in the display device 100, lines extending in the first direction X, such as light-emitting signal lines, low-potential voltage lines, and high-potential voltage lines, can also be electrically connected by the first connecting line CL1, as described above.

[0119] Additionally, the second connection line CL2 can connect data pads on two first board patterns 121 arranged side-by-side within the pad electrode PE, for example, data pads on multiple first board patterns 121 arranged adjacent to each other in the second direction Y. The second connection line CL2 can be used as a data line, a high-potential voltage line, a low-potential voltage line, or a reference voltage line. However, this disclosure is not limited thereto. Internal lines on multiple first board patterns 121 arranged in the second direction Y can be connected by multiple second connection lines CL2 used as data lines, enabling the transmission of a single data voltage.

[0120] like Figure 3 As shown, connecting lines CL1 and CL2 can be configured to be adjacent to the top and side surfaces of the planarization layer 148 disposed on the first line pattern 121. Furthermore, connecting lines CL1 and CL2 can extend to the top surface of the first line pattern 122. For example, connecting lines CL1 and CL2 can be configured to be directly adjacent to the top surface of the first line pattern 122. For example, since the first metal layer 131 disposed on the first line pattern 122 is removed (e.g., etched) before the deposition of connecting lines CL1 and CL2 (i.e., the seventh metal layer 138), the top surface of the first line pattern 122 is exposed during the deposition of the seventh metal layer 138. Therefore, connecting lines CL1 and CL2 included in the seventh metal layer 138 can be deposited to be in direct contact with the top surface of the first line pattern 122.

[0121] However, although not in Figure 3 The first line pattern 122, which is a rigid pattern, is not provided below the first connecting line CL1 and the second connecting line CL2 because the rigid pattern does not need to be provided in the area where the first connecting line CL1 and the second connecting line CL2 are not provided.

[0122] Reference Figure 3 A dam 149 may be formed on the seventh metal layer 138, such as the second connection pad CNT2, the connection lines CL1 and CL2, and the planarization layer 148. The dam 149 may include an insulating material and separate adjacent sub-pixels SPX. The dam 149 may be configured to at least partially cover the connection lines CL1 and CL2 and the planarization layer 148.

[0123] at the same time, Figure 3 The diagram shows that the height of the embankment 149 is lower than the height of the LED 170. However, this disclosure is not limited thereto. The height of the embankment 149 may be equal to the height of the LED 170.

[0124] Reference Figure 3The LED 170 can be disposed on the circuit element layer DCL. For example, the LED 170 can be disposed on the seventh metal layer 138, such as the second connection pad CNT2 and the connection lines CL1 and CL2. The LED 170 may include an n-type layer 171, an active layer 172, a p-type layer 173, an n-electrode 174, and a p-electrode 175. The LED 170 of the display device 100 according to the embodiments of the present disclosure may have a flip-chip structure, wherein the n-electrode 174 and the p-electrode 175 are formed on one surface of the flip-chip structure. However, this is provided for illustrative purposes only, and the structure of the LED 170 is not limited thereto. The LED 170 can be modified and implemented in various ways.

[0125] According to the embodiment, the n-type layer 171 can also be disposed on a separate base substrate made of a light-emitting material.

[0126] An active layer 172 can be disposed on the n-type layer 171. The active layer 172 can be a light-emitting layer disposed in the LED 170 and configured to emit light. A p-type layer 173 can be disposed on the active layer 172.

[0127] As described above, the LED 170 according to embodiments of this disclosure can be manufactured by sequentially stacking an n-type layer 171, an active layer 172, and a p-type layer 173, etching a predetermined portion, and then forming an n-electrode 174 and a p-electrode 175. In this case, the predetermined portion can be a space used to separate the n-electrode 174 and the p-electrode 175. The predetermined portion can be etched such that a portion of the n-type layer 171 is exposed. In other words, the surface of the LED 170 where the n-electrode 174 and the p-electrode 175 are disposed can be a surface with different height levels, rather than a planarized surface.

[0128] An n-electrode 174 can be disposed in the etched area as described above. The n-electrode 174 can be made of a conductive material. Furthermore, a p-electrode 175 can be disposed in the non-etched area. The p-electrode 175 can also be made of a conductive material. For example, the n-electrode 174 can be disposed on the n-type layer 171 exposed by the etching process, and the p-electrode 175 can be disposed on the p-type layer 173. The p-electrode 175 can be made of the same material as the n-electrode 174.

[0129] A bonding layer AD can be provided on the second connection pad CNT2 so that the LED 170 can be bonded to the second connection pad CNT2.

[0130] The bonding layer AD can be a conductive bonding layer made by dispersing conductive balls into an insulating base component. Therefore, when heat or pressure is applied to the bonding layer AD, the conductive balls are electrically connected in the portions where heat or pressure is applied, giving the bonding layer AD conductive properties. Areas not compressed can have insulating properties. The LED 170 can be transferred to the bonding layer AD by applying it to the second connection pad CNT2 using an inkjet printing method or similar means, and the LED 170 can be electrically connected by compressing and heating the second connection pad CNT2. However, except for a portion of the bonding layer AD disposed between the LED 170 and the second connection pad CNT2, other portions of the bonding layer AD can have insulating properties.

[0131] In addition, the second connection pad CNT2 can be electrically connected to the drain electrode DE of transistor T and receive the driving voltage from transistor T for operating LED 170. Figure 3 The diagram shows the second connection pad CNT2 and the drain electrode DE of transistor T connected by direct contact with each other. However, this disclosure is not limited thereto. The second connection pad CNT2 and the drain electrode DE of transistor T can be connected indirectly through another component.

[0132] The upper substrate 112 may be a substrate configured to support various component elements disposed below the upper substrate 112. Specifically, the upper substrate 112 may be formed by coating the lower substrate 111 and the first plate pattern 121 with a material constituting the upper substrate 112 and then curing the material. The upper substrate 112 may be configured to be adjacent to the lower substrate 111, the first plate pattern 121, the first line pattern 122, and the connecting lines CL1 and CL2.

[0133] At the same time, despite Figure 3 Although not shown, a polarizing layer can be provided on the upper substrate 112. The polarizing layer can be used to polarize light entering from the outside of the display device 100 and reduce the reflection of external light. In addition, other optical films, etc., besides the polarizing layer, can be provided on the upper substrate 112.

[0134] Additionally, a filler layer 190 may be disposed on the front surface of the lower substrate 111 and fill the portion between the constituent elements disposed on the upper substrate 112 and the lower substrate 111. The filler layer 190 may be made of a curable adhesive. Specifically, the filler layer 190 may be formed by coating the front surface of the lower substrate 111 with a material constituting the filler layer 190 and curing the material. The filler layer 190 may be disposed between the constituent elements disposed on the upper substrate 112 and the lower substrate 111.

[0135] Figures 4A to 4L This is a process diagram illustrating a method for manufacturing a display device according to an embodiment of the present disclosure.

[0136] at the same time, Figures 4A to 4L It is manufactured according to reference Figure 3 A cross-sectional view of the display device 100 processing according to an embodiment of the present disclosure. For example, Figures 4A to 4L The manufacturing process is shown sequentially according to the reference. Figure 3 The method of display device 100 according to the embodiments of the present disclosure is described.

[0137] At the same time, for ease of description, and reference Figure 1 and Figure 3 Content that is identical in description will not be described again.

[0138] At the same time, refer to Figures 4A to 4L The described insulating, semiconductor, and metal layers can be formed through typical processes used in manufacturing circuit elements (i.e., forming insulating, semiconductor, and metal layers through coating, deposition, etc., and selectively patterning the insulating, semiconductor, and metal layers through photolithography and etching processes to form various types of electrodes, various types of patterns, signal lines, etc.). Therefore, for ease of description, a detailed description of the method will be omitted.

[0139] First, refer to Figure 4A A sacrificial layer SFL can be formed on the mother substrate MSB.

[0140] The mother substrate (MSB) is a substrate used to support the constituent elements disposed on the lower substrate 111 during the manufacturing process of the display device 100. The mother substrate (MSB) can be made of a rigid material. For example, the mother substrate (MSB) can be made of glass. However, this disclosure is not limited thereto.

[0141] The master substrate (MSB) can be used to manufacture multiple display devices 100 simultaneously. For example, multiple units can be defined on the master substrate (MSB), and these units can each correspond to multiple display devices to be manufactured.

[0142] The sacrificial layer SFL formed on the mother substrate MSB is a layer used to separate the lower substrate 111 of the display device 100 from the mother substrate MSB. The sacrificial layer SFL can be made of a material that breaks down interfacial coupling forces when irradiated with a laser beam, thereby reducing the bonding force with the lower substrate 111 of the display device 100. The sacrificial layer SFL can be formed by depositing silicon nitride and silicon oxide on the entire surface of the mother substrate MSB. However, this disclosure is not limited thereto.

[0143] Subsequently, the lower substrate 111 can be disposed on the sacrificial layer SFL. (Refer to...) Figure 3 The lower substrate 111 can be divided into a first region A1 and a second region A2.

[0144] Subsequently, a pattern layer 120 may be provided on the lower substrate 111. For example, the pattern layer 120 may be provided on the lower substrate 111 and include a first plate pattern 121 configured to overlap with a first region A1 of the lower substrate 111 and a first line pattern 122 configured to overlap with a second region A2 of the lower substrate 111.

[0145] Subsequently, further reference Figure 4B A first metal layer 131 can be disposed on the pattern layer 120. For example, the first metal layer 131 can be disposed on the pattern layer 120 and disposed in a portion of the first region A1 and the second region A2.

[0146] Subsequently, a first insulating material to a seventh insulating material 141a, 142a, 143a, 144a, 145a, 146a and 147a can be sequentially disposed on the pattern layer 120 and the first metal layer 131.

[0147] More specifically, firstly, further refer to Figure 4C A first insulating material 141a can be disposed on the first metal layer 131. For example, the first insulating material 141a can be disposed on the first plate pattern 121 and cover the first metal layer 131. The first insulating material 141a can be formed over the first region A1 and the second region A2 of the lower substrate 111.

[0148] The first insulating material 141a may be used to form a reference. Figure 3 The material of the first buffer layer 141 is described.

[0149] Alternatively, a second metal layer 132 may be provided on the first insulating material 141a. In an embodiment, the barrier layer BSM can be formed by applying and depositing the second metal layer 132 onto the first insulating material 141a and then patterning at least a portion of the second metal layer 132.

[0150] Subsequently, further reference Figure 4D A second insulating material 142a can be disposed on the second metal layer 132. For example, the second insulating material 142a can be disposed on the first insulating material 141a and cover the second metal layer 132. The second insulating material 142a can be formed over the first region A1 and the second region A2 of the lower substrate 111.

[0151] The second insulating material 142a may be used to form a reference. Figure 3 The material of the second buffer layer 142 is described.

[0152] Alternatively, a semiconductor layer 133 may be disposed on the second insulating material 142a. In an embodiment, the active layer ACT of the transistor T may be formed by depositing the semiconductor layer 133 onto the second insulating material 142a and then patterning at least a portion of the semiconductor layer 133.

[0153] Subsequently, further reference Figure 4E A third insulating material 143a can be disposed on the semiconductor layer 133. For example, the third insulating material 143a can be disposed on the second insulating material 142a and cover the semiconductor layer 133. The third insulating material 143a can be formed over the first region A1 and the second region A2 of the lower substrate 111.

[0154] The third insulating material 143a may be used to form a reference. Figure 3 The material of the gate insulating layer 143 is described.

[0155] Alternatively, a third metal layer 134 may be disposed on the third insulating material 143a. In an embodiment, the gate electrode GE of the transistor T may be formed by depositing the third metal layer 134 onto the third insulating material 143a and then patterning at least a portion of the third metal layer 134.

[0156] Subsequently, further reference Figure 4F A fourth insulating material 144a may be disposed on the third metal layer 134. For example, the fourth insulating material 144a may be disposed on the third insulating material 143a and cover the third metal layer 134. The fourth insulating material 144a may be formed over the first region A1 and the second region A2 of the lower substrate 111.

[0157] The fourth insulating material 144a may be used to form a reference. Figure 3 The material of the first interlayer insulation layer 144 is described.

[0158] Additionally, a fourth metal layer 135 may be disposed on the fourth insulating material 144a. In an embodiment, an intermediate metal layer IM and a pad electrode PE may be formed by depositing the fourth metal layer 135 onto the fourth insulating material 144a and then patterning at least a portion of the fourth metal layer 135.

[0159] Subsequently, a fifth insulating material 145a can be disposed on the fourth metal layer 135. For example, the fifth insulating material 145a can be disposed on the fourth insulating material 144a and cover the fourth metal layer 135. The fifth insulating material 145a can be formed over the first region A1 and the second region A2 of the lower substrate 111.

[0160] The fifth insulating material 145a can be used to form a reference. Figure 3The material of the second interlayer insulation layer 145 is described.

[0161] Alternatively, a fifth metal layer 136 may be disposed on the fifth insulating material 145a. In an embodiment, the source electrode SE and drain electrode DE of the transistor T may be formed by depositing the fifth metal layer 136 onto the fifth insulating material 145a and then patterning at least a portion of the fifth metal layer 136.

[0162] Subsequently, further reference Figure 4G A sixth insulating material 146a may be disposed on the fifth metal layer 136. For example, the sixth insulating material 146a may be disposed on the fifth insulating material 145a and cover the fifth metal layer 136. The sixth insulating material 146a may be formed over the first region A1 and the second region A2 of the lower substrate 111.

[0163] The sixth insulating material 146a may be used to form a reference. Figure 3 The material of the third interlayer insulation layer 146 is described.

[0164] Alternatively, a sixth metal layer 137 may be provided on the sixth insulating material 146a. In an embodiment, the first connection pad CNT1 may be formed by depositing the sixth metal layer 137 onto the sixth insulating material 146a and then patterning at least a portion of the sixth metal layer 137.

[0165] Subsequently, further reference Figure 4H A seventh insulating material 147a may be disposed on the sixth metal layer 137. For example, the seventh insulating material 147a may be disposed on the sixth insulating material 146a and cover the sixth metal layer 137. The seventh insulating material 147a may be formed over the first region A1 and the second region A2 of the lower substrate 111.

[0166] The seventh insulating material 147a can be used to form a reference. Figure 3 The insulating material of the passivation layer 147 is described.

[0167] Subsequently, further reference Figure 4I The passivation layer 147 (or the seventh insulating layer), the third interlayer insulating layer 146 (or the sixth insulating layer), and the second interlayer insulating layer 145 (or the fifth insulating layer) can be formed by removing (e.g., etching) the seventh insulating material 147a, the sixth insulating material 146a, and the fifth insulating material 145a at least partially by the first mask MK1.

[0168] For example, a passivation layer 147 can be formed by removing a portion of the seventh insulating material 147a disposed in a part of the first region A1 and a portion disposed in the second region A2; a third interlayer insulating layer 146 can be formed by removing a portion of the sixth insulating material 146a disposed in a part of the first region A1 and a portion disposed in the second region A2; and a second interlayer insulating layer 145 can be formed by removing a portion of the fifth insulating material 145a disposed in a part of the first region A1 and a portion disposed in the second region A2. Specifically, the seventh insulating material 147a, the sixth insulating material 146a, and the fifth insulating material 145a disposed in the second region A2 and in a portion of the first region A1 adjacent to the second region A2 can be removed.

[0169] To this end, a photoresist (PR) is applied to a seventh insulating material 147a, a sixth insulating material 146a, and a fifth insulating material 145a disposed in the second region A2 and in a portion of the first region A1 adjacent to the second region A2. The seventh insulating material 147a, the sixth insulating material 146a, and the fifth insulating material 145a corresponding to the second region A2 and the portion of the first region A1 adjacent to the second region A2 are removed (e.g., etched) using a first mask MK1 having a first mask opening portion OP1-MK. The first mask opening portion OP1-MK overlaps with the second region A2 and with a portion of the first region A1 adjacent to the second region A2, such that a first opening portion OP1 corresponding to the first mask opening portion OP1-MK can be formed on the seventh insulating material 147a, the sixth insulating material 146a, and the fifth insulating material 145a. Therefore, a passivation layer 147, a third interlayer insulating layer 146, and a second interlayer insulating layer 145 can be formed.

[0170] According to the embodiment, the passivation layer 147, the third interlayer insulating layer 146, and the second interlayer insulating layer 145 are etched under soft etching conditions, such that the side surface of each of the passivation layer 147, the third interlayer insulating layer 146, and the second interlayer insulating layer 145 can have a tapered structure, the tapered structure having an inclined shape formed by overall tilting.

[0171] Subsequently, further reference Figure 4J The first interlayer insulating layer 144 (or the fourth insulating layer), the gate insulating layer 143 (or the third insulating layer), the second buffer layer 142 (or the second insulating layer) and the first buffer layer 141 (or the first insulating layer) can be formed by at least partially removing (e.g., etching) the fourth insulating material 144a, the third insulating material 143a, the second insulating material 142a and the first insulating material 141a using the second mask MK2.

[0172] For example, a first interlayer insulating layer 144 can be formed by removing a portion of the fourth insulating material 144a disposed in a part of the first region A1 and a portion disposed in the second region A2; a gate insulating layer 143 can be formed by removing a portion of the third insulating material 143a disposed in a part of the first region A1 and a portion disposed in the second region A2; a second buffer layer 142 can be formed by removing a portion of the second insulating material 142a disposed in a part of the first region A1 and a portion disposed in the second region A2; and a first buffer layer 141 can be formed by removing a portion of the first insulating material 141a disposed in a part of the first region A1 and a portion disposed in the second region A2. Specifically, the fourth insulating material 144a, the third insulating material 143a, the second insulating material 142a, and the first insulating material 141a disposed in the second region A2 and in a portion of the first region A1 adjacent to the second region A2 can be removed.

[0173] To this end, a photoresist (PR) is applied to a fourth insulating material 144a, a third insulating material 143a, a second insulating material 142a, and a first insulating material 141a disposed in the second region A2 and in a portion of the first region A1 adjacent to the second region A2. The fourth insulating material 144a, the third insulating material 143a, the second insulating material 142a, and the first insulating material 141a corresponding to the portion of the second region A2 and the first region A1 adjacent to the second region A2 are removed (e.g., etched) by using a second mask MK2 having a second mask opening portion OP2-MK. The second mask opening portion OP2-MK overlaps with the second region A2 and with a portion of the first region A1 adjacent to the second region A2, such that a second opening portion OP2 corresponding to the second mask opening portion OP2-MK can be formed on the fourth insulating material 144a, the third insulating material 143a, the second insulating material 142a, and the first insulating material 141a. Therefore, a first interlayer insulating layer 144, a gate insulating layer 143, a second buffer layer 142, and a first buffer layer 141 can be formed.

[0174] According to an embodiment, the first interlayer insulating layer 144, the gate insulating layer 143, the second buffer layer 142, and the first buffer layer 141 are etched under soft conditions such that the side surface of each of the first interlayer insulating layer 144, the gate insulating layer 143, the second buffer layer 142, and the first buffer layer 141 can have a tapered structure, the tapered structure having an inclined shape formed by overall tilting.

[0175] Meanwhile, since the first metal layer 131 is disposed on at least a portion of the first plate pattern 121 and above the first line pattern 122 during the etching process of the fourth insulating material 144a, the third insulating material 143a, the second insulating material 142a and the first insulating material 141a, including the insulating material, even if the etching process of the fourth insulating material 144a, the third insulating material 143a, the second insulating material 142a and the first insulating material 141a is performed, it is possible to prevent at least a portion of the first plate pattern 121 and the first line pattern 122 from being damaged by the first metal layer 131 during the etching process.

[0176] Subsequently, further reference Figure 4K A protective pattern SLD can be formed by removing (e.g., etching) at least a portion of the first metal layer 131 using a third mask MK3. For example, by performing wet etching on the first metal layer 131 using a third mask MK3 having a third mask opening portion OP3-MK, the third mask opening portion OP3-MK overlapping with the second region A2 and overlapping with a portion of the first region A1 adjacent to the second region A2, such that a third opening portion OP3 corresponding to the third mask opening portion OP3-MK can be formed on the first metal layer 131, and thus a protective pattern SLD can be formed.

[0177] Subsequently, further reference Figure 4L A planarization layer 148 can be formed on the passivation layer 147. For example, the planarization layer 148 can be formed by forming an insulating material constituting the planarization layer on the passivation layer 147 and then patterning the insulating material. For example, the planarization layer 148 can be patterned such that the top surface of at least a portion of the fifth metal layer 136 (e.g., the drain electrode DE of the transistor T) and the top surface of at least a portion of the sixth metal layer 137 (e.g., the first connection pad CNT1) are exposed.

[0178] The planarization layer 148 may be configured to cover the top and side surfaces of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147, and to cover at least a portion of the top surface of the first board pattern 121. Specifically, the planarization layer 148 may be configured to cover the top and side surfaces of the passivation layer 147, the side surface of the third interlayer insulating layer 146, the side surface of the second interlayer insulating layer 145, the side surface of the first interlayer insulating layer 144, the side surface of the gate insulating layer 143, the side surface of the second buffer layer 142, the side surface of the first buffer layer 141, and a portion of the top surface of the plurality of first board patterns 121. For example, the planarization layer 148 may be configured to cover the portion corresponding to a region spaced apart by a predetermined interval d from the top surface of the plurality of first board patterns 121 and the boundary between the first region A1 and the second region A2. Alternatively, the planarization layer 148 may not be set in the second region A2.

[0179] Subsequently, a seventh metal layer 138 can be formed on the planarization layer 148. For example, this includes a second connection pad CNT2 and a connection line CL1. Figure 4L (not shown in the diagram) and the seventh metal layer 138 of CL2 can be disposed on the planarization layer 148.

[0180] The connecting lines CL1 and CL2 can be disposed on at least a portion of the first line pattern 122 disposed in the second region A2 and the first board pattern 121 disposed in the first region A1, and are electrically connected to pads (e.g., pad electrodes PE) disposed on adjacent first board patterns 121.

[0181] At the same time, despite Figures 4A to 4L Not shown in the diagram, but after setting the seventh metal layer 138, the previously referenced... Figure 3 The process described involves setting a dam 149, LED 170, upper substrate 112, etc. on the seventh metal layer 138, and the display device 100 can be manufactured by laser lift-off (LLO) process that separates the sacrificial layer SFL and the mother substrate MSB from the lower substrate 111 of the display device.

[0182] Figure 5 It is used for explanation Figure 3 A view of an example of a protective pattern included in a display device.

[0183] at the same time, Figure 5 It shows Figure 3 An example of the arrangement relationship in a plan view of the components included in the display device 100, among which the first metal layer 131, the circuit element layer DCL and the planarization layer 148 are disposed in the first region A1.

[0184] Reference Figure 5 A circuit element layer DCL can be set in the first region A1, and a planarization layer 148 can be set on the circuit element layer DCL. In this case, as shown in the reference... Figure 3 The planarization layer 148 is configured to surround, together with a plurality of first board patterns 121, a first buffer layer 141, a second buffer layer 142, a gate insulating layer 143, a first interlayer insulating layer 144, a second interlayer insulating layer 145, a third interlayer insulating layer 146, and a passivation layer 147, such that the planarization layer 148 can be configured to surround the circuit element layer DCL. For example, in a plan view, the circuit element layer DCL (e.g., the first buffer layer 141) can overlap with the planarization layer 148 and be spaced apart from the planarization layer 148 by a predetermined interval d.

[0185] Additionally, the first metal layer 131 may include a protective pattern SLD. In a plan view, the protective pattern SLD may be spaced apart from the planarization layer 148 by a predetermined interval d. For example, the protective pattern SLD may be formed by removing (e.g., etching) the first metal layer 131 disposed in the second region A2 and in a portion of the first region A1 where no circuit element layer DCL (e.g., the first buffer layer 141) is disposed, such that the protective pattern SLD may be configured to overlap with the circuit element layer DCL (e.g., the first buffer layer 141) and spaced apart from the planarization layer 148 by a predetermined interval d in a plan view.

[0186] Figure 6 It is used for explanation Figure 3 Another example of a protective pattern included in a display device.

[0187] at the same time, Figure 6 References are shown Figures 3 to 5 The description describes a modified implementation of the protective pattern SLD_1. Therefore, redundant descriptions will not be repeated.

[0188] at the same time, Figure 6 It shows Figure 3 An example of the arrangement relationship in a plan view of the components included in the display device 100, among which the second metal layer 832, the circuit element layer DCL and the planarization layer 148 are disposed in the first region A1.

[0189] Reference Figure 6 A circuit element layer DCL can be set in the first region A1, and a planarization layer 148 can be set on the circuit element layer DCL.

[0190] In an implementation, the protective pattern SLD can be configured as a second metal layer 832. For example, with Figures 3 to 5The configuration shown differs in that the first metal layer 131 is not deposited separately during the manufacturing process of the display device 100. The protective pattern SLD_1 can be formed by performing wet etching on at least a portion of the second metal layer 832 using a third mask MK3 after the processes of forming the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, and the first interlayer insulating layer 144. This process involves depositing the second metal layer 832 on a portion of the first region A1 and the second region A2 on the pattern layer 120, and then etching the first insulating material to the fourth insulating materials 141a, 142a, 143a, and 144a during the manufacturing process of the second metal layer 832.

[0191] In this case, the manufacturing process of the display device 100 can be further simplified because during the etching process of the first insulating material to the fourth insulating materials 141a, 142a, 143a and 144a, a separate metal layer (e.g., the first metal layer 131) can be deposited without additionally to suppress damage to at least a portion of the first line pattern 122 and the first plate pattern 121 included in the pattern layer 120.

[0192] Figure 7 It shows along Figure 2 Another example of a cross-sectional view taken from line III-III' shown.

[0193] at the same time, Figure 7 A cross-sectional structure of a display device 900 according to another embodiment of the present disclosure is shown. For example, Figure 7 The display device 900 shown is a reference. Figure 3 The described display device 100 is a modified embodiment regarding the arrangement area of ​​the first metal layer 931 (e.g., the protective pattern SLD_2). Therefore, redundant descriptions will not be repeated.

[0194] Reference Figure 7 The first metal layer 931 can be disposed in a portion of the first region A1 where a plurality of first plate patterns 121 are provided, and in the second region A2 where a plurality of first line patterns 122 are provided.

[0195] The first metal layer 931 may include a protective pattern SLD_2. As described above, the protective pattern SLD_2 may be included in a portion of the first metal layer 931 formed above the portion of the first line pattern 122 adjacent to the first plate pattern 121, to suppress damage to the pattern layer 120 (e.g., the first line pattern 122) caused by etching of multiple insulating layers disposed in the second region A2 where the first line pattern 122 is disposed during the manufacturing process of the display device 900.

[0196] In the implementation method, compared with the reference Figure 3 Unlike the described display device 100, in the case of a display device 900 according to another embodiment of this disclosure, the process of removing (e.g., etching) the first metal layer 931 may not be included, such as... Figure 7 As shown. Therefore, the first metal layer 931 (e.g., the protective pattern SLD_2) can be provided in a portion of the first region A1 where a plurality of first plate patterns 121 are provided, and in the second region A2 where a plurality of first line patterns 122 are provided. Additionally, the process of removing (e.g., etching) the first metal layer 931 may be omitted.

[0197] Therefore, as Figure 7 As shown, a portion of the top surface of the first metal layer 931 can be covered by the first buffer layer 141, another portion of the top surface of the first metal layer 931 can be covered by the planarization layer 148, and yet another portion of the top surface of the first metal layer 931 can be covered by the connecting line CL1 of the seventh metal layer 138. Figure 7 (not shown in the image) and CL2 cover. For example, the first metal layer 931 may be disposed in the first region A1 between the first plate pattern 121 and the first buffer layer 141 and between the first plate pattern 121 and the planarization layer 148, and in the second region A2 between the first line pattern 122 and the connecting lines CL1 and CL2.

[0198] More specifically, such as Figure 7 As shown, the planarization layer 148 can be configured to cover the top surface of the uppermost insulating layer among the plurality of insulating layers included in the circuit element layer DCL, the side surface of each of the plurality of insulating layers, and a portion of the top surface of the first metal layer 931 disposed in the first region A1. For example, the planarization layer 148 can be configured to cover the top and side surfaces of the passivation layer 147, the side surface of the third interlayer insulating layer 146, the side surface of the second interlayer insulating layer 145, the side surface of the first interlayer insulating layer 144, the side surface of the gate insulating layer 143, the side surface of the second buffer layer 142, the side surface of the first buffer layer 141, and a portion of the top surface of the first metal layer 931.

[0199] In addition, such as Figure 7As shown, connecting lines CL1 and CL2 can be configured to extend from the top surface of the first metal layer 931 disposed in the second region A2 to the side and top surfaces of the planarization layer 148. For example, connecting lines CL1 and CL2 can be configured to be adjacent to the top and side surfaces of the planarization layer 148 disposed on the first plate pattern 121, and connecting lines CL1 and CL2 can be formed to extend to the top surface of the first metal layer 931 disposed on the first line pattern 122. For example, connecting lines CL1 and CL2 can be configured to be directly adjacent to the top surface of the first metal layer 931 disposed on the first line pattern 122. That is, the first line pattern 122 and connecting lines CL1 and CL2 can be spaced apart from each other, and the first metal layer 931 can be disposed between the first line pattern 122 and the connecting lines CL1 and CL2.

[0200] Figure 8 This is a process diagram illustrating a method for manufacturing a display device according to an embodiment of the present disclosure.

[0201] at the same time, Figure 8 It is manufactured according to reference Figure 7 A cross-sectional view of the processing of a display device 900 according to another embodiment of the present disclosure. For example, in accordance with the above reference... Figure 7 In the case of the display device 900 according to another embodiment of the present disclosure, the process of removing (e.g., etching) the first metal layer 931 may not be required. Therefore, manufacturing according to the reference Figures 4A to 4J The processing of the display device 100 according to the embodiments of this disclosure can be performed in a manner substantially the same as or similar to the processing of manufacturing the display device 900 according to another embodiment of this disclosure. Therefore, Figure 8 It is shown in the reference Figures 4A to 4J A cross-sectional view of the process of manufacturing the display device 900 after the manufacturing process described.

[0202] At the same time, for ease of description, and reference Figure 7 Content that is identical in description will not be described again.

[0203] Reference Figure 8 , as reference Figures 4A to 4JAs described above, a sacrificial layer SFL can be formed on the mother substrate MSB. A lower substrate 111, a pattern layer 120, a first metal layer 931, a first insulating material 141a, a second metal layer 132, a second insulating material 142a, a semiconductor layer 133, a third insulating material 143a, a third metal layer 134, a fourth insulating material 144a, a fourth metal layer 135, a fifth insulating material 145a, a fifth metal layer 136, a sixth insulating material 146a, a sixth metal layer 137, and a seventh insulating material 147a can be sequentially disposed on the sacrificial layer SFL. A mask MK1 at least partially removes (e.g., etches) the seventh insulating material 147a, the sixth insulating material 146a, and the fifth insulating material 145a to form a passivation layer 147, a third interlayer insulating layer 146, and a second interlayer insulating layer 145, and a second mask MK2 at least partially removes (e.g., etches) the fourth insulating material 144a, the third insulating material 143a, the second insulating material 142a, and the first insulating material 141a to form a first interlayer insulating layer 144, a gate insulating layer 143, a second buffer layer 142, and a first buffer layer 141.

[0204] Subsequently, a planarization layer 148 can be formed on the passivation layer 147 without removing (e.g., etching) the first metal layer 931. The planarization layer 148 can be formed to cover the top and side surfaces of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147, and to cover the top surface of the first metal layer 931 disposed on the first board pattern 121. Specifically, the planarization layer 148 can be formed to cover the top and side surfaces of the passivation layer 147, the side surface of the third interlayer insulating layer 146, the side surface of the second interlayer insulating layer 145, the side surface of the first interlayer insulating layer 144, the side surface of the gate insulating layer 143, the side surface of the second buffer layer 142, the side surface of the first buffer layer 141, and a portion of the top surface of the first metal layer 931 disposed on the plurality of first board patterns 121.

[0205] Subsequently, a seventh metal layer 138 can be formed on the planarization layer 148. For example, this includes a second connection pad CNT2 and a connection line CL1. Figure 8 (not shown in the diagram) and the seventh metal layer 138 of CL2 can be disposed on the planarization layer 148.

[0206] The connecting lines CL1 and CL2 can be disposed on at least a portion of the first line pattern 122 disposed in the second region A2 and the first board pattern 121 disposed in the first region A1, and are electrically connected to pads (e.g., pad electrodes PE) disposed on adjacent first board patterns 121.

[0207] In one embodiment, connecting lines CL1 and CL2 can be configured to directly contact the top surface of the first metal layer 931 on the first line pattern 122 disposed in the second region A2. That is, the first line pattern 122 and connecting lines CL1 and CL2 can be spaced apart from each other, and the first metal layer 931 can be configured to be disposed between the first line pattern 122 and the connecting lines CL1 and CL2.

[0208] Figure 9A It shows along Figure 2 A cross-sectional view of another example taken from line III-III' shown.

[0209] Figure 9B It is used for explanation Figure 9A A view of an example of a protective pattern included in a display device.

[0210] at the same time, Figure 9A A cross-sectional structure of a display device 1200 according to another embodiment of the present disclosure is shown. For example, Figure 9A The display device 1200 shown is a reference. Figure 3 This describes a modified embodiment of the display device 100 regarding the arrangement area of ​​the planarization layer 1248. Therefore, redundant descriptions will not be repeated.

[0211] at the same time, Figure 9B It shows Figure 9A An example of the arrangement relationship in a plan view of the components included in the display device 1200, among which the first metal layer 131, the circuit element layer DCL and the planarization layer 1248 are disposed in the first region A1.

[0212] Reference Figure 9A A planarization layer 1248 can be formed on the circuit element layer DCL. For example, the planarization layer 1248 can be formed on the passivation layer 147.

[0213] In one embodiment, the planarization layer 1248 may be configured to cover the top surface of the uppermost insulating layer among a plurality of insulating layers included in the circuit element layer DCL. For example, the planarization layer 1248 may be disposed on a plurality of first board patterns 121 and cover a portion of the top surface of the passivation layer 147.

[0214] In an implementation, the planarization layer 1248 may be patterned and formed only in regions overlapping with the plurality of first plate patterns 121 (e.g., first region A1). For example, with reference to... Figure 3Unlike the described display device 100, in the case of the display device 1200 according to another embodiment of the present disclosure, the planarization layer 1248 may not be formed on the side surfaces of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147. For example, during the process of manufacturing the planarization layer 1248, the planarization layer 1248 can be formed by providing an insulating material constituting the planarization layer on the passivation layer 147 and then patterning the insulating material.

[0215] Therefore, the second connecting line CL2_1 included in the seventh metal layer 1238 can be configured to extend from the first line pattern 122 to the side surface of each of the plurality of insulating layers included in the circuit element layer DCL, as well as the side surface and top surface of the planarization layer 1248. For example, the second connection line CL2_1 included in the seventh metal layer 1238 can be configured to abut a portion of the top surface of the passivation layer 147 (e.g., the top surface of the passivation layer 147 on which the planarization layer 1248 is not disposed), the side surface of the passivation layer 147, the side surface of the third interlayer insulating layer 146, the side surface of the second interlayer insulating layer 145, the side surface of the first interlayer insulating layer 144, the side surface of the gate insulating layer 143, the side surface of the second buffer layer 142, and the side surface of the first buffer layer 141 from the top surface and side surface of the planarization layer 1248 disposed on the first plate pattern 121, and the side surface of the passivation layer 147, the side surface of the third interlayer insulating layer 146, the side surface of the second interlayer insulating layer 145, the side surface of the first interlayer insulating layer 144, the side surface of the gate insulating layer 143, the side surface of the second buffer layer 142, and the side surface of the first buffer layer 141, and the second connection line CL2_1 can be formed to extend to the top surface of the first line pattern 122 disposed in the second region A2.

[0216] Meanwhile, in a typical stretchable display device, the planarization layer is deposited not only to planarize the upper part of the circuit element layer DCL, but also to reinforce the boundary between the first line pattern and the first board pattern, which may be damaged during the etching of the insulating material. In the case of the display device 1200 according to an embodiment of the present disclosure, the first metal layer 131 protects the first line pattern 122 and the first board pattern 121, and suppresses damage to the first line pattern 122 and the first board pattern 121 during the etching of the insulating material during the manufacturing process of the display device 1200. Therefore, even if the planarization layer 1248 is not formed on the boundary between the first board pattern 121 and the first line pattern 122, for example, on the top surface of the portion of the first board pattern 121 adjacent to the first line pattern 122, a display device 1200 in which damage to the first line pattern 122 and the first board pattern 121 is minimized (e.g., eliminated) can be manufactured.

[0217] Also, refer to Figure 9BThe planarization layer 1248 is formed only on a portion of the top surface of the passivation layer 147, and not on the side surfaces of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147. This allows the planarization layer 1248 to overlap with the circuit element layer DCL in the planar view, and is formed within a narrower area than the circuit element layer DCL (e.g., the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147 included in the circuit element layer DCL). For example, as... Figure 9B As shown in the planar diagram, the circuit element layer DCL can be configured to have a shape surrounding the planarization layer 1248.

[0218] Therefore, in a planar view, the protective pattern SLD included in the first metal layer 131 can be configured not to overlap with the planarization layer 1248. For example, since the planarization layer 1248 is only disposed on a portion of the top surface of the passivation layer 147, in a planar view, the protective pattern SLD can be configured to overlap with the circuit element layer DCL but not with the planarization layer 1248.

[0219] In addition, such as Figure 9A and Figure 9B As shown, since the planarization layer 1248 is only disposed on a portion of the top surface of the passivation layer 147, the end of the protective pattern SLD included in the first metal layer 131 can be adjacent to the boundary between the first region A1 and the second region A2, that is, the boundary between the first plate pattern 121 and the first line pattern 122.

[0220] As described above, in the case of the display device 1200 according to another embodiment of the present disclosure, the first board pattern 121 can be formed to ensure only the area where the circuit element layer DCL is provided, without the need to provide an additional area of ​​the planarization layer 1248. That is, the first board pattern 121 included in the display device 1200 according to another embodiment of the present disclosure does not need to ensure that it is consistent with the referenced area. Figure 3 The area corresponding to the predetermined interval d described. Therefore, the size and / or area of ​​the first plate pattern 121 can be reduced, and a high-resolution display device 1200 can be realized.

[0221] Figure 10A It shows along Figure 2 A cross-sectional view of another example taken from line III-III' shown.

[0222] Figure 10B It is used for explanation Figure 10A A view of an example of a protective pattern included in a display device.

[0223] at the same time, Figure 10A A cross-sectional structure of a display device 1300 according to another embodiment of the present disclosure is shown. For example, Figure 10A The display device 1300 shown is a reference. Figure 3 The described display device 100 is a modified embodiment with a configuration that does not include a separate planarization layer. Therefore, redundant descriptions will not be repeated.

[0224] at the same time, Figure 10B It shows Figure 10A An example of the arrangement relationship in a plan view between the first metal layer 131 and the circuit element layer DCL disposed in the first region A1 among the components included in the display device 1300.

[0225] Reference Figure 10A A passivation layer 1347 can be provided on the third interlayer insulating layer 146 of the circuit element layer DCL. For example, the passivation layer 1347 can be provided on the third interlayer insulating layer 146 and cover the sixth metal layer 137.

[0226] Figure 10A and Figure 10B In another embodiment of the present disclosure, the display device 1300 does not include a separate planarization layer, and the passivation layer 1347 can be used as a planarization layer. That is, the passivation layer 1347 can be disposed on the uppermost part of the circuit element layer DCL, and planarize the upper part of the circuit element layer DCL. Therefore, as... Figure 10A As shown, the passivation layer 1347 can have a flat top surface. For example... Figure 10A and Figure 10B As shown, the display device 1300 may not include a separate planarization layer.

[0227] Therefore, the second connection line CL2_2 included in the seventh metal layer 1338 can be configured to extend from the first line pattern 122 to the side surface of each of the plurality of insulating layers included in the circuit element layer DCL and the top surface of the uppermost insulating layer among the plurality of insulating layers. For example, the second connection line CL2_2 included in the seventh metal layer 1338 can be configured to abut the side surface of the third interlayer insulating layer 146, the side surface of the second interlayer insulating layer 145, the side surface of the first interlayer insulating layer 144, the side surface of the gate insulating layer 143, the side surface of the second buffer layer 142, and the side surface of the first buffer layer 141 from the top surface and side surface of the passivation layer 1347 disposed on the first plate pattern 121, and the second connection line CL2_2 can be formed to extend to the top surface of the first line pattern 122 disposed in the second region A2.

[0228] Meanwhile, in a typical stretchable display device, the planarization layer is deposited not only to planarize the upper portion of the circuit element layer DCL, but also to reinforce the boundary between the first line pattern and the first board pattern, which may be damaged during the etching of the insulating material. In the case of the display device 1300 according to an embodiment of the present disclosure, the passivation layer 1347 is used to planarize the upper portion of the circuit element layer DCL, and the first metal layer 131 protects the first line pattern 122 and the first board pattern 121, and suppresses damage to the first line pattern 122 and the first board pattern 121 during the etching of the insulating material during the manufacturing process of the display device 1300. Therefore, even without a separate planarization layer, it is possible to manufacture a display device 1300 in which the upper portion of the circuit element layer DCL is planarized and damage to the first line pattern 122 and the first board pattern 121 is minimized (e.g., eliminated).

[0229] Also, refer to Figure 10B Since the display device 1300 according to another embodiment of the present disclosure does not include a separate planarization layer, the first board pattern 121 can be formed to ensure only the area where the circuit element layer DCL is disposed, without requiring an additional area for the planarization layer. In other words, the first board pattern 121 included in the display device 1300 according to another embodiment of the present disclosure does not need to ensure that it is consistent with the referenced area. Figure 3 The area corresponding to the predetermined interval d described. Therefore, the size and / or area of ​​the first plate pattern 121 can be reduced, and a high-resolution display device 1300 can be realized.

[0230] Figure 11A It shows along Figure 2 A cross-sectional view of another example taken from line III-III' shown.

[0231] Figure 11B It is used for explanation Figure 11A A view of an example of a protective pattern included in a display device.

[0232] Figure 11C It is used for explanation Figure 11A Another example of a protective pattern included in a display device.

[0233] at the same time, Figure 11A A cross-sectional structure of a display device 1400 according to another embodiment of the present disclosure is shown. For example, Figure 11A The display device 1400 shown is a reference. Figure 7 This describes a modified embodiment of the display device 900 regarding the arrangement area of ​​the planarization layer 1448. Therefore, redundant descriptions will not be repeated.

[0234] at the same time, Figure 11B and Figure 11C It shows Figure 11A An example of the arrangement relationship in a plan view of the components included in the display device 1400, which are disposed in the first region A1, such as the first metal layer 931, the circuit element layer DCL, and the planarization layers 1448 and 1448_1.

[0235] Reference Figure 11A A planarization layer 1448 can be formed on the circuit element layer DCL. For example, the planarization layer 1448 can be formed on the passivation layer 147.

[0236] In an embodiment, the planarization layer 1448 may be configured to cover the top surface of the uppermost insulating layer among a plurality of insulating layers included in the circuit element layer DCL. For example, the planarization layer 1448 may be disposed on a plurality of first board patterns 121 and cover a portion of the top surface of the passivation layer 147.

[0237] In an implementation, the planarization layer 1448 may be patterned and formed only in regions overlapping with the plurality of first plate patterns 121 (e.g., first region A1). For example, with reference to... Figure 7 Unlike the described display device 900, in the case of the display device 1400 according to another embodiment of the present disclosure, the planarization layer 1448 may not be formed on the side surfaces of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147. For example, during the process of manufacturing the planarization layer 1448, the planarization layer 1448 can be formed by providing an insulating material constituting the planarization layer on the passivation layer 147 and then patterning the insulating material.

[0238] Therefore, the second connection line CL2_3 included in the seventh metal layer 1438 can be configured to extend from the top surface of the first metal layer 931 disposed in the second region A2 to the side surface of each of the plurality of insulating layers included in the circuit element layer DCL, as well as the side surface and top surface of the planarization layer 1448. For example, the second connection line CL2_3 included in the seventh metal layer 1438 can be configured to be adjacent to a portion of the top surface of the passivation layer 147 (e.g., the top surface of the passivation layer 147 on which the planarization layer 1448 is not disposed), the side surface of the passivation layer 147, the side surface of the third interlayer insulating layer 146, the side surface of the second interlayer insulating layer 145, the side surface of the first interlayer insulating layer 144, the side surface of the gate insulating layer 143, the side surface of the second buffer layer 142, and the side surface of the first buffer layer 141, and the second connection line CL2_3 can be formed to extend to the top surface of the first metal layer 931 disposed in the second region A2.

[0239] Meanwhile, in a typical stretchable display device, the planarization layer is deposited not only to planarize the upper part of the circuit element layer DCL, but also to reinforce the boundary between the first line pattern and the first board pattern, which may be damaged during the etching of the insulating material. In the case of the display device 1400 according to an embodiment of the present disclosure, the first metal layer 931 protects the first line pattern 122 and the first board pattern 121, and suppresses damage to the first line pattern 122 and the first board pattern 121 during the etching of the insulating material during the manufacturing process of the display device 1400. Therefore, even if the planarization layer 1448 is not formed on the boundary between the first board pattern 121 and the first line pattern 122, for example, on the top surface of the portion of the first board pattern 121 adjacent to the first line pattern 122, a display device 1400 in which damage to the first line pattern 122 and the first board pattern 121 is minimized (e.g., eliminated) can be manufactured.

[0240] Also, refer to Figure 11B The planarization layer 1448 is formed only on a portion of the top surface of the passivation layer 147, and not on the side surfaces of the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147. This allows the planarization layer 1448 to overlap with the circuit element layer DCL in the planar view, and is formed within a narrower area than the circuit element layer DCL (e.g., the first buffer layer 141, the second buffer layer 142, the gate insulating layer 143, the first interlayer insulating layer 144, the second interlayer insulating layer 145, the third interlayer insulating layer 146, and the passivation layer 147 included in the circuit element layer DCL). For example, as... Figure 11BAs shown in the planar diagram, the circuit element layer DCL can be configured to have a shape surrounding the planarization layer 1448.

[0241] Furthermore, in the planar view, the protective pattern SLD_2 included in the first metal layer 931 can be configured not to overlap with the planarization layer 1448. For example, since the planarization layer 1448 is only disposed on a portion of the top surface of the passivation layer 147, in the planar view, the protective pattern SLD_2 can be configured to overlap with the circuit element layer DCL, but not with the planarization layer 1448.

[0242] As described above, in the case of the display device 1400 according to another embodiment of the present disclosure, the first board pattern 121 can be formed to ensure only the area where the circuit element layer DCL is disposed, without the need to provide an additional area of ​​the planarization layer 1448. That is, the first board pattern 121 included in the display device 1400 according to another embodiment of the present disclosure does not need to ensure that it is consistent with the referenced area. Figure 7 The area corresponding to the predetermined interval d described. Therefore, the size and / or area of ​​the first plate pattern 121 can be reduced, and a high-resolution display device 1400 can be realized.

[0243] Furthermore, the planar shape of the planarization layer 1448 is not limited to this, and can be modified and implemented differently. For example, further refer to Figure 11C The planarization layer 1448_1 may include at least one protruding portion PRD that protrudes in one direction. The protruding portion PRD may be disposed in a portion of the boundary between the first plate pattern 121 and the first line pattern 122, for example, in the top surface of a portion of the first plate pattern 121 adjacent to the first line pattern 122, and connected to the protective pattern SLD_2 of the first metal layer 931. Therefore, the boundary between the first plate pattern 121 and the first line pattern 122 can be further strengthened.

[0244] Figure 12A It shows along Figure 2 A cross-sectional view of another example taken from line III-III' shown.

[0245] Figure 12B It is used for explanation Figure 12A A view of an example of a protective pattern included in a display device.

[0246] at the same time, Figure 12A A cross-sectional structure of a display device 1500 according to another embodiment of the present disclosure is shown. For example, Figure 12A The display device 1500 shown is a reference. Figure 7 The described display device 900 is a modified embodiment with a configuration that does not include a separate planarization layer. Therefore, redundant descriptions will not be repeated.

[0247] at the same time, Figure 12B It shows Figure 12A An example of the arrangement relationship in a plan view between the first metal layer 931 and the circuit element layer DCL disposed in the first region A1 among the components included in the display device 1500.

[0248] Reference Figure 12A A passivation layer 1547 can be provided on the third interlayer insulating layer 146 of the circuit element layer DCL. For example, the passivation layer 1547 can be provided on the third interlayer insulating layer 146 and cover the sixth metal layer 137.

[0249] Figure 12A and Figure 12B In another embodiment of the present disclosure, the display device 1500 does not include a separate planarization layer, and the passivation layer 1547 can be used as a planarization layer. That is, the passivation layer 1547 can be disposed on the uppermost part of the circuit element layer DCL, and planarize the upper part of the circuit element layer DCL. Therefore, as... Figure 12A As shown, the passivation layer 1547 can have a flat top surface. For example... Figure 12A and Figure 12B As shown, the display device 1500 may not include a separate planarization layer.

[0250] Therefore, the second connection line CL2_4 included in the seventh metal layer 1538 can be configured to extend from the top surface of the first metal layer 931 disposed in the second region A2 to the side surface of each of the plurality of insulating layers included in the circuit element layer DCL and the top surface of the uppermost insulating layer among the plurality of insulating layers. For example, the second connection line CL2_4 included in the seventh metal layer 1538 can be configured to abut the side surface of the third interlayer insulating layer 146, the side surface of the second interlayer insulating layer 145, the side surface of the first interlayer insulating layer 144, the side surface of the gate insulating layer 143, the side surface of the second buffer layer 142, and the side surface of the first buffer layer 141 from the top surface and side surface of the passivation layer 1547 disposed on the first board pattern 121, and the second connection line CL2_4 can be formed to extend to the top surface of the first line pattern 122 disposed in the second region A2.

[0251] Meanwhile, in a typical stretchable display device, the planarization layer is deposited not only to planarize the upper portion of the circuit element layer DCL, but also to reinforce the boundary between the first line pattern and the first board pattern, which may be damaged during the etching of the insulating material. In the case of the display device 1500 according to an embodiment of the present disclosure, the passivation layer 1547 is used to planarize the upper portion of the circuit element layer DCL, and the first metal layer 931 protects the first line pattern 122 and the first board pattern 121, and suppresses damage to the first line pattern 122 and the first board pattern 121 during the etching of the insulating material during the manufacturing process of the display device 1500. Therefore, even without a separate planarization layer, it is possible to manufacture a display device 1500 in which the upper portion of the circuit element layer DCL is planarized and damage to the first line pattern 122 and the first board pattern 121 is minimized (e.g., eliminated).

[0252] Also, refer to Figure 12B Since the display device 1500 according to another embodiment of the present disclosure does not include a separate planarization layer, the first board pattern 121 can be formed to ensure only the area where the circuit element layer DCL is disposed, without requiring an additional area for the planarization layer. In other words, the first board pattern 121 included in the display device 1500 according to another embodiment of the present disclosure does not need to ensure that it is aligned with the referenced area. Figure 7 The area corresponding to the predetermined interval d described. Therefore, the size and / or area of ​​the first plate pattern 121 can be reduced, and a high-resolution display device 1500 can be realized.

[0253] Figures 13A to 13D This is a view used to illustrate a defective portion of a line pattern included in a display device according to a comparative example of this disclosure.

[0254] Figure 14A and Figure 14B This is a view used to illustrate the line patterns included in a display device according to an embodiment of the present disclosure.

[0255] For example, Figures 13A to 13D This is a photomicrograph of the first line pattern 122_C included in the display device 100_C according to the comparative example of this disclosure. Figure 13A This is a photomicrograph showing an example of the first line pattern 122_C according to the comparative example of this disclosure when viewed from the side surface. Figure 13B This is a photomicrograph showing another example of the first line pattern 122_C according to the comparative example of this disclosure when viewed from the side surface. Figure 13C This is a photomicrograph showing a first line pattern 122_C of a comparative example according to this disclosure when viewed from the top surface, and Figure 13DThese are photomicrographs showing a first plate pattern 121_C and a first line pattern 122_C, as viewed from the top surface, in accordance with the present disclosure.

[0256] in addition, Figure 14A and Figure 14B These are photomicrographs of the first line pattern 122 included in the display device 100 according to an embodiment of the present disclosure. Figure 14A This is a photomicrograph showing the first line pattern 122 according to an embodiment of the present disclosure when viewed from the side surface, and Figure 14B This is a photomicrograph showing the first plate pattern 121 and the first line pattern 122 of an embodiment according to the present disclosure when viewed from the top surface.

[0257] First, refer to Figures 13A to 13D The display device 100_C according to the comparative example of this disclosure may correspond to the display device 100_C manufactured by etching and patterning the insulating material disposed above the first line pattern 122_C during the manufacturing process of the display device 100_C, without a separate first metal layer (e.g., protective pattern) being deposited on the first line pattern 122_C.

[0258] In the case of the display device 100_C according to the comparative example of this disclosure, since a portion of the first line pattern 122_C is also etched during the etching of the insulating material, a severe non-uniformity defect in the form of columnar seams may occur, such as... Figure 13A and Figure 13C As shown. Alternative sites, such as Figure 13B As shown, because a portion of the first line pattern 122_C is also etched during the etching of the insulating material, a defect occurs in the first line pattern 122_C, forming a recessed portion. In this case, as... Figure 13D As shown, the tensile reliability of the display device 100_C cannot be guaranteed because the first line pattern 122_C used to connect the adjacent first plate pattern 121_C is damaged without proper deposition.

[0259] In comparison, refer to Figure 14A and Figure 14B As described above, the display device 100 according to embodiments of the present disclosure can be manufactured by depositing a first metal layer 131 or 931 (e.g., a protective pattern SLD, SLD_1 or SLD_2) onto a first line pattern 122 and etching and patterning an insulating material disposed above the first line pattern 122 during the manufacturing process of the display device 100.

[0260] Therefore, in the case of the display device 100 according to the embodiments of this disclosure, such as Figure 14A As shown, during the etching of the insulating material, the first line pattern 122 is protected by the first metal layer 131 or 931, which can suppress damage caused by the etching process. In this case, as Figure 14B As shown, the first line pattern 122 used to connect adjacent first plate patterns 121 is deposited normally without being damaged, thereby improving the tensile reliability of the display device 100.

[0261] As described above, according to the display device and the method of manufacturing the display device according to the embodiments of the present disclosure, when the metal layer is disposed above the line pattern, the etching process of the insulating material disposed above the line pattern can be performed. This can suppress the damage of the line pattern and the boundary between the line pattern and the board pattern to the metal layer during the etching process of the insulating material. Therefore, the tensile reliability of the display device can be improved.

[0262] Furthermore, according to the display device and the method of manufacturing the display device according to the embodiments of the present disclosure, the damage to the metal layer above the line pattern and the boundary between the line pattern and the board pattern caused by etching the insulating material is suppressed. This allows the area where a planarization layer is provided on the board pattern to strengthen the boundary between the line pattern and the board pattern to be minimized, or the planarization layer may not be required. Therefore, the size and / or area of ​​the board pattern on which multiple pixels are provided can be reduced, and a high-resolution display device can be achieved.

[0263] Display devices according to various embodiments of this disclosure will be described below.

[0264] To achieve the aforementioned objectives, a display device according to embodiments of the present disclosure may include: a stretchable lower substrate divided into a first region and a second region different from the first region; a pattern layer disposed on the lower substrate and including a plate pattern disposed in the first region and a line pattern disposed in the second region; a first metal layer disposed on the plate pattern; a circuit element layer disposed on the plate pattern and the first metal layer and including at least one transistor; a light-emitting element disposed on the circuit element layer; and a connecting line disposed on the line pattern and connected to the circuit element layer, wherein the first metal layer is in an electrically floating state.

[0265] In an implementation, the first metal layer may be configured to be spaced apart from the boundary between the first region and the second region by a predetermined interval.

[0266] In an embodiment, the display device may further include a planarization layer disposed between the circuit element layer and the light-emitting element.

[0267] In an implementation, the circuit element layer may include a plurality of insulating layers arranged sequentially, and the planarization layer may be configured to cover the top surface of the uppermost insulating layer, the side surface of each of the plurality of insulating layers, and a portion of the top surface of the board pattern, and the connecting lines may be configured to extend from the top surface of the line pattern to the side and top surfaces of the planarization layer.

[0268] In an implementation, the circuit element layer may include a plurality of insulating layers arranged sequentially, a planarization layer may be configured to cover the top surface of the uppermost insulating layer among the plurality of insulating layers, and connecting lines may be configured to extend from the top surface of the line pattern to the side surface of each of the plurality of insulating layers as well as the side surface and top surface of the planarization layer.

[0269] In an implementation, in a planar view, the first metal layer may not overlap with the planarization layer.

[0270] In one embodiment, the circuit element layer may include a plurality of insulating layers arranged sequentially, and the connecting lines may be arranged to extend from the top surface of the line pattern to the side surface of each of the plurality of insulating layers and to the top surface of the uppermost insulating layer among the plurality of insulating layers.

[0271] To achieve the aforementioned objectives, a display device according to embodiments of the present disclosure may include: a stretchable lower substrate divided into a first region and a second region different from the first region; a pattern layer disposed on the lower substrate and including a plate pattern disposed in the first region and a line pattern disposed in the second region; a first metal layer disposed on the plate pattern and the line pattern; a circuit element layer disposed on the plate pattern and the first metal layer and including at least one transistor; a light-emitting element disposed on the circuit element layer; and a connecting line disposed on the line pattern and connected to the circuit element layer.

[0272] In one implementation, the first metal layer may be disposed between the online pattern and the connecting lines in the second region.

[0273] In an embodiment, the display device may further include a planarization layer disposed between the circuit element layer and the light-emitting element.

[0274] In an implementation, the circuit element layer may include a plurality of insulating layers arranged sequentially, and the planarization layer may be configured to cover the top surface of the uppermost insulating layer, the side surface of each of the plurality of insulating layers, and a portion of the top surface of the first metal layer disposed in the first region, and the connecting line may be configured to extend from the top surface of the first metal layer disposed in the second region to the side surface and the top surface of the planarization layer.

[0275] In an implementation, the circuit element layer may include a plurality of insulating layers arranged sequentially, a planarization layer may be configured to cover the top surface of the uppermost insulating layer among the plurality of insulating layers, and a connecting line may be configured to extend from the top surface of the first metal layer disposed in the second region to the side surface of each of the plurality of insulating layers as well as the side surface and top surface of the planarization layer.

[0276] In an implementation, in a planar view, the first metal layer may not overlap with the planarization layer.

[0277] In an implementation, the circuit element layer may include a plurality of insulating layers arranged sequentially, and the connecting lines may be configured to extend from the top surface of the first metal layer disposed in the second region to the side surface of each of the plurality of insulating layers and the top surface of the uppermost insulating layer among the plurality of insulating layers.

[0278] Exemplary embodiments of this disclosure can also be described as follows:

[0279] According to an aspect of this disclosure, a display device is provided. The display device includes: a stretchable lower substrate divided into a first region and a second region different from the first region. The display device further includes: a pattern layer disposed on the lower substrate, comprising a plate pattern disposed in the first region and a line pattern disposed in the second region. The display device further includes: a first metal layer disposed on the plate pattern; and a circuit element layer disposed on the plate pattern and the first metal layer, comprising at least one transistor. The display device further includes: a light-emitting element disposed on the circuit element layer; and a connecting line disposed on the line pattern and connected to the circuit element layer. The first metal layer is in an electrically floating state.

[0280] The first metal layer can be configured to be spaced apart from the boundary between the first region and the second region by a predetermined interval.

[0281] The display device may also include a planarization layer disposed between the circuit element layer and the light-emitting element.

[0282] The circuit element layer may include a plurality of insulating layers arranged in sequence, and the planarization layer may be configured to cover the top surface of the uppermost insulating layer, the side surface of each of the plurality of insulating layers, and a portion of the top surface of the board pattern, and the connecting lines may be configured to extend from the top surface of the line pattern to the side and top surfaces of the planarization layer.

[0283] The circuit element layer may include a plurality of insulating layers arranged in sequence, a planarization layer may be configured to cover the top surface of the uppermost insulating layer among the plurality of insulating layers, and connecting lines may be configured to extend from the top surface of the line pattern to the side surface of each of the plurality of insulating layers as well as the side surface and top surface of the planarization layer.

[0284] In a planar view, the first metal layer may not overlap with the planarization layer.

[0285] The circuit element layer may include a plurality of insulating layers arranged in sequence, and the connecting lines may be arranged to extend from the top surface of the line pattern to the side surface of each of the plurality of insulating layers and to the top surface of the uppermost insulating layer among the plurality of insulating layers.

[0286] The display device includes: a stretchable lower substrate divided into a first region and a second region different from the first region; and a pattern layer disposed on the lower substrate, including a plate pattern disposed in the first region and a line pattern disposed in the second region. The display device further includes: a first metal layer disposed on the plate pattern and the line pattern; and a circuit element layer disposed on the plate pattern and the first metal layer, including at least one transistor. The display device also includes: a light-emitting element disposed on the circuit element layer; and connecting lines disposed on the line pattern and connected to the circuit element layer.

[0287] The first metal layer can be positioned between the online pattern and the connecting lines in the second area.

[0288] The display device may also include a planarization layer disposed between the circuit element layer and the light-emitting element.

[0289] The circuit element layer may include a plurality of insulating layers arranged in sequence. The planarization layer may be configured to cover the top surface of the uppermost insulating layer, the side surface of each of the plurality of insulating layers, and a portion of the top surface of the first metal layer disposed in the first region. The connecting line may be configured to extend from the top surface of the first metal layer disposed in the second region to the side and top surfaces of the planarization layer.

[0290] The circuit element layer may include a plurality of insulating layers arranged in sequence, a planarization layer may be configured to cover the top surface of the uppermost insulating layer among the plurality of insulating layers, and connecting lines may be configured to extend from the top surface of the first metal layer disposed in the second region to the side surfaces of each of the plurality of insulating layers as well as the side and top surfaces of the planarization layer.

[0291] In a planar view, the first metal layer may not overlap with the planarization layer.

[0292] The circuit element layer may include a plurality of insulating layers arranged in sequence, and the connecting lines may be arranged to extend from the top surface of the first metal layer disposed in the second region to the side surface of each of the plurality of insulating layers and the top surface of the uppermost insulating layer among the plurality of insulating layers.

[0293] According to an aspect of this disclosure, a method for manufacturing a display device is provided. The method includes: providing a lower substrate divided into a first region and a second region different from the first region; and providing a pattern layer on the lower substrate, the pattern layer including a plate pattern configured to overlap with the first region and a line pattern configured to overlap with the second region. The method further includes: providing a first metal layer on the pattern layer, the first metal layer being configured to overlap with at least a portion of the first region and the second region; and sequentially providing a first insulating material, a second insulating material, a third insulating material, a fourth insulating material, a fifth insulating material, a sixth insulating material, and a seventh insulating material on the pattern layer and the first metal layer. The method further includes: forming a seventh insulating layer, a sixth insulating layer, and a fifth insulating layer on the plate pattern by removing the seventh insulating material, the sixth insulating material, and the fifth insulating material provided in the second region. The method further includes: forming a fourth insulating layer, a third insulating layer, a second insulating layer, and a first insulating layer on the plate pattern by removing the fourth insulating material, the third insulating material, the second insulating material, and the first insulating material provided in the second region.

[0294] The method of manufacturing the display device may further include forming a protective pattern on a plate pattern by removing a first metal layer disposed in a second region and in a portion of a first region adjacent to the second region.

[0295] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be construed as falling within the scope of the present disclosure.

Claims

1. A display device comprising: a stretchable lower substrate divided into a first region and a second region different from the first region; a pattern layer provided over the lower substrate and including a plate pattern provided in the first region and a line pattern provided in the second region; a first metal layer provided over the plate pattern; a circuit element layer provided over the plate pattern and the first metal layer and including at least a transistor; a light-emitting element provided over the circuit element layer; and a connection line provided over the line pattern and connected to the circuit element layer, wherein the first metal layer is in an electrically floating state. The first metal layer is provided at a predetermined interval from a boundary between the first region and the second region.

2. The display device according to claim 1, wherein 3. The display device according to claim 1, further comprising: a planarization layer provided between the circuit element layer and the light-emitting element. The circuit element layer includes a plurality of insulating layers provided in sequence, 4. The display device according to claim 3, wherein wherein the planarization layer is provided to cover a top surface of an insulating layer provided at an uppermost portion among the plurality of insulating layers, a side surface of each of the plurality of insulating layers, and a portion of a top surface of the plate pattern, and wherein the connection line is provided to extend from a top surface of the line pattern to the side surface and the top surface of the planarization layer. The circuit element layer includes a plurality of insulating layers provided in sequence, 5. The display device according to claim 3, wherein wherein the planarization layer is provided to cover a top surface of an insulating layer provided at an uppermost portion among the plurality of insulating layers, and wherein the connection line is provided to extend from a top surface of the line pattern to a side surface of each of the plurality of insulating layers and the side surface and the top surface of the planarization layer. The first metal layer does not overlap with the planarization layer in a plan view.

6. The display device of claim 5, wherein, An inclination angle of the side surface of the planarization layer is smaller than an inclination angle defined by the side surfaces of the plurality of insulating layers.

7. The display device according to claim 4, wherein The circuit element layer includes a plurality of insulating layers provided in sequence, and 8. The display device according to claim 1, wherein wherein the connection line is provided to extend from a top surface of the line pattern to a side surface of each of the plurality of insulating layers and a top surface of an insulating layer provided at an uppermost portion among the plurality of insulating layers.

9. A display device comprising: a stretchable lower substrate divided into a first region and a second region different from the first region; a pattern layer provided over the lower substrate and including a plate pattern provided in the first region and a line pattern provided in the second region; a first metal layer provided over the plate pattern and the line pattern; a circuit element layer provided over the plate pattern and the first metal layer and including at least a transistor; a light-emitting element provided over the circuit element layer; and a connection line provided over the line pattern and connected to the circuit element layer. The first metal layer is provided between the line pattern and the connection line in the second region.

11. The display device according to claim 9, further comprising:

10. The display device of claim 9, wherein, a planarization layer provided between the circuit element layer and the light-emitting element. The circuit element layer includes a plurality of insulating layers provided in sequence, ​ 12. The display device of claim 11, wherein, ​ wherein the planarization layer is disposed to cover a top surface of an insulating layer disposed on an uppermost portion among the plurality of insulating layers, a side surface of each of the plurality of insulating layers, and a portion of a top surface of the first metal layer disposed in the first region, and wherein the connection line is disposed to extend from the top surface of the first metal layer disposed in the second region to the side surface and the top surface of the planarization layer.

13. The display device of claim 11, wherein, The circuit element layer includes a plurality of insulating layers disposed in sequence, wherein the planarization layer is disposed to cover a top surface of an insulating layer disposed on an uppermost portion among the plurality of insulating layers, and wherein the connection line is disposed to extend from the top surface of the first metal layer disposed in the second region to the side surface of each of the plurality of insulating layers and the side surface and the top surface of the planarization layer.

14. The display device of claim 13, wherein, In a plan view, the first metal layer does not overlap the planarization layer.

15. The display device of claim 9, wherein, The circuit element layer includes a plurality of insulating layers disposed in sequence, and wherein the connection line is disposed to extend from the top surface of the first metal layer disposed in the second region to the side surface of each of the plurality of insulating layers and the top surface of an insulating layer disposed on an uppermost portion among the plurality of insulating layers.

16. A method of manufacturing a display device, the method comprising: providing a lower substrate divided into a first region and a second region different from the first region; providing a pattern layer on the lower substrate, the pattern layer including a plate pattern configured to overlap the first region and a line pattern configured to overlap the second region; providing a first metal layer on the pattern layer, the first metal layer configured to overlap at least a part of the first region and the second region; sequentially providing a first insulating material, a second insulating material, a third insulating material, a fourth insulating material, a fifth insulating material, a sixth insulating material, and a seventh insulating material on the pattern layer and the first metal layer; forming a seventh insulating layer, a sixth insulating layer, and a fifth insulating layer on the plate pattern by removing the seventh insulating material, the sixth insulating material, and the fifth insulating material provided in the second region; and forming a fourth insulating layer, a third insulating layer, a second insulating layer, and a first insulating layer on the plate pattern by removing the fourth insulating material, the third insulating material, the second insulating material, and the first insulating material provided in the second region.

17. The method according to claim 16, further comprising: forming a protection pattern on the plate pattern by removing the first metal layer provided in the second region and in a portion of the first region adjacent to the second region.

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