Josephson junction, layout structure and manufacturing method thereof

Abstract

The invention discloses a Josephson junction, a layout structure and a manufacturing method of the Josephson junction, and belongs to the technical field of quantum chip manufacturing. The method for manufacturing the layout structure comprises the steps that actual parameters corresponding to preset standard parameters are obtained; according to actual parameters, obtaining a correction amount used for correcting the theoretical line width of the graph; and adjusting the width of the evaporation pattern from the theoretical width of the pattern to the actual width of the pattern according to the correction amount. Through the mode, the layout structure can be improved and manufactured, and the theoretical width of the layout structure is corrected to the actual width, so that the layout structure is matched with the evaporation source, and the quantum device with the target line width is manufactured in an oblique evaporation mode.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of quantum chip manufacturing, and particularly relates to a Josephson junction, a layout structure and a manufacturing method thereof. BACKGROUND

[0002] The Josephson junction or superconducting tunnel junction is generally a structure formed by sandwiching a certain thin barrier layer between two superconductors, for example, a Josephson junction formed by a superconductor (S)-insulator (I)-superconductor (S) structure, referred to as SIS. The Josephson junction described above is a key component for modern quantum computing implementation and application. Specifically, in a superconducting quantum computer, a superconducting quantum bit that performs logical operation can be formed by manufacturing one or more Josephson junctions, together with some other additional circuit elements (capacitive elements, inductive elements, etc.). Therefore, the preparation quality of the Josephson junction is a key to producing the superconducting quantum bit.

[0003] At present, the Josephson junction is formed by evaporation on the surface of the layout structure in batches. As an example below, a plurality of evaporation patterns at different positions are arranged on the surface of the substrate in the layout structure, and an evaporation source is arranged in a space on one side of the layout structure having the evaporation patterns. The evaporation source forms a superconducting metal film in the evaporation patterns in a slant evaporation manner to form the Josephson junction. It is worth noting that since the positions of each evaporation pattern on the surface of the substrate are different, the difference between different positions relative to the evaporation source cannot be ignored, which will cause the actual line width of the formed Josephson junction to be smaller than the preset line width, thereby causing the junction area of the Josephson junction in this batch to be different and the normal resistance to be uneven, so that the production requirements cannot be met. SUMMARY

[0004] The purpose of the present application is to provide a Josephson junction, a layout structure and a manufacturing method thereof, so as to solve the problem that in the prior art, there are a plurality of evaporation patterns on the surface of the layout structure, and the evaporation source performs slant evaporation towards the evaporation patterns, but since the positions of the plurality of evaporation patterns on the surface of the layout structure are different and the difference between them cannot be ignored, the position structure will cause the line width of the formed Josephson junction to be smaller than the preset line width, and the line width between all the Josephson junctions is uneven. Before evaporation, the evaporation patterns of the layout structure are improved, specifically, the line width is compensated, so that the line width of the formed Josephson junction becomes uniform, that is, the junction area is also uniform, so that the normal resistance is uniform, thereby meeting the production requirements.

[0005] To solve the above technical problems, the present application provides a method for manufacturing a layout structure, which comprises:

[0006] obtaining an actual parameter corresponding to a preset standard parameter; wherein the layout structure has an evaporation pattern, the evaporation pattern is used to cooperate with an evaporation source under the standard parameter and manufacture a quantum device in a slant evaporation manner, the standard parameter is associated with a structure of the evaporation pattern and a relative spatial distribution manner of the evaporation pattern and the evaporation source, the quantum device has a target line width, and the evaporation pattern has a pattern theoretical line width associated with the target line width;

[0007] obtaining a correction amount for correcting the pattern theoretical line width according to the actual parameter; and

[0008] adjusting a width of the evaporation pattern from the pattern theoretical width to a pattern actual width according to the correction amount; and the actual parameter is configured to make the evaporation pattern cooperate with the evaporation source under the actual parameter and manufacture the quantum device with the target line width in the slant evaporation manner.

[0009] Preferably, the actual parameter is associated with the structure of the evaporation pattern, the relative spatial distribution manner of the evaporation pattern and the evaporation source, and an actual line width of the quantum device formed by the evaporation pattern cooperating with the evaporation source under the actual parameter.

[0010] Preferably, the method for obtaining the actual line width comprises:

[0011] slant evaporating the layout structure by the evaporation source under the actual parameter to form the quantum device in the trench of the evaporation pattern; and the quantum device has the actual line width.

[0012] Preferably, the layout structure comprises a substrate and a photoresist layer formed on a surface of the substrate and having a standard thickness.

[0013] Preferably, the evaporation pattern is formed by etching the photoresist layer to expose the trench of the substrate, and the trench is used to accommodate the quantum device formed by evaporation.

[0014] The width of the trench is the width of the evaporation pattern.

[0015] Preferably, a deviation angle is formed between an evaporation path between the evaporation source and the layout structure and a side wall of the trench.

[0016] Preferably, the method for obtaining the correction amount for correcting the pattern theoretical line width comprises:

[0017] slant evaporating the layout structure by the evaporation source under the actual parameter to form the quantum device in the trench;

[0018] calculating the correction amount according to the deviation angle and the standard thickness of the photoresist layer; wherein the correction amount is a tangent value corresponding to the thickness of the photoresist layer and the deviation angle.

[0019] Preferably, the method for adjusting the width of the vapor-deposited pattern from the theoretical width of the pattern to the actual width of the pattern includes:

[0020] The photoresist layer on the sidewalls of the trench is etched; the etching amount is the correction amount, so that the width of the trench is widened to the actual width of the pattern.

[0021] This application also provides a layout structure, including:

[0022] The layout structure manufactured by the aforementioned method for manufacturing layout structures.

[0023] This application also provides a Josephson knot, comprising:

[0024] The Josephson junction is formed within the vapor-deposited pattern of the aforementioned layout structure.

[0025] Compared with existing technologies, this application improves and manufactures the pattern structure by first obtaining actual parameters through standard parameters, then obtaining the correction amount of the theoretical linewidth of the vapor-deposited pattern in the pattern structure based on the actual parameters, and finally adjusting the width of the vapor-deposited pattern from the theoretical width to the actual width based on the correction amount. This allows for the compensation and modification of the width of multiple vapor-deposited sites on the surface of the pattern structure according to the actual parameters, so that the pattern structure and the evaporation source can cooperate to form Josephson junctions with uniform linewidths in multiple vapor-deposited sites in the pattern structure. This ensures that all Josephson junctions have uniform linewidths, uniform junction areas, and uniform room-temperature resistance, thereby meeting production and testing requirements. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the structure related to the oblique evaporation coating provided in the embodiments of this application;

[0027] Figure 2 A schematic diagram of the Josephson junction provided in an embodiment of this application;

[0028] Figure 3 This is a schematic diagram of a method for manufacturing a layout structure provided in an embodiment of this application;

[0029] Figure 4 A top view schematic diagram of the oblique evaporation coating provided in the embodiments of this application;

[0030] Figure 5 This is a side view schematic diagram of the oblique evaporation coating provided in the embodiments of this application;

[0031] Figure 6 This is a schematic diagram illustrating the spatial relationship between the evaporation source and the layout structure provided in an embodiment of this application.

[0032] Figure 7This is a schematic diagram illustrating the spatial relationship between the evaporation source and the layout structure provided in an embodiment of this application.

[0033] Figure 8 This is a schematic diagram showing the deviation angle between the evaporation path and the photoresist layer provided in the embodiments of this application. Detailed Implementation

[0034] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0035] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0036] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0037] Quantum computing is a technology that uses the principles of quantum mechanics to process information, and it has enormous potential in realizing qubit and quantum gate operations. The Josephson junction, as a core component in superconducting quantum computing, plays a crucial role.

[0038] A Josephson junction consists of two superconductors sandwiching a very thin insulating layer. This structure allows the superconducting wave function to diffuse and interfere with the other superconductor layer through the insulating layer; this is known as the Josephson junction effect. This effect causes the Josephson junction to exhibit complex nonlinear behavior in circuits, especially under low current conditions, where it exhibits zero energy loss.

[0039] In existing technologies, the fabrication of Josephson junctions in qubits typically employs an oblique evaporation deposition process. For example... Figure 1 and Figure 2As shown, a mask layer is formed on the substrate. Using processes such as exposure, development, and etching, a pattern for fabricating a Josephson junction is formed on the mask layer. This pattern includes a first trench and a second trench that intersect each other perpendicularly. During Josephson junction fabrication in conjunction with an evaporation source, the substrate is tilted at a specific angle. An evaporation particle stream is ejected from the evaporation source onto the tilted substrate, with the first trench facing the direction of the evaporation particle stream. This allows metal material to be deposited on the substrate within the first trench to form the first electrode. However, due to the obstruction of the mask layer, the metal deposited in the first evaporation cannot be deposited on the substrate within the second trench, which intersects perpendicularly with the first trench. Therefore, after obtaining the first electrode, the overall angle of the substrate is adjusted so that the second trench faces the direction of the evaporation particle stream, forming the second electrode of the Josephson junction on the substrate at the bottom of the second trench.

[0040] The performance parameters of Josephson junctions are related to the fabrication conditions. For example, when a barrier layer is obtained through controlled oxidation, the oxidation conditions will affect the performance parameters of the resulting Josephson junction. Therefore, in the actual fabrication process of Josephson junctions, it is common to find that the linewidths of the first or second electrode of each Josephson junction are inconsistent, and the junction area is also inconsistent. The performance parameters of the resulting Josephson junctions are often unstable, making it difficult to fabricate all Josephson junctions that meet the testing requirements on quantum chips.

[0041] It should be noted that Josephson junctions typically operate in ultra-low temperature environments, such as the MC layer of a dilution refrigerator. The resistance of a Josephson junction at room temperature reflects its performance parameters under operating conditions. Therefore, the performance parameters of a Josephson junction can often be obtained by measuring its resistance at room temperature.

[0042] More specifically, during the fabrication of Josephson junctions using the biclinic evaporation process, the distance and angle from the junction to the evaporation source vary at different locations on the chip, resulting in differences in the junction area of ​​each Josephson junction. This leads to non-uniform room-temperature resistance of the Josephson junctions with varying linewidths. In this application, the linewidth of the Josephson junctions is compensated by simulating the distance and angle from the evaporation source to different locations on the chip, thereby obtaining a chip with uniform Josephson junction resistance.

[0043] like Figure 3 As shown in the embodiment of this application, a method for manufacturing a layout structure is provided, the method comprising:

[0044] S1: Obtain the actual parameters corresponding to the preset standard parameters;

[0045] S2: Based on the actual parameters, obtain the correction amount used to correct the theoretical line width of the graphic;

[0046] S3: Based on the correction amount, adjust the width of the vapor-deposited pattern from the theoretical width of the pattern to the actual width of the pattern.

[0047] The layout structure may consist of at least a substrate and a photoresist layer formed on the surface of the substrate. Optionally, the photoresist layer is made of positive or negative photoresist. For example, the photoresist layer is PMMA photoresist, and the vapor deposition pattern is obtained on the photoresist by processes such as exposure and development.

[0048] Furthermore, the layout structure has a vapor deposition pattern, which is used to manufacture quantum devices by cooperating with an evaporation source under standard parameters and by oblique evaporation. The standard parameters are related to the structure of the vapor deposition pattern, the relative spatial distribution of the vapor deposition pattern and the evaporation source, and the quantum device having a target linewidth. The vapor deposition pattern has an image theoretical linewidth related to the target linewidth.

[0049] The above-described method for fabricating quantum devices by combining the layout structure with the evaporation source and by oblique evaporation is exemplified in one specific way: when preparing a Josephson junction, the substrate is placed in the evaporation chamber of an electron beam evaporation device, and an oblique evaporation deposition process is used to tilt the substrate at a certain angle, so that the evaporation particle stream is directed toward the tilted substrate to form a thin metal layer in batches within the evaporation pattern.

[0050] The standard parameters mainly include: the structure of the vapor deposition pattern, which is formed by etching trenches of photoresist to expose the substrate, wherein the thickness of the photoresist, the width of the trenches, and the coordinates of each vapor deposition pattern on the substrate surface are included in the above-mentioned structure of the vapor deposition pattern; the relative spatial distribution of the vapor deposition pattern and the evaporation source, including but not limited to the distance and angle from the evaporation source to each vapor deposition pattern.

[0051] Furthermore, a correction amount is used to correct the theoretical line width of the pattern. The correction amount is relative to the vapor-deposited pattern. The theoretical width of the vapor-deposited pattern is adjusted to achieve the actual width by increasing the correction amount.

[0052] Based on the above conditions, the actual parameters are configured such that the vapor deposition pattern is matched with the evaporation source under the actual parameters, and a quantum device with a target linewidth is manufactured by oblique evaporation.

[0053] Please refer to Figure 4 , Figure 5 and Figure 6 In one embodiment of this application, the radiation source is treated as a point radiation source. The evaporation linewidth of the quantum device at different positions on the substrate will be inconsistent, and the linewidth of the corresponding quantum device can be calculated according to the corresponding spatial relative position relationship.

[0054] In one example, the evaporation source and the layout structure are used to perform a double-oblique evaporation operation, depositing metal films on the layout structure twice. The first evaporation can directly calculate the linewidth of the quantum device located in the trench based on the angle, photoresist thickness, and trench width. In the second evaporation, in addition to considering the angle, photoresist thickness, and trench width, it is important to note that due to the first evaporation, a metal film is formed on the top surface of the photoresist. This film, located on the top surface of the photoresist layer, effectively increases the thickness of the photoresist layer.

[0055] In the first vapor deposition, the actual width of the vapor deposition pattern can be obtained by correcting the amount of correction according to the above steps. In the second vapor deposition, the thickness of the metal film layer deposited on the top surface of the photoresist layer in the first vapor deposition needs to be included in the aforementioned photoresist thickness, and the linewidth of the quantum device formed by the second vapor deposition is compensated using the same calculation method.

[0056] In one embodiment of this application, the actual parameters are related to the structure of the vapor deposition pattern, the relative spatial distribution of the vapor deposition pattern and the evaporation source, and the actual linewidth of the quantum device formed by the vapor deposition pattern and the evaporation source under the actual parameters.

[0057] The vapor deposition pattern is formed by etching trenches in photoresist to expose the substrate. The thickness of the photoresist, the width of the trenches, and the coordinates of each vapor deposition pattern on the substrate surface are included in the structure of the vapor deposition pattern. The relative spatial distribution of the vapor deposition pattern and the evaporation source includes, but is not limited to, the distance and angle from the evaporation source to each vapor deposition pattern.

[0058] In one embodiment of this application, a method for obtaining the actual line width is provided, the method comprising:

[0059] Based on actual parameters, the evaporation source performs oblique evaporation onto the patterned structure, forming quantum devices within the evaporation pattern; these quantum devices possess actual linewidths. The evaporation source ejects a particle stream, forming quantum devices of specific shapes within the evaporation pattern, and the actual linewidth of the quantum devices is primarily limited by the theoretical width of the evaporation pattern.

[0060] In one embodiment of this application, the layout structure includes a substrate and a photoresist layer formed on the surface of the substrate, having a standard thickness. Specifically, the substrate is first selected and cleaned, such as by appropriate cleaning and drying, to ensure good adhesion between the photoresist and the substrate. Heating on a hot plate is typically required to remove surface moisture. Then, the photoresist is dispensed using either static or dynamic spin coating onto a high-speed rotating substrate. Due to centrifugal force, the photoresist diffuses on the substrate to form a uniform thin film, and the thickness of the film can be controlled by adjusting the substrate's rotation speed. Finally, the photoresist is exposed and developed, i.e., the pattern on the mask is transferred to the photoresist using ultraviolet light and dissolved to form a vapor-deposited pattern of theoretical width.

[0061] It is worth noting that the photoresist is etched, and the etched pattern is completely exposed on the substrate. The exposed substrate and the vertical photoresist sidewalls on both sides of the substrate together form a trench. The particle stream is ejected from the evaporation source and forms the desired quantum device in the trench. Here, the width of the trench is the width of the vapor-deposited pattern, or in other words, the trench is equivalent to the vapor-deposited pattern.

[0062] Further, please refer to Figure 7 and Figure 8 There is a deviation angle between the evaporation path and the sidewall of the trench between the evaporation source and the pattern structure. The main reason for this deviation angle is that the pattern structure itself has a non-negligible area, and the evaporation pattern is distributed on the surface of the pattern structure. As a result, not all evaporation patterns can be directly aligned with the evaporation source. Therefore, the evaporation sites located in the peripheral area of ​​the pattern structure will have a very obvious deviation angle, resulting in insufficient linewidth of the quantum device formed within the evaporation pattern.

[0063] In one embodiment of this application, a method is provided for obtaining the correction amount used to correct the theoretical linewidth of a graphic:

[0064] Step 1: Based on actual parameters, the evaporation source performs oblique evaporation towards the pattern structure to form quantum devices within the trenches;

[0065] Step 2: Calculate the correction amount based on the deviation angle and the standard thickness of the photoresist; where the correction amount is the tangent of the deviation angle corresponding to the thickness of the photoresist.

[0066] Furthermore, a method is provided to adjust the width of a vapor-deposited pattern from its theoretical width to its actual width: etching the photoresist layer on the trench sidewalls; the etching amount is a correction amount, widening the trench width to the actual pattern width. That is, the photoresist layer is precisely etched using reactive ion etching or plasma etching, maintaining high selectivity and anisotropy while precisely removing the photoresist layer material corresponding to the correction amount. Here, the etching amount is considered a correction amount, appropriately widening the trench width to achieve the required actual pattern width. This correction is due to the deviation angle between the vapor deposition path and the vapor deposition pattern, resulting in a smaller actual linewidth of the formed quantum device compared to the target linewidth; the linewidth of the quantum device is compensated to reach the target linewidth.

[0067] This application also provides a layout structure, which is manufactured by the aforementioned method for manufacturing layout structures.

[0068] This application also provides a Josephson junction, which is formed within the vapor-deposited pattern of the aforementioned layout structure, and the Josephson junction has a target linewidth. The Josephson junction corresponds to the aforementioned quantum device.

[0069] The intricate fabrication of the substrate layout involves several key steps. The first is substrate preparation, where a photoresist layer is uniformly coated onto the surface. This is followed by selective etching of the photoresist layer to form the vapor-deposited pattern. This process removes only the areas not protected by the photoresist, exposing the surface of these areas and creating trenches to house the Josephson junctions. The dimensions of these trenches are crucial and must match the actual width of the vapor-deposited pattern.

[0070] In one embodiment of this application, the photoresist includes a first photoresist layer and a second photoresist layer stacked sequentially from bottom to top;

[0071] And / or, the vapor deposition pattern includes a first channel and a second channel, both of which are cross-shaped, wherein the first channel and the second channel overlap;

[0072] And / or, the first channel is formed on the first photoresist layer, and the second channel is formed on the second photoresist layer;

[0073] And / or, the width of the first channel is greater than the width of the second channel, such that the second channel partially obscures the first channel.

[0074] Furthermore, the photoresist sensitivity of the first photoresist layer is greater than that of the second photoresist layer. This allows the first photoresist layer to initiate a photochemical reaction with less exposure energy under the same exposure conditions, thereby dissolving during the development process.

[0075] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0076] The above description, based on the embodiments shown in the drawings, details the structure, features, and effects of this application. The above description is only a preferred embodiment of this application, but this application does not limit the scope of implementation to what is shown in the drawings. Any changes made in accordance with the concept of this application, or modifications to equivalent embodiments, that do not exceed the spirit covered by the specification and drawings, should be within the protection scope of this application.

Claims

1. A method of manufacturing a layout structure, characterized by, The method comprises: obtaining an actual parameter corresponding to a preset standard parameter; wherein the layout structure has an evaporation pattern, the evaporation pattern is used to cooperate with an evaporation source under a standard parameter and manufacture a quantum device in a slant evaporation manner, the standard parameter is associated with a structure of the evaporation pattern and a relative spatial distribution manner of the evaporation pattern and the evaporation source, the quantum device has a target line width, and the evaporation pattern has a pattern theoretical line width associated with the target line width; obtaining a correction amount for correcting the pattern theoretical line width according to the actual parameter; and adjusting a width of the evaporation pattern from the pattern theoretical width to a pattern actual width according to the correction amount; the actual parameter is configured to make the evaporation pattern cooperate with the evaporation source under the actual parameter and manufacture the quantum device with the target line width in the slant evaporation manner.

2. The method of claim 1, wherein, The actual parameter is associated with the structure of the evaporation pattern, the relative spatial distribution manner of the evaporation pattern and the evaporation source, and an actual line width of the quantum device formed by the evaporation pattern cooperating with the evaporation source under the actual parameter.

3. The method of claim 2, wherein, The method for obtaining the actual line width comprises: slant evaporation of the evaporation source to the layout structure under the actual parameter to form the quantum device in the trench; the quantum device has the actual line width.

4. The method of claim 1, wherein, The layout structure comprises a substrate and a photoresist layer formed on a surface of the substrate and having a standard thickness.

5. The method of claim 4, wherein, The evaporation pattern is formed by etching the photoresist layer to expose a trench of the substrate, and the trench is used to accommodate the quantum device formed by evaporation; The width of the trench is the width of the evaporation pattern.

6. The method of claim 5, wherein, An evaporation path between the evaporation source and the layout structure and a side wall of the trench form a deviation angle.

7. The method of claim 6, wherein, The method for obtaining the correction amount for correcting the pattern theoretical line width comprises: slant evaporation of the evaporation source to the layout structure under the actual parameter to form the quantum device in the trench; The correction amount is calculated according to the deviation angle and the standard thickness of the photoresist layer; wherein the correction amount is a tangent value corresponding to the thickness of the photoresist layer and the deviation angle.

8. The method of claim 5, wherein, The method for adjusting the width of the evaporation pattern from the pattern theoretical width to the pattern actual width comprises: etching the photoresist layer of the trench side wall; the etching amount is the correction amount, so that the width of the trench is widened to the pattern actual width.

9. A layout structure, characterized by, The method comprises: The layout structure manufactured by the method for manufacturing a layout structure according to any one of claims 1-8.

10. A Josephson junction, characterized in that, The method comprises: The Josephson junction is formed in the evaporation pattern of the layout structure according to claim 9.

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