Semiconductor device and manufacturing method and testing method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method and a testing method thereof. The semiconductor device includes: a substrate including a chip region and a scribe line region surrounding the chip region; the at least one Fabry-Perot cavity structure is located on one side of the substrate in the first direction, the first direction is perpendicular to the substrate, the Fabry-Perot cavity structure is located in the cutting channel area, the Fabry-Perot cavity structure comprises a first metal layer and a second metal layer which are oppositely arranged in the first direction, and the first metal layer and the second metal layer are parallel to each other; the first metal layer is located between the substrate and the second metal layer; the dielectric structure is positioned between the first metal layer and the second metal layer; the cavity structure is located in the medium structure; wherein the stress distribution of the substrate is monitored by using the deformation degree of the Fabry-Perot cavity structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, including but not limited to a semiconductor device and its manufacturing and testing methods. Background Technology

[0002] As semiconductor manufacturing processes advance and breakthroughs in process nodes occur, the number of transistors in a chip increases dramatically, leading to significant improvements in chip performance. However, this advancement also exposes silicon wafers to stress, impacting the chip's electrical performance and reliability. Therefore, monitoring the stress distribution on silicon wafers is crucial to identifying potential problems caused by uneven stress distribution. Summary of the Invention

[0003] To address at least one of the aforementioned technical problems, this disclosure provides a semiconductor device and a method for manufacturing and testing the same.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device comprising: a substrate, the substrate including a chip region and a dicing region surrounding the chip region; at least one Fabry-Perot cavity structure located on one side of the substrate along a first direction, the first direction being perpendicular to the substrate, the Fabry-Perot cavity structure being located in the dicing region, the Fabry-Perot cavity structure including: a first metal layer and a second metal layer disposed opposite to each other along the first direction, the first metal layer and the second metal layer being parallel to each other, the first metal layer being located between the substrate and the second metal layer; a dielectric structure located between the first metal layer and the second metal layer; and a cavity structure located in the dielectric structure; wherein the degree of deformation of the Fabry-Perot cavity structure is used to monitor the stress distribution of the substrate.

[0005] In some embodiments, the cavity structure includes: a first surface and a second surface disposed opposite to each other along the first direction, and at least one third surface located between the first surface and the second surface; wherein the first surface, the second surface, and the at least one third surface together form a closed cavity structure; the dielectric structure includes: a first dielectric layer, the first dielectric layer including a first portion and a second portion connected together, the first portion being in contact with the first metal layer, and the first portion forming the first surface; the second portion forming the third surface; a second dielectric layer, the second dielectric layer being in contact with the second metal layer, and at least a portion of the second dielectric layer forming the third surface.

[0006] In some embodiments, the semiconductor device further includes a plurality of said Fabry-Perot cavity structures surrounding the chip region.

[0007] In some embodiments, along the first direction, the thickness of the first metal layer is greater than the thickness of the second metal layer.

[0008] In some embodiments, the cavity structure includes at least one of nitrogen and an inert gas.

[0009] In some embodiments, the reflectivity of the first metal layer is greater than 85%; the transmittance of the second metal layer is greater than 20%; and the transmittance of both the first dielectric layer and the second dielectric layer is greater than 90%.

[0010] In a second aspect, embodiments of this disclosure provide a method for manufacturing a semiconductor device, the method comprising: providing a substrate, the substrate including a chip region and a dicing region surrounding the chip region; forming at least one Fabry-Perot cavity structure on one side of the substrate along a first direction, the first direction being perpendicular to the substrate, the Fabry-Perot cavity structure being located in the dicing region, the Fabry-Perot cavity structure including: a first metal layer and a second metal layer disposed opposite to each other along the first direction, the first metal layer and the second metal layer being parallel to each other, the first metal layer being located between the substrate and the second metal layer; a dielectric structure located between the first metal layer and the second metal layer; and a cavity structure located in the dielectric structure; wherein the degree of deformation of the Fabry-Perot cavity structure is used to monitor the stress distribution of the substrate.

[0011] In some embodiments, forming at least one Fabry-Perot cavity structure on one side of the substrate along a first direction includes: sequentially forming a first metal layer and an isolation layer on the substrate; etching the isolation layer to form an etching trench, the bottom of the etching trench exposing the first metal layer; forming a first dielectric layer, the first dielectric layer including a first portion covering the bottom of the etching trench, a second portion covering the sidewalls of the etching trench, and a third portion covering the surface of the isolation layer; and forming a sacrificial layer in the etching trench, the surface of the sacrificial layer being substantially flush with the surface of the third portion.

[0012] In some embodiments, forming at least one Fabry-Perot cavity structure on one side of the substrate along a first direction further includes: forming a first material layer on the third portion and the sacrificial layer; etching the first material layer to form an etch hole, the bottom of the etch hole exposing the sacrificial layer; removing the sacrificial layer through the etch hole; forming an initial second material layer on the first material layer to close the etch hole and form the cavity structure; planarizing the initial second material layer to form a second material layer, the first material layer and the second material layer forming a second dielectric layer, the dielectric structure including the first dielectric layer and the second dielectric layer; and forming a second metal layer on the second dielectric layer.

[0013] In some embodiments, the ratio between the size of the etched hole and the size of the etched trench is less than 1 / 3 along the second direction; wherein the first direction and the second direction are perpendicular to each other.

[0014] Thirdly, embodiments of this disclosure provide a testing method applied to a semiconductor device as described in the first aspect of this disclosure; the testing method includes: inputting a first optical signal into a Fabry-Perot cavity structure through a second metal layer; receiving a second optical signal output from the Fabry-Perot cavity structure through the second metal layer; and determining the stress distribution of a substrate based on the first optical signal and the second optical signal.

[0015] In this embodiment, a Fabry-Perot cavity structure is provided in the dicing region of the substrate. The Fabry-Perot cavity structure includes: a first metal layer and a second metal layer disposed opposite to and parallel to each other along a first direction, a dielectric structure located between the first metal layer and the second metal layer, and a cavity structure located in the dielectric structure. In a first aspect, the deformation degree of the Fabry-Perot cavity structure is determined using a first optical signal incident on the Fabry-Perot cavity structure and a second optical signal emitted from the Fabry-Perot cavity structure, thereby determining the local stress distribution of the substrate, to achieve the purpose of monitoring the stress distribution of the substrate using the Fabry-Perot cavity structure. In a second aspect, a semiconductor structure is provided in the chip region of the substrate. Based on the local stress distribution of the substrate, potential problems in the electrical performance and reliability of the semiconductor structure can be identified in a timely manner, thereby accelerating the research and development progress. Attached Figure Description

[0016] Figure 1 A schematic diagram of the base provided for some examples; Figure 2 Schematic diagrams of chip areas and dicing areas provided for some examples; Figure 3 A top view schematic diagram of a semiconductor device provided in some embodiments of this disclosure; Figure 4 A top view schematic diagram of a semiconductor device provided in some other embodiments of this disclosure; Figure 5 A schematic cross-sectional view of a semiconductor device provided in some embodiments of this disclosure; Figure 6 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this disclosure; Figures 7 to 19 A cross-sectional structural diagram of a semiconductor device during the manufacturing process provided in some embodiments of this disclosure; Figure 20 A flowchart illustrating the testing methods provided in some embodiments of this disclosure; Figure 21 A schematic diagram of a test mold provided for some embodiments of this disclosure; Figure 22 This is a schematic diagram of a Fabry-Perot cavity structure provided for some embodiments of this disclosure. Detailed Implementation

[0017] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0018] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0019] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0021] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0024] Here, we first define the various directions that may be involved in the following text. The thickness direction of the substrate is defined as the first direction, that is, the first direction is perpendicular to the substrate. In the plane containing the substrate, intersecting second and third directions are defined, that is, the first direction, the second direction, and the third direction are all perpendicular to each other. In some embodiments, any two of the first direction (i.e., direction D1), the second direction (i.e., direction D2), and the third direction (i.e., direction D3) are perpendicular to each other.

[0025] refer to Figure 1 and Figure 2 , Figure 1 A schematic diagram of the base provided for some examples. Figure 2 This provides a magnified illustration of a single chip region on the substrate and its corresponding dicing area. Combined with... Figure 1 and Figure 2As shown, the substrate 102 includes: a plurality of die areas 104 arranged along the D2 and D3 directions; and scribe lines 106 surrounding the die areas 104. Figure 1 The dashed circle in the middle indicates the first part of the cutting channel area 106, which extends along the D2 direction and is used to separate the chip areas 104 of different rows. Figure 1 The dashed circle in the middle indicates the second part of the cutting channel area 106, which extends along the D3 direction and is used to separate the chip areas 104 of different columns.

[0026] Here, chip region 104 is the area in substrate 102 that is ultimately cut and packaged into an independent functional chip. All core structures used to implement circuit functions, such as transistors, resistors, capacitors, and interconnect metal layers, are integrated in chip region 104.

[0027] Here, the dicing zone 106 is an isolation strip between two adjacent chip regions 104 arranged along the D2 direction or along the D3 direction, and all auxiliary structures are integrated into the dicing zone 106. Firstly, the dicing zone 106 may include a blank area to accommodate the dicing tool and prevent damage to the circuit structure in the chip region 104 during the dicing process. Secondly, the dicing zone 106 may also include test pads, which are connected to test probes to perform electrical testing on the circuit structure in the chip region 104. Thirdly, the dicing zone 106 may also include alignment marks to achieve precise positioning of the photolithography process and ensure the overlay accuracy of each layer of the circuit structure.

[0028] In some examples, conventional methods can monitor the stress distribution or warpage changes of the entire silicon wafer.

[0029] However, the lack of effective monitoring methods for the local stress distribution of silicon wafers makes it difficult to investigate potential problems with the electrical performance and reliability of the circuit structure in the chip area.

[0030] In view of the above, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing and testing the same.

[0031] refer to Figure 3 and Figure 4 , Figure 3 and Figure 4 All of these are top view structural schematic diagrams of the semiconductor devices provided in the embodiments of this disclosure. The following will be combined with... Figure 3 and Figure 4 The shape and location of the Fabry-Perot cavity in semiconductor devices are described.

[0032] like Figure 3As shown, this disclosure provides a semiconductor device 200, which includes: a substrate 202, the substrate 202 including a chip region 204 and a dicing region 206 surrounding the chip region 204; and at least one Fabry-Perot cavity structure 238 located on one side of the substrate 202 along the D1 direction, the Fabry-Perot cavity structure 238 being located in the dicing region 206. Figure 3 The exemplary diagram shows that the orthographic projection shape of the Fabry-Perot cavity structure 238 in the plane (i.e., the D2D3 plane) where the substrate 202 is located is square.

[0033] In some embodiments, substrate 202 may include a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. It may also include other substrates containing semiconductor materials, such as silicon-on-insulator (SOI) substrates, germanium-on-insulator (GeOI) substrates, polycrystalline semiconductor layers on insulating layers, silicon-germanium substrates, etc.

[0034] like Figure 4 As shown, a Fabry-Perot cavity structure 208 is provided in the cutting channel region 206. Figure 4 The exemplary diagram shows that the orthographic projection shape of the Fabry-Perot cavity structure 208 in the plane (i.e., the D2D3 plane) where the substrate 202 is located is circular.

[0035] In some embodiments, the orthographic projection shape of the Fabry-Perot cavity structure in the plane (i.e., the D2D3 plane) where the substrate 202 is located includes, but is not limited to, a square, a circle, an ellipse, a rhombus, a sector, a polygon, or any other shape, and this disclosure does not impose any particular limitation on it.

[0036] Here, the Fabry-Pérot cavity structure 208 can also be called the Fabry-Pérot Cavity.

[0037] like Figure 3 As shown, in some embodiments, the semiconductor device 200 further includes a plurality of Fabry-Perot cavity structures 238 surrounding the chip region 204.

[0038] In some embodiments, the number of Fabry-Perot cavity structures provided in the cutting channel region 206 may be one, two, three, four or more, and there are no special limitations in this disclosure. Figure 3 (or, Figure 4The diagram illustrates, for example, that four Fabry-Perot cavity structures 238 (or Fabry-Perot cavity structures 208) are provided in the cutting channel region 206, and the four Fabry-Perot cavity structures 238 (or Fabry-Perot cavity structures 208) are respectively located at the four corner positions corresponding to the chip region 204.

[0039] In some embodiments, a plurality of Fabry-Perot cavity structures 238 (or Fabry-Perot cavity structures 208) may be uniformly surrounding chip region 204. Thus, by increasing the number of Fabry-Perot cavity structures 238 (or Fabry-Perot cavity structures 208), the number of monitoring points for local stress distribution on substrate 202 can be increased.

[0040] refer to Figure 5 , Figure 5 This is a schematic cross-sectional view of a semiconductor device provided in some embodiments of this disclosure. For example... Figure 5 As shown, this disclosure provides a semiconductor device 200, which includes a Fabry-Perot cavity structure 208. The Fabry-Perot cavity structure 208 includes a first metal layer 210 and a second metal layer 212 disposed opposite to each other along the D1 direction, the first metal layer 210 and the second metal layer 212 being parallel to each other, the first metal layer 210 being located between a substrate 202 and the second metal layer 212; a dielectric structure 214 located between the first metal layer 210 and the second metal layer 212; and a cavity structure 226 located in the dielectric structure 214. The degree of deformation of the Fabry-Perot cavity structure 208 is used to monitor the stress distribution of the substrate 202.

[0041] In some embodiments, both the first metal layer 210 and the second metal layer 212 comprise a metallic material, such as silver (Ag).

[0042] In some embodiments, the medium structure 214 includes a medium material.

[0043] In some embodiments, the semiconductor device 200 further includes a semiconductor structure located on one side of the substrate 202 along the D1 direction, the semiconductor structure being located in the chip region 204.

[0044] In this embodiment, a Fabry-Perot cavity structure 208 is disposed in the dicing region 206 of the substrate 202. The Fabry-Perot cavity structure 208 includes: a first metal layer 210 and a second metal layer 212 disposed opposite to each other and parallel to each other along the D1 direction, a dielectric structure 214 located between the first metal layer 210 and the second metal layer 212, and a cavity structure 226 located in the dielectric structure 214. In a first aspect, the deformation degree of the Fabry-Perot cavity structure 208 is determined by using a first optical signal incident on the Fabry-Perot cavity structure 208 and a second optical signal emitted from the Fabry-Perot cavity structure 208, thereby determining the local stress distribution of the substrate 202, to achieve the purpose of monitoring the stress distribution of the substrate 202 using the Fabry-Perot cavity structure 208. In a second aspect, a semiconductor structure is disposed in the chip region 204 of the substrate 202. Based on the local stress distribution of the substrate 202, potential problems in the electrical performance and reliability of the semiconductor structure can be identified in a timely manner, thereby accelerating the research and development process.

[0045] In some embodiments, the semiconductor device 200 further includes a first isolation layer 234 located on one side of the substrate 202 along the D1 direction, the first isolation layer 234 being located between the substrate 202 and the first metal layer 210. Here, the first isolation layer 234 is used to isolate the substrate 202 and the first metal layer 210.

[0046] In some embodiments, the first isolation layer 234 comprises a dielectric material, such as silicon nitride.

[0047] In some embodiments, the first isolation layer 234 comprises an oxygen-free dielectric material. This prevents the oxygen in the first isolation layer 234 from contacting and reacting with the first metal layer 210, thus improving the stability of the first metal layer 210 and further enhancing the stability of the Fabry-Perot cavity structure 208.

[0048] In some embodiments, the cavity structure 226 includes: a first surface 228 and a second surface 230 disposed opposite to each other along the D1 direction, and at least one third surface 232 located between the first surface 228 and the second surface 230; wherein the first surface 228, the second surface 230 and the at least one third surface 232 together form a closed cavity structure 226.

[0049] It should be noted that the orthographic projection shape of the Fabry-Perot cavity structure 208 in the plane containing the substrate 202 (i.e., the D2D3 plane) refers to the orthographic projection shape of the cavity structure 226 in the plane containing the substrate 202 (i.e., the D2D3 plane). In other words, the orthographic projection shape of the Fabry-Perot cavity structure 208 in the plane containing the substrate 202 depends on the orthographic projection shape of the cavity structure 226 in the plane containing the substrate 202, and not on the orthographic projection shapes of the first metal layer 210 and the second metal layer 212 in the plane containing the substrate 202. For example, the orthographic projection shape of the Fabry-Perot cavity structure 208 in the plane containing the substrate 202 may be circular, wherein the orthographic projection shape of the cavity structure 226 in the plane containing the substrate 202 may also be circular.

[0050] In some embodiments, the orthographic projection of the cavity structure 226 onto the plane (i.e., the D2D3 plane) where the substrate 202 is located lies within the orthographic projection range of the first metal layer 210 and the second metal layer 212 onto the plane (i.e., the D2D3 plane) where the substrate 202 is located.

[0051] In some embodiments, the shape of the cavity structure 226 in three-dimensional space may include, but is not limited to, a cube, a cuboid, and a cylinder. This disclosure does not impose any special limitations on the shape of the cavity structure 226. For example, when the cavity structure 226 is a cube, the first surface 228 and the second surface 230 are both square planes and parallel to each other. Four third surfaces 232, all of which are square planes, are disposed between the first surface 228 and the second surface 230. The four third surfaces 232 include two third surfaces 232 disposed opposite to each other along the D2 direction and two third surfaces 232 disposed opposite to each other along the D3 direction. As another example, when the cavity structure 226 is a cylinder, the first surface 228 and the second surface 230 are both circular planes and parallel to each other. A third surface 232, which is curved, is disposed between the first surface 228 and the second surface 230.

[0052] In some embodiments, the dielectric structure 214 includes: a first dielectric layer 216, the first dielectric layer 216 including a first portion 218 and a second portion 220 connected to each other, the first portion 218 being in contact with a first metal layer 210, and the first portion 218 forming a first surface 228; the second portion 220 forming a third surface 232; and a second dielectric layer 224, the second dielectric layer 224 being in contact with a second metal layer 212, and at least a portion of the second dielectric layer 224 forming a second surface 230.

[0053] In some embodiments, the semiconductor device 200 further includes a second isolation layer 236, which is located between the first metal layer 210 and the second metal layer 212, and surrounds the second portion 220, that is, the second isolation layer 236 surrounds the cavity structure 226.

[0054] Combination Figure 5 As shown, at the location of the second isolation layer 236, along the D1 direction, a substrate 202, a first isolation layer 234, a first metal layer 210, a second isolation layer 236, a dielectric structure 214, and a second metal layer 212 are stacked sequentially. At the location of the cavity structure 226, along the D1 direction, a substrate 202, a first isolation layer 234, a first metal layer 210, a first dielectric layer 216, a cavity structure 226, a second dielectric layer 224, and a second metal layer 212 are stacked sequentially.

[0055] Here, the first part 218 includes two surfaces disposed opposite to each other along the D1 direction, one of the two surfaces being in contact with the first metal layer 210, and the other of the two surfaces forming the first surface 228 of the cavity structure 226. Figure 5 The schematic diagram of the D1D2 cross-sectional structure shows that the second part 220 includes two surfaces arranged opposite each other along the D2 direction. One of the two surfaces is in contact with the second isolation layer 236, and the other surface forms a third surface 232 of the cavity structure 226. The second dielectric layer 224 includes two surfaces arranged opposite each other along the D1 direction. One of the two surfaces is in contact with the second metal layer 212, and the other surface forms a second surface 230 of the cavity structure 226.

[0056] In some embodiments, the first dielectric layer 216 further includes a third portion 222, and the second isolation layer 236 is located between the first metal layer 210 and the third portion 222.

[0057] In some embodiments, at least a portion of the second dielectric layer 224 forms the second surface 230, and the remaining portion of the second dielectric layer 224 is located between the third portion 222 and the second metal layer 212. In other embodiments, the entire second dielectric layer forms the third surface, and the third portion 222 is located between the second insulating layer 236 and the second metal layer 212.

[0058] In some embodiments, the first dielectric layer 216, the second dielectric layer 224, and the second isolation layer 236 all include dielectric materials, such as silicon oxide, silicon nitride, and silicon oxynitride.

[0059] In some embodiments, the first dielectric layer 216, the second dielectric layer 224, the first isolation layer 234, and the second isolation layer 236 may comprise the same material or different materials. It should be noted that... Figure 5 The example illustrates that the first isolation layer 234, the first dielectric layer 216, and the second dielectric layer 224 all include the same material and use the same filling pattern; and are different from the material included in the second isolation layer 236. Figure 5The dashed line in the middle indicates the boundary line between the first dielectric layer 216 and the second dielectric layer 224. It is only used to indicate the relative positional relationship between the first dielectric layer 216 and the second dielectric layer 224. In fact, when the first dielectric layer 216 and the second dielectric layer 224 contain the same material, there is no interface between the first dielectric layer 216 and the second dielectric layer 224.

[0060] In some embodiments, the dimensions of the first portion 218 along the D1 direction, the second portion 220 along the D2 direction, and the third portion 222 along the D1 direction are the same. Here, the first dielectric layer 216 can be formed using an atomic layer deposition (ALD) process, and the thickness of the first dielectric layer 216 is the same at all locations.

[0061] In some embodiments, along the D1 direction, the thickness of the first metal layer 210 is greater than the thickness of the second metal layer 212.

[0062] Here, the first metal layer 210 needs to have a certain reflectivity, and the second metal layer 212 needs to have a certain transmittance. In this way, the first optical signal is injected into the Fabry-Perot cavity structure 208 by the second metal layer 212, and the second optical signal emitted from the Fabry-Perot cavity structure 208 is received by the second metal layer 212.

[0063] In some embodiments, the cavity structure 226 includes at least one of nitrogen and an inert gas. The inert gas may include, for example, helium and argon. Here, a certain amount of gas may be introduced during the formation of the cavity structure 226. In subsequent testing methods, due to the different stress distributions in the local area of ​​the substrate 202, the Fabry-Perot cavity structure 208 deforms, the gas density in the cavity structure 226 changes, and the second optical signal emitted from the Fabry-Perot cavity structure 208 also changes. Therefore, based on the first and second optical signals, the local stress distribution of the substrate 202 can be determined.

[0064] In some embodiments, the reflectivity of the first metal layer 210 is greater than 85%. Exemplarily, the reflectivity of the first metal layer 210 can be 86%, 87%, 88%, 89%, 90%, 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 99%, 100%, or a value within a range of any two values. Here, the first metal layer 210 can form total internal reflection.

[0065] In some embodiments, the transmittance of the second metal layer 212 is greater than 20%. Exemplarily, the transmittance of the second metal layer 212 can be 25%, 30%, 40%, 45%, 50%, 55%, 65%, 75%, 80%, 90%, or any value within a range of two such values. Optionally, the transmittance of the second metal layer 212 is greater than 50%. Thus, the first optical signal can enter the Fabry-Perot cavity structure 208 through the second metal layer 212, and the second optical signal can also exit the Fabry-Perot cavity structure 208 through the second metal layer 212.

[0066] In some embodiments, the transmittance of both the first dielectric layer 216 and the second dielectric layer 224 is greater than 90%. Exemplarily, the transmittance of the first dielectric layer 216 and the second dielectric layer 224 can be 91%, 92%, 93%, 94%, 95%, 96%, 97%, 98%, 99%, 100%, or any value within a range of two such values. Thus, the first optical signal can be incident into the Fabry-Perot cavity structure 208 through the second metal layer 212, for example, sequentially passing through the second metal layer 212, the second dielectric layer 224, the cavity structure 226, and the first dielectric layer 216 to reach the first metal layer 210; after reflection by the first metal layer 210, it exits sequentially through the first dielectric layer 216, the cavity structure 226, the second dielectric layer 224, and the second metal layer 212. Of course, the above process is only an exemplary illustration of the optical signal transmission process. In reality, considering that the transmittance of the second metal layer 212 may not be 100%, the reflectance of the first metal layer 210 may not be 100%, and the transmittance of the first dielectric layer 216 and the second dielectric layer 224 may not be 100%, the optical signal transmission process will be more complicated, and the optical signal may be reflected multiple times between the first metal layer 210 and the second metal layer 212.

[0067] In some embodiments, the thickness of the first metal layer 210 along the D1 direction is greater than 5 nanometers.

[0068] In some embodiments, the thickness of the second metal layer 212 along the D1 direction is from 0.5 nanometers to 200 nanometers. Optionally, the thickness of the second metal layer 212 is less than 10 nanometers.

[0069] In some embodiments, the thickness of the second dielectric layer 224 along the D1 direction is 1 nanometer to 5 micrometers.

[0070] refer to Figures 6 to 19 , Figure 6 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this disclosure. Figures 7 to 19 This is a cross-sectional structural diagram illustrating the manufacturing process of a semiconductor device provided in some embodiments of this disclosure. The following will be combined with... Figure 6 and Figures 7 to 19This section explains the manufacturing process of semiconductor devices.

[0071] like Figure 6 As shown in the embodiments of this disclosure, a method for manufacturing a semiconductor device is provided, the method comprising: Step S310: Provide a substrate, the substrate including a chip region and a dicing region surrounding the chip region; Step S320: At least one Fabry-Perot cavity structure is formed on one side of the substrate along a first direction, the first direction being perpendicular to the substrate. The Fabry-Perot cavity structure is located in the cutting channel region. The Fabry-Perot cavity structure includes: a first metal layer and a second metal layer disposed opposite to each other along the first direction, the first metal layer and the second metal layer being parallel to each other, the first metal layer being located between the substrate and the second metal layer; a dielectric structure located between the first metal layer and the second metal layer; and a cavity structure located in the dielectric structure; wherein the degree of deformation of the Fabry-Perot cavity structure is used to monitor the stress distribution of the substrate.

[0072] like Figure 7 As shown, in some embodiments, the manufacturing method further includes: providing a substrate 202; and forming a first isolation layer 234 on the substrate 202.

[0073] In some embodiments, the process for forming the first isolation layer 234 may include, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, or any combination thereof. In this embodiment, the process for forming the first isolation layer 234 is CVD.

[0074] like Figure 8 As shown, in some embodiments, the manufacturing method described above further includes forming an initial first metal layer 402 on the first isolation layer 234.

[0075] In some embodiments, the process for forming the initial first metal layer 402 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof. In this embodiment, the process for forming the initial first metal layer 402 is PVD.

[0076] like Figure 9 As shown, in some embodiments, step S320 includes: planarizing the initial first metal layer 402 to form the first metal layer 210.

[0077] In some embodiments, planarization of the initial first metal layer 402 may include, but is not limited to, chemical mechanical polishing (CMP). In this embodiment, CMP treatment of the initial first metal layer 402 is performed to form a mirror surface, which helps to form a Fabry-Perot cavity structure in subsequent manufacturing processes.

[0078] like Figure 10 As shown, in some embodiments, step S320 includes: forming a second isolation layer 236 on the first metal layer 210.

[0079] In some embodiments, the process for forming the second isolation layer 236 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof. In this embodiment, the process for forming the second isolation layer 236 is CVD.

[0080] like Figure 11 As shown, in some embodiments, step S320 includes: etching a second isolation layer 236 to form an etch trench 404, the bottom of which exposes a first metal layer 210.

[0081] For example, forming the etching trench 404 may include the following steps: forming a photoresist layer on the second isolation layer 236; using a photolithography process to transfer a pattern on a mask to the photoresist layer to form a patterned photoresist layer; using the patterned photoresist layer as a mask layer to etch the second isolation layer 236 to transfer the pattern on the patterned photoresist layer to the second isolation layer 236 to form the etching trench 404; and removing the patterned photoresist layer.

[0082] In some embodiments, the process of forming the etched groove 404 may include, for example, a dry etching process.

[0083] like Figure 12 As shown, in some embodiments, step S320 includes: forming a first dielectric layer 216, the first dielectric layer 216 including a first portion 218 covering the bottom of the etched trench 404, a second portion 220 covering the sidewalls of the etched trench 404, and a third portion 222 covering the surface of the second isolation layer 236 away from the first metal layer 210. Figure 12 The dashed line in the middle indicates the boundary line between the first part 218, the second part 220, and the third part 222, and is only used to illustrate the relative positional relationship between the first part 218, the second part 220, and the third part 222. In order to describe the relative positional relationship between the first dielectric layer 216 and other structures, the first dielectric layer 216 is divided into the first part 218, the second part 220, and the third part 222. In fact, the first dielectric layer 216 is a one-piece molded structure, formed simultaneously in the same process.

[0084] In some embodiments, the process of forming the first dielectric layer 216 may include, for example, ALD.

[0085] Here, the first dielectric layer 216 formed by the ALD process has high density. Each cycle of the ALD process includes alternately introducing a first reaction precursor and a second reaction precursor into the reaction chamber. When the first reaction precursor is introduced into the reaction chamber, it adsorbs onto the sidewalls and bottom of the etching tank 404, as well as the surface of the second isolation layer 236 away from the first metal layer 210, and binds to the active sites at these locations; excess first reaction precursor is removed by purging; the second reaction precursor is introduced into the reaction chamber, and the second reaction precursor reacts with the first reaction precursor to form a single-atom layer of the first dielectric layer 216 on the sidewalls and bottom of the etching tank 404, as well as the surface of the second isolation layer 236 away from the first metal layer 210; excess second reaction precursor is removed by purging. That is, each cycle includes "introducing the first reaction precursor - purging - introducing the second reaction precursor - purging", and each cycle corresponds to forming a single-atom layer of the first dielectric layer 216 with a fixed thickness, which is also referred to as the self-limiting property of the ALD process. By controlling the number of cycle times, the thickness of the first dielectric layer 216 can be precisely controlled.

[0086] Here, in the ALD process, whether in a plane or in a complex three-dimensional structure such as an etched groove, hole or step, the first dielectric layer 216 can uniformly cover the entire surface, and the thickness of the first dielectric layer 216 is basically the same at different locations. This is also known as the conformal property of the ALD process.

[0087] In some embodiments, the first dielectric layer 216 may include, for example, silicon oxide. Here, silicon oxide has high transmittance, which meets the usage requirements.

[0088] like Figure 13 As shown, in some embodiments, the above manufacturing method further includes: forming an initial sacrificial layer 406, the initial sacrificial layer 406 filling the etched trench 404 and also covering the surface of the second isolation layer 236 away from the first metal layer 210.

[0089] Here, during the formation of the initial sacrificial layer 406, the surface of the first portion 218 covering the bottom of the etch trench 404 is lower than the surface of the third portion 222 covering the second isolation layer 236. Therefore, corresponding to the location of the etch trench 404, the surface of the deposited initial sacrificial layer 406 may have a depression. That is, the lowest point of the surface of the initial sacrificial layer 406 away from the substrate 202 needs to be higher than the surface of the third portion 222 away from the substrate 202, which helps to planarize the initial sacrificial layer 406 in subsequent manufacturing processes.

[0090] In some embodiments, the process for forming the initial sacrificial layer 406 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0091] like Figure 14 As shown, in some embodiments, step S320 includes: planarizing the initial sacrificial layer 406 to form a sacrificial layer 408 and exposing the surface of the third portion 222 away from the substrate 202, wherein the surface of the sacrificial layer 408 and the surface of the third portion 222 away from the substrate 202 are substantially flush.

[0092] Here, "basically flush" means that the height difference along the D1 direction between the surface of the sacrificial layer 408 away from the substrate 202 and the surface of the third part 222 away from the substrate 202 is 0 or meets the process error range requirements.

[0093] In some embodiments, planarization of the initial sacrificial layer 406 may include, but is not limited to, CMP processing.

[0094] like Figure 15 As shown, in some embodiments, step S320 further includes forming a first material layer 410 on the third portion 222 and the sacrificial layer 408.

[0095] In some embodiments, the process for forming the first material layer 410 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0096] In some embodiments, the first dielectric layer 216 and the first material layer 410 both comprise the same material. Figure 15 The dashed line indicates the interface between the first dielectric layer 216 and the first material layer 410, and is only used to illustrate the relative positional relationship between the first dielectric layer 216 and the first material layer 410. When the first dielectric layer 216 and the first material layer 410 contain the same material, there is no interface between the first dielectric layer 216 and the first material layer 410.

[0097] like Figure 16 As shown, in some embodiments, step S320 further includes: etching the first material layer 410 to form an etched hole 412, the bottom of which exposes the sacrificial layer 408.

[0098] In some embodiments, the process of forming the etched hole 412 may include, for example, a dry etching process.

[0099] In some embodiments, along the D2 direction, the ratio between the size of the etched hole 412 and the size of the etched trench 404 is less than 1 / 3. Thus, by limiting the ratio between the size of the etched hole 412 and the size of the etched trench 404, the sacrificial layer 408 can be sufficiently removed through the etched hole 412, and the etched hole 412 can be closed in subsequent manufacturing processes to form a closed cavity structure.

[0100] like Figure 17 As shown, in some embodiments, step S320 further includes removing the sacrificial layer 408 through the etched hole 412. Here, the etched hole 412 leaves the initial cavity structure formed therein in an unclosed state, the surface of the first portion 218 of the first dielectric layer 216 away from the substrate 202 forms a first surface 228, and the surface of the second portion 220 of the first dielectric layer 216 away from the second isolation layer 236 forms a third surface 232.

[0101] For example, removing the sacrificial layer 408 may include the following steps: using a diluted wet etching solution, which has good fluidity and can enter the etching hole to etch and remove the sacrificial layer 408; after etching, rinsing with pure water to replace the residual etching solution in the initial cavity structure; rotating the substrate 202 to remove as much pure water as possible from the initial cavity structure, purging with, for example, nitrogen gas, and then further replacing the residual etching solution in the initial cavity structure with isopropanol (IPA) solution; and allowing the isopropanol to evaporate naturally by heating.

[0102] In some embodiments, the process of removing the sacrificial layer 408 may include, for example, a wet etching process.

[0103] In some embodiments, during the process of removing the sacrificial layer 408, the etching solution removes the sacrificial layer 408 at a rate greater than it removes the first dielectric layer 216 and the first material layer 410. This allows for sufficient removal of the sacrificial layer 408 while avoiding damage to the first dielectric layer 216 and the first material layer 410.

[0104] like Figure 18 As shown, in some embodiments, step S320 further includes: forming an initial second material layer 414 on the first material layer 410 to close the etched hole 412 and form a cavity structure 226. That is, a first portion of the initial second material layer 414 is located in the etched hole 412, a second portion of the initial second material layer 414 is located on the surface of the first material layer 410 away from the substrate 202, and a third portion of the initial second material layer 414 is located on the surface of the first material layer 410 facing the cavity structure 226. Here, the surface of the initial second material layer 414 facing the cavity structure 226 forms the second surface 230 of the cavity structure 226. Figure 18 This situation is illustrated in the diagram.

[0105] In some embodiments, a first portion of the initial second material layer is located within an etched hole, and a second portion of the initial second material layer is located on the surface of the first material layer away from the substrate. Here, the surface of the first material layer facing the cavity structure and the surface of the first portion of the initial second material layer facing the cavity structure together form the second surface of the cavity structure.

[0106] In some embodiments, the process for forming the initial second material layer 414 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof.

[0107] In some embodiments, the first dielectric layer 216, the first material layer 410, and the initial second material layer 414 comprise the same material. Figure 18 The dashed line in the middle indicates the interface between the first dielectric layer 216, the first material layer 410, and the initial second material layer 414. It is only used to illustrate the relative positional relationship between the first dielectric layer 216, the first material layer 410, and the initial second material layer 414. In fact, when the first dielectric layer 216, the first material layer 410, and the initial second material layer 414 contain the same material, there is no interface between the first dielectric layer 216, the first material layer 410, and the initial second material layer 414.

[0108] like Figure 19 As shown, in some embodiments, step S320 further includes: planarizing the initial second material layer 414 to form a second material layer 416, wherein the first material layer 410 and the second material layer 416 form a second dielectric layer 224, and the dielectric structure 214 includes the first dielectric layer 216 and the second dielectric layer 224.

[0109] In some embodiments, planarization of the initial second material layer 414 may include, but is not limited to, CMP processing.

[0110] In some embodiments, the first dielectric layer 216, the first material layer 410, and the second material layer 416 comprise the same material. Figure 19 The dashed line in the middle indicates the interface between the first dielectric layer 216, the first material layer 410, and the second material layer 416. It is only used to illustrate the relative positional relationship between the first dielectric layer 216, the first material layer 410, and the second material layer 416. In fact, when the first dielectric layer 216, the first material layer 410, and the second material layer 416 contain the same material, there is no interface between the first dielectric layer 216, the first material layer 410, and the second material layer 416.

[0111] In some embodiments, the initial second material layer 414 is planarized by removing a portion of the initial second material layer 414 located on the surface of the first material layer 410 away from the substrate 202. That is, the first dielectric layer 216, the first material layer 410, and the remaining second material layer 416 are sequentially stacked along the D1 direction on the surface of the second isolation layer 236 away from the substrate 202. Figure 19 This situation is illustrated in the diagram, where the third portion of the first dielectric layer 216, the first material layer 410, and the second material layer 416 are located between the second isolation layer 236 and the subsequently formed second metal layer 212.

[0112] In other embodiments, the initial second material layer is planarized by removing all of the initial second material layer located on the surface of the first material layer away from the substrate. That is, the first dielectric layer and the first material layer are sequentially stacked along the D1 direction on the surface of the second insulating layer away from the substrate. Here, a third portion of the first dielectric layer and all of the first material layer are located between the second insulating layer and the subsequently formed second metal layer.

[0113] In some embodiments, the initial second material layer and the first material layer are planarized, and a portion of the first material layer located on the surface of the third portion away from the substrate is removed. That is, the first dielectric layer and the first material layer are sequentially stacked along the D1 direction on the surface of the second isolation layer away from the substrate. Here, the third portion of the first dielectric layer and the portion of the first material layer are located between the second isolation layer and the subsequently formed second metal layer.

[0114] In other embodiments, the initial second material layer and the first material layer are planarized, and all of the first material layer located on the surface of the third portion away from the substrate is removed; that is, the first dielectric layer is disposed on the surface of the second insulating layer away from the substrate. Here, the third portion of the first dielectric layer is located between the second insulating layer and the subsequently formed second metal layer.

[0115] This disclosure does not impose any particular limitations on the thickness of the first dielectric layer 216, the thickness of the first material layer 410, and the thickness of the initial second material layer 414. Based on the amount of material removed during the planarization process, the surface of the second isolation layer 236 away from the substrate 202 can be determined to be the first dielectric layer 216; or the first dielectric layer 216 and the first material layer 410; or the first dielectric layer 216, the first material layer 410, and the second material layer 416.

[0116] like Figure 19 As shown, in some embodiments, step S320 further includes: forming a second metal layer 212 on the second dielectric layer 224.

[0117] In some embodiments, the process for forming the second metal layer 212 may include, but is not limited to, CVD, PVD, ALD, or any combination thereof. In this embodiment, the process for forming the second metal layer 212 is PVD.

[0118] refer to Figures 20 to 22 , Figure 20 This is a flowchart illustrating the testing methods provided in some embodiments of this disclosure. Figure 21 This is a schematic diagram of a test mold provided in some embodiments of this disclosure. Figure 22 This is a schematic diagram of a Fabry-Perot cavity structure provided for some embodiments of this disclosure. The following will be combined with... Figures 20 to 22 The test method utilizing the Fabry-Perot cavity structure in the aforementioned semiconductor device is described.

[0119] like Figure 20 As shown, this disclosure provides a testing method, which is applied to the semiconductor device 200 as described above; the testing method includes: Step S510: Input the first optical signal into the Fabry-Perot cavity structure through the second metal layer; Step S520: Receive the second optical signal output from the Fabry-Perot cavity structure through the second metal layer; Step S530: Determine the stress distribution of the substrate based on the first optical signal and the second optical signal.

[0120] Here, we will take as an example a semiconductor device that includes four Fabry-Perot cavity structures 208, and the four Fabry-Perot cavity structures 208 are located at the four corners of the dicing channel region 206 corresponding to the chip region 204.

[0121] Four holes are made in, for example, the test mold 602 for stress distribution, and optical fibers 604 are implanted in each of the four holes. The positions of the optical fibers 604 correspond to the Fabry-Perot cavity structure 208 in the cleavage region 206. In the testing method, the test mold 602 and the substrate are bonded together, and the positions of the optical fibers 604 and the Fabry-Perot cavity structure 208 correspond, that is, the orthographic projection of the optical fiber 604 in the plane where the substrate 202 is located and the orthographic projection of the Fabry-Perot cavity structure 208 in the plane where the substrate 202 is located at least partially overlap.

[0122] Combination Figure 5 and Figure 21As shown, in step S510, a first optical signal (i.e., input optical signal) is input into the Fabry-Perot cavity structure 208 via the second metal layer 212 using optical fiber 604; in step S520, the second metal layer 212 receives the second optical signal (i.e., output optical signal) output from the Fabry-Perot cavity structure 208; in step S530, the stress distribution of the substrate 202 is determined based on the first and second optical signals. Due to the different local stress distributions of the substrate 202, the Fabry-Perot cavity structure 208 may be compressed or stretched, causing deformation of the Fabry-Perot cavity structure 208, i.e., the volume of the Fabry-Perot cavity structure 208 changes, and the density of the gas inside changes, resulting in a change in its refractive index for optical signals. Therefore, based on the input and output optical signals, the degree of deformation of the Fabry-Perot cavity structure 208 can be determined, thereby determining the local stress distribution of the substrate 202.

[0123] Due to the varying stress distribution in different parts of the substrate 202, the Fabry-Perot cavity structure 208 deforms, potentially causing changes in the dimensions of the cavity structure 226 within it. For example, the cavity structure 226 may be stretched along the D1 direction, resulting in an increase in its dimension along the D1 direction; or it may be compressed along the D1 direction, resulting in a decrease in its dimension along the D1 direction. Of course, the dimensions of the cavity structure 226 along either the D2 or D3 direction may also change. Figure 22 An exemplary illustration shows that the size of the cavity structure 226 decreases along the D2 direction and the size of the cavity structure 226 increases along the D1 direction to form the cavity structure 240.

[0124] It should be noted that a Fabry-Perot cavity structure 208 is formed in the dicing region 206 of the substrate 202, and the Fabry-Perot cavity structure 208 has a predetermined size. A semiconductor structure is formed in the chip region 204 of the substrate 202. During the formation of the semiconductor structure, the local stress distribution of the substrate 202 changes, causing deformation of the Fabry-Perot cavity structure 208. The Fabry-Perot cavity structure 208 is stretched or compressed, and the density and refractive index of the gas in the Fabry-Perot cavity structure 208 change. A first optical signal is injected into the Fabry-Perot cavity structure, and a second optical signal is emitted from the Fabry-Perot cavity structure. Based on the first and second optical signals, the stress distribution of the substrate at this time can be determined. This disclosure does not impose any special restrictions on the formation order of the Fabry-Perot cavity structure 208 and the semiconductor structure. In some embodiments, the Fabry-Perot cavity structure 208 can be formed first, followed by the semiconductor structure. In other embodiments, the Fabry-Perot cavity structure 208 and the semiconductor structure can be formed simultaneously, utilizing the fact that the semiconductor structure may involve the same or similar process steps as the Fabry-Perot cavity structure 208, thus saving manufacturing steps.

[0125] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0126] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: a substrate comprising a chip region and a scribe lane region surrounding the chip region; at least one Fabry-Perot cavity structure located on one side of the substrate along a first direction, the first direction being perpendicular to the substrate, the Fabry-Perot cavity structure being located in the scribe lane region, the Fabry-Perot cavity structure comprising: a first metal layer and a second metal layer oppositely arranged along the first direction, the first metal layer and the second metal layer being parallel to each other, the first metal layer being located between the substrate and the second metal layer; a dielectric structure located between the first metal layer and the second metal layer; and a cavity structure located in the dielectric structure; wherein a deformation degree of the Fabry-Perot cavity structure is used to monitor a stress distribution of the substrate.

2. The semiconductor device according to claim 1, wherein The cavity structure comprises: a first surface and a second surface oppositely arranged along the first direction, and at least one third surface located between the first surface and the second surface; wherein the first surface, the second surface and the at least one third surface together enclose the closed cavity structure; The dielectric structure comprises: a first dielectric layer, the first dielectric layer comprising a first part and a second part connected to each other, the first part being in contact with the first metal layer, and the first part forming the first surface; the second part forming the third surface; a second dielectric layer, the second dielectric layer being in contact with the second metal layer, and at least part of the second dielectric layer forming the third surface.

3. The semiconductor device of claim 1, wherein The semiconductor device further comprises: a plurality of the Fabry-Perot cavity structures surrounding the chip region.

4. The semiconductor device of claim 1, wherein In the first direction, the thickness of the first metal layer is greater than the thickness of the second metal layer.

5. The semiconductor device of claim 1, wherein At least one of nitrogen and inert gas is included in the cavity structure.

6. The semiconductor device of claim 2, wherein The reflectivity of the first metal layer is greater than 85%; the transmittance of the second metal layer is greater than 20%; the transmittance of the first dielectric layer and the second dielectric layer is greater than 90%.

7. A method of manufacturing a semiconductor device, characterized by The manufacturing method comprises: providing a substrate comprising a chip region and a scribe lane region surrounding the chip region; forming at least one Fabry-Perot cavity structure on one side of the substrate along a first direction, the first direction being perpendicular to the substrate, the Fabry-Perot cavity structure being located in the scribe lane region, the Fabry-Perot cavity structure comprising: a first metal layer and a second metal layer oppositely arranged along the first direction, the first metal layer and the second metal layer being parallel to each other, the first metal layer being located between the substrate and the second metal layer; a dielectric structure located between the first metal layer and the second metal layer; and a cavity structure located in the dielectric structure; wherein a deformation degree of the Fabry-Perot cavity structure is used to monitor a stress distribution of the substrate.

8. The manufacturing method according to claim 7, wherein The forming at least one Fabry-Perot cavity structure on one side of the substrate along a first direction comprises: forming a first metal layer and an isolation layer on the substrate in sequence; etching the isolation layer to form an etching groove, the bottom of the etching groove exposing the first metal layer; forming a first dielectric layer, the first dielectric layer including a first portion covering a bottom of the etching groove, a second portion covering a sidewall of the etching groove, and a third portion covering a surface of the isolation layer; forming a sacrificial layer in the etching groove, a surface of the sacrificial layer and a surface of the third portion being substantially flush.

9. The production method according to claim 8, wherein The method further includes: forming a first material layer on the third portion and the sacrificial layer; etching the first material layer to form an etching hole, a bottom of the etching hole exposing the sacrificial layer; removing the sacrificial layer through the etching hole; forming an initial second material layer on the first material layer to close the etching hole and form the cavity structure; planarizing the initial second material layer to form a second material layer, the first material layer and the second material layer forming a second dielectric layer, the dielectric structure including the first dielectric layer and the second dielectric layer; forming a second metal layer on the second dielectric layer.

10. The manufacturing method according to claim 9, wherein In a second direction, a ratio between a size of the etching hole and a size of the etching groove is less than 1 / 3; wherein the first direction and the second direction are perpendicular to each other.

11. A test method characterized by, The test method is applied to the semiconductor device of any one of claims 1 to 6; the test method includes: inputting a first optical signal into the FP cavity structure through the second metal layer; receiving a second optical signal output by the FP cavity structure through the second metal layer; determining a stress distribution of the substrate based on the first optical signal and the second optical signal.

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