Semiconductor device

Abstract

The invention provides a semiconductor device capable of suppressing generation of defects. According to one embodiment, a semiconductor device includes: a wiring layer including a plurality of wirings; and a columnar electrode provided integrally with the wiring and extending from the bottom of the wiring in a direction substantially perpendicular to the wiring layer. The wiring has a conductive film and a first film different from the conductive film, which are alternately laminated in a direction substantially perpendicular to the wiring layer.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a semiconductor device. BACKGROUND

[0002] A wiring such as a damascene wiring is formed, for example, by processing a film formed by CVD (Chemical Vapor Deposition). Depending on the roughness of the surface of the film formed by CVD, the wiring can have a concave defect. SUMMARY

[0003] Provided is a semiconductor device capable of suppressing generation of a defect.

[0004] A semiconductor device of one embodiment includes a wiring layer including a plurality of wirings, and a columnar electrode provided integrally with the wirings and extending in a direction substantially perpendicular to the wiring layer from a bottom of the wirings, and the wirings include a conductive film and a first film different from the conductive film alternately stacked in a direction substantially perpendicular to the wiring layer. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1 FIG. 1 is a cross-sectional view illustrating an example of a structure of a semiconductor device of a first embodiment.

[0006] Figure 2A FIG. 2 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device of the first embodiment.

[0007] Figure 2B FIG. 3 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 2A FIG. 4 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0008] Figure 3A FIG. 5 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device of the first embodiment.

[0009] Figure 3B FIG. 6 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 3A FIG. 7 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0010] Figure 3C FIG. 8 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 3B FIG. 9 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0011] Figure 3D FIG. 10 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 3C FIG. 11 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0012] Figure 3E FIG. 12 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 3D FIG. 13 is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device.

[0013] Figure 4 is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example.

[0014] Figure 5 is a graph showing an example of a relationship between a film thickness of a conductive film and generation of defects of a wiring of the first comparative example and the first embodiment.

[0015] Figure 6A is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example.

[0016] Figure 6B is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example. Figure 6A is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example.

[0017] Figure 6C is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example. Figure 6B is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example.

[0018] Figure 6D is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example. Figure 6C is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example.

[0019] Figure 6E is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example. Figure 6D is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first comparative example.

[0020] Figure 7 is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the second comparative example.

[0021] Figure 8 is a cross-sectional view showing an example of a configuration of a semiconductor device of the fourth embodiment. DETAILED DESCRIPTION

[0022] Hereinafter, an embodiment of the present application will be described with reference to the drawings.

[0023] The present embodiment is not restrictive of the present application. The drawings are schematic or conceptual, and the proportions of the parts, and the like, are not necessarily the same as actual ones. In the specification and the drawings, the same symbols are attached to elements having the same function in order to make the drawings clear, and detailed description is appropriately omitted.

[0024] (First Embodiment)

[0025] Figure 1 is a cross-sectional view showing an example of a configuration of a semiconductor device of the first embodiment. Figure 1 A wiring layer 50 used in a semiconductor device is shown.

[0026] The semiconductor device includes a wiring layer 50, an insulating layer 60, a barrier metal film 70, a columnar electrode (via) 80, and an insulating film 90.

[0027] The wiring layer 50 is provided in an XY plane. The wiring layer 50 includes a plurality of wirings 51 in the layer. In a case where the semiconductor device is a memory (storage element), the wiring layer 50 includes, for example, a wiring for a memory cell array, a wiring for a peripheral circuit such as a circuit, and the like. Hereinafter, a case where the semiconductor device is a memory will be described, but is not limited thereto, and the semiconductor device can be a logic circuit (logic element) or the like.

[0028] The plurality of wirings 51 are arranged, for example, in a prescribed pattern. The plurality of wirings 51 are arranged, for example, in a line-and-gap pattern. The wirings 51 extend in a direction (Y direction) perpendicular to a plane of the paper of the drawing. Figure 1 The plurality of wirings 51 are arranged in an X direction. The wirings 51 are used, for example, as bit lines of the memory.

[0029] A material of the wirings 51 uses, for example, a conductive material such as tungsten (W). Details of the configuration of the wirings 51 will be described later. Figures 3A-3E

[0030] The insulating layer 60 insulates between the wirings 51. A material of the insulating layer 60 uses, for example, SiO2. The insulating layer 60 is formed using, for example, TEOS (Tetraethoxysilane).

[0031] The barrier metal film 70 suppresses diffusion of W included in a material of the wirings 51. The barrier metal film 70 is provided between the wirings 51 and the insulating layer 60. The barrier metal film 70 is provided between the columnar electrode 80 and the insulating layer 60. The barrier metal film 70 uses, for example, titanium (Ti), Ta (tantalum), or a tantalum nitride film (TaN), or the like.

[0032] The columnar electrode 80 electrically connects the wirings 51 and a lower layer wiring (not shown). The columnar electrode 80 is provided integrally with the wirings 51 and extends in a direction (Z direction) substantially perpendicular to the wiring layer 50 from a bottom of the wirings 51. A material of the columnar electrode 80 is the same as that of the wirings 51. The material of the columnar electrode 80 uses, for example, a conductive material such as tungsten (W).

[0033] The insulating film 90 is provided on the wirings 51. A material of the insulating film 90 uses, for example, SiN.

[0034] Figures 2A-2B is a cross-sectional view showing an example of a manufacturing method of the semiconductor device of the first embodiment.

[0035] First, as shown in Figure 2A ​As shown, a hole H is formed in the insulating film 61, a barrier metal film 70 is formed on the insulating film 61 and in the hole H to bury the hole H, the wiring member 52 is formed in a manner to be disposed on the insulating film 61, the insulating film 90 is formed on the wiring member 52, and the semiconductor film 100 is formed on the insulating film 90. The wiring member 52 is formed, for example, by CVD (Chemical Vapor Deposition). The material of the semiconductor film 100 is, for example, amorphous silicon.

[0036] Further, the wiring member 52 buried in the hole H becomes the columnar electrode 80. That is, the columnar electrode 80 is formed at the same time as the wiring member 52 which becomes the wiring 51 after processing.

[0037] Further, details of formation of the wiring member 52 will be described with reference to Figures 3A-3E in the following.

[0038] Next, as shown in Figure 2B , a plurality of wirings 51 arranged in a prescribed pattern are formed by processing the wiring member 52. The processing of the wiring member 52 is performed, for example, by RIE (Reactive Ion Etching).

[0039] Then, the wirings 51 are buried with the same insulating film as the insulating film 61, and polishing processing (for example, CMP (Chemical Mechanical Polishing)) is performed until the insulating film 90 is exposed, whereby the Figure 1 configuration shown is completed.

[0040] Next, formation of the wiring member 52 will be described.

[0041] Figures 3A-3E is a cross-sectional view showing an example of a manufacturing method of a semiconductor device of the first embodiment. Further, the barrier metal film 70 is omitted.

[0042] First, as shown in Figure 3A , a core formation layer 53 is formed on the insulating film 61. The core formation layer 53 is formed, for example, by alternately supplying diborane (B2H6) gas and tungsten hexafluoride (WF6) gas into a processing chamber and performing processing.

[0043] Next, as shown in Figure 3BAs shown, a conductive film 54 is formed. The conductive film 54 is formed by growing and enlarging the grain size of the metal contained in the nucleation layer 53. The main component of the conductive film 54 is, for example, tungsten (W). The conductive film 54 is formed, for example, by processing while supplying tungsten hexafluoride (WF6) and hydrogen (H2) gas into the processing chamber. The conductive film 54 is formed, for example, until its thickness reaches approximately 15 nm. The thickness of the conductive film 54 is the thickness in the vertical direction (Z direction) of the paper. Furthermore, as shown in the reference… Figure 5 The thickness of the conductive film 54 is determined within a range where the wiring 51 described below will not produce defects. Furthermore, Figure 3B The grain boundary 54a of the conductive film 54 is shown in the figure.

[0044] Next, as Figure 3C As shown, a film 55 is formed on the conductive film 54. Film 55 is an amorphous film. Film 55 is formed, for example, by impregnation (soaking) with diborane. In this case, film 55 is a film containing diborane adsorbed on the surface of the conductive film 54. As an impregnated film, film 55 is formed, for example, by processing while supplying diborane gas into the processing chamber. Furthermore, Figure 3C The upper surface of the membrane 55 shown is flat, but the upper surface of the membrane 55 may not be flat.

[0045] Next, as Figure 3D As shown, a conductive film 54 is formed on the film 55. The conductive film 54, for example, is... Figure 3B Similarly, it is formed until the thickness becomes approximately 15 nm.

[0046] Next, as Figure 3E As shown, execute repeatedly. Figure 3C and Figure 3D The steps shown (cyclic film formation) are followed. This forms the wiring component 52. Figure 3E In the example shown, three conductive films 54 are formed.

[0047] The wiring component 52 has conductive films 54 and 55 alternately deposited in a direction substantially perpendicular to the wiring layer 50 (Z direction). Therefore, Figure 1 The wiring 51 shown also has conductive films 54 and 55 alternately stacked in a direction substantially perpendicular to the wiring layer 50 (Z direction). The main component of the conductive film 54 is, for example, tungsten (W). The type of film 55 is different from that of the conductive film 54. In the first embodiment, the main component of the film 55 is boron (B), which is different from the main component of the conductive film 54. The number of layers of the conductive films 54 and 55 is, for example, two or more. For example, when the wiring component 52 is formed with a thickness of 40 nm, three conductive films 54 of approximately 13 nm are formed.

[0048] The auxiliary film 55 functions as a segmentation film, arranged in a manner that segments the grains of the conductive films 54 between the two conductive films 54 sandwiched between the film 55. Using the film 55, grain growth of the conductive films 54 can be prevented, thereby ensuring that the grain size of the conductive films 54 is below a specified grain size. This suppresses the large grain size of the conductive films 54, thereby suppressing (improving) the surface roughness of the wiring component 52. As a result, defects in the wiring 51 during the processing of the wiring component 52 can be suppressed. Furthermore, details regarding defects in the wiring 51 caused by the surface roughness of the wiring component 52 will be provided in [reference needed]. Figures 6A-6E This will be explained below.

[0049] Furthermore, the film 55 is formed until its thickness is sufficient to cover the conductive film 54 and appropriately break down the crystallinity of the conductive film 54. Therefore, the film 55 can be thinner than the conductive film 54. Since the film 55 is an impregnated film, it can be formed simply by adsorbing diborane onto the surface of the conductive film 54. In addition, the impregnated film containing diborane acts as a reducing agent during the formation of the conductive film 54, thus further thinning the film 55. As a result, the ratio of the thickness of the conductive film 54 to the overall thickness of the wiring component 52 can be increased. Consequently, the wiring resistance of the wiring 51 can be further reduced.

[0050] As described above, according to the first embodiment, the wiring 51 has conductive films 54 and 55 alternately deposited in a direction substantially perpendicular to the wiring layer 50 (Z direction). Furthermore, the wiring 51 has at least two or more conductive films 54. This suppresses the large particle size of the conductive films 54, thereby suppressing (improving) the surface roughness of the wiring component 52. As a result, defects in the wiring 51 can be suppressed. Surface step difference of the wiring component 52 (reference) Figure 5 The larger the value, that is, the higher the distance between the protrusion on the upper surface of the wiring component 52 and the reference surface, the greater the roughness.

[0051] In addition, such as Figure 2A As shown, the wiring component 52 and the columnar electrode 80 are integrally formed simultaneously using CVD. This reduces the number of steps.

[0052] In addition, the insulating film 90 is provided on the plurality of wirings 51. The insulating film 90 is configured in accordance with the shape of the plurality of wirings 51 as viewed from a direction (Z direction) substantially perpendicular to the wiring layer 50. In more detail, the plurality of insulating films 90 are provided along the plurality of wirings 51. For example, the outer edge shape of the plurality of insulating films 90 can be substantially the same as the outer edge shape of the plurality of wirings 51 as viewed from the direction (Z direction) substantially perpendicular to the wiring layer 50. When forming an upper columnar electrode (not shown) that is electrically connected to the upper portion of the wiring 51, a portion of the insulating film 90 on the wiring 51 is recessed (machined) and embedded with a conductive material. Thereby, it is possible to adjust the shape of the bottom of the upper columnar electrode, for example, to make the bottom of the upper columnar electrode be located only above the wiring 51. As a result, it is possible to suppress concerns about the withstand voltage.

[0053] Further, the film 55 is not limited to the example described above. The film 55 is more preferably a film that can be formed in the same chamber or in the same device.

[0054] (First Comparative Example)

[0055] Figure 4 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device of the first comparative example. The first comparative example differs from the first embodiment in that the conductive film 54 is continuously grown without the film 55 being provided.

[0056] In the first comparative example, the step shown in Figure 3B is performed, and a wiring member 52 having a conductive film 54 with a large particle diameter is formed. Since the larger the particle diameter of the conductive film 54, the smaller the specific resistance of the wiring 51, it is possible to reduce the wiring resistance of the wiring 51. However, the larger the particle diameter of the conductive film 54, the worse the roughness of the surface of the wiring member 52 becomes. In the example shown in Figure 4 , a local protrusion is generated on the upper surface of the wiring member 52. Figure 4 The protrusion 52a shown in

[0057] Figure 5 is a graph showing an example of the relationship between the film thickness of the conductive film 54 and the generation of defects in the wiring 51 of the first comparative example. The horizontal axis of the graph indicates the film thickness of the conductive film 54. The vertical axis of the graph indicates the surface step difference. The surface step difference is the maximum value of the height difference of the local protrusion generated on the upper surface of the wiring member 52. (In the example shown in Figure 4 , the height difference of the protrusion 52a shown in Figure 4

[0058] In the case where the film thickness of the conductive film 54 is about 38 nm or more (first comparative example), the surface step difference of the wiring member 52 is about 35 nm or more, and the wiring 51 can have defects.

[0059] ​On the other hand, when the thickness of the conductive film 54 is about 15 nm or less (first embodiment), the surface step difference of the wiring component 52 is about 15 nm or less, and no defects are generated in the wiring 51. When the conductive film 54 is formed on the film 55, the conductive film 54 is grown from a state where the thickness of the conductive film 54 is reset to zero nm (the horizontal axis of the figure). Therefore, even if the total thickness of the conductive film 54 increases, the surface roughness of the wiring component 52 can be suppressed.

[0060] Next, the defects will be explained.

[0061] Figures 6A-6E This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the first comparative example.

[0062] Figure 6A Reference shown in the middle Figure 4 Wiring component 52, as described. (Example) Figure 6A As shown, a localized protrusion 52a is formed on the upper surface of the wiring component 52 due to surface roughness. The protrusion 52a causes the upper surfaces of the insulating film 90 and the semiconductor film 100 above the protrusion 52a to also have protrusions.

[0063] First, such as Figure 6A As shown, an insulating film 90, a semiconductor film 100 serving as a mask film, a mask film 110, and an insulating film 120 are sequentially formed on the wiring component 52. A photoresist 130 is formed in a designated area on the insulating film 120, and a spacer 140 is formed on the insulating film and the photoresist 130.

[0064] The insulating film 120 is, for example, an SOG (Spin On Glass) film. The spacer 140 contains, for example, SiO2.

[0065] Next, as Figure 6B As shown, the mask film 110, insulating film 120, photoresist 130, and spacer 140 are processed until the semiconductor film 100 is exposed, and spacer 150 is formed. The processing is performed, for example, using a re-embedded optical fiber (RIE).

[0066] Next, as Figure 6C As shown, the mask film 110, insulating film 120, and spacer 150 are processed. The processing is performed, for example, using a RIE / WET. Figure 6C As shown, the spacer 150 located above the protrusion 52a is thinner than the spacers 150 located in other positions.

[0067] Next, as Figure 6D As shown, the spacer 150 is used as a mask to process the semiconductor film 100. The processing of the semiconductor film 100 is performed, for example, using a resonant electronic material (RIE). Figure 6DAs shown, the spacer 150 disposed above the protrusion 52a completely disappears during processing. Since the spacer 150, which serves as a mask, disappears, the semiconductor film 100 above the protrusion 52a also disappears.

[0068] Next, as Figure 6E As shown, the spacer 150 is used as a mask to process the wiring component 52. Through the processing of the wiring component 52, wiring 51 arranged in a specified pattern, such as a line and gap pattern, is formed. Furthermore, from... Figure 6D The steps shown are as follows: Figure 6E The steps shown are continued. As... Figure 6E As shown, because the spacer 150, which serves as a mask, disappears, the wiring 51 is not formed at the location where the protrusion 52a is generated. In other words, the wiring 51 has a recessed defect.

[0069] In contrast, in the first embodiment, by cyclically forming the conductive film 54 and the film 55, the large particle size of the conductive film 54 can be suppressed, thereby improving the surface roughness of the wiring component 52. As a result, the formation of protrusions 52a can be suppressed, thereby suppressing defects in the wiring 51.

[0070] In addition, for example, through experiments Figure 5 The thickness of the conductive film 54 is determined by the relationship between the thickness of the conductive film 54 and the defects generated in the wiring 51.

[0071] (Comparative Example 2)

[0072] Figure 7 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device according to the second comparative example. The second comparative example differs from the first embodiment in that the wiring component 52 is entirely composed of a nucleation layer 53.

[0073] In the second comparative example, the first embodiment was continued. Figure 3A The steps shown are as follows. The nucleation layer 53 is amorphous. Therefore, the surface roughness of the wiring component 52 is improved compared to the first comparative example. However, the resistivity of the wiring 51 increases. As a result, the wiring resistance of the wiring 51 increases.

[0074] In contrast, in the first embodiment, a plurality of conductive films 54 with a certain particle size are formed. This reduces the specific resistance of the wiring 51. As a result, a wiring component 52 with low resistance and improved surface roughness can be formed.

[0075] (Second Implementation)

[0076] The second embodiment differs from the first embodiment in that the film 55 is an oxide film.

[0077] The main component of the film 55 is an oxide of a metal element that is the main component of the conductive film 54.

[0078] The film 55 that is an oxide film is formed, for example, by oxidizing the surface of the conductive film 54. The conductive film 54 contains tungsten (W), and therefore the film 55 contains WO x as the main component. Further, the film 55 is an amorphous film.

[0079] Since the film 55 is an oxide film, the film 55 can be formed more easily.

[0080] In addition, there is a case where, if tungsten hexafluoride and hydrogen gas are supplied to WO x , the WO x is reduced to make the film 55 thin. In this case, it is possible to increase the proportion of the thickness of the conductive film 54 to the thickness of the entire wiring member 52. As a result, it is possible to further reduce the wiring resistance of the wiring 51.

[0081] The film 55 can be an oxide film as in the second embodiment. In this case, the same effects as in the first embodiment can be obtained.

[0082] (Third Embodiment)

[0083] The third embodiment differs from the first embodiment in that the film 55 is a core formation layer of the conductive film 54.

[0084] The main component of the film 55 is the same as the main component of the conductive film 54. More specifically, the film 55 is a core formation layer of the conductive film 54.

[0085] The film 55 that is a core formation layer is formed, for example, in the same manner as the core formation layer 53 of the steps shown in Figure 3A . In this case, the film 55 is a tungsten film that contains more boron (B) based on diborane, which is a material gas used to form the core formation layer. Therefore, the film 55 contains boron (B) based on diborane. Further, the film 55 is an amorphous film.

[0086] The film 55 is a metal film, and therefore the electric resistance is relatively low. Thus, it is possible to further reduce the wiring resistance of the wiring 51.

[0087] The film 55 can be a core formation layer as in the third embodiment. In this case, the same effects as in the first embodiment can be obtained.

[0088] (Fourth Embodiment)

[0089] Figure 8 is a cross-sectional view that shows an example of the configuration of a semiconductor device according to the fourth embodiment. Figure 8 The semiconductor device shown in is a three-dimensional memory in which an array chip C1 and a circuit chip C2 are bonded.

[0090] The array chip C1 has a memory cell array 11 including a plurality of memory cells arranged in three dimensions, an insulating film 12 on the memory cell array 11, and an interlayer insulating film 13 under the memory cell array 11. The insulating film 12 is, for example, a silicon oxide film or a silicon nitride film. The interlayer insulating film 13 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film.

[0091] The circuit chip C2 is provided under the array chip C1. The symbol S represents a bonding surface of the array chip C1 and the circuit chip C2. The circuit chip C2 has an interlayer insulating film 14 and a substrate 15 under the interlayer insulating film 14. The interlayer insulating film 14 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and another insulating film. The substrate 15 is an example of a first substrate, and is, for example, a semiconductor substrate such as a silicon substrate. Figure 8 The X direction and the Y direction parallel to the surface, i.e., the upper surface, of the substrate 15 and perpendicular to each other, and the Z direction perpendicular to the surface of the substrate 15 are shown. The Y direction is an example of a first direction, the X direction is an example of a second direction intersecting the first direction, and the Z direction is an example of a third direction intersecting the first and second directions.

[0092] The array chip C1 has a plurality of word lines WL and a source line SL as a plurality of electrode layers within the memory cell array 11. Figure 8 A step structure portion 21 of the memory cell array 11 is shown. Each word line WL is electrically connected to a word wiring layer 23 via a contact plug 22. Each columnar portion CL penetrating a plurality of word lines WL is electrically connected to a bit line BL via a via plug 24, and is electrically connected to a source line SL. The source line SL includes a first layer SL1 which is a semiconductor layer, and a second layer SL2 which is a metal layer. The symbol V represents a via plug provided under the bit line BL.

[0093] The circuit chip C2 has a plurality of transistors 31. Each transistor 31 has a gate electrode 32 provided on the substrate 15 with a gate insulating film interposed, and a source diffusion layer and a drain diffusion layer not shown which are provided within the substrate 15. In addition, the circuit chip C2 has a plurality of contact plugs 33 provided on the source diffusion layer or the drain diffusion layer of these transistors 31, a wiring layer 34 provided on these contact plugs 33 and including a plurality of wirings, and a wiring layer 35 provided on the wiring layer 34 and including a plurality of wirings.

[0094] The circuit chip C2 further has a wiring layer 36 provided on the wiring layer 35 and including a plurality of wirings, a plurality of via plugs 37 provided on the wiring layer 36, and a plurality of metal pads 38 provided on these via plugs 37. The metal pad 38 is, for example, a Cu (copper) layer or an Al (aluminum) layer. The circuit chip C2 functions as a control circuit (logic circuit) which controls the operation of the array chip C1. The control circuit includes the transistors 31 and the like, and is electrically connected to the metal pad 38.

[0095] The array chip C1 has a plurality of metal pads 41 provided on the metal pad 38, and a plurality of via plugs 42 provided on the metal pads 41. In addition, the array chip C1 has a wiring layer 43 provided on the via plugs 42, which includes a plurality of wirings, and a wiring layer 44 provided on the wiring layer 43, which includes a plurality of wirings including a bit line BL. The metal pads 41 are, for example, Cu layers or Al layers. The via plugs V are connected to the wiring layer 43 and the bit line BL.

[0096] The array chip C1 further has a plurality of via plugs 45 provided on the wiring layer 44, a metal pad 46 provided on the via plugs 45 or the insulating film 12, and a passivation film 47 provided on the metal pad 46 or the insulating film 12. The metal pad 46 is, for example, a Cu layer or an Al layer, and functions as an external connection pad (bonding pad) of the semiconductor device. The passivation film 47 is, for example, an insulating film such as a silicon oxide film, and has an opening portion P exposing an upper surface of the metal pad 46. The metal pad 46 can be connected to a mounting substrate or another device via the opening portion P by a bonding wire, a solder ball, a metal bump, or the like. Figure 8

[0097] Here, the wirings 51 in the wiring layer 50 described in the first to third embodiments correspond to, for example, the wirings in the wiring layer 44. In addition, the up-down direction of the wirings 51 in the wiring layer 50 is reversed with respect to the up-down direction of the wirings in the wiring layer 44. Figure 8 Figure 1

[0098] The embodiments of the present application have been described, but these embodiments are presented as examples, and are not intended to limit the scope of the application. The embodiments can be implemented in other various ways, and various omissions, substitutions, and changes can be made without departing from the scope of the application. The embodiments or changes thereof are included in the scope or spirit of the application, and are also included in the application and the equivalent scope described in the claims.

[0099] [Explanation of Symbols]

[0100] 11: memory cell array

[0101] 50: wiring layer

[0102] 51: wiring

[0103] 54: conductive film

[0104] 55: film

[0105] 80: columnar electrode

[0106] 90: insulating film

[0107] CL: columnar portion​​​

Claims

1. A semiconductor device comprising: a wiring layer including a plurality of wirings; and a columnar electrode provided integrally with the wiring and extending from a bottom portion of the wiring in a direction substantially perpendicular to the wiring layer; and the wiring has a conductive film and a first film different from the conductive film alternately laminated in the direction substantially perpendicular to the wiring layer.

2. The semiconductor device according to claim 1, wherein the first film is provided in a manner to break a crystal grain of the conductive film between two conductive films sandwiching the first film.

3. The semiconductor device according to claim 1, wherein a main component of the first film is different from a main component of the conductive film.

4. The semiconductor device according to claim 3, wherein the main component of the first film is boron (B).

5. The semiconductor device according to claim 3, wherein the main component of the first film is an oxide of a metal element that is the main component of the conductive film.

6. The semiconductor device according to claim 1, wherein the main component of the first film is the same as the main component of the conductive film.

7. The semiconductor device according to claim 6, wherein the first film is a core formation layer of the conductive film.

8. The semiconductor device according to claim 7, wherein the first film includes boron (B).

9. The semiconductor device according to claim 1, wherein the first film is an amorphous film.

10. The semiconductor device according to claim 1, wherein the main component of the conductive film is tungsten (W).

11. The semiconductor device according to claim 1, wherein a number of laminations of the conductive film and the first film is two or more.

12. The semiconductor device according to claim 1, wherein a thickness of the conductive film in the direction substantially perpendicular to the wiring layer is 15 nm or less.

13. The semiconductor device according to claim 1, further comprising an insulating film provided on the plurality of wirings, and the insulating film is configured in accordance with a shape of the plurality of wirings as viewed from the direction substantially perpendicular to the wiring layer.

14. The semiconductor device according to claim 1, further comprising: a memory cell array; and a plurality of columnar portions penetrating the memory cell array; and the plurality of wirings and the plurality of columnar portions are electrically connected respectively.

15. A semiconductor device comprising a wiring layer including a plurality of wirings, the wiring has a conductive film and a first film different from the conductive film alternately laminated in a direction substantially perpendicular to the wiring layer, a main component of the first film is different from a main component of the conductive film, and a number of laminations of the conductive film and the first film is five or more.

16. The semiconductor device according to claim 3, wherein the main component of the first film is boron (B) or an oxide of a metal element that is the main component of the conductive film, or the first film is an amorphous film.

17. The semiconductor device according to claim 1, wherein a thickness of the conductive film in the direction substantially perpendicular to the wiring layer is 15 nm or less.

18. A semiconductor device comprising: a wiring layer including a plurality of wirings; and ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ a columnar electrode provided integrally with the wiring and extending from a bottom of the wiring in a direction substantially perpendicular to the wiring layer; the wiring has a conductive film and a first film different from the conductive film alternately stacked in a direction substantially perpendicular to the wiring layer, and a main component of the first film is the same as a main component of the conductive film, or the first film is an amorphous film.

19. The semiconductor device according to claim 18, wherein in the case where the main component of the first film is the same as the main component of the conductive film, the first film is a core formation layer of the conductive film.

20. The semiconductor device according to claim 19, wherein in the case where the main component of the first film is the same as the main component of the conductive film, the first film contains boron (B).

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