Method and apparatus for operating storage device

Abstract

The invention provides a method, a device and a system for managing storage equipment. In one aspect, a method for operating a memory device includes programming a memory block of the memory device by programming each of a set of memory strings included in the memory block; and validating the memory block by validating memory strings of the set of memory strings in the memory block that are less than all of the memory strings.

Description

Technical Field

[0001] In general, this disclosure relates to storage devices and storage systems, and more specifically, to managing programming time in storage systems. Background Technology

[0002] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as programming (writing) and erasing operations, to change the threshold voltage of each storage cell to a corresponding level. For NAND flash memory, erasing operations can be performed at the block level, programming operations can be performed at the page level, and reading operations can be performed at the page level. Summary of the Invention

[0003] This disclosure relates to methods, apparatus, and systems for managing program timing in a storage device. One aspect of this disclosure is characterized by an example method for operating a storage device. The method includes: programming a storage block of the storage device by programming each of a set of storage strings in the storage block; and verifying the storage block by verifying a smaller number of storage strings from the set of storage strings compared to all other storage strings.

[0004] In some embodiments, the method further includes: determining the number of faulty memory cells in a set of memory strings that is fewer than all memory strings in the memory block; and determining whether the programming of the memory block was successful based on the number of faulty memory cells.

[0005] In some implementations, programming the memory block includes programming the set of memory strings using a set of programming pulses. Verifying the memory block includes verifying a smaller number of memory strings in the set of memory strings compared to all memory strings using one or more verification pulses. The amount of the one or more verification pulses is less than the amount of the set of programming pulses.

[0006] In some implementations, programming the memory block includes programming the set of memory strings by applying a set of programming pulses to a word line coupled to the memory cells of the set of memory strings. Verifying the memory block includes verifying only one of the set of memory strings by applying a verification pulse to the word line.

[0007] In some implementations, verifying a smaller number of storage strings in the set of storage strings within the storage block compared to all storage strings includes: identifying one or more selected storage strings in the set of storage strings; and verifying the one or more selected storage strings by applying the one or more verification pulses.

[0008] In some embodiments, the method further includes reading configuration data from a register of the storage device. The configuration data indicates one or more selected memory strings.

[0009] In some implementations, a first memory string, which is a smaller number of memory strings compared to all memory strings in the set, is programmed using a first programming pulse from the set of programming pulses. The first memory string is verified using a first verification pulse from one or more verification pulses, and the first verification pulse immediately follows the first programming pulse.

[0010] In some implementations, the storage block comprises a single-level unit.

[0011] In some embodiments, programming each of the set of memory strings included in the memory block includes: applying a first programming pulse to a word line to program a first memory cell of the first memory string; and applying a second programming pulse to the word line to program a second memory cell of the second memory string. The word line is coupled to the first memory cell in the first memory string and the second memory cell in the second memory string. The first memory string and the second memory string are included in the memory block. Verifying a memory string that is fewer than all the memory strings in the set of memory strings in the memory block includes: applying a verification pulse to the word line to verify one of the first memory string or the second memory string. The second programming pulse and the first programming pulse are applied consecutively, and the verification pulse is applied after the second programming pulse.

[0012] In some implementations, programming each of the set of memory strings includes: when the first programming pulse is applied, applying a first voltage to a first select line coupled to a first select gate transistor of the first memory string; and applying a ground voltage to a second select line coupled to a second select gate transistor of the second memory string.

[0013] In some implementations, programming each of the set of memory strings includes: when the second programming pulse is applied: applying the ground voltage to the first select line; and applying the first voltage to the second select line.

[0014] In some implementations, verifying a smaller number of memory strings in the set of memory strings in the memory block compared to all memory strings includes: when the verification pulse is applied: applying a second voltage to one of the first select line or the second select line; and applying the ground voltage to the other of the first select line or the second select line.

[0015] In some implementations, the second voltage is higher than the first voltage.

[0016] One aspect of this disclosure provides a storage device. The storage device includes: a storage array including storage blocks, the storage blocks comprising a set of storage strings; and peripheral circuitry coupled to the storage array. The peripheral circuitry is configured to perform operations including: programming the storage blocks by programming each of the storage strings in the set; and verifying the storage blocks by verifying a smaller number of storage strings in the set compared to all the storage strings.

[0017] In some implementations, the operation further includes: determining the number of faulty memory cells in a set of memory strings that is fewer than all memory strings in the memory block; and determining whether the programming of the memory block was successful based on the number of faulty memory cells.

[0018] In some implementations, programming the memory block includes programming the set of memory strings using a set of programming pulses. Verifying the memory block includes verifying a smaller number of memory strings in the set of memory strings compared to all memory strings using one or more verification pulses. The amount of the one or more verification pulses is less than the amount of the set of programming pulses.

[0019] In some implementations, programming the memory block includes programming the set of memory strings by applying a set of programming pulses to a word line coupled to the memory cells of the set of memory strings. Verifying the memory block includes verifying only one of the set of memory strings by applying a verification pulse to the word line.

[0020] In some implementations, verifying a smaller number of storage strings in the set of storage strings within the storage block compared to all storage strings includes: identifying one or more selected storage strings in the set of storage strings; and verifying the one or more selected storage strings by applying the one or more verification pulses.

[0021] In some embodiments, the method further includes reading configuration data from a register of the storage device. The configuration data indicates one or more selected memory strings.

[0022] One aspect of this disclosure is a storage system. The storage system includes a storage device and a memory controller coupled to the storage device and configured to control the storage device. Another aspect of this disclosure is a storage device. The storage device includes: a storage array comprising storage blocks, the storage blocks comprising a set of storage strings; and peripheral circuitry coupled to the storage array. The peripheral circuitry is configured to perform operations including: programming the storage block by programming each of the storage strings in the set; and verifying the storage block by verifying a smaller number of storage strings in the set compared to all other storage strings.

[0023] Although generally described as computer-implemented software embodied on a tangible medium for processing and transforming corresponding data, some or all aspects may be computer-implemented methods or further included in a corresponding system or other device for performing the described functions. These and other aspects of this disclosure, along with details of implementation, are set forth in the accompanying drawings and the description below. Other features, objectives, and advantages of this disclosure will be apparent from the description, figures, and claims. Attached Figure Description

[0024] Figure 1 An example of a schematic diagram of a storage device, including peripheral circuitry, is shown according to some aspects of this disclosure.

[0025] Figure 2 An example of a side view of a cross-section of a storage array including storage strings, according to some aspects of this disclosure, is shown.

[0026] Figure 3 A schematic example of a storage cell block including a storage string is shown, according to some aspects of this disclosure.

[0027] Figure 4 An example plan view of a cross-section of a storage block of a storage array is shown, according to some aspects of this disclosure.

[0028] Figure 5 Some example peripheral circuits are shown in accordance with some aspects of this disclosure.

[0029] Figure 6A An example pulse scheme for programming a memory string in a memory block is shown, according to some aspects of this disclosure.

[0030] Figure 6B Another example pulse scheme for programming a memory string in a memory block is shown, based on some aspects of this disclosure.

[0031] Figure 7 This disclosure illustrates some aspects and applications of the content. Figure 6A The pulse scheme in the image is an example of the voltage of each component in the storage block.

[0032] Figure 8 This disclosure illustrates some aspects and applications of the content. Figure 6B The pulse scheme in the image is an example of the voltage of each component in the storage block.

[0033] Figure 9 An example flowchart of a method for performing programming operations in a storage device according to some aspects of this disclosure is shown.

[0034] Figure 10 A memory block diagram of an example system having a storage device is shown, according to some aspects of this disclosure.

[0035] Figure 11A A diagram of a memory card with storage devices is shown, according to some aspects of this disclosure.

[0036] Figure 11B A diagram of a solid-state drive (SSD) having a storage device is shown, according to some aspects of this disclosure.

[0037] The same reference numerals and symbols in the various figures indicate the same elements. Detailed Implementation

[0038] This specification relates to storage devices, storage systems, and methods for managing programming time in flash memory. Flash memory, such as NAND flash memory with single-level cell (SLC), is known for its high reliability and fast programming speed and is widely used in applications such as aerospace and cache programming. With the increasing demand for system-level performance improvements, NAND flash memory with SLC needs to improve programming speed by reducing programming time.

[0039] In some cases, NAND flash memory with SLC implements a program-to-verify (1P1V) programming method, where each memory string is programmed using a programming pulse and then verified using a verification pulse. The 1P1V programming method can require a relatively long programming time, which can affect the programming speed of the storage device.

[0040] This disclosure provides techniques for reducing programming time in SLC-based NAND flash memory. Since the memory strings in SLC-based NAND flash memory are generally similar to each other, the success of programming a single memory string can be used to indicate whether a group of memory strings (e.g., a group of memory strings included in a memory block) has been successfully programmed. In some embodiments, after programming a group of memory strings in a memory block, a smaller number of memory strings in the group are verified compared to all the memory strings. In some embodiments, after programming a group of memory strings in a memory block using a set of programming pulses, verification pulses are used to verify only one memory string. For example, programming a group of memory strings includes applying a set of programming pulses to selected word lines coupled to memory cells of the group of memory strings, and verifying only one memory string includes applying verification pulses to the selected word lines. The storage device can determine whether the group of memory strings has been successfully programmed based on the verification result of verifying one memory string in the group. As another example, more than one memory string in the group may be selected for verification, while the remaining memory strings in the group are not verified.

[0041] In some implementations, the storage device may receive configuration data that indicates one or more storage strings to be selected for verification after being programmed, while retaining the option to verify all storage strings in that group.

[0042] In some implementations, the technique can achieve one or more technical effects. For example, the technique can reduce the programming time of NAND flash memory with SLC, enabling faster programming speeds for storage devices without compromising performance margins. In some implementations, additional or different technical effects can be achieved.

[0043] Figure 1 An example of a schematic circuit diagram of a storage device 100, including peripheral circuitry, according to some aspects of this disclosure is shown. The storage device 100 may include a storage array 101 and peripheral circuitry 102 coupled to the storage array 101. The storage array 101 may be a NAND flash memory array comprising NAND memory cells 106 arranged in rows and columns. In some embodiments, the memory cells 106 in columns (e.g., along the z-direction) of the storage array 101 are coupled in series and stacked vertically. The memory cells 106 in rows (e.g., along the x-direction) of the storage array 101 are coupled to and controlled by word lines 118. Each memory cell 106 may maintain a continuous analog value, such as voltage or charge, depending on the number of electrons trapped within the storage layer of the memory cell 106. The logic state (i.e., data) of each memory cell 106 may be based on a threshold voltage V of the memory cell 106. thTo determine. Each memory cell 106 can be a floating-gate type memory cell including a floating-gate transistor or a charge-trap type memory cell including a charge-trap transistor.

[0044] In some implementations, each memory cell 106 is a single-level cell (SLC) with two possible memory states, capable of storing one bit of data. For example, a first memory state "0" (e.g., erase state) may correspond to a first voltage range, while a second memory state "1" (e.g., program state) may correspond to a second voltage range. In some implementations, to increase storage capacity, each memory cell 106 may be a multi-level cell (MLC), a three-level cell (TLC), or a four-level cell (QLC). An MLC stores 2 bits of data and has four logic states: logic {11, 10, 01, and 00}, i.e., the erase state, and programming states P1, P2, and P3. A TLC stores 3 bits of data and has eight logic states: logic {111, 110, 101, 100, 011, 010, 001, and 000}, i.e., the erase state, and programming states P1-P7. The QLC stores 4 bits of data and has 16 logical states, namely {1111, 1110, 1101, 1100, 1011, 1010, 1001, 1000, 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000}, which are the erase state and the programming state P1-P15.

[0045] like Figure 1 As shown, memory cells 106 in a column of memory array 101 can be coupled to a source-select-gate (SSG) transistor 110 at their source end and to a drain-select-gate (DSG) transistor 112 at their drain end. SSG transistors 110 and 112 can be configured to activate a selected column of memory array 101 during read and program operations. In some embodiments, the sources of SSG transistors in the same memory block are coupled via the same source line 114. The drain of each DSG transistor is coupled to a corresponding bit line 116. Data can be read from or written to a memory cell in a column of memory array 101 from bit line 116. In some embodiments, each column of memory array 101 is configured to be selected or deselected by applying a DSG select voltage or DSG deselect voltage to the gate of the corresponding DSG transistor 112 via one or more DSG lines 113, and / or applying a select voltage or deselect voltage to the gate of the corresponding SSG transistor 110 via one or more SSG lines 115.

[0046] In some implementations, adjacent columns of memory cells can be coupled via word lines 118. Word lines 118 can select which row of the memory array 101 is affected by read and program operations. In some implementations, memory cells 106 are SLCs, and each word line 118 is coupled to a physical page 120 of memory cell 106, where a physical page is a basic data unit used for programming operations. The size of a physical page 120 (in bits) is associated with the number of columns of memory cells in the memory block coupled by word lines 118. Each word line 118 may include a gate line coupled to multiple control gates (gate electrodes) of multiple memory cells 106 within a corresponding physical page 120. Figure 1 The example word lines shown include WL0, WL1, WL2, WL3, WL4, and WL5 between DSG line 113 and SSG line 115. In some embodiments, word lines may also include dummy word lines coupled to dummy memory cells.

[0047] In some implementations, the storage array 101 may include multiple storage blocks, and each storage block may include multiple storage strings 134, 134a, 134b. For example... Figure 1 As shown, each memory string 134, 134a, 134b may include memory cells 106 arranged in rows (e.g., coupled to word lines along the x-direction) and columns (e.g., connected in series along the z-direction). The SSG lines 115 of different memory strings 134, 134a, 134b within the same memory block are coupled together, allowing each memory block to be selected or deselected by applying a selection voltage or deselection voltage to the SSG lines 115. The DSG lines 115 of different memory strings 134, 134a, 134b within the same memory block are separated from each other, allowing each memory string 134, 134a, 134b within the memory block to be selected or deselected by applying a selection voltage or deselection voltage to the DSG lines 113. For example, the first memory string 134 can be selected for programming by applying a selection voltage to the DSG line 113; the second DSG line (106) coupled to the DSG transistor in memory string 134a can be selected or deselected by applying a selection voltage to the DSG line 113. Figure 1 The second memory string 134a can be selected for programming by applying a selection voltage (not shown in the image); and the third DSG line (coupled to the DSG transistor in memory string 134b) can be used for programming. Figure 1 (Not shown) Apply a selection voltage to select the third memory string 134b for programming.

[0048] Peripheral circuitry 102 can be coupled to memory array 101 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory array 101 by applying and sensing voltage and / or current signals to and from each target memory cell 106 via bit line 116, word line 118, source line 114, SSG line 115, and DSG line 113. Peripheral circuitry 102 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0049] Figure 2 An example of a side view of a cross-section of a storage array 101 according to some aspects of this disclosure is shown. (See example...) Figure 2 As shown, the memory cells 106 in the columns of the memory array 101 can be connected in series and extend vertically through the memory stack 204 above the substrate 202. The substrate 202 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0050] The memory stack 204 may include interlaced pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208. The number of interlaced pairs of gate conductive layers 206 and gate-to-gate dielectric layers 208 in the memory stack 204 determines the number of memory cells 106 in the memory array 101. The gate conductive layers 206 may include conductive materials, including but not limited to one or more of the following: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, or silicides. In some embodiments, each gate conductive layer 206 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 206 includes a doped polysilicon layer. Each gate conductive layer 206 may include a control gate surrounding a memory cell 106, a DSG transistor 112, or an SSG transistor 110, and may extend laterally as a DSG line 113 at the top of the memory stack 204, an SSG line 115 at the bottom of the memory stack 204, or a word line 118 between DSG lines 113 and SSG lines 115.

[0051] Figure 3 Storage block 304 of a storage array is shown according to some aspects of this disclosure (e.g., Figure 1An example of a plan view of a cross-section of the memory array 101. In some embodiments, each memory block 304 can serve as the basic data unit for an erase operation, such that all memory cells 106 on the same memory block 304 are erased simultaneously. To erase memory cells 106 in a selected memory block 304, an erase voltage can be used to bias the source lines coupled to the selected memory block 304 and unselected memory blocks in the same plane (e.g., ...). Figure 1 (Source line 114). For example, the erase voltage can be a high positive voltage (e.g., 20V or higher). In some implementations, the erase operation can be performed at the half-block level, the quarter-block level, or at a level with any appropriate number of blocks or a fraction of blocks.

[0052] In some embodiments, storage block 304 may include multiple storage strings 134. Storage strings 134 are separated from each other by DSG cutouts 332, which electrically separate the DSG lines 113 of different storage strings 134. Therefore, each storage string 134 can be individually selected or deselected by applying a DSG voltage to the corresponding DSG line 113. In some embodiments, storage strings 134 may be arranged into fingers 334 via SSG cutouts 330, where SSG lines 115 electrically separate the different fingers 334. Therefore, each finger 334 can be individually selected or deselected by applying an SSG voltage to the corresponding SSG line 115. Figure 3 In the example shown, memory block 304 includes three fingers 334 separated by SSG cutouts 330, and each finger 334 includes two memory strings 134 separated by DSG cutouts 332. In some embodiments, memory block 304 may include a different number of fingers 334, and each finger 334 may include a different number of memory strings 134. In some embodiments, memory block 304 does not include SSG cutouts 330, and the SSG lines 115 of all memory strings 134 in memory block 304 are electrically connected. Therefore, by applying a select or deselect voltage to the SSG lines in memory block 304, the entire memory block 304 can be selected or deselected.

[0053] Figure 4An example schematic diagram of a memory block 304 of a memory array 101 is shown. According to certain aspects of this disclosure, the memory block 304 may include memory strings 134. In some embodiments, the memory block 304 may be divided into fingers 334a and 334b. Each finger 334 may include one or more memory strings 134. The SSG transistors 110 of the memory strings 134 in the same finger 334 are coupled to the same SSG line 115. For example, the SSG transistors 110 of the memory strings 134 of the first finger 334a are coupled to a first SSG line represented by SSG0; the SSG transistors 110 of the memory strings 134 of the second finger 334b ​​are coupled to a second SSG line represented by SSG1.

[0054] In some embodiments, DSG transistors 112 in the same memory string 134 are coupled to the same DSG line 113. For example, the DSG transistors 112 of the first memory string in memory block 304 are coupled to the first DSG line represented by DSG0; the DSG transistors 112 of the second memory string in memory block 304 are coupled to the second DSG line represented by DSG1; the DSG transistors 112 of the third memory string in memory block 304 are coupled to the third DSG line represented by DSG2; and the DSG transistors 112 of the fourth memory string in memory block 304 are coupled to the fourth DSG line represented by DSG3.

[0055] In some implementations, memory cells 106 in adjacent memory strings 134 can be coupled via word lines. Figure 4 The example word lines shown include dummy WL, WL1, WL2, WL3, WL4, and WL5 between the DSG and SSG lines. For example, memory cells 106 at the same vertical position (e.g., along the z-direction) in adjacent memory strings 134 are coupled to the same word line.

[0056] In some embodiments, the memory block 304 may include a different number of fingers 334, and each finger 334 may include a different number of memory strings 134. In some embodiments, the memory strings 134 are not arranged as fingers 334, for example, by coupling the SSG transistors of all memory strings 134 of the memory block 304 to the same SSG line.

[0057] Figure 5 Some example peripheral circuitry according to certain aspects of this disclosure is shown. The example peripheral circuitry includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus. In some examples, it may also include... Figure 5 Additional peripheral circuitry not shown.

[0058] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory array 101 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store one page of programming data (write data) to be programmed into memory array 101. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 106 coupled to the selected word line 118. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 116 representing data bits stored in memory cell 106 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 to select one or more memory strings 408, 418 by applying a bit line voltage generated from voltage generator 510.

[0059] The line decoder / word line driver 508 can be configured to be controlled by control logic 512 to select / deselect memory blocks 304 of memory array 101 and select / deselect word lines 118 of memory blocks 304. The line decoder / word line driver 508 can also be configured to drive word lines 118 using word line voltages generated from voltage generator 510. In some embodiments, the line decoder / word line driver 508 can select / deselect and drive SSG lines 115 and DSG lines 113. As described in detail below, the line decoder / word line driver 508 is configured to apply a programming voltage to the selected word line 118 during programming operations on memory cells 106 coupled to the selected word line 118.

[0060] Voltage generator 510 can be configured to be controlled by control logic 512 to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be applied to memory array 101.

[0061] Control logic 512 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and may include a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0062] Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer control commands received from the host (not shown) and status information received from control logic 512, and relay control commands to control logic 512 and status information to the host. Interface 516 can also be coupled to column decoder / bit line driver 506 via a data bus and act as a data input / output (I / O) interface and data buffer to buffer and relay data to and from memory array 101.

[0063] Figures 6A-6B Example pulse schemes 601 and 602 for programming memory strings in a memory block are shown, according to some aspects of this disclosure. (Reference) Figure 4 Storage cells in different storage strings 134 of storage block 304 are coupled via word lines. For example, storage cells at the same vertical position (e.g., along the z-direction) in each storage string 134 are coupled to the same word line. When storage block 304 is programmed, the storage cells coupled to different word lines are programmed sequentially, for example, from top to bottom (e.g., from WL1 to WL5) or from bottom to top (e.g., from WL5 to WL1). When programming the storage cells coupled to each word line (e.g., one of WL1 to WL5), multiple programming pulses 610 are applied to the word line. Each programming pulse is used to program the storage cell of the corresponding storage string coupled to the word line. As an example, storage block 304 may include six storage strings 134, for example, storage strings 0-5. When storage block 304 is programmed, six programming pulses 610 may be applied to each word line. Each of the six programming pulses 610 is used to program the storage cell of the corresponding storage string in the six storage strings. For example, the starting programming pulse can be used to program memory string 0, and the sixth programming pulse can be used to program memory string 5.

[0064] like Figure 6AAs shown, in pulse scheme 601, each programming pulse 610 is followed by a verification pulse 612. By applying the programming pulse 610 to the word line, the memory cells coupled to the word line can be programmed from an erase state to a programmed state. Each programming pulse may have a programming voltage (e.g., a voltage between 10V and 30V) and may have a pulse length during which the programming voltage is applied (e.g., a duration between 1μs and 30μs). Each verification pulse may have a verification voltage (e.g., a voltage between -1.5V and 5V) and may have a pulse length during which the verification pulse 612 is applied (e.g., a duration between 1μs and 30μs). By applying the verification pulse 612 to the word line after the programming pulse 610, the storage device can verify whether the memory cells in the memory string have been successfully programmed to the programmed state. For example, by applying the verification pulse 612, the storage device can determine the number of faulty memory cells in each memory string of the memory block and determine whether each memory string has been successfully programmed based on the number of faulty memory cells. If the number of faulty memory cells in a memory string exceeds a threshold, in some cases the storage device can apply another programming pulse to the word line to reprogram the memory string, or in some other cases the storage device can report the faulty memory string or the faulty memory block containing the faulty memory string to the memory controller.

[0065] In some implementations, programming pulses are used to program an SLC having two possible states corresponding to one bit of information, and the programming voltage and pulse length are the same for each programming pulse 610 in pulse scheme 601. By applying a verification pulse 612 after each programming pulse 610, the programming time (e.g., the time required to apply the programming pulse 610 and the verification pulse 612 in pulse scheme 601) can be long, which can affect the speed and efficiency of the storage device.

[0066] like Figure 6BAs shown, in pulse scheme 602, to reduce programming time, when programming the memory block, only a smaller number of memory strings in the memory block compared to all memory strings are verified. The number of verification pulses 612 in pulse scheme 602 is less than the number of programming pulses 610. That is, after programming with programming pulse 610, only the selected memory strings in the memory block are verified, and the remaining memory strings are not verified. In some embodiments, the verification of the selected memory strings can indicate whether all memory strings in the memory block have been successfully programmed. As an example, when programming a memory block comprising 6 memory strings, after applying 6 programming pulses to the word line, a verification pulse 612a can be applied to the word line to verify whether the memory cell in one of the 6 memory strings (e.g., memory string 5) has been successfully programmed into a programmed state. In some embodiments, more than one of the selected memory strings in the memory block is verified. For example, the selected memory strings used for verification may include memory string 3. The verification pulse 612 used to verify the memory string 3 can follow the last programming pulse 610b of the pulse scheme 602, or it can immediately follow the fourth programming pulse 610a used to program the memory string 3.

[0067] In pulse scheme 602, by verifying one or more selected memory strings in the memory block, the storage device can determine the number of faulty memory cells in one or more selected memory strings, and determine whether the memory block has been successfully programmed based on the number of faulty memory cells. If the number of faulty memory cells in one or more memory strings is greater than a threshold, in some cases, the storage device can apply another set of programming pulses to the word line to reprogram all memory strings in the memory block, or in some other cases, the storage device can report the faulty memory block to the memory controller.

[0068] In some implementations, the memory controller can send configuration data to the storage device indicating which memory strings in the memory block are selected for verification. The storage device can store the configuration data, for example, in a register of the storage device. During programming operations, the storage device can read the configuration data from the register to identify the memory strings selected for verification. Verification of the selected memory strings is performed after programming.

[0069] In some embodiments, pulse schemes 601 and 602 are used to program a single-level cell (SLC). In other embodiments, pulse schemes 601 and 602 are used to program a multi-level cell (MLC), three-level cell (TLC), or four-level cell (QLC) operating in SLC mode, such as worn MLCs, TLCs, or QLCs that can be programmed and accessed like SLCs.

[0070] Based on some aspects of this disclosure, Figure 7 It shows when the application Figure 6A The pulse scheme 601 in the memory block (e.g., Figures 3-4 An example of the voltage of a component in storage block 304. A storage block may include a set of storage strings (e.g., ...). Figure 1 , Figure 2 and Figure 4 The memory strings (134), for example, memory strings 0-5, are coupled to DSG line 712 in DSG lines 0-5. All memory strings in a set of memory strings in a memory block are coupled to the same SSG line 716. The selected word line 714 represents the word line in the memory block selected for programming and verification.

[0071] A pulse scheme 601 is applied to the selected word line 714. The pulse scheme 601 includes a verification pulse 612 following each programming pulse 610. When the programming pulse 610 is applied to the selected word line 714 to program a memory string (e.g., memory string 0) of the memory block, a first selection voltage 722 is applied to the DSG line 712 of the memory string to turn on the DSG transistors in the memory string, while an unselected voltage (e.g., ground voltage) is applied to the DSG lines 712 of other memory strings. This allows memory strings (e.g., memory string 0) to be selected for programming, while other memory strings are deselected for programming. Furthermore, when the verification pulse 612 is applied to the selected word line 714 to verify the memory string of the memory block, a second selection voltage 724 is applied to the DSG line 712 of the memory string, and a third selection voltage 726 is applied to the SSG line 716, while deselection voltages are applied to the DSG lines 712 of other memory strings. This allows memory strings to be selected for verification, while other memory strings are deselected for verification. In some implementations, the first selection voltage 722, the second selection voltage 724, and the third selection voltage 726 may have the same or different voltage values. For example, the second selection voltage 724 may be greater than the first selection voltage 722.

[0072] like Figure 7 The example shown demonstrates that a memory block comprising six memory strings can be programmed and verified using six programming pulses and six verification pulses. A first programming pulse is applied to the selected word line 714 to program memory string 0. When the first programming pulse is applied during a first programming interval, a first selection voltage 722 is applied to the DSG line 0 coupled to memory string 0. A first verification pulse is applied to the selected word line 714 to verify memory string 0. When the first verification pulse is applied during a first verification interval, a second selection voltage 724 is applied to DSG line 0, and a third selection voltage 726 is applied to SSG line 716.

[0073] During another time interval, a second programming pulse is applied to the selected word line 714 to program memory string 1. When the second programming pulse is applied, a first selection voltage 722 is applied to DSG line 1 coupled to memory string 1. A second verification pulse is applied to the selected word line 714 to verify memory string 1. When the second verification pulse is applied, a second selection voltage 724 is applied to DSG line 1, and a third selection voltage 726 is applied to SSG line 716.

[0074] During another time interval, a third programming pulse is applied to the selected word line 714 to program memory string 2. When the third programming pulse is applied, a first selection voltage 722 is applied to DSG line 2 coupled to memory string 2. A third verification pulse is applied to the selected word line 714 to verify memory string 2. When the third verification pulse is applied, a second selection voltage 724 is applied to DSG line 2, and a third selection voltage 726 is applied to SSG line 716.

[0075] During another time interval, a fourth programming pulse is applied to the selected word line 714 to program the memory string 3. When the fourth programming pulse is applied, a first selection voltage 722 is applied to the DSG line 3 coupled to the memory string 3. A fourth verification pulse is applied to the selected word line 714 to verify the memory string 3. When the fourth verification pulse is applied, a second selection voltage 724 is applied to the DSG line 3, and a third selection voltage 726 is applied to the SSG line 716.

[0076] During another time interval, a fifth programming pulse is applied to the selected word line 714 to program the memory string 4. When the fifth programming pulse is applied, a first selection voltage 722 is applied to the DSG line 4 coupled to the memory string 4. A fifth verification pulse is applied to the selected word line 714 to verify the memory string 4. When the fifth verification pulse is applied, a second selection voltage 724 is applied to the DSG line 4, and a third selection voltage 726 is applied to the SSG line 716.

[0077] During another time interval, a sixth programming pulse is applied to the selected word line 714 to program the memory string 5. When the sixth programming pulse is applied, a first selection voltage 722 is applied to the DSG line 5 coupled to the memory string 5. A sixth verification pulse is applied to the selected word line 714 to verify the memory string 5. When the sixth verification pulse is applied, a second selection voltage 724 is applied to the DSG line 5, and a third selection voltage 726 is applied to the SSG line 716.

[0078] In some implementations, the storage block may include a different number of storage strings. Depending on the number of storage strings, the storage block may include a different number of DSG lines 712, and the pulse scheme 601 may include a different number of programming pulses and a different number of verification pulses.

[0079] Based on some aspects of this disclosure, Figure 8 It shows when the application Figure 6B The pulse scheme 602 in the memory block (e.g., Figures 3-4 An example of the voltage of a component in storage block 304. A storage block may include a set of storage strings (e.g., ...). Figure 1 , Figure 2 and Figure 4 The memory strings (134), for example, memory strings 0-5, are coupled to DSG line 812 in DSG lines 0-5. All memory strings in a set of memory strings in a memory block are coupled to the same SSG line 816. The selected word line 814 represents the word line in the memory block selected for programming and verification.

[0080] Pulse scheme 602 is applied to the selected word line 814. Pulse scheme 602 includes fewer verification pulses 612 than the programming pulse 610. In some implementations, one or more selected memory strings are verified after programming, while the remaining memory strings are not verified after programming. As an example, memory string 5 is verified after programming, while memory strings 0-4 are not verified after programming.

[0081] When a programming pulse 610 is applied to the selected word line 814 to program a memory string (e.g., memory string 0) of a memory block, a first selection voltage 822 is applied to the DSG line 812 of the memory string to turn on the DSG transistors in the memory string, while an unselected voltage (e.g., ground voltage) is applied to the DSG lines 812 of other memory strings (e.g., memory strings 1-5). Therefore, a memory string can be selected for programming, while other memory strings are deselected for programming. Furthermore, when a verification pulse 612 is applied to the selected word line 814 to verify a memory string (e.g., memory string 5) of a memory block, a second selection voltage 824 is applied to the DSG line 812 of the memory string, a third selection voltage 826 is applied to the SSG line 816, and a deselection voltage is applied to the DSG lines 812 of other memory strings (e.g., memory strings 0-4). In this way, a memory string can be selected for verification, while other memory strings are deselected for verification. In some implementations, the voltage values ​​of the first selection voltage 822, the second selection voltage 824, and the third selection voltage 826 may be different. For example, the second selection voltage 824 may be greater than the first selection voltage 822.

[0082] like Figure 8The example shown allows for the programming of a memory block comprising six memory strings using six programming pulses, and the verification of the memory block using only one verification pulse. In a first time interval, a first programming pulse is applied to the selected word line 814 to program memory string 0. When the first programming pulse is applied, a first selection voltage 822 is applied to DSG line 0 coupled to memory string 0. In another time interval, a second programming pulse is applied to the selected word line 814 to program memory string 1. When the second programming pulse is applied, the first selection voltage 822 is applied to DSG line 1 coupled to memory string 1. In another time interval, a third programming pulse is applied to the selected word line 814 to program memory string 2. When the third programming pulse is applied, the first selection voltage 822 is applied to DSG line 2 coupled to memory string 2. In another time interval, a fourth programming pulse is applied to the selected word line 814 to program memory string 3. When the fourth programming pulse is applied, the first selection voltage 822 is applied to DSG line 3 coupled to memory string 3. In another time interval, a fifth programming pulse is applied to the selected word line 814 to program memory string 4. When the fifth programming pulse is applied, a first selection voltage 822 is applied to the DSG line 4 coupled to memory string 4. In another time interval, a sixth programming pulse is applied to the selected word line 814 to program memory string 5. When the sixth programming pulse is applied, the first selection voltage 822 is applied to the DSG line 5 coupled to memory string 5. After applying six programming pulses 610, a verification pulse 612 is applied to the selected word line to verify memory string 5. When the verification pulse 612 is applied, a second selection voltage 824 is applied to DSG line 5, and a third selection voltage 826 is applied to SSG line 816.

[0083] In some implementations, one or more different memory strings can be selected for verification. For example, memory string 2 can be selected instead of memory string 5 for verification. In this case, after applying a third programming pulse to programming memory string 2, a verification pulse can be applied to the selected word line 814 to verify memory string 2. As another example, memory strings 2 and 5 can be selected for verification. In this case, after applying a third programming pulse to programming memory string 2, a verification pulse can be applied to the selected word line 814 to verify memory string 2, and after applying six programming pulses 610, a verification pulse 612 is applied to the selected word line to verify memory string 5.

[0084] Figure 9 A flowchart of an example process 900 for performing programming operations in a storage device, according to some aspects of this disclosure, is shown. Process 900 can be performed by any suitable device or system described herein, for example, according to [the description of the process]. Figures 1-8The described example technology. For example, process 900 can be performed by a storage device, such as one including storage array 101. Figure 1 and Figure 5 Storage device 100. Storage array 101 may include one or more storage blocks (e.g., storage block 304), each storage block including a set of storage strings (e.g., Figures 3-4 (Memory string 134). Memory cells (e.g., SLCs) in different memory strings are coupled via word lines. In some embodiments, the storage device may also include peripheral circuitry (e.g., Figure 1 (External circuitry 102). The storage device can be part of the storage system, for example... Figure 10 The storage system 1002. Programming operations can be based on a pulse scheme (e.g., Figure 6B The pulse scheme 602 is executed, which includes fewer verification pulses than the programming pulses.

[0085] The operations shown in process 900 are not exhaustive, and other operations can be performed before, after, or between any of the illustrated operations. Furthermore, some of these operations can be performed simultaneously, or in conjunction with... Figure 9 The different sequences of execution are shown. In some implementations, some operations may be performed by one or more components of the device or system (e.g., peripheral circuitry of a storage device).

[0086] At 902, the storage block of the storage device is programmed by programming each of the storage strings in a set of storage strings included in the storage block. When programming a storage string in a set of storage strings (e.g., multiple storage strings), a programming pulse (e.g., ...) is generated. Figure 8 The programming pulse 610 in the memory string is applied to the word line coupled to the memory cell and the selection voltage (e.g., Figure 8 The selection voltage (822) is applied to the DSG line of the memory string.

[0087] At 904, the memory block is verified by verifying a smaller number of memory strings compared to all memory strings in the set of memory strings. In some implementations, one or more selected memory strings in a set of memory strings are verified without verifying the remaining memory strings. The one or more selected memory strings can be verified after all memory strings in the set have been programmed, or they can be verified immediately after programming the selected memory strings. When verifying a selected memory string, a verification pulse (e.g., ...) is applied. Figure 8 The verification pulse 612) is applied to the word line, which will select the voltage (e.g., Figure 8 The selection voltage (824) is applied to the DSG line of the storage string, and the selection voltage (e.g., Figure 8A selection voltage (826) is applied to the SSG line of the memory block. In some implementations, only one memory string in the group is verified after programming. In some implementations, more than one memory string in the group is verified after programming. By verifying one or more selected memory strings, the storage device can determine whether the memory block has been successfully programmed by determining the number of faulty memory cells in one or more selected memory strings.

[0088] Figure 10 A memory block diagram of an example system 1000 having storage devices according to some aspects of this disclosure is shown. System 1000 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. System 1000 may include a host 1008 and a storage system 1002 having one or more storage devices 1004 and a memory controller 1006. Host 1008 may be a processor (e.g., central processing unit (CPU)) or system-on-a-chip (SoC) (e.g., application processor (AP)) of an electronic device. Host 1008 may be configured to send data to or receive data from storage device 1004.

[0089] Storage device 1004 can be any storage device disclosed herein. According to some embodiments, memory controller 1006 is coupled to storage device 1004 and host 1008 and is configured to control storage device 1004. Memory controller 1006 can manage data stored in storage device 1004 and communicate with host 1008. In some embodiments, memory controller 1006 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for electronic devices, such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 1006 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMC) used for data storage in mobile devices (e.g., smartphones, tablets, laptops, etc.) and enterprise storage arrays. Memory controller 1006 can be configured to control the operation of storage device 1004, such as read, erase, and program operations. The memory controller 1006 can also be configured to manage various functions related to data stored or to be stored in the storage device 1004, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some implementations, the memory controller 1006 is also configured to handle error correction codes (ECC) for data read from or written to the storage device 1004. Any other suitable functions can also be performed by the memory controller 1006, such as formatting the storage device 1004.

[0090] The memory controller 1006 can communicate with external devices (e.g., host 1008) according to a specific communication protocol. For example, the memory controller 1006 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0091] The memory controller 1006 and one or more storage devices 1004 can be integrated into various types of storage devices. For example, the memory controller 1006 and one or more storage devices 1004 can be packaged in a universal flash memory (UFS) package or an eMMC package. Figure 11AIn one example shown, the memory controller 1006 and a single storage device 1004 can be integrated into a memory card 1102. The memory card 1102 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 1102 may also include a connection between the memory card 1102 and a host computer (e.g., Figure 10 The memory card connector 1104 is coupled to the host 1008. Figure 11B In another example shown, the memory controller 1006 and multiple storage devices 1004 can be integrated into the SSD 1106. The SSD 1106 may also include a connection between the SSD 1106 and a host (e.g., Figure 10 The SSD connector 1108 is coupled to the host 1008. In some embodiments, the storage capacity and / or operating speed of the SSD 1106 are greater than those of the memory card 1102.

[0092] While this specification contains numerous specific details of implementation, these details should not be construed as limiting the scope of possible claims, but rather as descriptions of features that may be specific to particular implementations. Some features described in this specification in individual implementations may also be implemented in combinations of individual implementations. Conversely, various features described in the context of individual implementations may also be implemented individually or in any sub-combination in multiple implementations. Furthermore, although previously described features may be described as operating in certain combinations, or even initially claimed as such, one or more features from a claimed combination may be removed from the combination in certain circumstances, and the claimed combination may involve sub-combinations or variations of sub-combinations.

[0093] As used in this disclosure, the terms “a,” “an,” or “the” are used to include one or more, unless the context clearly specifies otherwise. The term “or” is used to refer to a non-exclusive “or,” unless otherwise stated. “At least one of A and B” has the same meaning as “A, B, or A and B.” Furthermore, the wording or terms used in this disclosure, unless otherwise defined, are for descriptive purposes only and not for limitation. Any use of section headings is intended to aid in reading the document and should not be construed as restrictive; information relating to a section heading may appear within or outside that particular section.

[0094] As used in this disclosure, the terms “about” or “approximately” may allow for a degree of variability in a value or range, for example, within 10%, 5%, or 1% of a specified value or range.

[0095] As used in this disclosure, the term “substantially” means the majority or most, at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0096] Values ​​expressed in range format should be interpreted flexibly to include not only the numerical value explicitly referenced as a range limit, but also all individual numerical values ​​or subranges covered within that range, as if each numerical value and subrange were explicitly referenced. For example, a range of “0.1% to about 5%” or “0.1% to 5%” should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the specified range. Unless otherwise stated, “X to Y” has the same meaning as “about X to about Y”. Similarly, unless otherwise stated, the statement “X, Y, or Z” has the same meaning as “about X, about Y, or about Z”.

[0097] Specific embodiments of the subject matter have been described. Other embodiments, variations, and arrangements of the described embodiments are within the scope of the appended claims and will be apparent to those skilled in the art. Although operations are described in a specific order in the drawings or claims, these operations need not be performed in the specific order or sequence shown, or all illustrated operations need not be performed (some operations may be considered optional) to achieve the desired result. In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and considered appropriate.

[0098] Moreover, the separation or integration of the various system modules and components in the above embodiments is not required in all embodiments. The described components and systems can generally be integrated together or packaged into multiple products.

[0099] Therefore, the exemplary embodiments described above do not define or limit the scope of this disclosure. Other changes, substitutions, and modifications are possible without departing from the spirit and scope of this disclosure.

Claims

1. A method for operating a storage device, comprising: programming a storage block of the storage device by programming each of a set of storage strings included in the storage block; and verifying the storage block by verifying fewer than all of the set of storage strings in the storage block.

2. The method of claim 1, further comprising: determining a number of faulty storage cells in the fewer than all of the set of storage strings in the storage block; and determining whether the programming of the storage block was successful based on the number of faulty storage cells. The programming of the storage block comprises programming the set of storage strings using a set of programming pulses, wherein the verifying of the storage block comprises verifying the fewer than all of the set of storage strings using one or more verify pulses, and 3. The method of claim 1 or 2, wherein, wherein an amount of the one or more verify pulses is less than an amount of the set of programming pulses. The programming of the storage block comprises programming the set of storage strings by applying a set of programming pulses to a word line coupled to storage cells of the set of storage strings, and wherein the verifying of the storage block comprises verifying only one of all of the set of storage strings by applying one verify pulse to the word line.

4. The method of any one of claims 1 to 3, wherein, The verifying of the fewer than all of the set of storage strings in the storage block comprises: identifying one or more selected storage strings of the set of storage strings; and 5. The method of claim 3, wherein, verifying the one or more selected storage strings by applying the one or more verify pulses.

6. The method of claim 5, further comprising: reading configuration data from a register of the storage device, wherein the configuration data indicates the one or more selected storage strings. A first storage string of the fewer than all of the set of storage strings is programmed using a first programming pulse of the set of programming pulses, wherein the first storage string is verified using a first verify pulse of the one or more verify pulses, and 7. The method of claim 3, 5 or 6, wherein, wherein the first verify pulse immediately follows the first programming pulse. The storage block comprises single level cells. The programming each of the set of storage strings included in the storage block comprises:

8. The method of any one of claims 1 to 7, wherein, applying a first programming pulse to a word line to program a first storage cell of a first storage string, wherein the word line is coupled to the first storage cell in the first storage string and a second storage cell in a second storage string, wherein the first storage string and the second storage string are included in the storage block; and 9. The method of any one of claims 1 to 8, wherein, applying a second programming pulse to the word line to program the second storage cell of the second storage string, and wherein the verifying of the fewer than all of the set of storage strings in the storage block comprises: ​ ​ applying a verify pulse to the word line to verify one of the first storage string or the second storage string, wherein the second program pulse and the first program pulse are applied consecutively and the verify pulse is applied after the second program pulse.

10. The method of claim 9, wherein, programming each of the set of storage strings includes: when applying the first program pulse: applying a first voltage to a first select line coupled to a first select gate transistor of the first storage string; and applying a ground voltage to a second select line coupled to a second select gate transistor of the second storage string.

11. The method of claim 10, wherein, programming each of the set of storage strings includes: when applying the second program pulse: applying the ground voltage to the first select line; and applying the first voltage to the second select line.

12. The method of claim 10 or 11, wherein, verifying fewer than all of the set of storage strings in the storage block includes: when applying the verify pulse: applying a second voltage to one of the first select line or the second select line; and applying the ground voltage to the other of the first select line or the second select line.

13. The method of claim 12, wherein, the second voltage is higher than the first voltage.

14. A storage device, comprising: a storage array including a storage block, wherein the storage block includes a set of storage strings; and peripheral circuitry coupled to the storage array and configured to perform operations including: programming the storage block by programming each of the set of storage strings; and verifying the storage block by verifying fewer than all of the set of storage strings.

15. The storage device of claim 14, wherein, the operations further include: determining a number of faulty storage cells in the fewer than all of the set of storage strings in the storage block; and determining whether the programming of the storage block was successful based on the number of faulty storage cells.

16. The storage device of claim 14 or 15, wherein, programming the storage block includes programming the set of storage strings using a set of program pulses, wherein verifying the storage block includes verifying fewer than all of the set of storage strings using one or more verify pulses, and wherein a quantity of the one or more verify pulses is less than a quantity of the set of program pulses.

17. The storage device of any one of claims 14-16, wherein, programming the storage block includes programming the set of storage strings by applying a set of program pulses to a word line coupled to storage cells of the set of storage strings, and wherein verifying the storage block includes verifying only one of all of the set of storage strings by applying a verify pulse to the word line.

18. The storage device of claim 16, wherein, verifying fewer than all of the set of storage strings in the storage block includes: identifying one or more selected storage strings of the set of storage strings; and verifying the one or more selected storage strings by applying the one or more verify pulses.

19. The storage device of claim 18, wherein, the operations include: reading configuration data from a register of the storage device, wherein the configuration data indicates the one or more selected storage strings.

20. A storage system comprising: a storage device comprising a storage array and a peripheral circuit coupled to the storage array, wherein the peripheral circuit is configured to perform operations comprising: programming a storage block of the storage array by programming each of a group of storage strings included in the storage block; and verifying the storage block by verifying fewer than all of the group of storage strings in the storage block; and a memory controller coupled to the storage device and configured to control the storage device.

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