Gate drive control device and power conversion device

Abstract

A gate drive control device that drives a gate of a first semiconductor element is provided with: a Miller clamp circuit that maintains a gate voltage at a low level when the gate voltage of the first semiconductor element is less than a predetermined control threshold value; and a gate monitoring circuit that detects that the gate voltage of the first semiconductor element is lower than a predetermined detection threshold value of a positive potential. In the gate drive control device, when a first semiconductor element is turned off, a gate monitoring circuit detects that the gate voltage of the first semiconductor element is lower than a detection threshold value while or after the start of operation of a Miller clamp circuit.

Description

Technical Field

[0001] The present invention relates to a gate drive control device for driving the gate of a semiconductor element and a power conversion device using the gate drive control device. Background Technology

[0002] The power conversion device has functions such as AC-DC conversion, DC-AC conversion, AC power frequency conversion, and DC power voltage conversion. To achieve these conversion functions, the power conversion device includes a power conversion circuit. This circuit converts power by switching a power semiconductor module with switching capabilities on and off. The power semiconductor module is in a conducting state by controlling the gate voltage between its gate terminal and the source terminal (or emitter terminal) to a High (positive voltage) state via a gate drive circuit, and in a de-energized state by controlling it to a Low (0V or negative voltage) state. Furthermore, the gate drive circuit is controlled by a higher-level controller.

[0003] Among power semiconductor modules, there are 1-in-1 modules that carry one or more parallel-connected semiconductor switching elements (hereinafter referred to as "switching elements"), and 2-in-1 modules that connect two switching elements in series inside the module and form a half-bridge circuit with one module.

[0004] Patent Document 1 describes a power semiconductor driving circuit. Patent Document 1 describes a power semiconductor driving circuit comprising: "a parallel circuit connected to the gate side of a power semiconductor element, consisting of at least two transistors for setting the gate resistance of the power semiconductor element; a gate voltage monitoring circuit connected to the gate side of the power semiconductor element and the parallel circuit, setting a predetermined monitoring voltage for monitoring the gate voltage of the power semiconductor element"; and "a signal delay circuit that delays the output signal from the gate voltage monitoring circuit; and a gate control circuit that switches the combined resistance of the parallel circuit based on the output signal output from the signal delay circuit side."

[0005] To date, silicon (Si) devices have been used as switching elements. In recent years, to improve the performance of power conversion circuits, silicon carbide (SiC) devices, which offer excellent low on-resistance, high-speed switching, and high-temperature operation, have become widely used. Hereinafter, semiconductor devices using SiC will be referred to as "SiC devices".

[0006] To support high-speed SiC driving and shorten the dead time, an active dead-time configuration with dead-time control by a gate driver IC (GDIC) is proposed. In the active dead-time configuration, by inputting the gate monitoring signal of the GDIC to the GDIC of the opposite arm, it is determined that the SiC element of the opposite arm is turned off, and the SiC element of this arm can be turned on.

[0007] Existing technical documents

[0008] Patent documents

[0009] Patent Document 1: Japanese Patent Application Publication No. 2019-080359 Summary of the Invention

[0010] The problem that the invention aims to solve

[0011] However, in an active dead-time configuration, each arm is connected to a Miller clamp circuit that controls the gate with low impedance and a gate voltage monitoring circuit that monitors the gate voltage of the semiconductor element. The Miller clamp circuit maintains the gate voltage at a low level when the gate voltage of the semiconductor element is less than a predetermined control threshold. The gate voltage monitoring circuit determines that the gate is off when the gate voltage of the semiconductor element is lower than the turn-off detection threshold and that the gate is on when the gate voltage of the semiconductor element is higher than the turn-on detection threshold. The turn-off detection threshold of existing GDICs is set higher than the operating threshold of the Miller clamp circuit. Under this setting, sometimes even if the SiC element in this arm is in a semi-conducting state, the gate monitoring signal will detect that it is off. Furthermore, in the semi-conducting state, when the switching noise of other phase arms overlaps with the gate voltage, the SiC element in this arm may sometimes turn on again. Therefore, in an active dead-time configuration, a short circuit may occur between the upper and lower arms.

[0012] The present invention was made in view of the above situation, and its object is to drive the semiconductor element constituting the arm at high speed in a gate drive control device equipped with a Miller clamp circuit and a gate voltage monitoring circuit, and to prevent short circuits between the upper and lower arms.

[0013] Methods for solving problems

[0014] To address the aforementioned problems, one aspect of the gate drive control device of the present invention is a gate drive control device for driving the gate of a first semiconductor element, characterized by comprising: a Miller clamp circuit that maintains the gate voltage of the first semiconductor element at a low level when the gate voltage is less than a predetermined control threshold; and a gate monitoring circuit that detects when the gate voltage of the first semiconductor element is lower than a predetermined detection threshold of a positive potential. Furthermore, in the gate drive control device, when the first semiconductor element is turned off, the gate monitoring circuit is configured to detect when the gate voltage of the first semiconductor element is lower than the detection threshold, either simultaneously with or after the start of operation of the Miller clamp circuit.

[0015] The effects of the invention

[0016] According to at least one aspect of the present invention, after the Miller clamping circuit determines that the gate of the semiconductor element on its side arm is turned off by operation, the gate monitoring circuit detects that the gate is turned off. This operation allows for a more accurate gate turn-off detection result. If the dead time is generated in the control computer using the gate turn-off detection result, the semiconductor element of the side arm can be driven at high speed, and short circuits between the upper and lower arms can be prevented.

[0017] Other issues, structures, and effects not mentioned above will be clarified through the following description of the implementation methods. Attached Figure Description

[0018] Figure 1 This is a block diagram illustrating an example of the configuration of an inverter device equipped with the gate drive control device of the first embodiment of the present invention.

[0019] Figure 2 This is a diagram illustrating an example of the configuration of the gate monitoring unit in the first embodiment of the present invention.

[0020] Figure 3 This is an example of a timing diagram that schematically illustrates the gate detection operation of the gate monitoring unit in the first embodiment of the present invention.

[0021] Figure 4 This diagram illustrates an example of the minimum configuration of the gate monitoring unit in the first embodiment of the present invention.

[0022] Figure 5 This is a diagram illustrating an example of the configuration of an inverter device according to the second embodiment of the present invention.

[0023] Figure 6 This is an example of a timing diagram schematically illustrating the gate drive operation of an inverter device according to the second embodiment of the present invention.

[0024] Figure 7 This is a diagram illustrating one example of the configuration of an inverter device according to the third embodiment of the present invention.

[0025] Figure 8 This is a diagram illustrating an example (second example) of the configuration of an inverter device according to the third embodiment of the present invention.

[0026] Figure 9 This is an example of a timing diagram schematically illustrating the gate driving operation in the third embodiment of the present invention.

[0027] Figure 10 This is a diagram illustrating an example of the configuration of the gate monitoring unit in the fourth embodiment of the present invention.

[0028] Figure 11This is a schematic diagram illustrating an example of a timing diagram of the threshold change operation according to the fourth embodiment of the present invention.

[0029] Figure 12 This is a diagram showing a modified example (separate configuration) of the gate monitoring section according to an embodiment of the present invention.

[0030] Figure 13 This is a diagram showing a modified example of the configuration of the gate monitoring unit according to an embodiment of the present invention (a partial threshold sharing configuration). Detailed Implementation

[0031] Hereinafter, examples of methods for carrying out the present invention (hereinafter referred to as "implementation methods") will be described with reference to the accompanying drawings.

[0032] In this specification and accompanying drawings, the same or similar constituent elements are sometimes given the same symbols, and repeated descriptions are omitted, or only descriptions focusing on the differences are provided. Furthermore, when multiple identical or similar constituent elements exist, different subscripts are sometimes added to the same symbols for description. Additionally, when it is not necessary to distinguish these multiple constituent elements, the subscripts are sometimes omitted for description. Unless otherwise specified, the number of constituent elements can be singular or plural.

[0033] Before describing the present invention, the reason why the turn-off detection threshold of the conventional GDIC is set higher than the operation threshold of the Miller clamp circuit will be explained here. Conventional gate monitoring results are used only for monitoring functions in diagnostic applications. In order to reduce the error between the detection timing of the actual power device's turn-on / turn-off and the actual turn-on / turn-off operation timing, the conventional turn-off detection threshold is set to a value close to the gate threshold of the actual power device.

[0034] However, in the active dead-time configuration of the present invention described later, the gate monitoring result needs to be used not only for monitoring but also as the gate input signal for the opposite arm. Therefore, if the power device is mistakenly turned on again after being turned off once due to noise or other reasons generated during gate turn-off, a short circuit occurs between the upper and lower arms, resulting in the opposite arm being turned on and the current arm being mistakenly turned on, due to the first gate turn-off result. To avoid this situation, in the present invention, gate turn-off is only determined after Miller clamping action (gate is completely turned off).

[0035] Furthermore, it was previously envisioned to use IGBTs (Insulated Gate Bipolar Transistors) for driving. In SiC, which can be driven at high speeds, the gate voltage transition time (delay time) is shorter than that of IGBTs, and the impact caused by deviations between the actual gate threshold and the turn-off detection threshold is smaller.

[0036] In inverters, large noise is generated when the gates of the self-phase / other phase arms are turned on / off due to the intermittent flow of large currents through the power devices (semiconductor elements). In fact, due to common-mode noise generated during gate drive of other phase arms, the gate of the self-phase arm may sometimes be mistakenly turned on again after a single turn-off. If this mistaken turn-on occurs in an inverter with an active dead time, the power device on the opposite arm will be turned on after the initial gate turn-off, leading to a mistaken turn-on of the power device on this side arm, resulting in a short circuit between the upper and lower arms.

[0037] When the gate drive control device can more reliably detect gate turn-off, short circuits in the upper and lower arm circuits as described above can be avoided in inverters with active dead time. This improves the reliability of the inverter and further enhances vehicle safety.

[0038] <First Implementation>

[0039] First, the gate drive control device and power conversion device of the first embodiment of the present invention will be described.

[0040] [Composition of an inverter device]

[0041] Figure 1 This is a block diagram illustrating an example of the configuration of an inverter device equipped with the gate drive control device of the first embodiment of the present invention.

[0042] Figure 1 The inverter device 100 shown (an example of a power conversion device) includes a first semiconductor element 31 that functions as an upper arm and a second semiconductor element 32 that functions as a lower arm. Figure 1 In this embodiment, the first semiconductor element 31 and the second semiconductor element 32 are n-channel MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) constructed using SiC. However, the first semiconductor element 31 and the second semiconductor element 32 are not limited to this example. For example, they are suitable for transistors with excellent high-speed switching performance, such as transistors constructed of SiC.

[0043] Inverter device 100 controls the switching operations of first semiconductor element 31 and second semiconductor element 32 according to instructions from MCU (Micro-Control Unit) 1, thereby supplying power to the load. For example, the load is a motor. MCU1 is a microcontroller and an example of a control computer. In MCU1, arithmetic processing units (e.g., CPU), memory devices (RAM or ROM), input / output circuits (I / O), timer circuits, etc., are mounted in an integrated circuit.

[0044] The inverter device 100 includes a gate drive control device 10 for controlling the switching operation of a first semiconductor element 31 and a gate drive control device 20 for controlling the switching operation of a second semiconductor element 32. The gate drive control device 10 controls the gate voltage supplied to the first semiconductor element 31, and the gate drive control device 20 controls the gate voltage supplied to the second semiconductor element 32.

[0045] The MCU1 and the gate drive control device 10 are electrically isolated from each other via the signal transmission unit 2_1. The input and output sides of the signal transmission unit 2_1 are magnetically coupled, maintaining electrical isolation between them while transmitting signals. Signal exchange between the MCU1 and the gate drive control device 10 is performed via the signal transmission unit 2_1. For example, the signal transmission unit 2_1 can be a signal transmission unit utilizing magnetic coupling via a transformer or an optical signal transmission unit utilizing an optocoupler.

[0046] The gate drive control device 10 will be described below, but the gate drive control device 20 will be described in the same way.

[0047] The gate drive control device 10 includes a gate state determination circuit 14, a Miller clamp circuit 15, and a reference voltage generation circuit 13. The gate state determination circuit 14 detects the gate turn-off of the first semiconductor element 31 at the same time as or after the Miller clamp circuit 15 begins operation. The configuration and operation of such a gate drive control device 10 will be described.

[0048] The gate drive control device 10 consists of a gate drive unit 11 and a gate monitoring unit 12.

[0049] The gate driving unit 11 controls the gate G1 of the first semiconductor element 31 according to the driving command cmd1 input from the MCU1 via the signal transmission unit 2_1.

[0050] The gate monitoring unit 12 determines the gate state based on the gate G1 voltage and outputs the gate state determination result in the gate monitoring signal Mon_g1. Furthermore, based on the gate state determination result, the gate monitoring unit 12 controls the gate G1 with low impedance.

[0051] (Gate driving section)

[0052] The gate drive unit 11 includes transistors Mp1 and Mn1, and a NOT circuit INV1_1. Transistor Mp1 is a p-channel MOSFET, and transistor Mn1 is an n-channel MOSFET. The NOT circuit INV1_1 inverts the logic level of the drive command cmd1 and outputs it. The output signal of the NOT circuit INV1_1 is input as a switch control signal cnt1 to the gates of transistors Mp1 and Mn1.

[0053] If the drive instruction cmd1 becomes logic high (hereinafter referred to as "High"), then through the NOT circuit INV1_1, the switch control signal cnt1 becomes logic low (hereinafter referred to as "Low"). As a result, transistor Mp1 is turned on, and transistor Mn1 is turned off. With gate G1 at High, the first semiconductor element 31 is turned on.

[0054] On the other hand, when the drive command cmd1 becomes Low, the switch control signal cnt1 becomes High through the NOT circuit INV1_1. As a result, transistor Mp1 is turned off, and transistor Mn1 is turned on. With gate G1 at Low, the first semiconductor element 31 is turned off.

[0055] The resistor Ron1 set between the drain and gate G1 of transistor Mp1 and the resistor Roff1 set between the drain and gate G1 of transistor Mn1 are set to adjust the charging and discharging speed of the gate G1 voltage.

[0056] (Gate monitoring unit)

[0057] The gate monitoring unit 12 includes a gate state determination circuit 14, a Miller clamping circuit 15, and a reference voltage generation circuit 13.

[0058] The gate state determination circuit 14 (an example of a gate monitoring circuit) determines the on / off state of the first semiconductor element 31 by comparing the gate G1 voltage with a gate state determination threshold (hereinafter referred to as "Vth_mon"), and outputs a gate monitoring signal Mon_g1. The gate state determination threshold is equivalent to the on-state determination threshold described above. Furthermore, since this embodiment relates to the timing of detecting the off-state of the semiconductor element, the gate state determination threshold can also be called the off-state determination threshold.

[0059] The Miller clamp circuit 15 controls the gate G1 with low impedance when the gate voltage G1 is less than the Miller clamp action threshold (hereinafter referred to as "Vth_mc"). That is, the Miller clamp circuit 15 is a circuit that keeps the gate voltage of the semiconductor element at a low level when the gate voltage is less than a predetermined control threshold.

[0060] The reference voltage generation circuit 13 generates the reference voltage that determines Vth_mon and Vth_mc.

[0061] The gate monitoring signal Mon_g1, which includes the gate state determination result, is input to MCU1 via signal transmission unit 2_1. Furthermore, MCU1 outputs a turn-on command to the gate drive control device 20 located on the opposite arm via signal transmission unit 2_2, based on the gate state determination result of the first semiconductor element 31 being turned off. The gate state determination result of the first semiconductor element 31 input to MCU1 is used for adjusting the drive timing of the second semiconductor element 32, etc.

[0062] The gate drive control device 20, like the gate drive control device 10, includes a gate drive unit 21 and a gate monitoring unit 22. The operation of the gate drive control device 20 is the same as that of the gate drive control device 10, therefore, its description is omitted.

[0063] Furthermore, the gate driving unit 11 of this embodiment shows a configuration in which the output terminals of transistor Mp1 and transistor Mn1 are separated into two, but the outputs of transistors Mp1 and Mn1 can also be configured as a single terminal. Additionally, the gate driving unit 11 can be configured not only as a p-channel MOS-n-channel MOS, but also as a p-channel MOS-p-channel MOS or an n-channel MOS-n-channel MOS. Furthermore, when no negative voltage is generated, the source potential (VSS1_1) of transistor Mn1 is connected to the same potential as the source potential. When a negative voltage is generated, the source potential (VSS1_1) of transistor Mn1 is connected to the same potential as the source potential, or to a potential lower than the source potential (e.g., a negative power supply voltage).

[0064] [Structure of the gate monitoring section]

[0065] Reference Figure 2 The gate monitoring unit 12 of this embodiment will be described in more detail.

[0066] Figure 2 This is a diagram showing an example of the configuration of the gate monitoring section 12.

[0067] (Reference voltage determination circuit)

[0068] The reference voltage generation circuit 13 generates the voltages Vth_mon (gate state determination threshold) and Vth_mc (Miller clamp action threshold). In this embodiment, it is assumed that Vth_mon and Vth_mc are the same value. Figure 2 The diagram shows a configuration that allows Vth_mon and Vth_mc to share a common reference voltage. Furthermore, when Vth_mon and Vth_mc have different values, etc., as described later. Figure 12 and Figure 13 As shown, it can also be configured to generate a reference voltage independently.

[0069] (Gate state determination circuit)

[0070] The gate state determination circuit 14 includes a comparator CMP1_1 that takes the voltage Vth_mon and the voltage of the gate G1 as two inputs, and a NOT circuit INV1_2 that inverts the logic output of CMP1_1. For example, the comparator CMP1_1 inputs the voltage Vth_mon to its non-inverting input terminal, inputs the voltage of the gate G1 to its inverting input terminal, and outputs a gate state determination result to the NOT circuit INV1_2. If the voltage of the gate G1 is less than Vth_mon, the comparator CMP1_1 outputs a turn-off determination (in this embodiment, Low) indicating that the gate is in the off state to the gate monitoring signal Mon_g1 via INV1_2. Conversely, if the voltage of the gate G1 is greater than or equal to Vth_mon, the comparator CMP1_1 outputs a turn-on determination (in this embodiment, High) indicating that the gate is in the on state to the gate monitoring signal Mon_g1 via INV1_2.

[0071] Alternatively, the gate G1 can be connected to the non-inverting input terminal of CMP1_1, and Vth_mon can be connected to the inverting input terminal. In this case, the NOT circuit INV1_2 is not needed.

[0072] (Miller clamping circuit)

[0073] The Miller clamping circuit 15 includes a comparator CMP2_1 and a Miller clamping transistor Q1.

[0074] Comparator CMP2_1 is a comparator that takes the voltage Vth_mc and the voltage of gate G1 as two inputs. For example, the voltage Vth_mc is input to the non-inverting input terminal, and the voltage of gate G1 is input to the inverting input terminal. If the voltage of gate G1 is less than Vth_mc, comparator CMP2_1 outputs a low-impedance control command (High in this embodiment) to the Miller clamp control signal cnt1_mc. If the voltage of gate G1 is greater than Vth_mc, comparator CMP2_1 outputs a high-impedance control command (Low in this embodiment) to the Miller clamp control signal cnt1_mc.

[0075] In addition, the reference potentials (VSS3_1) of Vth_mon and Vth_mc are connected to the same potential as the source potential.

[0076] In addition, the source potential (VSS2_1) of the Miller clamp transistor Q1 is connected to a potential that is the same as the source potential or a potential that is smaller than the source potential (e.g., a negative power supply voltage).

[0077] The Miller clamping transistor Q1 controls the gate G1 of the first semiconductor element 31 with low impedance according to the output of comparator CMP2_1, i.e., the Miller clamping control signal cnt1_mc. The Miller clamping transistor Q1 is turned on when the Miller clamping control signal cnt1_mc is a low-impedance control command (High). Through the conduction between the drain and source of the Miller clamping transistor Q1, a low impedance is formed between the gate G1 and the source (VSS2_1). Therefore, the voltage of the gate G1 remains low. As an example of the Miller clamping transistor Q1, an n-channel MOSFET can be used, but it is not limited to this.

[0078] [Gate probe operation]

[0079] Next, refer to Figure 3 This describes the gate detection operation of the gate drive control device 10, which includes a gate monitoring unit 12.

[0080] Figure 3 This is an example of a timing diagram schematically showing the gate detection operation of the gate monitoring unit 12.

[0081] At time t1: While a shutdown command is input to drive command cmd1, a shutdown command (Low) is input to drive command cmd2. Transistor Mp2 (not shown) in the gate drive control device 20 is turned off, and transistor Mn2 (not shown) is turned on, causing the gate G2 potential of the second semiconductor element 32 to begin to decrease. Transistors Mp2 and Mn2 correspond to transistors Mp1 and Mn1 in the gate drive control device 10, respectively.

[0082] At time t2: the gate voltage G2 reaches the Miller voltage of the second semiconductor element 32, and the gate potential G2 becomes constant.

[0083] At time t3: After the drain voltage D2 of the second semiconductor element 32 rises, the gate potential G2 begins to decrease.

[0084] At time t4: the gate G2 potential is less than Vth_mc, and the Miller clamp circuit 15 starts operating, controlling the relationship between gate G2 and VSS2_2 with low impedance, thereby causing the gate G2 potential to drop to the VSS2_2 potential. Simultaneously, by making the gate G2 potential less than Vth_mon, a turn-off determination (Low) result is output to the gate monitoring signal Mon_g2. During the period from the moment t1 when the gate G2 potential begins to drop to the moment t4 when the gate G2 potential drops to VSS2_2, the second semiconductor element 32 is in a semi-conducting state.

[0085] At time t5: When the gate monitoring signal Mon_g2 changes to Low, MCU1 outputs a turn-on command (High) to the drive instruction cmd1. The period from the moment t4 when the gate monitoring signal Mon_g2 changes to Low to the time Tdelay after which the gate G1 begins to rise is called the dead time. When the turn-on command (High) is input to the drive instruction cmd1, after the delay time (Tdelay), transistor Mp1 in the gate drive control device 10 turns on, and transistor Mn1 turns off. As a result, the potential of the gate G1 of the first semiconductor element 31 begins to rise.

[0086] At time t6: When the potential of the gate G1 of the second semiconductor element 32 is above Vth_mon, a turn-on determination (High) is output to the gate monitoring signal Mon_g1. At the same time, the Miller clamp transistor Q1 stops operating.

[0087] At time t7: the potential of the gate G1 of the first semiconductor element 31 rises to VCC1 ( Figure 1 The first semiconductor element 31 becomes conductive.

[0088] In the gate monitoring unit 12 of the above embodiment, the detection threshold (Vth_mon) of the gate state determination circuit 14 is set to the same value as the control threshold (Vth_mc) of the Miller clamp circuit 15.

[0089] Based on this configuration, in this embodiment, by detecting gate turn-off at the same time as or after the start of operation of the Miller clamp circuit, the accuracy of gate turn-off detection can be improved compared to the past.

[0090] Additionally, if as Figure 2 As shown, since there is a common reference voltage, the circuit area can be reduced compared to the past, and the cost and size can be reduced.

[0091] Alternatively, the Miller clamp circuit can be configured to stop operating simultaneously with the input of a turn-on command to the gate drive section of the arm on this side.

[0092] [Minimum Configuration of Gate Monitoring Unit]

[0093] Here, refer to Figure 4 This describes an example of the minimum configuration of the gate monitoring unit in this embodiment.

[0094] Figure 4 This diagram shows an example of the minimum configuration of the gate monitoring section.

[0095] exist Figure 4 In the gate monitoring unit 12A shown, through a shared Figure 2The comparators CMP1_1 and CMP2_1 shown can reduce the number of comparators by one. Furthermore, regarding the gate monitoring unit 12A below, in conjunction with... Figure 2 The different configurations of the gate monitoring unit 12 shown will be explained in detail.

[0096] If we focus on the above Figure 2 In the different configuration shown, the gate monitoring unit 12A replaces comparators CMP1_1 and CMP2_1 with comparator CMP3_1. Furthermore, the gate monitoring unit 12A includes a buffer circuit BUF1 on the output line of comparator CMP3_1. A NOT circuit INV3_1 is connected between the input side of the buffer circuit BUF1 and the output side of comparator CMP3_1.

[0097] Comparator CMP3_1 compares the voltage at gate G1 and the voltage at Vth_mon (=Vth_mc) as inputs, and outputs the comparison result to the Miller clamp control signal cnt1A_mc. Comparator CMP3_1 operates identically to comparator CMP2_1, therefore a detailed operational description is omitted. Additionally, since the NOT circuit INV3_1 operates identically to the NOT circuit INV1_2, a detailed operational description is also omitted.

[0098] The buffer circuit BUF1 adjusts the logic level output by the NOT circuit INV3_1 to the desired logic level (the voltage level of the logic can be determined by the signal transmission unit 2_1) and outputs it as the gate monitoring signal Mon_g1.

[0099] Here, it is assumed that the logic determination threshold (Vdet_st1) used to determine the logic level of the signal transmission unit 2_1 and the high output voltage (Vinv_h) of the NOT circuit INV3_1 are related by the following equation (1). Furthermore, the high output voltage (Vbuf1_h) of the buffer circuit BUF1 is set to satisfy the following equation (1).

[0100] Vinv_h<Vdet_st1<Vbuf1_h・・・(1)

[0101] When the high voltage (Vinv_h) of the NOT circuit INV3_1 is lower than the logic determination threshold (Vdet_buf1) used to determine the logic level of the buffer circuit BUF1, the buffer circuit BUF1 outputs Low to the monitoring signal Mon_g1. The low-level gate monitoring signal Mon_g1 transmits information (at the Low level) to MCU1 via the signal transmission unit 2_1.

[0102] On the other hand, when the potential of the High voltage (Vinv_h) of the NOT circuit INV3_1 is above Vdet_buf1, High (Vbuf1_h) is output to the gate monitoring signal Mon_g1. Therefore, the signal transmission unit 2_1 identifies the signal transmitted from the gate monitoring unit 12A as High and transmits the signal to the MCU1.

[0103] Furthermore, if Vdet_st1 and Vinv_h satisfy the following equation (2), the High output voltage (Vinv_h) of the NOT circuit INV3_1 is sufficiently large. In this case, it is also possible to configure the circuit without the buffer circuit BUF1.

[0104] Vdet_st1<Vinv_h・・・(2)

[0105] according to Figure 4 The gate monitoring unit 12A shown can be made smaller and thus reduce costs by using a shared terminal or a portion of the internal circuitry.

[0106] (Modification of the gate monitoring section (separate configuration))

[0107] Here, a modified example of the configuration of the gate monitoring unit in this embodiment will be further explained.

[0108] Figure 12 This illustrates a modified example (separate configuration) of the gate monitoring unit in this embodiment.

[0109] Figure 12 The gate monitoring unit 12C shown is configured to generate reference voltages for Vth_mon (gate state determination threshold) and Vth_mc (Miller clamping action threshold).

[0110] Comparator CMP1_1 takes the voltage of Vth_mon and the voltage of gate G1 as two inputs. The reference voltage generation circuit 1310 generates the voltage of Vth_mon and inputs it to the input terminal (e.g., the non-inverting input terminal) of comparator CMP1_1.

[0111] Comparator CMP2_1 takes the voltage of Vth_mc and the voltage of gate G1 as two inputs. The reference voltage generation circuit 1320 generates the voltage of Vth_mc and inputs it to the input terminal (e.g., the non-inverting input terminal) of comparator CMP2_1.

[0112] (A variation of the gate monitoring section (partially composed of shared thresholds))

[0113] Figure 13 This illustrates a modified example of the configuration of the gate monitoring unit in this embodiment (a portion of which shares a threshold value).

[0114] Figure 13 The gate monitoring unit 12D shown is configured to generate reference voltages for Vth_mon (gate state determination threshold) and Vth_mc (Miller clamp action threshold) respectively. However, some threshold voltages are shared.

[0115] A series circuit of reference voltage generation circuit 1410 and reference voltage generation circuit 1420 is connected between the reference potential (VSS3_1) and the input terminal (e.g., the non-inverting input terminal) of comparator CMP2_1. The connection point of reference voltage generation circuit 1410 and reference voltage generation circuit 1420 is connected to the input terminal (e.g., the non-inverting input terminal) of comparator CMP1_1.

[0116] Comparator CMP1_1 takes the voltage of Vth_mon and the voltage of gate G1 as two inputs. The reference voltage generation circuit 1410 generates the voltage of Vth_mon and inputs it to the input terminal (e.g., the non-inverting input terminal) of comparator CMP1_1.

[0117] The comparator CMP2_1 takes the voltage of Vth_mc and the voltage of the gate G1 as two inputs. The voltage of Vth_mc is obtained by adding the voltage generated by the reference voltage generation circuit 1420 to the voltage of Vth_mon generated by the reference voltage generation circuit 1410.

[0118] exist Figure 12 and Figure 13 In the gate monitoring unit shown, the gate state determination threshold (Vth_mon) of the gate state determination circuit 14 is set to the same value as the Miller clamping action threshold (Vth_mc) of the Miller clamping circuit 15, or a value smaller than the Miller clamping action threshold (Vth_mc).

[0119] As described above, the gate driving device (gate driving control device 10) of this embodiment is a gate driving control device for driving the gate of a first semiconductor element (first semiconductor element 31). This gate driving control device includes: a Miller clamp circuit (Miller clamp circuit 15) that maintains the gate voltage at a low level when the gate voltage of the first semiconductor element is less than a predetermined control threshold (Vth_mc); and a gate monitoring circuit (gate state determination circuit 14) that detects when the gate voltage of the first semiconductor element is lower than a predetermined detection threshold (Vth_mon) of a positive potential. Furthermore, in this gate driving control device, when the first semiconductor element is turned off, the gate monitoring circuit is configured to detect when the gate voltage of the first semiconductor element is lower than the detection threshold, either simultaneously with or after the start of operation of the Miller clamp circuit.

[0120] According to the above-described embodiment, after the Miller clamp circuit activates to determine that the gate of the semiconductor element in this side arm is turned off, the gate turn-off is detected by the gate monitoring circuit. This allows for a more accurate gate turn-off detection result, enabling the use of more precise gate information for gate drive control. If the dead time is generated by an MCU or similar device using the gate turn-off detection result, the semiconductor element in the side arm can be driven at high speed, and short circuits between the upper and lower arms can be prevented.

[0121] Additionally, by making the detection threshold (Vth_mon) a positive potential relative to GND ( Figure 3 This allows for earlier determination of the gate potential to be low and earlier detection of gate turn-off. Consequently, it also shortens the dead time of the active dead time control unit, which will be described later.

[0122] In addition, by setting each threshold to a positive potential, the generation circuit and the diagnostic circuit for negative potentials can be reduced, thereby achieving cost reduction.

[0123] <Second Implementation Method>

[0124] Below, refer to Figure 5 The configuration of the inverter device according to the second embodiment of the present invention will be described.

[0125] [Composition of an inverter device]

[0126] Figure 5 This is a diagram illustrating an example of the configuration of an inverter device according to the second embodiment of the present invention. Hereinafter, regarding... Figure 5 The inverter device 600 shown is for use with Figure 1 The following description focuses on the different configurations of the inverter device 100 of the first embodiment shown.

[0127] In addition to the configuration of the inverter device 100 in the first embodiment, the inverter device 600 also includes an active dead-time control unit 40. The active dead-time control unit 40 corresponds to the active dead-time configuration described in the background section. The active dead-time control unit 40 is provided between the signal transmission units 2_1 and 2_2 and the gate drive control devices 10 and 20. The active dead-time control unit 40 uses the gate state determination results in the gate monitoring units 12 and 22 within the gate drive control devices 10 and 20 to turn on the other semiconductor element after the first semiconductor element is turned off, thereby generating the dead time of the first semiconductor element 31 and the second semiconductor element 32.

[0128] The active dead time control unit 40 includes NOT circuit INV2, NOT circuit INV3, AND circuit 41, and AND circuit 42.

[0129] The NOT circuit INV2 outputs the inverted logic of the gate monitoring signal Mon_g2 to the AND circuit 41.

[0130] The NOT circuit INV3 outputs the inverted logic of the gate monitoring signal Mon_g1 to the AND circuit 42.

[0131] The AND circuit 41 takes the inverted logic of the drive instruction cmd1 and the gate monitoring signal Mon_g2 as two inputs, and outputs the logic product of the two inputs as the drive instruction cmd3 to the gate drive unit 11.

[0132] The AND circuit 42 takes the inverted logic of the drive instruction cmd2 and the gate monitoring signal Mon_g1 as two inputs, and outputs the logic product of the two inputs as the drive instruction cmd4 to the gate drive unit 21.

[0133] The operation of the AND circuit 41 will be explained. When the drive instruction cmd1 is a turn-on instruction (High) and the inverted logic of the gate monitoring signal Mon_g2 is a turn-off decision (High), the AND circuit 41 outputs a turn-on instruction (High) as the drive instruction cmd3. On the other hand, when at least one of the drive instruction cmd1 or the inverted logic of the gate monitoring signal Mon_g2 is Low, the AND circuit 41 outputs a turn-off instruction (Low) as the drive instruction cmd3.

[0134] In addition, the only difference between AND circuit 42 and AND circuit 41 is the signal line connected; the operation itself is the same, so the description of the operation is omitted.

[0135] [Gate probe operation]

[0136] Next, refer to Figure 6 This describes the gate drive operation of the inverter device 600 equipped with an active dead-time control unit 40.

[0137] Figure 6 This is an example of a timing diagram schematically illustrating the gate drive operation of an inverter device 600 equipped with an active dead-time control unit 40. The following will discuss... Figure 6 The timing diagram shown is in conjunction with Figure 3 The timing diagram of the first embodiment shown is explained focusing on different parts.

[0138] t1 time point: When a shutdown instruction is input to drive instruction cmd1, when a shutdown instruction (Low) is input to drive instruction cmd2, drive instruction cmd4 via AND circuit 42 also becomes a shutdown instruction (Low).

[0139] At time t5: The processing load in MCU1 increases, and dead time cannot be guaranteed in MCU1. At the half-conduction time of the second semiconductor element 32, a turn-on instruction (High) is input to the drive instruction cmd1. However, the gate monitoring signal Mon_g2 is in a turn-on determination (High). Through the operation of the AND circuit 41, the drive instruction cmd3 maintains the turn-off instruction (Low).

[0140] At time t4: the gate G2 potential is less than Vth_mc, and the Miller clamp circuit 15 starts operating, controlling the gate G2 and VSS2_2 with low impedance, thereby causing the gate G2 potential to drop to the VSS2_2 potential. Simultaneously, because the gate G2 potential is less than Vth_mon, a turn-off determination (Low) is output to the gate monitoring signal Mon_g2. Therefore, the drive command cmd1 of the AND circuit 41 becomes a turn-on command (High), and the NOT circuit INV2 inverts the gate monitoring signal Mon_g2, outputting a turn-on command (High) to the drive command cmd3. Furthermore, after a delay time (Tdelay), transistor Mp2 in the gate drive control device 20 turns on, and transistor Mn2 turns off. Thus, the potential of the gate G1 of the first semiconductor element 31 begins to rise, and the first semiconductor element 31 begins to transition to the on state.

[0141] During the period from the point when the gate G1 potential starts to rise after a delay time Tdelay from time t4 to the point when the gate G1 begins to rise to the end of time t7, the first semiconductor element 31 is in a semi-conducting state.

[0142] As described above, the gate driving device of this embodiment includes an active dead time control unit (active dead time control unit 40). After the active dead time control unit 40 detects that the gate voltage of the first semiconductor element (first semiconductor element 31) is lower than the detection threshold (Vth_mon) by the gate monitoring circuit (gate state determination circuit 14), it turns on the second semiconductor element (second semiconductor element 32) of the opposite arm connected in series with the first semiconductor element.

[0143] According to the above-described embodiment, the active dead-time control unit 40 uses the gate state determination results in the gate monitoring units 12 and 22 within the gate drive control devices 10 and 20 to turn on the other semiconductor element after one semiconductor element is turned off. Therefore, in this embodiment, short circuits between the upper and lower arms can be prevented, and the semiconductor elements constituting the arms can be driven at a higher speed than in the first embodiment.

[0144] Furthermore, according to this embodiment, even if the MCU1 (microcontroller) cannot ensure sufficient dead time, the gate drive control device (GDIC) can ensure dead time.

[0145] For example, according to the inverter device 600 of this embodiment described above, in the active dead time configuration, vehicle malfunctions caused by short circuits in the upper arm and lower arm can be avoided.

[0146] Furthermore, without adding any additional circuitry to the existing circuitry, it is possible to detect the gate-off state of semiconductor devices with higher accuracy.

[0147] <Third Implementation Method>

[0148] Below, refer to Figure 7 The configuration of the inverter device according to the third embodiment of the present invention will be described.

[0149] [Composition of an inverter device]

[0150] Figure 7 This is a diagram illustrating one example of the configuration of an inverter device according to the third embodiment of the present invention. Figure 8 This is a diagram illustrating an example (second example) of the configuration of an inverter device according to the third embodiment of the present invention. Figure 7 and Figure 8 The difference lies in the logic level of the signal flowing through the signal line. The following is about... Figure 7 and Figure 8 The inverter device 800 shown is for use with Figure 5 The description will focus on the different configurations of the inverter device 600 of the second embodiment shown.

[0151] In addition to the configuration of the inverter device 600 in the second embodiment, the inverter device 800 also includes a simultaneous conduction prevention circuit 50. The simultaneous conduction prevention circuit 50 is provided between the signal transmission units 2_1 and 2_2 and the active dead time control unit 40.

[0152] Simultaneous conduction prevention circuit 50 is a circuit designed to prevent simultaneous conduction of the upper and lower arms in response to simultaneous conduction commands from MCU1 in the gate drive control devices 10 and 20. When a conduction command (High) arrives at one of the drive commands, the simultaneous conduction prevention circuit 50 prevents the upper and lower arms from conducting simultaneously by blocking the conduction command arriving at the other drive command.

[0153] Meanwhile, the conduction prevention circuit 50 includes resistor R1, resistor R2, diode Di1, and diode Di2.

[0154] Resistor R1 transmits the drive command cmd1 as a simultaneous conduction prevention command c2_onp to the NOT circuit INV3.

[0155] Resistor R2 transmits the drive command cmd2 as a simultaneous conduction prevention command c1_onp to the NOT circuit INV2.

[0156] Diode Di1 transmits the gate monitoring signal Mon_g1 as a simultaneous conduction prevention instruction c2_onp to the NOT circuit INV3.

[0157] Diode Di2 transmits the gate monitoring signal Mon_g2 as a simultaneous conduction prevention instruction c1_onp to the NOT circuit INV2.

[0158] Here, resistor R1 and diode Di1 determine which logic level is used as the simultaneous conduction prevention instruction c2_onp output, depending on the different logic levels of the drive instruction cmd1 and the gate monitoring signal Mon_g1. For example, if the gate monitoring signal Mon_g1 is Low and the drive instruction cmd1 is High, then diode Di1 becomes a reverse voltage. Therefore, the logic level of the drive instruction cmd1 is used as the simultaneous conduction prevention instruction c2_onp output.

[0159] On the other hand, if the gate monitoring signal Mon_g1 is High and the drive instruction cmd1 is Low, then diode Di1 becomes forward-biased. Therefore, the logic of the gate monitoring signal Mon_g1 is to output the simultaneous conduction prevention instruction c2_onp.

[0160] Resistor R1 is set to prioritize the logic of the drive instruction cmd1 and the gate monitoring signal Mon_g1, where the latter is High. When the drive instruction cmd1 is High and the gate monitoring signal Mon_g1 is Low, diode Di1 is reverse biased and becomes OFF, simultaneously preventing the on instruction c2_onp from becoming High. Figure 7 Even if High (simultaneous conduction control) is input to the drive instruction cmd2, simultaneous conduction can still be prevented because the simultaneous conduction prevention instruction c2_onp is High (disable instruction).

[0161] On the other hand, such as Figure 8 As shown, when the drive command cmd1 is Low and the gate monitoring signal Mon_g1 is High, diode Di1 becomes ON due to forward bias, while simultaneously preventing the turn-on command c2_onp from being High. Here, even if High is input to the drive command cmd2, it is still related to... Figure 5 The operation of the inverter device 600 shown also prevents simultaneous conduction.

[0162] Resistor R1 is set to maintain its respective logic value even when the logic of the preventive instruction c2_onp and the drive instruction cmd1 are different, even if they are simultaneously turned on. For example, if the value of resistor R1 is too large, the logic may be reversed. Additionally, resistor R2 and diode Di2 differ only in the signal lines they are connected to; their operation is the same as that of resistor R1 and diode Di1, so a description of their operation is omitted.

[0163] Thus, in the inverter device 800 of this embodiment, the gate monitoring circuit (e.g., the gate state determination circuit 14) detects that the gate voltage of the first semiconductor element 31 and the gate voltage of the second semiconductor element 32 are lower than a predetermined detection threshold. Furthermore, the inverter device 800 includes: a gate driving unit (gate driving units 11, 12) that drives the gate of the first semiconductor element 31 and the gate of the second semiconductor element 32; and a simultaneous conduction prevention circuit (simultaneous conduction prevention circuit 50) that, when the gate monitoring circuit does not detect that the gate voltage of one semiconductor element is lower than the predetermined detection threshold, prohibits the gate driving unit from driving the gate of the other semiconductor element.

[0164] According to the above-described embodiment, an active dead time that prevents the upper and lower arms from conducting simultaneously can be achieved with fewer components.

[0165] [Gate drive operation]

[0166] Below, refer to Figure 9 This describes the gate drive operation of the inverter device 800, which has a simultaneous conduction prevention circuit 50.

[0167] Figure 9 This is an example of a timing diagram schematically illustrating the gate drive operation of an inverter device 800 equipped with a simultaneous conduction prevention circuit 50. The following is about... Figure 9 The timing diagram shown is in conjunction with Figure 6 The timing diagram of the second embodiment shown is explained focusing on different parts. Additionally, in... Figure 9 In the diagram, from time t8 to time t11, only the driven semiconductor element changes; the operation itself is the same as from time t4 to time t7, so the description of the operation is omitted. Additionally, Figure 9 The example assumes that the driver instructions cmd1 and cmd2 mistakenly become high instructions at the same time.

[0168] At time t1: When the inverted logic of the simultaneous turn-on prevention instruction c1_onp is in the turn-on enabled state (High), if a turn-on instruction (High) is input to the drive instruction cmd1, then the drive instruction cmd3 becomes a turn-on instruction (High). As a result, the gate voltage G1 begins to rise. Simultaneously, via resistor R1, the inverted logic of the simultaneous turn-on prevention instruction c2_onp becomes the turn-on disabled state (Low).

[0169] At time t2: Even if a conduction instruction (High) is input to the drive instruction cmd2, a conduction inhibition instruction (Low) is input via resistor R1 as the inverted logic of the simultaneous conduction prevention instruction c2_onp. Therefore, the AND circuit 42 maintains the shutdown instruction (Low) of the drive instruction cmd4.

[0170] At time t3: when the potential through gate G1 becomes above Vth_mon, the gate monitoring signal Mon_g1 becomes the turn-on determination. Figure 9 In the example, a shutdown instruction (Low) is input to the drive instruction cmd2 before time t4.

[0171] At time t4: After the aforementioned turn-off instruction, a turn-on instruction (High) is input to the drive instruction cmd2, but the inverting logic input to the simultaneous turn-on prevention instruction c2_onp is turned off (Low) via diode Di1. Therefore, the AND circuit 42 maintains the turn-off instruction (Low) of the drive instruction cmd4.

[0172] At time t5: A turn-off instruction (Low) is input to the drive instruction cmd1, and the potential of gate G1 begins to decrease.

[0173] At time t6: the potential of gate G1 is less than Vth_mc, the Miller clamp circuit 15 starts to operate, and the potential of gate G1 drops to the VSS2_1 potential. Simultaneously, by making the potential of gate G1 less than Vth_mon, a turn-off determination (Low) result is output to the gate monitoring signal Mon_g1. Therefore, the inverted logic of the simultaneous turn-on prevention instruction c2_onp becomes turn-on enabled (High). Here, because a turn-on instruction is input to the drive instruction cmd2, the potential of gate G2 begins to rise. At the same time, the inverted logic of the simultaneous turn-on prevention instruction c1_onp becomes turn-on disabled (Low) via diode Di2.

[0174] At time t7: when the gate G2 potential becomes above Vth_mon, the gate monitoring signal Mon_g2 becomes the turn-on determination.

[0175] Thus, in the inverter device 800 of this embodiment, the simultaneous conduction prevention circuit 50 is connected to the gate drive control device 10 via the active dead-time control unit 40. In this embodiment, by providing the simultaneous conduction prevention circuit 50, when the gate state determination circuit 14 does not detect that the gate voltage of one semiconductor element is lower than a predetermined detection threshold, the other semiconductor element is prevented from conducting.

[0176] According to the above-described embodiment, even if a simultaneous ON command for the upper and lower arms is input due to a software malfunction of the microcontroller (MCU1), the simultaneous ON of the upper and lower arms can be prevented from occurring simultaneously on the side of the simultaneous ON prevention circuit 50 (GDIC).

[0177] <Fourth Implementation Method>

[0178] Below, refer to Figure 10 The configuration of the inverter device according to the fourth embodiment of the present invention will be described.

[0179] Figure 10 This illustrates an example of the configuration of the gate monitoring unit included in the inverter device according to the fourth embodiment of the present invention. Figure 10 The gate monitoring unit 12B shown is an example of a configuration that can rewrite the values ​​of Vth_mon and Vth_mc via SPI communication.

[0180] The following describes the gate monitoring section 12B in relation to... Figure 2 The following description focuses on different configurations of the gate monitoring unit 12 in the first embodiment shown. The gate monitoring unit 12B includes a buffer circuit BUF1, but if referred to... Figure 4 If the conditions are met as described, then the buffer circuit BUF1 may not need to be set.

[0181] In addition to the configuration of the gate monitoring unit 12 in the first embodiment, the gate monitoring unit 12A also includes an SPI communication circuit 1100 and a memory 1110. SPI (Serial Peripheral Interface) is one of the standards for data transmission paths. SPI is a bus-type connection method in which multiple devices share a transmission path, and it adopts a serial communication method that uses one signal line for communication in one direction.

[0182] The SPI communication circuit 1100 executes actions corresponding to commands input via SPI communication Com_s1. For example, the SPI communication circuit 1100 rewrites the value of Vth_mon stored in memory 1110 by inputting a command via SPI communication Com_s1 to change the value of Vth_mon. Furthermore, the SPI communication circuit 1100 can also use SPI communication Com_s1 to transmit information about whether gate driving is in progress (the status of drive instructions cmd1 and cmd2). Additionally, SPI communication can also be configured to exchange bidirectional data via additional signal lines.

[0183] The memory 1110 reflects the stored information in Vth_mon or Vth_mc. When the gate drive of the semiconductor device stops (when both drive instructions cmd1 and cmd2 are in the off instruction state), the memory 1110 changes the value of Vth_mon according to the value stored inside the memory 1110. As the memory 1110, non-volatile memory such as ROM, RAM, or SSD (Solid State Drive) can be used.

[0184] [Threshold Change Action]

[0185] Next, refer to Figure 11 Explain the threshold change operation of the gate monitoring unit 12B.

[0186] Figure 11 This is an example of a timing diagram schematically illustrating the threshold change operation of the gate monitoring unit 12B. Figure 11 Indicates having Figure 10 An example of the start-up operation of the gate drive control device 10 of the gate monitoring unit 12B shown.

[0187] t1 time point: from power supply VCC1 ( Figure 1 When power is supplied, the potential of power supply VCC1 begins to rise.

[0188] At time t2: After the potential of power supply VCC1 rises, the SPI communication circuit 1100 sets the memory rewrite permission signal of memory 1110 to permission (High in this embodiment). Memory 1110 reflects the initial value (Vth_L) of Vth_mon stored in memory 1110 in Vth_mon.

[0189] At time t3: via SPI communication Com_s1, instruction 1 is input to change the value of Vth_mon to the value of Vth_H. SPI communication circuit 1100 rewrites the initial value (Vth_L) in memory 1110 to the SPI write value (Vth_H) according to instruction 1.

[0190] At time t4: Memory 1110 reflects the newly recorded Vth_H into Vth_mon.

[0191] At time t5: MCU1 inputs drive instruction cmd1 to SPI communication circuit 1100, and gate driving begins according to the turn-on / turn-off instructions of drive instruction cmd1. At this time, SPI communication circuit 1100 receives command 2 (during gate driving) via SPI communication Com_s1. SPI communication circuit 1100 sets the memory rewrite permission signal to disabled (Low in this embodiment) according to command 2.

[0192] In the gate monitoring unit 12B of this embodiment described above, a reference voltage is provided to determine the control threshold (Vth_mc) and the detection threshold (Vth_mon). The reference voltage can be set before the gate drive begins. The reference voltage can be generated, for example, by the reference voltage generation circuit 13 ( Figure 2 )generate.

[0193] In this embodiment with such a configuration, Miller clamping action and gate turn-off detection can be performed at the optimal time based on the control threshold (Vth_mc) and detection threshold (Vth_mon) of the power devices (first semiconductor element 31, second semiconductor element 32) driving the target.

[0194] Furthermore, in this embodiment, an example is shown where Vth_mon is changed via SPI communication Com_s1 when the gate drive control device is started. However, Vth_mon can also be changed according to the system state as long as the gate drive is stopped after startup. For example, suppose the gate voltage threshold of the power devices (first semiconductor element 31, second semiconductor element 32) decreases due to long-term use. In this case, the degradation of the power devices can also be detected by a microcontroller such as MCU1, and the Vth_mon can be changed to a suitable value at any time via SPI communication Com_s1.

[0195] In the gate monitoring unit 12B of this embodiment, at least one of the control threshold (Vth_mc) and the detection threshold (Vth_mon) can be set by an external signal. Furthermore, after being set before the gate drive begins, it can be changed according to the system state.

[0196] In this embodiment with such a configuration, when starting the inverter device, by using SPI or an external port (not shown), the control threshold and detection threshold can be set to the optimal threshold for the power device of the drive target without changing the circuit configuration.

[0197] The present invention is not limited to the above-described embodiments. Various other modifications and applications may be adopted without departing from the inventive spirit described herein.

[0198] For example, the above embodiments are embodiments for which the structure has been described in detail and specifically to facilitate understanding of the present invention, and are not necessarily limited to having all the described constituent elements. Furthermore, constituent elements of other embodiments can be used to replace a portion of the structure of certain embodiments. Constituent elements of other embodiments can also be added to the structure of some embodiments. Additionally, for a portion of the structure of each embodiment, other constituent elements can be added, replaced, or deleted.

[0199] For example, Figure 2 , Figure 4 , Figure 12 and Figure 13 The configuration of the gate monitoring units 12, 12A, 12C, and 12D shown is applicable not only to the first embodiment but also to the second to fourth embodiments. Furthermore, the gate monitoring unit 12B in the fourth embodiment is also applicable to the first to third embodiments.

[0200] Furthermore, to shorten the signal transmission delay time, a portion of the configuration, circuitry, and functions shown in each embodiment can be integrated into a single semiconductor device. That is, any one or more of the gate drive unit, Miller clamp circuit, gate monitoring circuit (e.g., gate state determination circuit 14), active dead-time control unit (active dead-time control unit 40), and simultaneous conduction prevention circuit can be integrated into a single semiconductor device. Moreover, it can be configured to output a detection threshold to the outside of the semiconductor device when the gate voltage of either the first semiconductor element or the second semiconductor element falls below a predetermined detection threshold.

[0201] With this configuration, integration can shorten the wiring length for transmitting each signal and reduce signal transmission delay.

[0202] Furthermore, the aforementioned components, functions, and processing units can be implemented in hardware, for example, by designing some or all of them using integrated circuits. As hardware, broader processor devices such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits) can also be used.

[0203] Furthermore, in the above embodiments, control lines and information lines refer to lines deemed necessary in the description, and may not necessarily represent all control lines and information lines on the product. In reality, it can be considered that almost all constituent elements are interconnected.

[0204] Explanation of symbols

[0205] 10, 20… Gate drive control device, 11… Gate drive unit, 12, 12A to 12D… Gate monitoring unit, 13… Reference voltage generation circuit, 14… Gate state determination circuit, 15… Miller clamping circuit, 21… Gate drive unit, 22… Gate monitoring unit, 31… First semiconductor element, 32… Second semiconductor element, 40… Active dead time control unit, 50… Simultaneous conduction prevention circuit, 100, 600, 800… Inverter device, G1, G2… Gate.

Claims

1. A gate drive control device that drives a gate of a first semiconductor element, characterized by, Possessing: a Miller clamp circuit that holds a gate voltage of the first semiconductor element to a low level when the gate voltage is less than a prescribed control threshold value; and a gate monitoring circuit that detects when the gate voltage of the first semiconductor element is less than a prescribed detection threshold value of a positive potential, the gate monitoring circuit is configured to detect when the gate voltage of the first semiconductor element is less than the detection threshold value at the same time as or after the start of operation of the Miller clamp circuit when the first semiconductor element is off.

2. The gate drive control device according to claim 1, characterized in that a positive dead time control section is provided that turns on the second semiconductor element of the opposite arm connected in series with the first semiconductor element after the gate monitoring circuit detects when the gate voltage of the first semiconductor element is less than the detection threshold value.

3. The gate drive control device according to claim 2, characterized in that the detection threshold value of the gate monitoring circuit is set to the same value as the control threshold value of the Miller clamp circuit or a value less than the control threshold value.

4. The gate drive control device according to claim 3, characterized in that the other semiconductor element is prohibited from turning on when the gate monitoring circuit does not detect when the gate voltage of one of the semiconductor elements is less than a prescribed detection threshold value.

5. The gate drive control device according to claim 4, characterized in that the gate monitoring circuit detects when the gate voltage of the first semiconductor element and the gate voltage of the second semiconductor element are less than a prescribed detection threshold value, the gate drive control device possesses: a gate drive section that drives the gate of the first semiconductor element and the gate of the second semiconductor element; and a simultaneous conduction prevention circuit that prohibits the gate drive section from driving the gate of the other semiconductor element when the gate monitoring circuit does not detect when the gate voltage of one of the semiconductor elements is less than a prescribed detection threshold value.

6. The gate drive control device according to claim 3, characterized in that a reference voltage that determines the control threshold value and the detection threshold value is possessed, the reference voltage is set before the start of gate drive.

7. The gate drive control device according to claim 3, characterized in that at least either the detection threshold value or the control threshold value can be set by information of an external signal, and after being set before the start of gate drive, is changed according to the state of the first semiconductor element by information of the external signal.

8. The gate drive control device according to any one of claims 1 to 7, characterized in that any one or more of the gate drive section, the Miller clamp circuit, the gate monitoring circuit, the positive dead time control section, and the simultaneous conduction prevention circuit are integrated in one semiconductor device, A case where a gate voltage of either one of the first semiconductor element and the second semiconductor element is lower than a prescribed detection threshold is output to the outside of the semiconductor device.

9. A power conversion device, characterized by, Provided are: a gate drive section that drives a gate of a first semiconductor element and a gate of a second semiconductor element that constitute an upper arm and a lower arm; a Miller clamp circuit that holds a gate voltage of the semiconductor element at a low level when the gate voltage of the first semiconductor element and the gate voltage of the second semiconductor element are less than a prescribed control threshold; and a gate monitoring circuit that detects a case where the gate voltage of the first semiconductor element and the gate voltage of the second semiconductor element are lower than a prescribed detection threshold of a positive potential, the gate monitoring circuit being configured to detect a case where the gate voltage of one of the semiconductor elements is lower than the detection threshold at the same time as or after the start of operation of the Miller clamp circuit when the one of the semiconductor elements is turned off.

Images