Oscillator based on BAW resonator

Abstract

A circuit (100) includes a resonator (104), a transistor pair (102), and a common mode feedback circuit (106). The transistor pair (102) is cross-coupled across the resonator (104). The common mode feedback circuit (106) is coupled to the transistor pair (102). The common mode feedback circuit (106) includes a first degradation unit (132) and a second degradation unit (134). The second degradation unit (134) is connected in parallel with the first degradation unit (132). The second degradation unit (134) is configured to switchably vary current through the transistor pair (102).

Description

Background Technology

[0001] A resonator is a device or system that oscillates naturally at a frequency called its resonant frequency. Resonators can be, for example, crystal resonators (also known as quartz resonators), inductive-capacitive (LC) resonators, or microelectromechanical systems (MEMS) resonators. Resonators are typically passive devices that are combined with active circuitry to form an oscillator. An oscillator generates a periodic signal at its resonant frequency. For example, a crystal oscillator is an electronic circuit that uses the mechanical resonance of a vibrating crystal to generate an electrical signal with a very precise frequency. Crystal oscillators can be used to generate frequencies for time recording or to generate clock signals for digital integrated circuits. MEMS resonators can be used instead of crystal resonators to record time and generate stable clock signals for analog and digital integrated circuits. Summary of the Invention

[0002] In one example, a circuit includes a resonator, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor, as well as a first switch and a second switch. The resonator has a first terminal and a second terminal. The first transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the first transistor is coupled to the first terminal of the resonator. The control terminal is coupled to the second terminal of the resonator. The second transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor is coupled to the second terminal of the resonator. The control terminal of the second transistor is coupled to the first terminal of the resonator. The third transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor is coupled to the second terminal of the first transistor. The control terminal of the third transistor is coupled to the first terminal of the resonator. The first resistor is coupled between the second terminal of the third transistor and a reference voltage terminal. The fourth transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the fourth transistor is coupled to the second terminal of the first transistor. The control terminal of the fourth transistor is coupled to the first terminal of the resonator. The second resistor and the first switch are coupled in series between the second terminal of the fourth transistor and the reference voltage terminal. The fifth transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the fifth transistor is coupled to the second terminal of the second transistor. The control terminal of the fifth transistor is coupled to the second terminal of the resonator. The third resistor is coupled between the second terminal of the fifth transistor and the reference voltage terminal. The sixth transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the sixth transistor is coupled to the second terminal of the second transistor. The control terminal of the sixth transistor is coupled to the second terminal of the resonator. A fourth resistor and a second switch are coupled in series between the second terminal of the sixth transistor and the reference voltage terminal.

[0003] In another example, a circuit includes a resonator, a pair of transistors, and a common-mode feedback circuit. The transistor pair is cross-coupled across the resonator. The common-mode feedback circuit is coupled to the transistor pair. The common-mode feedback circuit includes a first degradation unit and a second degradation unit. The second degradation unit is connected in parallel with the first degradation unit. The second degradation unit is configured to switchably change the current through the transistor pair.

[0004] In another example, a clock generator circuit includes an oscillator circuit, a frequency divider circuit, and a driver circuit. The frequency divider circuit is coupled to the oscillator circuit. The driver circuit is coupled to the frequency divider circuit. The oscillator circuit includes a resonator, a pair of transistors, and a common-mode feedback circuit. The pair of transistors is cross-coupled across the resonator. The common-mode feedback circuit is coupled to the pair of transistors. The common-mode feedback circuit includes a first degradation unit and a second degradation unit. The second degradation unit is connected in parallel with the first degradation unit. The second degradation unit is configured to switchably change the current through the pair of transistors. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of an example oscillator circuit that includes a bulk acoustic wave (BAW) resonator and variable common-mode feedback.

[0006] Figure 2 To show Figure 1 The graphs show the small-signal loop gain and large-signal loop gain in an example oscillator circuit.

[0007] Figure 3 This is a schematic diagram of an example oscillator circuit that includes a BAW resonator and a current ramp.

[0008] Figure 4 To show Figure 3 The graph shows examples of small-signal gain for oscillator circuits with different currents.

[0009] Figure 5 To show Figure 4 The magnified portion of the curve graph.

[0010] Figure 6 To show Figure 3 The graph shows the small-signal gain and corresponding large-signal gain of an example oscillator circuit.

[0011] Figure 7 This is a schematic diagram of an example oscillator circuit that includes a BAW resonator and a low-pass filter to reduce high-frequency gain.

[0012] Figure 8 To show Figure 7 A graph showing an example of how the small-signal gain of an oscillator circuit decreases at higher frequencies.

[0013] Figure 9This is a schematic diagram of an example oscillator circuit that includes a BAW resonator, variable common-mode feedback, current ramp, and low-pass filter.

[0014] Figure 10 This is a block diagram of an example clock generator circuit that includes the oscillator circuit described herein. Detailed Implementation

[0015] Oscillator circuits that include resonators such as bulk acoustic wave (BAW) resonators may oscillate at frequencies other than the fundamental frequency required by the resonator. In some cases, oscillator circuits may oscillate at parasitic frequencies higher or lower than the fundamental frequency of the resonator. Some oscillator circuits may include inductive-capacitive filters to prevent parasitic oscillations, which can take up a significant amount of circuit area. Alternatively, devices exhibiting parasitic oscillations can be discarded, which reduces yield.

[0016] The oscillator circuits described herein may include a linearized common-mode feedback loop and / or a current ramp in the oscillator circuit to eliminate parasitic oscillations, rather than using a passive filter containing large inductors and capacitors to reduce gain at parasitic frequencies. Some examples may include a resistor connected in series with the control terminals of the oscillator's transistor to reduce gain at frequencies above the resonator's fundamental frequency, thereby eliminating parasitic oscillations above the fundamental frequency.

[0017] Figure 1 This is a schematic diagram of an example oscillator circuit 100. The oscillator circuit 100 includes a transistor pair 102 and a resonator 104, a common-mode feedback circuit 106, a transistor pair 108, capacitors 118, 120, 126, and 128, resistors 122 and 124, and transistors 162 and 164. The resonator 104 may be a BAW resonator or another type of resonator. Inductors 130 and / or 131 may be coupled in series with the resonator 104 between the terminals of transistor pair 102 and transistor pair 108. Inductors 130 and 131 may be components or parasitic. A capacitor 120 is coupled in parallel with the resonator 104 between the terminals of transistor pair 102 and transistor pair 108. The capacitance of capacitor 120 may be variable to provide adjustment of the oscillation frequency of the oscillator circuit 100.

[0018] Transistor pair 102 includes transistors 110 and 112. Transistors 110 and 112 may be n-type field-effect transistors (NFETs), as shown. Transistors 110 and 112 are cross-coupled across resonator 104. Therefore, a first current terminal, or simply terminal (e.g., drain), of transistor 110 is coupled to a first terminal of resonator 104, and a control terminal (e.g., gate) of transistor 110 is coupled to a second terminal of resonator 104. Furthermore, in the cross-coupled configuration, a first current terminal (e.g., drain) of transistor 112 is coupled to a second terminal of resonator 104, and a control terminal (e.g., gate) of transistor 112 is coupled to a first terminal of resonator 104. A second current terminal (e.g., source) of transistor 110 is coupled to common-mode feedback circuit 106 and to the first conductor (also referred to as a terminal) of capacitor 118. A second current terminal (e.g., source) of transistor 112 is coupled to common-mode feedback circuit 106 and to the second conductor (also referred to as a terminal) of capacitor 118. Capacitor 118 provides control over the gain contribution of transistor pair 102 at low frequencies. Capacitor 118 can be variable to allow for process variations in capacitance.

[0019] Transistor pair 108 includes transistors 114 and 116. Transistors 114 and 116 may be p-type field-effect transistors (PFETs), as shown. Transistors 114 and 116 are cross-coupled across resonator 104. Thus, a first current terminal (e.g., drain) of transistor 114 is coupled to a first terminal of resonator 104, and a control terminal (e.g., gate) of transistor 114 is coupled to a second terminal of resonator 104 via capacitor 128. Furthermore, in the cross-coupled configuration, a first current terminal (e.g., drain) of transistor 116 is coupled to a second terminal of resonator 104, and a control terminal (e.g., gate) of transistor 116 is coupled to a first terminal of resonator 104 via capacitor 126. A second current terminal (e.g., source) of transistor 114 is coupled to a current source, in this example, transistor 162. A second current terminal (e.g., source) of transistor 116 is coupled to a current source, in this example, transistor 164. Resistor 122 is coupled at the bias voltage terminal VBIAS between the control terminal of transistor 114 and the bias voltage circuit (not shown). In some examples of the oscillator circuit 100, the bias voltage provided at VBIAS can be in the range of 0.5 to 0.7 volts. Resistor 124 is coupled at the bias voltage terminal VBIAS between the control terminal of transistor 116 and the bias voltage circuit. Resistor 122 and capacitor 128 form a first high-pass filter, and resistor 124 and capacitor 126 form a second high-pass filter to control the gain of transistor pair 108 at low frequencies. The resistance of resistors 122 and 124 can be variable to provide control over the filter cutoff frequency in the presence of process variations.

[0020] Transistors 162 and 164 supply current to oscillator circuit 100. A first current terminal (e.g., source) of transistor 162 is coupled to a power supply terminal Vdd, and a second current terminal (e.g., drain) of transistor 162 is coupled to a second current terminal of transistor 114. A control terminal (e.g., gate) of transistor 162 is coupled to bias circuit 166. Bias circuit 166 provides a bias voltage 168 to transistors 162 and 164. Transistor 164 is coupled in parallel with transistor 162. More specifically, a first current terminal (e.g., source) of transistor 164 is coupled to a first current terminal of transistor 162 and to the power supply terminal Vdd. A second current terminal (e.g., drain) of transistor 164 is coupled to a second current terminal of transistor 116. A control terminal (e.g., gate) of transistor 164 is coupled to bias circuit 166 to receive bias voltage 168. In some instances of bias circuit 166, bias voltage 168 may be in the range of 0.5 to 0.7 volts. Transistors 162 and 164 can be PFETs, as shown.

[0021] The common-mode feedback circuit 106 includes degradation units 132, 134, 136, and 138. Degradation units 132 and 134 are coupled to transistor 110. Degradation units 136 and 138 are coupled to transistor 112. Degradation units 132 and 138 are coupled to a reference voltage terminal 160 (e.g., ground) via a fixed conductor. Degradation units 134 and 136 are switchably coupled to the reference voltage terminal 160. Examples of the common-mode feedback circuit 106 may include more than one instance of degradation unit 134 and more than one instance of degradation unit 136. Each instance of degradation units 134 and 136 can be controlled independently. Therefore, the resistance of the path between transistor pair 102 and reference voltage terminal 160 can be changed by controlling the number of degradation units that conduct current to reference voltage terminal 160.

[0022] Degradation unit 132 includes transistor 140 and resistor 142. A first current terminal (e.g., drain) of transistor 140 is coupled to a second current terminal of transistor 110. Resistor 142 is coupled between the second current terminal (e.g., source) of transistor 140 and a reference voltage terminal 160. A control terminal (e.g., gate) of transistor 140 is coupled to a first terminal of resonator 104.

[0023] Degradation unit 134 includes transistor 144, resistor 146, and switch 148. Switch 148 may include a field-effect transistor or other switching device. A first current terminal (e.g., drain) of transistor 144 is coupled to a first current terminal of transistor 140. A control terminal (e.g., gate) of transistor 144 is coupled to a control terminal of transistor 140. Resistor 146 and switch 148 are coupled in series between a second current terminal (e.g., source) of transistor 144 and a reference voltage terminal 160.

[0024] The degradation unit 138 includes a transistor 156 and a resistor 158. A first current terminal (e.g., drain) of transistor 156 is coupled to a second current terminal of transistor 112. Resistor 158 is coupled between the second current terminal (e.g., source) of transistor 156 and a reference voltage terminal 160. A control terminal (e.g., gate) of transistor 156 is coupled to a second terminal of resonator 104.

[0025] The degradation unit 136 includes a transistor 150, a resistor 152, and a switch 154. Switch 154 may include a field-effect transistor or other switching device. A first current terminal (e.g., drain) of transistor 150 is coupled to a first current terminal of transistor 156. A control terminal (e.g., gate) of transistor 150 is coupled to a control terminal of transistor 156. Resistor 152 and switch 154 are coupled in series between a second current terminal (e.g., source) of transistor 150 and a reference voltage terminal 160.

[0026] Figure 2 To illustrate the graphs of the small-signal loop gain and large-signal loop gain in an example of oscillator circuit 100. Figure 2 In the diagram, curve 204 represents the small-signal loop gain of oscillator circuit 100. Figure 2 In the diagram, curve 202 represents the large-signal loop gain in a variable-degradation oscillator circuit lacking the common-mode feedback circuit 106. In this circuit, the current in the common-mode feedback transistor can be modulated, which generates a nonlinear transconductance (g) in the feedback loop. m The low-frequency gain peaks, caused by the addition of a component, increase the impedance of large signals at low frequencies, resulting in low-frequency peaking above 0 dB, as shown in curve 202. In addition to or replacing the oscillation at the fundamental frequency of the resonator, the low-frequency gain peaks can lead to low-frequency oscillations.

[0027] The common-mode feedback circuit 106 provides resistive degradation by reducing the nonlinearity g of the transistor in the common-mode feedback circuit 106. m The influence of the components is used to prevent the low-frequency peaking of curve 202.

[0028] ,for , (1)

[0029] Wherein: g m,eff For the effective transconductance of the common-mode feedback circuit 106; g m The transconductance of the transistor in the common-mode feedback circuit 106; and R E The resistor is the parallel degradation resistor of the common-mode feedback circuit 106.

[0030] Equation (1) shows that if g m R E If the effective transconductance (g) of the common-mode feedback circuit 106 is greater than one, then... m,eff The resistance (R) of the degradation resistors (resistors 142, 146, 152, and 158) in the common-mode feedback circuit 106. E Therefore, the g of the common-mode feedback circuit 106 can be controlled by degradation. mThis also prevents low-frequency oscillations caused by curve 202. However, to maintain a constant swing across process and voltage, the oscillator current needs to be changed, which will significantly alter g. m This will also change For low current values, and In this situation, the desired degradation may not be achievable with fixed degradation. Oscillator circuit 100 addresses this by adjusting the number of degradation units 134 and 136 activated in common-mode feedback circuit 106 based on the current drawn by oscillator circuit 100 (by closing switches 148 and 154) to maintain... Constant (or nearly constant). For example, the number of degradation units to be activated can be selected during manufacturing / testing at 100, and the switches of the degradation units can be closed during manufacturing, testing, or operation to set the desired degradation.

[0031] exist Figure 2 In the diagram, curve 206 represents the large-signal loop gain of oscillator circuit 100. Common-mode feedback circuit 106 maintains the large-signal loop gain below 0 dB at low frequencies to prevent low-frequency oscillations caused by curve 202.

[0032] Figure 3 This is a schematic diagram of an example oscillator circuit 300. Oscillator circuit 300 is similar to oscillator circuit 100. Oscillator circuit 300 includes transistor pair 102, resonator 104, transistor pair 108, capacitors 118, 120, 126, and 128, and resistors 122 and 124. Oscillator circuit 300 includes a common-mode feedback circuit 314, as shown, which includes only transistors 140 and 156, the second terminals of which are directly coupled to a reference voltage terminal 160. In some examples of oscillator circuit 300, common-mode feedback circuit 106 can be used as common-mode feedback circuit 314.

[0033] The oscillator circuit 300 also includes a current ramp circuit 316, which comprises transistors 162 and 164, ramp units 318 and 320, and control circuitry 318. Ramp unit 318 includes transistor 304 and switch 306. Ramp unit 320 includes transistor 308 and switch 310. Transistors 304 and 308 may be PFETs, as shown. Although Figure 3 Two ramp units are shown, but the current ramp circuit 316 may contain more than two ramp units.

[0034] In ramp unit 318, transistor 304 and switch 306 are coupled in series, such that the first current terminal (e.g., source) of transistor 304 is coupled to the first current terminals of transistors 162 and 164 via switch 306. Furthermore, the second current terminal (e.g., drain) of transistor 304 is coupled to the second current terminals of transistors 162 and 164. The control terminal (e.g., gate) of transistor 304 is coupled to bias circuit 166 to receive bias voltage 168. In ramp unit 320, transistor 308 and switch 310 are coupled in series, such that the first current terminal (e.g., source) of transistor 308 is coupled to the first current terminals of transistors 162 and 164 via switch 310. Furthermore, the second current terminal (e.g., drain) of transistor 308 is coupled to the second current terminal of transistor 162. The control terminal (e.g., gate) of transistor 308 is coupled to bias circuit 166 to receive bias voltage 168.

[0035] Switches 306 and 310 are coupled to control circuit 318 (also referred to as ramp control circuit) to receive control signals (C1 and CN) controlling the opening and closing of switches 306 and 310. An example of current ramp circuit 316 may include more than two ramp units coupled in parallel with transistors 162 and 164 between Vdd and transistor pair 108. Upon startup of oscillator circuit 300, control circuit 318 may time the sequential closing of switches 306 and 310 (and any number of additional switches, according to a predetermined startup timing function) to gradually increase the current in oscillator circuit 300. In oscillator circuit 300, oscillation may occur at a frequency with a loop gain greater than 1. The loop gain varies with transconductance, which depends on the current. Current ramp circuit 316 provides reliable startup oscillation at the desired frequency (e.g., the fundamental frequency of resonator 104) by gradually increasing the current flowing in oscillator circuit 300 upon startup. The resonator 104 has a high impedance at the fundamental frequency, which causes the gain of the oscillator circuit 300 at the fundamental frequency to be higher than the gain at higher or lower peak frequencies. Therefore, as the current ramp circuit 316 increases the current flowing in the oscillator circuit 300, the gain at the fundamental frequency first exceeds 0 dB, which causes the oscillation to begin only at the fundamental frequency.

[0036] Figure 4 and 5 A graph is shown to illustrate the increase in small-signal gain in oscillator circuit 300 as the current increases during startup (e.g., as switch 310 is closed after a predetermined time following switch 306). Figure 5 for Figure 4Enlarged views of curves 402, 404, and 406 in interval 408. Curve 402 represents the gain of oscillator circuit 300 at the first current. Curve 404 represents the gain of oscillator circuit 300 at a second current higher than the first current. Curve 406 represents the gain of oscillator circuit 300 at a third current higher than the second current. Figure 5 The small-signal gain of the oscillator circuit 300 is shown to exceed 0 dB only at the fundamental frequency of the resonator 104.

[0037] Figure 6 The graphs of the large-signal loop gain 604 and small-signal loop gain 602 in an example of oscillator circuit 300 are shown. For all frequencies below the fundamental frequency, the large-signal gain remains below 0 dB, making the oscillation stable at the fundamental frequency of resonator 104.

[0038] Figure 7 This is a schematic diagram of an example oscillator circuit 700. Oscillator circuit 700 is similar to oscillator circuit 100 and / or oscillator circuit 300. Oscillator circuit 700 includes transistor pair 102, resonator 104, transistor pair 108, capacitors 118, 120, 126, and 128, and resistors 122 and 124. Oscillator circuit 700 includes common-mode feedback circuit 314. In some examples of oscillator circuit 700, common-mode feedback circuit 106 may be used as common-mode feedback circuit 314. Some examples of oscillator circuit 700 may also include current ramp circuit 316.

[0039] Compared to oscillator circuits 100 and 300, oscillator circuit 700 provides additional margin at frequencies above the fundamental frequency of resonator 104 by reducing the small-signal loop gain at high frequencies. This additional margin increases the immunity of oscillator circuit 700 to oscillations at high frequencies related to aging, changes in bond wire inductance, etc. This increased margin is provided by adding resistors 702, 704, 706, and 708 at the control terminals of transistors 114, 116, 110, and 112. The resistances of resistors 702, 704, 706, and 708 can be selected based on the capacitance of the control terminals of transistors 114, 116, 110, and 112 to provide the desired low-pass filter attenuating frequencies above the fundamental frequency of resonator 104. Resistor 702 is coupled between the control terminal of transistor 114 and the second terminal of resonator 104. Resistor 704 is coupled between the control terminal of transistor 116 and the first terminal of resonator 104. Resistor 706 is coupled between the control terminal of transistor 110 and the second terminal of resonator 104. Resistor 708 is coupled between the control terminal of transistor 112 and the first terminal of resonator 104. Resistors 702, 704, 706, and 708, together with the control terminal capacitance (e.g., gate capacitance) of the transistors coupled to the resistors, provide a low-pass filter to reduce high-frequency gain and prevent high-frequency oscillations.

[0040] Figure 8 A graph illustrating the small-signal loop gain in an example of oscillator circuit 700. Figure 8 Curves 802 and 804 are shown. Curve 802 represents the small-signal loop gain of the oscillator without resistors 702, 704, 706, and 708, and curve 804 represents the small-signal loop gain of oscillator circuit 700. Comparing curves 802 and 804, oscillator circuit 700 reduces the gain at high frequencies by approximately 2 dB compared to the oscillator circuit lacking resistors 702, 704, 706, and 708. This helps prevent oscillations at frequencies higher than the fundamental frequency of resonator 104.

[0041] Figure 9 This is a schematic diagram of an example oscillator circuit 900. Oscillator circuit 900 is similar to oscillator circuits 100, 300, and 700. Oscillator circuit 900 includes transistor pair 102, resonator 104, transistor pair 108, capacitors 118, 120, 126, and 128, and resistors 122 and 124. Oscillator circuit 900 also includes the common-mode feedback circuit 106, current ramp circuit 316, and resistors 702, 704, 706, and 708 described with respect to oscillator circuits 100, 300, and 700. Therefore, oscillator circuit 900 provides all the advantages of oscillator circuits 100, 300, and 700.

[0042] Figure 10 This is a block diagram of an example clock generator circuit 1000. The clock generator circuit 1000 includes an oscillator circuit 1002, a frequency divider circuit 1004, an output driver circuit 1006, a temperature sensor 1008, control logic 1010, a digital-to-analog converter (DAC) 1012, and a filter 1014. The oscillator circuit 1002 may be an implementation of oscillator circuit 100, oscillator circuit 300, oscillator circuit 700, or oscillator circuit 900. The output of the oscillator circuit 1002 is coupled to the input of the frequency divider circuit 1004. The frequency divider circuit 1004 includes a circuit system that divides the frequency of the output signal received from the oscillator circuit 1002 by an integer or non-integer divisor to generate the desired clock frequency. The output of the frequency divider circuit 1004 is coupled to the input of the output driver circuit 1006. The output driver circuit 1006 buffers the output of the frequency divider circuit 1004 to generate an output clock signal (CLKOUT) provided to external circuitry (not shown).

[0043] Temperature sensor 1008 measures the temperature of the operating environment of oscillator circuit 1002. Temperature sensor 1008 is coupled to control logic 1010 and provides the temperature measurement value to control logic 1010. Control logic 1010 generates an adjustment value based on the temperature measurement value received from temperature sensor 1008. For example, control logic 1010 may include a lookup table storing the adjustment value for a temperature value or temperature range. The output of control logic 1010 is coupled to DAC 1012. Control logic 1010 provides the adjustment value to DAC 1012, and DAC 1012 converts the adjustment value into an analog signal. The output of DAC 1012 is coupled to filter 1014. Filter 1014 filters the analog signal received from DAC 1012 (e.g., a low-pass filter) and provides the filtered signal to oscillator circuit 1002. Oscillator circuit 1002 applies the filtered signal to adjust the frequency of oscillator circuit 1002 for temperature. For example, an analog signal may be applied to adjust capacitor 120 (…). Figure 9 The capacitor can adjust the frequency generated by the oscillator circuit 1002.

[0044] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0045] Furthermore, in this description, the term "based on" means "at least partially based on". Therefore, if X is based on Y, then X can depend on Y and any number of other factors.

[0046] A device “configured” to perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigurable) by the user after manufacturing to perform the function and / or other additional or alternative functions. This configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components, and through the interconnection of the device, or a combination thereof.

[0047] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0048] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the said passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0049] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuit system. For example, field-effect transistors (“FETs”) (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, such as NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in or on a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0050] Reference may be made to the control input and current terminals of the transistor in the claims. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0051] In this document, the reference to "FET on" or "enabled" means that a conductive channel exists in the FET and drain current can flow through it. The reference to "FET off" or "disabled" means that no conductive channel exists, and therefore drain current does not flow through the FET. However, a "disabled" FET may have current flowing through the body diode of the transistor.

[0052] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0053] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Furthermore, some or all of the features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0054] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of said parameter, or, if the parameter is zero, within a reasonable range of approximately zero.

[0055] Within the scope of the claims, modifications to the described instances are possible, and other instances are also possible.

Claims

1. A circuit comprising: a resonator having a first terminal and a second terminal; a first transistor having a first terminal coupled to the first terminal of the resonator, a second terminal, and a control terminal coupled to the second terminal of the resonator; a second transistor having a first terminal coupled to the second terminal of the resonator, a second terminal, and a control terminal coupled to the first terminal of the resonator; a third transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal, and a control terminal coupled to the first terminal of the resonator; a first resistor coupled between the second terminal of the third transistor and a reference voltage terminal; a fourth transistor having a first terminal coupled to the second terminal of the first transistor, a second terminal, and a control terminal coupled to the first terminal of the resonator; a second resistor and a first switch coupled in series between the second terminal of the fourth transistor and the reference voltage terminal; a fifth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal, and a control terminal coupled to the second terminal of the resonator; a third resistor coupled between the second terminal of the fifth transistor and the reference voltage terminal; a sixth transistor having a first terminal coupled to the second terminal of the second transistor, a second terminal, and a control terminal coupled to the second terminal of the resonator; and a fourth resistor and a second switch coupled in series between the second terminal of the sixth transistor and the reference voltage terminal.

2. The circuit of claim 1, further comprising: a seventh transistor having a first terminal coupled to the first terminal of the resonator, a second terminal, and a control terminal coupled to the second terminal of the resonator; and an eighth transistor having a first terminal coupled to the second terminal of the resonator, a second terminal coupled to the second terminal of the seventh transistor, and a control terminal coupled to the first terminal of the resonator.

3. The circuit of claim 2, further comprising: a fifth resistor coupled between the control terminal of the first transistor and the second terminal of the resonator; a sixth resistor coupled between the control terminal of the second transistor and the first terminal of the resonator; a seventh resistor coupled between the control terminal of the seventh transistor and the second terminal of the resonator; and an eighth resistor coupled between the control terminal of the eighth transistor and the first terminal of the resonator.

4. The circuit of claim 3, further comprising: a first capacitor coupled between the control terminal of the first transistor and the second terminal of the resonator; and a second capacitor coupled between the control terminal of the second transistor and the first terminal of the resonator.

5. The circuit of claim 2, further comprising: ​ ​ ​ ​ a ninth transistor having a first terminal, a second terminal coupled to the second terminal of the seventh transistor, and a control terminal coupled to a bias voltage circuit; a tenth transistor having a first terminal, a second terminal coupled to the second terminal of the seventh transistor, and a control terminal coupled to the control terminal of the ninth transistor; and a third switch having a first terminal coupled to the first terminal of the tenth transistor, a second terminal coupled to the first terminal of the ninth transistor, and a control terminal.

6. The circuit of claim 5, further comprising: a control circuit having an output coupled to the control terminal of the third switch, the control circuit configured to close the third switch based on a predetermined start-up timing function.

7. The circuit of claim 6, further comprising: an eleventh transistor having a first terminal coupled to the first terminal of the ninth transistor, a second terminal coupled to the second terminal of the seventh transistor, and a control terminal coupled to the control terminal of the ninth transistor; a twelfth transistor having a first terminal coupled to the first terminal of the ninth transistor, a second terminal coupled to the second terminal of the seventh transistor, and a control terminal coupled to the control terminal of the ninth transistor; and a fourth switch having a first terminal coupled to the first terminal of the twelfth transistor, a second terminal coupled to the first terminal of the ninth transistor, and a control terminal coupled to a second output of the control circuit.

8. The circuit of claim 7, wherein the control circuit is configured to close the fourth switch a predetermined time after the control circuit closes the third switch.

9. A circuit comprising: a resonator; a pair of transistors cross-coupled across the resonator; and a common mode feedback circuit coupled to the pair of transistors, the common mode feedback circuit including: a first degeneration cell and a second degeneration cell connected in parallel with the first degeneration cell, the second degeneration cell configured to switchably vary current through the pair of transistors.

10. The circuit of claim 9, wherein: the first degeneration cell includes a first transistor and a first resistor coupled in series between the pair of transistors and a reference voltage terminal; and the second degeneration cell includes a second transistor, a second resistor, and a switch coupled in series between the pair of transistors and the reference voltage terminal.

11. The circuit of claim 9, wherein: the pair of transistors is a first pair of transistors; and the circuit includes: a second pair of transistors cross-coupled across the resonator; and a current ramping circuit coupled to the second pair of transistors, the current ramping circuit configured to increase current in the second pair of transistors over time.

12. The circuit of claim 11, wherein the current ramping circuit includes: a first transistor coupled between the second pair of transistors and a power supply terminal; a first ramp unit coupled in parallel with the first ramp unit between the second transistor pair and a power supply terminal, the second ramp unit including a third transistor and a second switch coupled in series between the second transistor pair and the power supply terminal.

13. The circuit of claim 12, wherein the current ramp circuit includes a ramp control circuit coupled to the first switch and the second switch, the ramp control circuit configured to sequentially close the first switch and the second switch.

14. The circuit of claim 11, wherein: the first transistor pair includes a first transistor and a second transistor; the second transistor pair includes a third transistor and a fourth transistor; and the circuit includes: a first resistor coupled between a control terminal of the first transistor and a first terminal of the resonator; a second resistor coupled between a control terminal of the second transistor and a second terminal of the resonator; a third resistor coupled between a control terminal of the third transistor and the first terminal of the resonator; and a fourth resistor coupled between a control terminal of the fourth transistor and the second terminal of the resonator.

15. The circuit of claim 14, wherein resistances of the first resistor, the second resistor, the third resistor, and the fourth resistor are selected to provide a low pass filter that attenuates frequencies above a fundamental frequency of the resonator.

16. A clock generator circuit, comprising: an oscillator circuit including: a resonator; a transistor pair cross-coupled across the resonator; a common mode feedback circuit coupled to the transistor pair, the common mode feedback circuit including: a first degeneration unit; and a second degeneration unit connected in parallel with the first degeneration unit, the second degeneration unit configured to switchably vary a current through the transistor pair; a divider circuit coupled to the oscillator circuit; and a driver circuit coupled to the divider circuit.

17. The clock generator circuit of claim 16, wherein: the first degeneration unit includes a first transistor and a first resistor coupled in series between the transistor pair and a reference voltage terminal; and the second degeneration unit includes a second transistor, a second resistor, and a switch coupled in series between the transistor pair and a reference voltage terminal.

18. The clock generator circuit of claim 16, wherein: the transistor pair is a first transistor pair; and the oscillator circuit includes: a second transistor pair cross-coupled across the resonator; and a current ramp circuit coupled to the second transistor pair, the current ramp circuit configured to increase a current in the second transistor pair over time.

19. The clock generator circuit of claim 18, wherein the current ramp circuit includes: ​ ​ ​ ​ a first transistor coupled between the second transistor pair and a power supply terminal; a first ramp unit coupled in parallel with the first transistor between the second transistor pair and a power supply terminal, the first ramp unit including a second transistor and a first switch coupled in series between the second transistor pair and a power supply terminal; a second ramp unit coupled in parallel with the first ramp unit between the second transistor pair and the power supply terminal, the second ramp unit including a third transistor and a second switch coupled in series between the second transistor pair and the power supply terminal; and a ramp control circuit coupled to the first switch and the second switch, the ramp control circuit configured to sequentially close the first switch and the second switch.

20. The clock generator circuit of claim 18, wherein: the first transistor pair includes a first transistor and a second transistor; the second transistor pair includes a third transistor and a fourth transistor; and the oscillator circuit includes: a first resistor coupled between a control terminal of the first transistor and a first terminal of the resonator; a second resistor coupled between a control terminal of the second transistor and a second terminal of the resonator; a third resistor coupled between a control terminal of the third transistor and the first terminal of the resonator; and a fourth resistor coupled between a control terminal of the fourth transistor and the second terminal of the resonator; wherein resistances of the first resistor, the second resistor, the third resistor, and the fourth resistor are selected to provide a low pass filter that attenuates frequencies above a fundamental frequency of the resonator. ​ ​

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