Semiconductor device high-temperature reverse bias test method
By employing a step-by-step heating and pressurization method and real-time leakage current monitoring, the problems of device internal resistance fluctuation and surge current in traditional high-temperature reverse bias tests have been solved, enabling safe, reliable, and accurate high-temperature reverse bias testing under extreme conditions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-08
- Publication Date
- 2026-03-13
AI Technical Summary
In traditional high-temperature reverse bias tests, the simultaneous heating and pressurization leads to fluctuations in the device's internal resistance and surge currents, causing distortion of monitoring data and the risk of device damage. This makes it difficult to meet the durability and stability requirements of modern power semiconductors in high-reliability fields such as new energy vehicles.
A step-by-step heating and pressurization method is adopted, first heating to the target temperature and then gradually applying the target voltage. The voltage application is controlled by real-time leakage current monitoring and setting a clear current surge threshold. Combined with constant temperature and pressure testing and standardized data recording, the safety and reliability of the device under extreme high stress conditions are ensured.
It effectively avoids device internal resistance fluctuations and surge currents, improves the accuracy of monitoring data, reduces the risk of device instantaneous breakdown and test equipment damage, and achieves safe, reliable and accurate testing under extreme high stress conditions.
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Figure CN121656786A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device reliability testing technology, and specifically to a high-temperature reverse bias test method for semiconductor devices. Background Technology
[0002] High-Temperature Reverse Bias (HTRB) testing, a core component of power semiconductor reliability assessment, is widely used for long-term stability verification of devices such as power MOSFETs and IGBTs. This test simulates the aging process of devices under extreme operating conditions by applying a superimposed stress of high temperature and reverse bias voltage, effectively identifying potential risks such as material defects, junction degradation, and package failure. Traditional HTRB testing typically employs standardized test conditions, such as placing the device in a 150°C environment and applying 80% of the rated breakdown voltage (Vce), determining the device's reliability level by continuously monitoring changes in reverse leakage current. This method has mature applications in industry, providing important basis for device screening in routine scenarios.
[0003] However, with the widespread adoption of power semiconductors in high-reliability fields such as new energy vehicles and rail transportation, traditional testing conditions are no longer sufficient to meet the extreme requirements for device durability and stability. The industry is gradually attempting to use higher ambient temperatures (such as 175°C or 185°C) and higher reverse bias voltages (such as 90% or even 100% Vce) to accelerate stress testing, but the introduction of high-stress conditions also brings new technical challenges. Especially in the initial stage of testing, if the heating and pressurization processes are carried out simultaneously, the device's internal resistance will fluctuate significantly due to drastic temperature changes, leading to surge currents under instantaneous high voltage. This phenomenon not only causes severe distortion of leakage current detection data but may also trigger instantaneous breakdown of the device or damage to the testing equipment. Summary of the Invention
[0004] To address the above technical problems, this invention provides a technical solution for a high-temperature reverse bias test method for semiconductor devices.
[0005] The technical problem solved by this invention can be achieved by the following technical solutions:
[0006] A method for high-temperature reverse bias testing of semiconductor devices, comprising:
[0007] Step S1: Preprocess the semiconductor device under test and record the initial reverse leakage current I0 of the semiconductor device under test under standard atmospheric conditions.
[0008] Step S2: Load the pre-processed semiconductor device under test into the test system;
[0009] Step S3: The semiconductor device under test in the test system is subjected to heating and pressurization operations in sequence to obtain the target temperature T and the target voltage V;
[0010] Step S4: At the target temperature T and the target voltage V, perform a constant temperature and constant voltage test on the semiconductor device under test for a preset duration.
[0011] Step S5: After the test is completed, record the final reverse leakage current I1 of the semiconductor device under test, and determine the pass / fail status of the semiconductor device under test based on the initial reverse leakage current I0 and the final reverse leakage current I1.
[0012] Preferably, step S3 includes:
[0013] Step S31: Turn off the DC power supply and raise the ambient temperature of the test system to the target temperature T;
[0014] Step S32: After the target temperature T stabilizes, turn on the DC power supply and gradually apply a reverse bias voltage to the semiconductor device under test until the reverse bias voltage reaches and is maintained at the target voltage V.
[0015] Preferably, in step S32, during the gradual application of the reverse bias voltage, the real-time leakage current I2 of the semiconductor device under test is monitored. If I2 > nI0, the application of the bias voltage is stopped.
[0016] Preferably, the current mutation threshold coefficient n is a preset adjustable parameter, and the current mutation threshold coefficient n is set according to the type of semiconductor device under test, application scenario or test standard.
[0017] Preferably, in step S4, during the constant temperature and constant pressure test, the leakage current, ambient temperature, and bias voltage data of the semiconductor device under test are recorded at fixed time intervals.
[0018] Preferably, in step S4, the preset duration ranges from 1000 hours to 2000 hours.
[0019] Preferably, step S5 specifically includes:
[0020] Step S51: Turn off the DC power supply. After the ambient temperature of the test system cools down to the temperature under the standard atmospheric conditions, measure the final reverse leakage current I1.
[0021] Step S52: Compare and analyze the initial reverse leakage current I0 and the final reverse leakage current I1. If I1≤mI0 and the semiconductor device under test has no electrical breakdown or open circuit phenomenon, then the semiconductor device under test is determined to have passed the test.
[0022] Preferably, the degradation tolerance coefficient m is a preset adjustable parameter, and the degradation tolerance coefficient m is set according to the reliability requirements of the semiconductor device under test, the test duration, or industry standards.
[0023] Preferably, the target temperature T ranges from 175°C to 185°C.
[0024] Preferably, the target voltage V is in the range of 90% to 100% of the rated reverse voltage Vce of the semiconductor device under test.
[0025] Beneficial effects: By performing the heating and pressurization processes sequentially in steps, this invention effectively avoids the problems of drastic fluctuations in device internal resistance and surge current caused by the simultaneous application of temperature and voltage in traditional methods. This improves the accuracy of reverse leakage current monitoring data, reduces the risk of instantaneous device breakdown and damage to test equipment, and enhances the safety and reliability of high-temperature reverse bias tests under extreme high-stress conditions. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the method flow of the present invention;
[0027] Figure 2 This is a schematic diagram of step S3 of the present invention. Detailed Implementation
[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0029] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0030] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.
[0031] Reference Figure 1 This invention provides a method for high-temperature reverse bias testing of semiconductor devices, comprising:
[0032] Step S1: Preprocess the semiconductor device under test and record the initial reverse leakage current I0 of the semiconductor device under test under standard atmospheric conditions.
[0033] Step S2: Load the pre-processed semiconductor device under test into the test system;
[0034] Step S3: The semiconductor device under test in the test system is subjected to heating and pressurization operations in sequence to obtain the target temperature T and the target voltage V;
[0035] Step S4: At the target temperature T and the target voltage V, perform a constant temperature and constant voltage test on the semiconductor device under test for a preset duration.
[0036] Step S5: After the test is completed, record the final reverse leakage current I1 of the semiconductor device under test, and determine the pass / fail status of the semiconductor device under test based on the initial reverse leakage current I0 and the final reverse leakage current I1.
[0037] Specifically, in this embodiment of the invention, in order to address the problem that simultaneous heating and pressurization in traditional tests can easily lead to fluctuations in internal resistance and surge currents, the operation sequence of "first heating to the target temperature, and then gradually applying the target voltage" is clearly defined and strictly followed. This avoids the risk of data distortion and device / equipment damage caused by applying high voltage during drastic temperature changes, and achieves safe, reliable and accurate high-temperature reverse bias testing under high stress conditions.
[0038] The preprocessing in step S1 includes: screening the semiconductor devices to be tested and removing samples with physical defects such as appearance damage or pin deformation; then, under standard atmospheric conditions (such as room temperature 25°C), applying a low-voltage test voltage to the screened semiconductor devices, measuring and recording their initial reverse leakage current I0, which serves as a benchmark for subsequent performance degradation.
[0039] The loading operation in step S2 includes: fixing the pre-treated semiconductor device onto the insulating test fixture inside the high-temperature reverse bias test system and connecting the test circuit; it is necessary to carefully ensure that the pins of each device make good and reliable contact with the fixture contacts to prevent measurement errors caused by contact resistance or connection failure during the test.
[0040] As a preferred embodiment of the present invention, refer to Figure 2 Step S3 includes:
[0041] Step S31: Turn off the DC power supply and raise the ambient temperature of the test system to the target temperature T;
[0042] Step S32: After the target temperature T stabilizes, turn on the DC power supply and gradually apply a reverse bias voltage to the semiconductor device under test until the reverse bias voltage reaches and is maintained at the target voltage V.
[0043] Specifically, considering that the heating and pressurization processes are carried out simultaneously in traditional HTRB tests, the device will be subjected to high voltage when the temperature changes drastically and the internal thermal stress distribution is uneven, which can easily induce uncontrollable surge current, leading to distorted test data or even instantaneous device failure. In this embodiment of the invention, by strictly separating the heating and pressurization operations and executing them in sequence, the coupling effect of thermal shock and electrical shock is effectively isolated.
[0044] More specifically, applying high pressure when the temperature is unstable can easily lead to uneven thermal stress distribution and contact resistance drift, further reducing the repeatability and accuracy of the test and limiting the widespread application of high-stress HTRB testing. Therefore, in this embodiment of the invention, the heating phase is first ensured to be sufficient and stable. That is, with the DC power supply off, the ambient temperature is raised to the target temperature T and maintained at this temperature for 30 to 60 minutes, allowing the entire semiconductor device under test (including the chip, bonding wires, and packaging materials) to reach a uniform thermal equilibrium state and eliminate internal thermal gradients. After the target temperature T stabilizes, the pressure application operation is then performed, i.e., the DC power supply is turned on, and a reverse bias voltage is gradually applied to the target voltage V at a controlled rate.
[0045] In a preferred embodiment of the present invention, the target temperature T is in the range of 175°C to 185°C.
[0046] Specifically, in order to achieve stress acceleration while ensuring the effectiveness of the test and fully stimulate the potential failure modes of the device under extreme high-temperature conditions, the test temperature is set to 175°C to 185°C in this embodiment of the invention. This temperature range is significantly higher than the 150°C standard of the traditional HTRB test, which can greatly improve the thermal stress intensity on key parts such as the chip junction region, bonding interface and passivation layer, while ensuring that common packaging materials and structures do not experience atypical thermal failures. This effectively simulates and evaluates the long-term high-temperature tolerance and thermal stability of the device in harsh application environments such as new energy vehicles and industrial drives.
[0047] In a preferred embodiment of the present invention, the target voltage V is in the range of 90% to 100% of the rated reverse voltage Vce of the semiconductor device under test.
[0048] Specifically, in order to apply electrical stress to the maximum extent within a safe and controllable range, and to efficiently screen out early defects and design weaknesses when approaching the operating limits, in this embodiment of the invention, the test voltage is set to 90% to 100% of the device's rated reverse voltage Vce. Applying such a high proportion of the rated voltage aims to put extreme tests on the junction electric field strength, termination protection structure, and dielectric layer reliability of the device, effectively exposing material defects or process fluctuations that only appear when approaching the breakdown voltage.
[0049] Combined with the aforementioned high-temperature conditions, this high-voltage strategy constitutes a "highly accelerated" assessment of the device's reliability limits, significantly shortening the testing cycle. At the same time, thanks to the protection mechanism of step-by-step application and real-time monitoring, the high risk controllability of the testing process itself is ensured.
[0050] In a preferred embodiment of the present invention, in step S32, during the gradual application of the reverse bias voltage, the real-time leakage current I2 of the semiconductor device under test is monitored. If I2 > nI0, the application of the bias voltage is stopped.
[0051] Specifically, to prevent the risk of instantaneous overcurrent or breakdown caused by the activation of potential defects inside the device under high reverse bias, and to ensure the safety and traceability of the testing process, this embodiment of the invention introduces an intelligent interruption mechanism based on real-time leakage current I2 monitoring. The current surge threshold coefficient n is a preset adjustable parameter, and the current surge threshold coefficient n is set according to the type of semiconductor device under test, application scenario, or testing standard.
[0052] In this embodiment, the current mutation threshold coefficient n is preferably set to 10. When the system detects that the real-time leakage current I2 exceeds 10 times the initial reverse leakage current I0, it indicates that the device may have entered an abnormal conduction or near breakdown state. The system will immediately trigger the protection logic, automatically cut off the DC power supply output, stop the voltage application, and record the current voltage value, temperature and abnormal current data.
[0053] This mechanism not only effectively prevents chain reactions caused by the failure of a single device, protecting the test system and other parallel samples, but also provides clear electrical stress trigger points for subsequent failure analysis, enhancing the interpretability of test results and their engineering guidance value.
[0054] In a preferred embodiment of the present invention, in step S4, during the constant temperature and constant pressure test, the leakage current, ambient temperature and bias voltage data of the semiconductor device under test are recorded at fixed time intervals.
[0055] Specifically, in this embodiment of the invention, in order to achieve fine tracking and traceability analysis of the performance degradation process of devices under long-term, high-stress conditions, the system is set to automatically collect and record the real-time leakage current, the precise ambient temperature inside the test chamber, and the actual applied bias voltage value of each semiconductor device under test every 24 hours as a fixed cycle.
[0056] This systematic data recording mechanism can construct a complete time-series curve of the device aging process, which can be used to monitor the stability of the test process (such as whether the fluctuations in temperature and voltage are within the allowable tolerance range). More importantly, by analyzing the trend of leakage current change over time (such as whether there is a step increase, slow drift or sudden failure), it can effectively identify and distinguish reliability failure modes caused by different physical mechanisms such as material interface degradation, ion migration, and charge trap filling, providing key data support for evaluating the long-term life of the device and design optimization.
[0057] In a preferred embodiment of the present invention, in step S4, the preset duration ranges from 1000 hours to 2000 hours.
[0058] Specifically, in this embodiment of the invention, the duration of the isothermal and isobaric test is set to 1000 to 2000 hours. This time range is based on a comprehensive consideration of the accelerated lifespan model for typical applications of power semiconductor devices and industry reliability testing standards (such as JEDEC and AEC-Q101). Setting a lower limit of 1000 hours aims to ensure sufficient time for most long-term failure mechanisms induced by high temperature and high electric field (such as gate oxide breakdown over time, metal electromigration, and contact degradation) to fully manifest, thus completing the assessment of the device's basic long-term reliability. Extending the upper limit to 2000 hours provides the possibility of evaluating the ultra-long-term stability of devices under extremely harsh conditions and screening top-tier devices for applications with extremely high reliability requirements (such as aerospace and deep earth exploration). This time range covers typical needs from routine quality assessment to in-depth reliability research, achieving an effective balance between testing costs and evaluation depth.
[0059] In a preferred embodiment of the present invention, step S5 includes:
[0060] Step S51: Turn off the DC power supply. After the ambient temperature of the test system cools down to the temperature under the standard atmospheric conditions, measure the final reverse leakage current I1.
[0061] Step S52: Compare and analyze the initial reverse leakage current I0 and the final reverse leakage current I1. If I1≤mI0 and the semiconductor device under test has no electrical breakdown or open circuit phenomenon, then the semiconductor device under test is determined to have passed the test.
[0062] Specifically, to achieve an objective and standardized final assessment of the device's reliability status after the high-temperature reverse bias test, this embodiment of the invention strictly defines the test termination, condition recovery, and judgment criteria. First, after reaching the preset time, the DC power supply must be turned off to disconnect the bias voltage, avoiding unnecessary electrothermal coupling stress on the device due to temperature changes during cooling. Subsequently, the system under test (including the sample itself) is allowed to cool naturally or in a controlled manner and stabilize to the same standard atmospheric conditions as the initial measurement (e.g., room temperature 25°C). Under these stable conditions, the reverse leakage current of the device is remeasured and recorded as the final reverse leakage current I1, to eliminate the direct influence of temperature on the conductivity characteristics of semiconductor devices and ensure the uniformity of the evaluation benchmark.
[0063] Next, the final reverse leakage current I1 is quantitatively compared with the initial reverse leakage current I0 to determine the reliability of the semiconductor device under test. Specifically, the present invention sets a specific degradation tolerance coefficient m, which is a preset adjustable parameter, and the degradation tolerance coefficient m is set according to the reliability requirements of the semiconductor device under test, the test duration, or industry standards.
[0064] In this embodiment, the degradation tolerance coefficient m is preferably set to 5, i.e., the criterion is I1≤5I0. This criterion means that after long-term high-stress aging, the leakage current growth of the device is limited to within 5 times the initial value. This requirement not only tests the stability of the electrical parameters of the semiconductor device under extreme stress, but also indirectly reflects that its internal junction integrity, interface characteristics, and packaging sealing have not undergone catastrophic degradation.
[0065] Simultaneously, this criterion also requires a comprehensive judgment based on whether the semiconductor device has experienced a functional hard failure. That is, it must be confirmed that the device has not exhibited a failure mode that results in complete breakdown (short circuit) or open circuit, leading to a loss of basic functionality. Only when both conditions are met—"leakage current increment within the allowable range" (I1≤5I0) and "no functional hard failure"—can the semiconductor device under test be ultimately deemed to have passed this high-temperature reverse bias reliability test. This evaluation method, combining the examination of parameter degradation and functional status, constitutes a comprehensive and rigorous reliability qualification judgment system.
[0066] The following two specific examples illustrate in detail the application process and effects of the high-temperature reverse bias test method described in this invention on typical power semiconductor devices:
[0067] Example 1: High-temperature reverse bias test of a certain type of IGBT device (rated reverse voltage Vce = 1200V).
[0068] Five IGBT samples were selected, and the initial reverse leakage current I0 of the five IGBT samples was measured under standard atmospheric conditions at room temperature (25℃) and did not exceed 5μA. The initial reverse leakage current I0 of these five IGBT samples was recorded.
[0069] Load the IGBT sample onto the insulation test fixture in the test system and make the circuit connection to ensure a reliable connection.
[0070] Stepwise stress application was performed: First, with the DC power supply off, the ambient temperature was raised to 175°C and maintained for 40 minutes. After the temperature stabilized, the DC power supply was turned on, and a reverse bias voltage was gradually applied to 1080V (i.e., 90% Vce). During the application process, the leakage current was monitored in real time. Its value steadily increased to 12-15mA as the voltage increased, and no sudden increase of more than 10 times the initial reverse leakage current I0 was observed, indicating that there was no abnormality.
[0071] Under constant stress of T=175℃ and V=1080V, a constant temperature and constant pressure test was conducted for 1000 hours. During the test, the system automatically recorded data every 24 hours. The leakage current value remained stable in the range of 15-20mA, with no trend drift or step change observed.
[0072] After the test, the DC power supply was turned off, and the system was allowed to cool to room temperature. The final reverse leakage current I1 of all IGBT samples was then measured to be ≤5I0 (25μA). Furthermore, no hard failures such as electrical breakdown or open circuits were observed in any of the samples. Therefore, this batch of IGBT samples was deemed to have passed the high-temperature reverse bias reliability test.
[0073] Example 2: High-temperature reverse bias test of a certain type of SiC Schottky diode (rated reverse voltage Vce = 1400V)
[0074] Five diode samples were selected, and after pretreatment, the initial reverse leakage current I0 was measured at room temperature. All samples did not exceed 3μA. The initial reverse leakage current I0 of these five diode samples was recorded.
[0075] Load the diode sample onto the insulation test fixture in the test system and make the circuit connection to ensure a reliable connection.
[0076] Stress was applied in stages: First, the DC power supply was turned off, the temperature was raised to 185℃, and maintained stably for 60 minutes; after the temperature stabilized, the DC power supply was turned on, and a reverse bias voltage was gradually applied to 1400V (i.e., 100% Vce). During the pressurization process, the leakage current rose steadily to 10-15μA, with no abnormal sudden increases throughout the process.
[0077] Under extreme stress conditions of T=185℃ and V=1400V, a constant temperature and voltage test was conducted for up to 1500 hours. Regular monitoring data during this period showed that the leakage current remained stable at 15-20μA, demonstrating stable performance.
[0078] After the test was terminated, the samples were cooled to room temperature according to procedure and then retested. The final measured reverse leakage current I1 ≤ 5I0 (15μA) for all samples, and all samples showed good physical and electrical functionality. Therefore, this batch of SiC diode samples was deemed to have passed the test.
[0079] As demonstrated by the above embodiments, the test method provided by this invention, through the strict implementation of a step-by-step stress application procedure of "first heating and stabilizing, then pressurizing and monitoring," and the establishment of a clear real-time interruption mechanism and final judgment criteria, successfully conducted high-accelerated stress tests on two typical power devices, IGBTs and SiC diodes, at near or near their rated limits (90%-100% Vce, 175℃-185℃). Throughout the entire long-term test, the devices exhibited stable performance, the test was safe and controllable, and a clear reliability qualification judgment could be made based on quantified criteria (I1≤5I0 and no hard failure). This verifies that the method, while ensuring test safety and data accuracy, can effectively support high-intensity, high-standard long-term reliability assessment of power semiconductor devices.
[0080] In summary, this invention constructs a complete, safe, and accurate high-acceleration high-temperature reverse bias test scheme for semiconductor devices by implementing a step-by-step stress loading strategy of "heating first and then pressurizing", introducing a real-time leakage current monitoring interruption mechanism, executing a standardized data acquisition process, and adopting a final reliability determination method based on quantitative degradation criteria.
[0081] Compared with the prior art, the present invention has the following significant advantages:
[0082] This invention fundamentally avoids the risk of surge impact in the early stages of testing: by establishing and strictly implementing a step-by-step operation procedure of "first stabilizing the temperature, then gradually increasing the pressure," the initial coupling of thermal stress and electrical stress is effectively decoupled. This method completely eliminates the surge current generated by directly applying high voltage due to the rapid fluctuation of the device's internal resistance during drastic temperature changes, making the transition of the device from its initial state to the high-stress test state more smooth and controllable, thereby significantly reducing the risk of accidental device breakdown or damage to the test equipment due to instantaneous overcurrent.
[0083] This invention achieves reliable adaptation and safe application under extreme high-stress conditions: Addressing the increasingly stringent requirements of modern power semiconductor reliability assessments, including high-temperature (175-185°C) and high-voltage (90%-100% of rated voltage) applications, this invention ensures process stability under high accelerated stress conditions through precise and independent temperature and voltage control timing. This successfully solves the problem of equipment failure and test interruption easily induced by stress superposition when applying extremely high temperatures and voltages simultaneously using traditional methods, enabling safe and repeatable execution of ultra-high stress reliability testing.
[0084] This invention comprehensively improves the reliability and accuracy of the testing process and results data: By applying the test voltage only after the temperature has fully stabilized, it effectively suppresses the drift of contact resistance between the test fixture and the device pins caused by thermal expansion, ensuring the stability of the electrical connection. Simultaneously, combined with periodic standardized data recording, it ensures that the leakage current data monitored throughout the long-term test truly reflects the changes in the device's own characteristics, rather than fluctuations in the test system. This provides a high-precision, traceable data foundation for long-term reliability degradation analysis and lifespan assessment of the device.
[0085] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.
Claims
1. A method for high-temperature reverse bias testing of semiconductor devices, characterized in that, include: Step S1: Preprocess the semiconductor device under test and record the initial reverse leakage current I0 of the semiconductor device under test under standard atmospheric conditions. Step S2: Load the pre-processed semiconductor device under test into the test system; Step S3: The semiconductor device under test in the test system is subjected to heating and pressurization operations in sequence to obtain the target temperature T and the target voltage V; Step S4: At the target temperature T and the target voltage V, perform a constant temperature and constant voltage test on the semiconductor device under test for a preset duration. Step S5: After the test is completed, record the final reverse leakage current I1 of the semiconductor device under test, and determine the pass / fail status of the semiconductor device under test based on the initial reverse leakage current I0 and the final reverse leakage current I1.
2. The high-temperature reverse bias test method for semiconductor devices according to claim 1, characterized in that, Step S3 includes: Step S31: Turn off the DC power supply and raise the ambient temperature of the test system to the target temperature T; Step S32: After the target temperature T stabilizes, turn on the DC power supply and gradually apply a reverse bias voltage to the semiconductor device under test until the reverse bias voltage reaches and is maintained at the target voltage V.
3. The high-temperature reverse bias test method for semiconductor devices according to claim 2, characterized in that, In step S32, during the gradual application of the reverse bias voltage, the real-time leakage current I2 of the semiconductor device under test is monitored. If I2 > nI0, the application of the bias voltage is stopped.
4. The high-temperature reverse bias test method for semiconductor devices according to claim 3, characterized in that, The current surge threshold coefficient n is a preset adjustable parameter, and the current surge threshold coefficient n is set according to the type of semiconductor device under test, application scenario or test standard.
5. The high-temperature reverse bias test method for semiconductor devices according to claim 1, characterized in that, In step S4, during the constant temperature and constant pressure test, the leakage current, ambient temperature, and bias voltage data of the semiconductor device under test are recorded at fixed time intervals.
6. The high-temperature reverse bias test method for semiconductor devices according to claim 1, characterized in that, In step S4, the preset duration ranges from 1000 hours to 2000 hours.
7. The high-temperature reverse bias test method for semiconductor devices according to claim 1, characterized in that, Step S5 includes: Step S51: Turn off the DC power supply. After the ambient temperature of the test system cools down to the temperature under the standard atmospheric conditions, measure the final reverse leakage current I1. Step S52: Compare and analyze the initial reverse leakage current I0 and the final reverse leakage current I1. If I1≤mI0 and the semiconductor device under test has no electrical breakdown or open circuit phenomenon, then the semiconductor device under test is determined to have passed the test.
8. The high-temperature reverse bias test method for semiconductor devices according to claim 7, characterized in that, The degradation tolerance factor m is a preset adjustable parameter, and the degradation tolerance factor m is set according to the reliability requirements of the semiconductor device under test, the test duration, or industry standards.
9. The high-temperature reverse bias test method for semiconductor devices according to claim 1, characterized in that, The target temperature T ranges from 175℃ to 185℃.
10. The high-temperature reverse bias test method for semiconductor devices according to claim 1, characterized in that, The target voltage V is in the range of 90% to 100% of the rated reverse voltage Vce of the semiconductor device under test.