Linear voltage regulator with high power supply rejection ratio

Abstract

The invention provides a linear voltage regulator with a high power supply rejection ratio. The linear voltage regulator with the high power supply rejection ratio (LDO) comprises a power supply preprocessing module, a main amplification module, a reverse nested Miller compensation module, a power supply ripple introduction module and a power tube module. Through segmented processing, under the condition that the LDO low power supply voltage is 1V, power supply preprocessing is added to the main amplification module, and power supply ripples are introduced to the input end of a power tube, so that the problem that the full-band power supply rejection ratio is too poor is well solved. Meanwhile, the reverse nested Miller compensation module is utilized, the loop stability of the multi-stage circuit is guaranteed, the LDO high in power supply rejection ratio, low in power supply voltage and high in stability is obtained, and the application requirement of a system-level integrated circuit is met.

Description

Technical Field

[0001] This invention relates to the field of power management, and more particularly to a high power supply rejection ratio linear regulator. Background Technology

[0002] Low-dropout regulators (LDOs), as key modules in power management systems, are widely used in mobile devices, communication systems, sensor nodes, and various analog / mixed-signal integrated circuits. Their function is to provide a stable, low-noise supply voltage for subsequent sensitive circuits. Among the performance metrics of LDOs, the Power Supply Rejection Ratio (PSRR) is crucial, characterizing the LDO's ability to suppress noise or ripple at the input power supply. Especially in applications such as radio frequency (RF) circuits, high-precision data converters (ADCs / DACs), and phase-locked loops (PLLs), power supply noise can directly couple to the signal path, leading to severe degradation of system performance. Therefore, high PSRR LDO design is a hot research topic in both academia and industry. The PSRR performance of traditional LDOs mainly depends on the open-loop gain of the error amplifier in the low-frequency range, but drops sharply in the high-frequency range (typically exceeding the unity-gain bandwidth of the error amplifier). This is mainly because the parasitic capacitance of the power transistor gate provides a direct path for power supply noise to couple to the output. To improve high-frequency PSRR, an N-channel MOSFET is typically stacked on top of the LDO's output power transistor for isolation. However, this results in additional power consumption, reduced efficiency, and increased requirements on the power supply voltage. Under voltage conditions, it is difficult to achieve high loop gain and bandwidth to improve the power supply rejection ratio. Summary of the Invention

[0003] Based on this, the purpose of this invention is to propose a high power supply rejection ratio (PSRR) linear regulator, so as to achieve both high loop gain at low voltage and improved power supply rejection ratio at high frequency at low voltage.

[0004] To achieve the above objectives, this invention proposes a high power supply rejection ratio linear regulator, which includes a power supply preprocessing module, a main amplification module, an inverted nested Miller compensation module, a power supply ripple introduction module, and a power transistor module.

[0005] The power preprocessing module is used for:

[0006] It provides power to the main amplifier module, making the main amplifier module basically unaffected by power supply ripple and ensuring that the main amplifier module will not generate power supply ripple at the output.

[0007] The main amplification module is used for:

[0008] It receives the output voltage VOUT and the reference voltage VREF, amplifies the difference between the output voltage VOUT and the reference voltage VREF, and generates an error signal.

[0009] The reverse nested Miller compensation module is used for:

[0010] Pole splitting is used in circuits to separate the dominant pole from the two secondary poles to ensure the stability of the high power supply rejection ratio linear regulator loop.

[0011] The power ripple introduction module is used for:

[0012] The power supply ripple is copied 1:1 and transmitted to the power transistor module to eliminate the ripple introduced by the power transistor module and improve the power supply rejection ratio of the linear regulator.

[0013] The power transistor module is used for:

[0014] It receives the control signal output from the power ripple introduction module and is responsible for outputting current to the output terminal;

[0015] The power preprocessing module includes:

[0016] A first error amplifier (EA1), a first resistor (R1), and a first capacitor (C1) are configured. The power supply and ground of the first error amplifier (EA1) are connected to VDD and GND, respectively. The positive input of the first error amplifier (EA1) is connected to the second error amplifier (EA2) and then to the VREF terminal. The negative input of the first error amplifier (EA1) is connected to the source of the first NMOS transistor (MN1) and also to the power supply terminals of the second error amplifier (EA2) and the first transconductance amplifier (-GM). The output of the first error amplifier (EA1) is connected to one end of a resistor and the gate of the first NMOS transistor (MN1). The first resistor (R1) is connected to both the output of the first error amplifier (EA1) and one end of the first capacitor (C1). The other end of the first capacitor (C1) is connected to GND. The drain of the first NMOS transistor (MN1) is connected to VDD.

[0017] The main amplification module includes:

[0018] The second error amplifier (EA2) and the first transconductance amplifier (-GM) are connected together. The power supply terminals of the second error amplifier (EA2) and the first transconductance amplifier (-GM) are connected to the negative input terminal of the first error amplifier (EA1) and the source terminal of the first NMOS transistor (MN1). The positive input terminal of the second error amplifier (EA2) is connected to the positive input terminal of the first error amplifier (EA1) and connected to the VREF terminal. The negative input terminal of the second error amplifier (EA2) is connected to one end of the second resistor (R2) and the third resistor (R3). The ground terminal of the second error amplifier (EA2) is connected to GND. The output terminal of the second error amplifier (EA2) is connected to the input terminal of the first transconductance amplifier (-GM), one end of the second capacitor (C2), and one end of the third capacitor (C3). The ground terminal of the first transconductance amplifier (-GM) is connected to GND. The output terminal of the first transconductance amplifier (-GM) is connected to the input terminal of the first power supply ripple injection module and the other end of the second capacitor (C2).

[0019] The reverse nested Miller compensation module includes:

[0020] The second capacitor (C2) and the third capacitor (C3) are connected together, with one end of the second capacitor (C2) connected to one end of the third capacitor (C3) and connected to the output of the second error amplifier (EA2) and the input of the first transconductance amplifier (-GM). The other end of the second capacitor (C2) is connected to the output of the first transconductance amplifier (-GM), and the other end of the third capacitor (C3) is connected to the output VOUT. One end of the second resistor (R2) is connected to the drain of the first PMOS transistor (MP1).

[0021] The power ripple introduction module includes:

[0022] The first power supply ripple injection module has its input terminal connected to one end of the second capacitor (C2) and the output terminal of the first transconductance amplifier (-GM). The power supply terminal of the first power supply ripple injection module is connected to VDD, its ground terminal is connected to GND, and its output terminal is connected to the gate terminal of the first PMOS transistor (MP1).

[0023] The power transistor module includes:

[0024] The first PMOS transistor (MP1), the second resistor (R2), and the third resistor (R3) are connected as follows: the gate terminal of the first PMOS transistor (MP1) is connected to the output terminal of the first power supply ripple injection module; the source terminal of the first PMOS transistor (MP1) is connected to VDD; the drain terminal of the first PMOS transistor (MP1) is connected to one end of the third capacitor (C3) and one end of the second resistor (R2) to VOUT; the other end of the second resistor (R2) is connected to the third resistor (R3) and the negative input terminal of the second error amplifier (EA2); and the other end of the third resistor (R3) is connected to GND.

[0025] The above-described solution of the present invention has at least the following beneficial effects:

[0026] In this embodiment of the invention, the main amplifier circuit module, the power supply ripple introduction module, and the power transistor module are integrated into a four-stage amplification system, providing high loop gain and good low-frequency voltage rejection ratio at low voltage. Simultaneously, loop stability is ensured through a reverse-nested Miller compensation module. Considering the low-voltage condition, a power supply preprocessing module is used before the main amplifier to help eliminate the influence of power supply ripple, and the power supply ripple introduction module eliminates the influence of power supply ripple from the power transistors, providing a high power supply rejection ratio for the circuit at low and intermediate frequencies. Therefore, the final high power supply rejection ratio linear regulator exhibits high loop gain and high power supply rejection ratio at low voltage.

[0027] Other features and advantages of the invention will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above.

[0028] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0029] Figure 1 This is a circuit diagram of a high power supply rejection ratio linear regulator in a specific embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of the error amplifier circuit structure in a specific embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of the transconductance amplifier circuit structure in a specific embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of the power supply ripple introduction circuit structure in a specific embodiment of the present invention;

[0033] Figure 5This is a schematic diagram of the power supply rejection ratio simulation structure in a specific embodiment of the present invention;

[0034] Explanation of reference numerals in the attached figures

[0035] 1 Power Preprocessing Circuit

[0036] 2. Main Amplifier Circuit

[0037] 3. Power supply ripple introduction circuit

[0038] 4 Power transistor circuit

[0039] VDD power supply

[0040] GND ground terminal

[0041] INP positive input terminal

[0042] INN inverted input terminal

[0043] IN signal input terminal

[0044] VOUT output terminal Detailed Implementation

[0045] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0047] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and is not limited to the embodiments set forth herein.

[0048] Please see Figures 1 to 4 As shown, this invention proposes a high power supply rejection ratio linear regulator and introduces four specific circuit structures, including a power supply preprocessing circuit 1, a main amplifier circuit 2, a power supply ripple introduction circuit 3, and a power transistor circuit 4.

[0049] Specifically, the overall structure is as follows: Figure 1As shown, the reference signal VREF is connected to the positive input terminals of the first error amplifier (EA1) and the second error amplifier (EA2). The power supply and ground terminals of the first error amplifier (EA1) are connected to VDD and GND, respectively. The positive input terminal of the first error amplifier (EA1) and the second error amplifier (EA2) are connected to the VREF terminal. The negative input terminal of the first error amplifier (EA1) is connected to the source terminal of the first NMOS transistor (MN1) and to the power supply terminals of the second error amplifier (EA2) and the first transconductance amplifier (-GM). The output terminal of the first error amplifier (EA1) is connected to one end of the first resistor (R1) and the gate terminal of the first NMOS transistor (MN1). The other end of the first resistor (R1) is connected to one end of the first capacitor (C1), and the other end of the first capacitor (C1) is connected to GND. The drain terminal of the first NMOS transistor (MN1) is connected to VDD. The negative input terminal of the second error amplifier (EA2) is connected to one end of the second resistor (R2) and the third resistor (R3). The ground terminal of the second error amplifier (EA2) is connected to GND. The output terminal of the second error amplifier (EA2) is connected to the input terminal of the first transconductance amplifier (-GM), one end of the second capacitor (C2), and one end of the third capacitor (C3). The ground terminal of the first transconductance amplifier (-GM) is connected to GND. The output terminal of the first transconductance amplifier (-GM) is connected to the input terminal of the first power supply ripple injection module (Ripple Injection) and the other end of the second capacitor (C2). The other end of the second capacitor (C2) is connected to the output terminal of the first transconductance amplifier (-GM), and the other end of the third capacitor (C3) is connected to the output VOUT. One end of the second resistor (R2) is connected to the drain terminal of the first PMOS transistor (MP1). The input terminal of the first power supply ripple injection module (Ripple Injection) is connected to one end of the second capacitor (C2) and the output terminal of the first transconductance amplifier (-GM). The power supply terminal of the first power ripple injection module is connected to VDD, and the ground terminal is connected to GND. The output terminal of the first power ripple injection module is connected to the gate terminal of the first PMOS transistor (MP1). The gate terminal of the first PMOS transistor (MP1) is connected to the output terminal of the first power ripple injection module. The source terminal of the first PMOS transistor (MP1) is connected to VDD. The drain terminal of the first PMOS transistor (MP1) is connected to one end of the third capacitor (C3) and one end of the second resistor (R2) to VOUT. The other end of the second resistor (R2) is connected to the third resistor (R3) and the negative input terminal of the second error amplifier (EA2). The other end of the third resistor (R3) is connected to GND.

[0050] Specifically, in the error amplifier (EA), such as Figure 2 As shown, the source terminal of the first PMOS transistor (MP1) is connected to the power supply terminal. The gate terminal of the first PMOS transistor (MP1) is connected to the drain terminal of the first PMOS transistor (MP1), the gate terminal of the second PMOS transistor (MP2), and one end of the current mirror (I1). The source terminal of the second PMOS transistor (MP2) is connected to the power supply terminal. The drain terminal of the second PMOS transistor (MP2) is connected to the source terminals of the third PMOS transistor (MP3) and the fourth PMOS transistor (MP4). The gate terminal of the third PMOS transistor (MP3) is connected to the inverting input terminal. The drain of the third PMOS transistor (MP3) is connected to the drain of the first NMOS transistor (MN1), the gate of the first NMOS transistor (MN1), and the gate of the second NMOS transistor (MN2). The source of the first NMOS transistor (MN1) and the source of the second NMOS transistor (MN2) are connected to ground. The drain of the second NMOS transistor (MN2) is connected to the drain of the fourth PMOS transistor (MP4) and the output terminal VOUT. The gate of the fourth PMOS transistor (MP4) is connected to the inverting input terminal INN.

[0051] Specifically, in transconductance amplifier circuits (-GM), such as Figure 3 As shown, the gate terminal of the first PMOS transistor (MP1) is connected to the signal input terminal IN, the source terminal of the first PMOS transistor (MP1) is connected to the power supply terminal, the drain terminal of the first PMOS transistor (MP1) is connected to the drain terminal of the first NMOS transistor (MN1), the gate terminal of the first NMOS transistor (MN1) and the output terminal VOUT, and the source terminal of the first NMOS transistor (MN1) is connected to the ground terminal.

[0052] Specifically, in power supply ripple injection circuits, such as... Figure 4As shown, the signal input terminal IN is connected to the gate terminal of the second NMOS transistor (MN2). The source terminal of the second NMOS transistor (MN2) is connected to ground. The drain terminal of the second NMOS transistor (MN2) is connected to the gate terminal of the first NMOS transistor (MN1) and the source terminal of the third NMOS transistor (MN3). The source terminal of the first NMOS transistor (MN1) is connected to ground. The drain terminal of the first NMOS transistor (MN1) is connected to one end of the current mirror (I1) and the gate terminal of the third NMOS transistor (MN3). The other end of the current mirror (I1) is connected to the power supply terminal. The drain terminal of the third NMOS transistor (MN3) is connected to the first PMOS transistor (MP). The gate of the first PMOS transistor (MP1) is connected to the drain of the first PMOS transistor (MP1) and the gate of the second PMOS transistor (MP2). The source of the first PMOS transistor (MP1) is connected to the power supply. The source of the second PMOS transistor (MP2) is connected to one end of the current mirror (I2), the output terminal VOUT and the drain of the fourth NMOS transistor (MN4). The drain of the second PMOS transistor (MP2) is connected to one end of the current mirror (I3) and the gate of the fourth NMOS transistor (MN4). The other ends of the current mirror (I2) and the current mirror (I3) are connected to the power supply and the ground, respectively. The source of the fourth NMOS transistor (MN4) is connected to the ground.

[0053] Specifically, this circuit structure can greatly improve the circuit's resistance to power supply ripple, and has a very good power supply rejection ratio, such as... Figure 5 As shown, under different process angles, its worst low-frequency power rejection ratio is as high as 104dB, and its worst mid-to-high frequency power rejection ratio is as high as 46dB.

[0054] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A high power supply rejection ratio linear regulator, characterized in that, The high power supply rejection ratio linear regulator includes a power supply preprocessing module, a main amplification module, an inverted nested Miller compensation module, a power supply ripple introduction module, and a power transistor module. The power preprocessing module is used for: It provides power to the main amplifier module, making the main amplifier module basically unaffected by power supply ripple and ensuring that the main amplifier module will not generate power supply ripple at the output. The main amplification module is used for: It receives the output voltage VOUT and the reference voltage VREF, amplifies the difference between the output voltage VOUT and the reference voltage VREF, and generates an error signal. The reverse nested Miller compensation module is used for: Pole splitting is used in circuits to separate the dominant pole from the two secondary poles to ensure the stability of the high power supply rejection ratio linear regulator loop. The power ripple introduction module is used for: The power supply ripple is copied 1:1 and transmitted to the power transistor module to eliminate the ripple introduced by the power transistor module and improve the power supply rejection ratio of the LDO. The power transistor module is used for: It receives the control signal output from the power ripple introduction module and is responsible for outputting current to the output terminal.

2. The high power supply rejection ratio linear regulator according to claim 1, characterized in that, The power preprocessing module includes: The system comprises a first error amplifier (EA1), a first resistor (R1), and a first capacitor (C1). The power supply and ground of the first error amplifier (EA1) are connected to VDD and GND, respectively. The positive input of the first error amplifier (EA1) is connected to the second error amplifier (EA2) and then to the VREF terminal. The negative input of the first error amplifier (EA1) is connected to the source of the first NMOS transistor (MN1) and also to the power supply of the second error amplifier (EA2) and the first transconductance amplifier (-GM). The output of the first error amplifier (EA1) is connected to one end of the first resistor (R1) and the gate of the first NMOS transistor (MN1). The other end of the first resistor (R1) is connected to one end of the first capacitor (C1), and the other end of the first capacitor (C1) is connected to GND. The drain of the first NMOS transistor (MN1) is connected to VDD.

3. A high power supply rejection ratio linear regulator according to claim 1, characterized in that, The main amplification module includes: The second error amplifier (EA2) and the first transconductance amplifier (-GM) are connected together. The power supply terminals of the second error amplifier (EA2) and the first transconductance amplifier (-GM) are connected to the negative input terminal of the first error amplifier (EA1) and the source terminal of the first NMOS transistor (MN1). The positive input terminal of the second error amplifier (EA2) is connected to the positive input terminal of the first error amplifier (EA1) and connected to the VREF terminal. The negative input terminal of the second error amplifier (EA2) is connected to one end of the second resistor (R2) and the third resistor (R3). The ground terminal of the second error amplifier (EA2) is connected to GND. The output terminal of the second error amplifier (EA2) is connected to the input terminal of the first transconductance amplifier (-GM), one end of the second capacitor (C2), and one end of the third capacitor (C3). The ground terminal of the first transconductance amplifier (-GM) is connected to GND. The output terminal of the first transconductance amplifier (-GM) is connected to the input terminal of the first power supply ripple injection module and the other end of the second capacitor (C2).

4. A high power supply rejection ratio linear regulator according to claim 1, characterized in that, The reverse nested Miller compensation module includes: The second capacitor (C2) and the third capacitor (C3) are connected together, with one end of the second capacitor (C2) connected to one end of the third capacitor (C3) and connected to the output of the second error amplifier (EA2) and the input of the first transconductance amplifier (-GM). The other end of the second capacitor (C2) is connected to the output of the first transconductance amplifier (-GM), and the other end of the third capacitor (C3) is connected to the output VOUT. One end of the second resistor (R2) is connected to the drain of the first PMOS transistor (MP1).

5. A high power supply rejection ratio linear regulator according to claim 1, characterized in that, The power ripple introduction module includes: The first power supply ripple injection module has its input terminal connected to one end of the second capacitor (C2) and the output terminal of the first transconductance amplifier (-GM). The power supply terminal of the first power supply ripple injection module is connected to VDD, its ground terminal is connected to GND, and its output terminal is connected to the gate terminal of the first PMOS transistor (MP1).

6. A high power supply rejection ratio linear regulator according to claim 1, characterized in that, The power transistor module includes: The first PMOS transistor (MP1), the second resistor (R2), and the third resistor (R3) are connected as follows: the gate terminal of the first PMOS transistor (MP1) is connected to the output terminal of the first power supply ripple injection module; the source terminal of the first PMOS transistor (MP1) is connected to VDD; the drain terminal of the first PMOS transistor (MP1) is connected to one end of the third capacitor (C3) and one end of the second resistor (R2) to VOUT; the other end of the second resistor (R2) is connected to the third resistor (R3) and the negative input terminal of the second error amplifier (EA2); and the other end of the third resistor (R3) is connected to GND.

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