Reference voltage circuit and DCDC converter

Abstract

The invention provides a reference voltage circuit and a DCDC converter, and relates to the technical field of semiconductors. The reference voltage circuit comprises a band-gap reference module and a feedback module, and the feedback module is configured to feed back a voltage balance signal to the band-gap reference module, so that the band-gap reference module outputs an initial reference voltage based on the voltage balance signal; the dynamic element matching switch network is configured to periodically switch the connection relation of mismatched devices in the band-gap reference module based on the accessed dynamic switching signal; the feedback module is further configured to access a chopping signal and modulate the detuning of the feedback module to a high frequency band; the low-pass filtering module is configured to access an initial reference voltage and perform low-pass filtering on the initial reference voltage. According to the technical scheme, the output precision and the temperature stability of the reference voltage can be improved, and the application requirement of a high-precision circuit can be met.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a reference voltage circuit and a DC-DC converter. Background Technology

[0002] A bandgap reference (BG) is a circuit that provides a stable voltage (or current) reference unaffected by temperature, power supply voltage, and process variations. It is a core module of analog integrated circuits. The accuracy of a bandgap reference (BG) is affected by the matching degree of various components in the circuit and the offset of operational amplifiers. Although the offset of operational amplifiers in the circuit can be optimized by chopping, it is still difficult to meet the reference voltage requirements of high-precision analog circuits.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this disclosure is to provide a reference voltage circuit and a DC-DC converter, which at least to some extent overcome the problem that bandgap reference sources in related technologies cannot meet the reference voltage requirements of high-precision analog circuits.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, a reference voltage circuit is provided, comprising: a bandgap reference module and a feedback module electrically connected, the feedback module being configured to feed back a voltage balance signal to the bandgap reference module so that the bandgap reference module outputs an initial reference voltage based on the voltage balance signal; a dynamic element matching switch network connected to the bandgap reference module and configured to periodically switch the connection relationship of mismatched devices in the bandgap reference module based on an accessed dynamic switching signal; the feedback module being further configured to access a chopper signal used to modulate the offset of the feedback module to a high frequency band, one period of the dynamic switching signal including multiple periods of the chopper signal; and a low-pass filter module configured to access the initial reference voltage and perform low-pass filtering on the initial reference voltage.

[0007] In one embodiment of this disclosure, the bandgap reference module and the feedback module have a first connection point and a second connection point. The feedback module includes: a first resistor and a second resistor having a common connection point, one of the first resistor and the second resistor being connected to the first connection point and the other being connected to the second connection point; an operational amplifier, the two input terminals of which are respectively connected to the first connection point and the second connection point; the voltage balance signal includes a first current flowing through the first resistor and a second current flowing through the second resistor; the operational amplifier is configured to make the first current and the second current equivalent based on negative feedback operation; wherein the chopping signal is configured to switch the first resistor to be connected to the first connection point and switch the second resistor to be connected to the second connection point, or switch the first resistor to be connected to the second connection point and switch the second resistor to be connected to the first connection point.

[0008] In one embodiment of this disclosure, the mismatch device in the bandgap reference module includes: a plurality of first bipolar transistors connected to a common emitter; a second bipolar transistor connected to the common base of the plurality of first bipolar transistors, and the initial reference voltage is output at the common base terminal; one of the common emitter terminal of the first bipolar transistor and the emitter terminal of the second bipolar transistor is connected to a third connection point, and the other is connected to a fourth connection point; wherein, the dynamic switching signal includes a first set of dynamic switching signals, the first set of dynamic switching signals being used to switch the collector of the second bipolar transistor to be connected to the first connection point, the collector of the first bipolar transistor to be connected to the second connection point, or to switch the collector of the second bipolar transistor to be connected to the second connection point, and to switch the collector of any one of the first bipolar transistors to be connected to the first connection point.

[0009] In one embodiment of this disclosure, the first bipolar transistor and the second bipolar transistor are configured as the same transistor.

[0010] In one embodiment of this disclosure, the switch network includes a first switch network comprising: a first group of switch components connected in parallel, wherein a first end of the first group of switch components is connected to the collectors of the plurality of first bipolar transistors and the collectors of the second bipolar transistors, and a second end of the first group of switch components is connected to the first connection point; a second group of switch components connected in parallel, wherein a first end of the second group of switch components is connected to the collectors of the plurality of first bipolar transistors and the collectors of the second bipolar transistors, and a second end of the second group of switch components is connected to the second connection point; and a third group of switch components connected in parallel, wherein a first end of the third group of switch components is connected to the emitters of the plurality of first bipolar transistors and the emitters of the second bipolar transistors, and a second end of the third group of switch components is connected to the third connection point; A fourth set of switching components is connected in parallel. The first end of the fourth set of switching components is connected to the emitter of the plurality of first bipolar transistors and the emitter of the second bipolar transistors in a one-to-one correspondence. The second end of the fourth set of switching components is connected to the fourth connection point.

[0011] In one embodiment of this disclosure, the first set of dynamic switching signals includes a first number of clock signals with sequentially shifted phases, configured to access the control terminals of corresponding switches in the first switching network. The first number is the same as the number of the first bipolar transistor and the second bipolar transistor, and the number of switches in each group of switching components in the first switching network.

[0012] In one embodiment of this disclosure, the mismatch device in the bandgap reference module further includes: a fourth resistor connected in series and a plurality of third resistors, wherein the plurality of third resistors and the fourth resistor have a fifth connection point, and one of the plurality of third resistors is connected between the third connection point and the fourth connection point, wherein the dynamic switching signal includes a second set of dynamic switching signals, the second set of dynamic switching signals being used to sequentially configure the plurality of third resistors to be connected to the emitter of the first bipolar transistor and the emitter of the second bipolar transistor, respectively.

[0013] In one embodiment of this disclosure, the switch network further includes a second switch network, the second switch network including: a branch switching switch assembly configured to sequentially connect one of the plurality of third resistors to the branch between the third connection point and the fourth connection point based on the second set of dynamic exchange signals; and a series path switch assembly configured to control the portions of the plurality of third resistors not connected to the branch to be connected in series sequentially and connected to the path between the fourth connection point and the fifth connection point based on the second set of dynamic exchange signals.

[0014] In one embodiment of this disclosure, the branch switching assembly includes: a first sub-switch group configured to control a first end of a target resistor among the plurality of third resistors to be connected to the third connection point; a second sub-switch group configured to control a second end of the target resistor to be connected to the fourth connection point; and a third sub-switch group configured to connect one of the third resistors adjacent to the target resistor to the fourth connection point.

[0015] In one embodiment of this disclosure, the series path switching assembly includes: a fourth sub-switch group configured to control communication between a first terminal of the third resistor not connected to a branch and a second terminal of a preceding adjacent resistor; a fifth sub-switch group configured to control communication between a second terminal of the third resistor not connected to a branch and a first terminal of a subsequent adjacent resistor; a sixth sub-switch group and a seventh sub-switch group for configuring additional series paths between adjacent third resistors not connected to branches; and an eighth sub-switch group configured to control communication between the second terminal of the terminal resistor among the plurality of third resistors and the fifth connection point.

[0016] In one embodiment of this disclosure, the second set of dynamic switching signals includes a second number of clock signals with sequentially shifted phases, configured to access the control terminals of corresponding switches in the second switching network, wherein the second number is the same as the number of the third resistors.

[0017] In one embodiment of this disclosure, the feedback module includes: a first chopper switch, the input terminals of the first chopper switch being connected to the first resistor and the second resistor respectively, and the output terminals of the first chopper switch being connected to the first connection point and the second connection point respectively.

[0018] In one embodiment of this disclosure, the feedback module further includes: a second chopper switch, the input terminals of which are respectively connected to the first connection point and the second connection point, and the output terminals of which are respectively connected to the first input terminal and the second input terminal of the operational amplifier; and a third chopper switch, the input terminals of which are respectively connected to the first output terminal and the second output terminal of the operational amplifier, and the output terminals of which are respectively connected to the output terminal and the positive bias voltage terminal of the operational amplifier.

[0019] In one embodiment of this disclosure, the phase offset between adjacent signals in the dynamic exchange signal corresponds to half a period of the chop signal.

[0020] In one embodiment of this disclosure, switching the connection relationship is adapted to convert the mismatch error of the mismatched device into a first group of high-frequency noise; the offset modulation to the high-frequency band is adapted to obtain a second group of high-frequency noise, so that the first group of high-frequency noise and the second group of high-frequency noise can be filtered out by the low-pass filter module.

[0021] According to another aspect of this disclosure, a DC-DC converter is provided, comprising: the reference voltage circuit provided in the above embodiments.

[0022] The voltage conversion scheme provided by the embodiments of this disclosure configures a dynamic element matching switch network for the bandgap reference module to receive dynamic exchange signals and inputs a chopper signal to the feedback signal. By combining the dynamic element matching switch network with chopper processing, the error of the mismatched device in the bandgap reference module can be converted into a first group of high-frequency noise using the dynamic element matching switch network, and the offset of the feedback module can be modulated into a second group of high-frequency noise using the chopper signal. Combined with the timing coordination mechanism that includes multiple chopper signal cycles within one dynamic exchange signal cycle, both types of high-frequency noise can be efficiently filtered out by the same low-pass filter module, ultimately suppressing the error source of the bandgap reference. This improves the output accuracy and temperature stability of the reference voltage, thereby helping to meet the application requirements of high-precision circuits.

[0023] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0024] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 A schematic diagram of a reference voltage circuit in the related art is shown; Figure 2 A schematic block diagram of a reference voltage circuit according to an embodiment of the present disclosure is shown; Figure 3 A schematic diagram of a reference voltage circuit according to an embodiment of this disclosure is shown; Figure 4 A schematic diagram of another reference voltage circuit according to an embodiment of this disclosure is shown; Figure 5 A schematic diagram of yet another reference voltage circuit according to an embodiment of this disclosure is shown; Figure 6 This diagram illustrates a timing sequence of a combination of a chopping signal and a dynamic switching signal in an embodiment of this disclosure. Figure 7 A schematic diagram of yet another reference voltage circuit according to an embodiment of this disclosure is shown; Figure 8 A schematic diagram of a second switching network according to an embodiment of this disclosure is shown; Figure 9A A signal schematic diagram of a chopper switch according to an embodiment of the present disclosure is shown; Figure 9B A schematic diagram of the structure of a chopper switch according to an embodiment of the present disclosure is shown; Figure 10A A schematic diagram of an operational amplifier according to an embodiment of the present disclosure is shown; Figure 10B A schematic diagram of one of the first group of chopper switches in an embodiment of this disclosure is shown; Figure 10C A schematic diagram of another of the first group of chopper switches in an embodiment of this disclosure is shown; Figure 11A A schematic diagram of an operational amplifier receiving a chopped signal is shown in an embodiment of this disclosure; Figure 11B An operational amplifier in an embodiment of this disclosure is shown receiving another... Figure 11B A schematic diagram of an operational amplifier receiving a chopped signal is shown in an embodiment of this disclosure. Detailed Implementation

[0026] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0027] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0028] A bandgap reference (BG) is a circuit that provides a stable voltage (or current) reference unaffected by temperature, power supply voltage, and process variations. It is a core module in analog integrated circuits (such as DC-DC converters and analog-to-digital / digital-to-analog converters). However, in practical applications, the accuracy of a bandgap reference is susceptible to various error factors, including: the input offset voltage of the operational amplifier, which can disrupt the ideal distribution of current and voltage in the reference circuit, directly causing the output to deviate from the design value; the proportional error introduced by the process mismatch of the internal resistors (such as voltage divider resistors and load resistors) of the bandgap reference module, which can also affect the voltage division accuracy of the reference voltage; and the characteristic mismatch of bipolar junction transistors (BJTs), which can disrupt temperature drift complementarity, further reducing the stability of the reference output.

[0029] Figure 1 This diagram illustrates a common bandgap reference source circuit in related technologies. By controlling the negative feedback of the operational amplifier BG_OP, PMOS current mirrors M1 and M2 are made to match the current in the R1-Q1 branch and the R2-Q2 branch. Utilizing the difference in emitter area between the multi-emitter transistor Q1 and the single-emitter transistor Q2 (with an area ratio of M:1), a positive temperature coefficient thermal voltage difference is generated. Combined with the negative temperature coefficient base-emitter voltage of Q2, the positive and negative temperature drifts are complementaryly canceled by adjusting the voltage divider of resistors R3 and R4, thereby outputting a stable reference voltage.

[0030] The main factors affecting the accuracy of this reference source circuit include: the matching degree of resistors R1 and R2; the offset of operational amplifier BG_OP; the matching degree of Q1 and Q2; and the matching degree of R3 and R4. Among these, the offset of the operational amplifier is usually the main factor affecting the accuracy of BG. To improve the accuracy of BG, BG_OP is usually chopping to significantly reduce the impact of BG_OP offset on the accuracy of BG. However, for applications requiring very high BG accuracy, this operation alone is insufficient to obtain a satisfactory BG.

[0031] Although a single chopper switch is used to suppress a certain type of error (such as suppressing only op-amp offset or single resistor mismatch), it is difficult to reduce the impact of at least two types of errors at the same time. Furthermore, the periodic design of a single chopper cannot achieve the reverse superposition and cancellation of multiple error sources, resulting in limited error suppression effect and difficulty in meeting the reference voltage requirements of high-precision analog circuits.

[0032] Therefore, there is an urgent need for a reference voltage circuit with better error suppression performance.

[0033] like Figure 2As shown, a reference voltage circuit according to an embodiment of the present disclosure includes: a bandgap reference module 202 and a feedback module 204 electrically connected. The feedback module is configured to feed back a voltage balance signal to the bandgap reference module so that the bandgap reference module outputs an initial reference voltage based on the voltage balance signal.

[0034] The dynamic element matching switch network 206, connected to the bandgap reference module, is configured to periodically switch the connection relationships of mismatched devices in the bandgap reference module based on the accessed dynamic switching signal.

[0035] The switching of the connection relationship is adapted to convert the mismatch error of the mismatched device into a first set of high-frequency noise.

[0036] The feedback module is also configured to receive a chopper signal, which is used to modulate the offset of the feedback module to a high frequency band. A cycle of a dynamic switching signal includes multiple cycles of the chopper signal.

[0037] Among them, the offset modulation to the high-frequency band is suitable for obtaining the second set of high-frequency noise.

[0038] In some embodiments, Dynamic Element Matching (DEM) is used to eliminate device mismatch errors in a circuit. By periodically switching the connection relationship of multiple devices of the same type through a switching network, the device mismatch error can be averaged over time, which is equivalent to converting static mismatch into high-frequency noise, which can then be filtered out by low-pass filtering to improve circuit accuracy.

[0039] The dynamic switching signal is a clock control signal that controls the dynamic element matching DEM switching network. It can periodically switch the connection relationship of mismatched devices so that the static mismatch of the devices is averaged over time.

[0040] In some embodiments, the mismatched device includes a bipolar transistor and / or resistor in a reference voltage circuit, and a switching network and corresponding dynamic switching signal are configured for the mismatched device, i.e., a DEM is performed on the adapter.

[0041] In some embodiments, the bandgap reference module is used to generate an initial reference voltage and may include multiple sets of bipolar transistors that can be interchanged in their connection positions and a first set of resistors. Through the physical characteristics of the bipolar transistors and the voltage division of the resistors, a stable initial reference voltage that does not change with temperature can be generated.

[0042] In some embodiments, the dynamic element matching switch network may include multiple sets of switch components. The control terminal of the switch component is connected to a dynamic switching signal, which can periodically switch the connection relationship between different transistors, different resistors and a specified node according to the timing instructions of the dynamic switching signal, and convert the static mismatch error of transistors and resistors into high-frequency noise.

[0043] In some embodiments, the feedback module is a closed-loop control unit for precise operation of the bandgap reference. It may include an operational amplifier with chopping function, a chopper switch, and a corresponding second set of resistors. It outputs a voltage balance signal through negative feedback to force the collector voltages of the transistors in the bandgap reference module to be equal, so as to ensure current ratio matching. At the same time, it receives the chopping signal and periodically switches the connection relationship between the second set of resistors and the operational amplifier to modulate the DC offset of the operational amplifier into a high-frequency signal.

[0044] The low-pass filter module 208 is configured to connect to the initial reference voltage and perform low-pass filtering on the initial reference voltage to filter out the first group of high-frequency noise and the second group of high-frequency noise and output the reference voltage.

[0045] In some embodiments, since the target reference in the initial reference voltage has low-frequency characteristics, while the periodic error signal generated by nested chopping is a high-frequency fluctuation component, by setting a specific cutoff frequency in the low-pass filter module LPF, the low-frequency target reference component is allowed to pass smoothly, while the high-frequency periodic error signal is attenuated and suppressed, thereby separating a reference voltage output with higher accuracy.

[0046] In some embodiments, an integrator can be used instead of a low-pass filter module to offset the cumulative effects of periodic errors through integration.

[0047] In some embodiments, a phase-locked loop (PLL) synchronous filter circuit may also be used to specifically filter out error signals based on the clock frequency of the chopper switch.

[0048] In this embodiment, by configuring a dynamic element matching switch network for the bandgap reference module to receive dynamic exchange signals and inputting a chopper signal to the feedback signal, the dynamic element matching switch network is combined with chopper processing. This allows the dynamic element matching switch network to convert the error of mismatched devices in the bandgap reference module into a first group of high-frequency noise, and the chopper signal to modulate the offset of the feedback module into a second group of high-frequency noise. Combined with a timing coordination mechanism that includes multiple chopper signal cycles within a dynamic exchange signal cycle, both types of high-frequency noise can be efficiently filtered out by the same low-pass filter module. Ultimately, this suppresses the error source of the bandgap reference, improves the output accuracy and temperature stability of the reference voltage, and thus helps meet the application requirements of high-precision circuits.

[0049] like Figure 3As shown, in one embodiment of this disclosure, a first connection point and a second connection point are provided between the bandgap reference module and the feedback module. The feedback module includes: a first resistor R1 and a second resistor R2 having a common connection point, one of the first resistor R1 and the second resistor R2 being connected to the first connection point and the other being connected to the second connection point; an operational amplifier BG_OP, the two input terminals of which are respectively connected to the first connection point and the second connection point; a voltage balance signal including a first current output by the first resistor R1 and a second current output by the second resistor R2; the operational amplifier BG_OP is configured to make the first current and the second current equivalent based on negative feedback operation, that is, the difference between the first current and the second current is within the range allowed by process error or design error.

[0050] The chopping signal is configured to switch the first resistor R1 to the first connection point and the second resistor R2 to the second connection point, or to switch the first resistor R1 to the second connection point and the second resistor R2 to the first connection point, such as... Figure 3 and Figure 4 As shown.

[0051] In some embodiments, the operational amplifier BG_OP connects its two input terminals to a first connection point and a second connection point respectively through a negative feedback loop, forcing the first current output by the first resistor R1 to be equivalent to the second current output by the second resistor R2, thereby generating a voltage balance signal that is fed back to the bandgap reference module. This ensures that the operating current of the transistors in the bandgap reference module matches the device area and that the initial reference voltage is generated accurately. Furthermore, the chopping signal periodically switches the connection relationships between the first resistor R1 and the second resistor R2 and the first and second connection points respectively. For example, the first resistor R1 is connected to the first connection point and the second resistor R2 is connected to the second connection point, and then the connection is switched to the first resistor R1 being connected to the second connection point and the second resistor R2 being connected to the first connection point, so as to modulate the DC offset voltage of the operational amplifier BG_OP into high-frequency noise.

[0052] In this embodiment, the current of the first resistor R1 and the second resistor R2 is kept consistent through the negative feedback current balancing mechanism to ensure the basic accuracy of the initial reference voltage. At the same time, the dynamic switching of the resistor connection relationship by the chopping signal helps to suppress the DC offset error of the operational amplifier and reduce the voltage deviation introduced by the feedback module. Combined with the DEM processing and low-pass filtering of the bandgap reference module, multi-dimensional suppression of device mismatch error and operational amplifier offset error is achieved.

[0053] In one embodiment of this disclosure, the mismatch device in the bandgap reference module includes: a plurality of first bipolar transistors connected to a common emitter; a second bipolar transistor connected to the common base of the plurality of first bipolar transistors and having an initial reference voltage applied at the common base terminal; one of the common emitter terminal of the first bipolar transistor and the emitter terminal of the second bipolar transistor is connected to a third connection point, and the other is connected to a fourth connection point.

[0054] like Figure 3 As shown, the first bipolar transistors with multiple common emitter connections may include transistors Q0 to Q7, and the second bipolar transistor is transistor Q8.

[0055] In some embodiments, the connection of multiple first bipolar transistors with their common emitter and second bipolar transistors with their common base can generate a negative temperature coefficient Vbe and a positive temperature coefficient ΔVbe. By connecting their emitters to a third connection point and a fourth connection point, and by alternately connecting these two points to voltage divider resistors of the same resistance value, ΔVbe is converted into a positive temperature coefficient voltage, which is then superimposed on Vbe to achieve temperature compensation.

[0056] The dynamic switching signal includes a first set of dynamic switching signals, which are used to switch the collector of the second bipolar transistor to be connected to the first connection point, and the collector of the first bipolar transistor to be connected to the second connection point, or to switch the collector of the second bipolar transistor to be connected to the second connection point, and to switch the collector of any first bipolar transistor to be connected to the first connection point.

[0057] In some embodiments, a DEM operation is performed based on the first set of dynamic switching signals, that is, the access positions of transistors Q0 to Q7 and transistor Q8 are sequentially swapped. The circuit after the access positions of Q0 and Q8 are swapped is as follows: Figure 4 As shown.

[0058] In some embodiments, the common-emitter first bipolar transistor and the common-base second bipolar transistor complement each other through the characteristics of negative temperature drift Vbe and positive temperature drift ΔVbe, thus constructing a temperature-stable voltage base. At the same time, the dynamic switching signal can also control the third and fourth connection points to alternately connect to different resistors, so that the mismatch error of different resistors periodically participates in the circuit, converting static mismatch into high-frequency noise. The superimposed voltage not only achieves temperature compensation, but also reduces the impact of resistor mismatch through dynamic switching, providing conditions for subsequent filtering to output a high-precision reference voltage.

[0059] In this embodiment, the complementary relationship between the negative temperature coefficient Vbe and the positive temperature coefficient ΔVbe is achieved through the common emitter connection of the first bipolar transistor and the common base connection of the first bipolar transistor and the second bipolar transistor. This cancels out most of the temperature drift at the circuit topology level, ensuring the basic temperature stability of the initial reference voltage. The dynamic switching method of connecting different resistors with the same resistance value to the third and fourth connection points in turn breaks the fixed influence of single resistor mismatch error. It transforms the static process deviation of the resistor into high-frequency fluctuations that change with the switching frequency. This not only avoids introducing additional temperature drift but also adapts to the subsequent low-pass filter module. It can reduce the voltage error caused by resistor mismatch without sacrificing temperature stability, achieving the dual gain of temperature drift suppression and mismatch error elimination.

[0060] In one embodiment of this disclosure, the first bipolar transistor and the second bipolar transistor are configured as the same transistor.

[0061] In this embodiment, transistors of the same model have consistent electrical and temperature response characteristics, ensuring that the base-emitter voltage Vbe of both transistors is determined solely by the difference in emitter junction current density, rather than by parameter deviations of the transistors themselves. This makes the compensation ratio between the positive temperature coefficient ΔVbe and the negative temperature coefficient Vbe more stable, preventing new temperature drift or voltage deviations from being introduced due to inconsistent transistor characteristics. At the same time, the mismatch error distribution of the same transistors is more uniform during the periodic switching of the dynamic element matching switching network, which is more conducive to converting it into high-frequency noise through time averaging, and further improving the output accuracy of the reference voltage.

[0062] In one embodiment of this disclosure, the switching network includes a first switching network, which includes: The first set of switching components is connected in parallel. The first end of the first set of switching components is connected to the collectors of multiple first bipolar transistors and the collectors of second bipolar transistors in a one-to-one correspondence. The second end of the first set of switching components is connected to the first connection point.

[0063] In some embodiments, taking an example having eight first bipolar transistors (Q0-Q7) and one second bipolar transistor Q8, the first set of switching components may include nine parallel independent switches, the first end of each switch being connected to the collector of Q0~Q8, i.e., VCQ<8:0>, and the second ends of the nine switches being connected to the second connection point VE2.

[0064] The second set of switching components is connected in parallel. The first end of the second set of switching components is connected to the collectors of the multiple first bipolar transistors and the collectors of the second bipolar transistors in a one-to-one correspondence. The second end of the second set of switching components is connected to the second connection point.

[0065] In some embodiments, the second set of switch components may include nine independent switches connected in parallel, with the first end of each switch corresponding to the collector of Q0 to Q8, i.e., VCQ<8:0>, and the second ends of the nine switches are connected to the first connection point VE1.

[0066] The third set of switching components is connected in parallel. The first end of the third set of switching components is connected to the emitters of the multiple first bipolar transistors and the emitters of the second bipolar transistors in a one-to-one correspondence. The second end of the third set of switching components is connected to the third connection point.

[0067] In some embodiments, the third set of switch components may include nine independent switches connected in parallel, with the first end of each switch corresponding to the emitter of Q0 to Q8, i.e., VEQ<8:0>, and the second ends of the nine switches are connected to the fourth connection point VE4.

[0068] The fourth set of switching components is connected in parallel. The first end of the fourth set of switching components is connected to the emitters of multiple first bipolar transistors and the emitters of second bipolar transistors in a one-to-one correspondence. The second end of the fourth set of switching components is connected to the fourth connection point.

[0069] In some embodiments, the fourth set of switch components may include nine independent switches connected in parallel. The first end of each switch is also connected to the emitter of Q0 to Q8, i.e., VEQ<8:0>. The second ends of the nine switches are connected to the third connection point VE3.

[0070] exist Figure 5 In the diagram, the first bipolar transistor and the second bipolar transistor are represented by the transistor symbol on the left. The four rows of switches on the right represent four sets of switch components. The first row of switch components represents the switches respectively set between the collector of a bipolar transistor and the second connection point VE2. The second row of switch components represents the switches respectively set between the emitter of a bipolar transistor and the fourth connection point VE4. The third row of switch components represents the switches respectively set between the collector of each bipolar transistor and the first connection point VE1. The fourth row of switch components represents the switches respectively set between the emitter of each bipolar transistor and the third connection point VE3.

[0071] like Figure 6 As shown, based on the first set of dynamic switching signals CK1 <0> To CK1 <8> The second set of dynamic exchange signals CK <0> To CK <5> , achieved Figure 3 Medium circuit connection method to Figure 4 Switching between circuit connection methods.

[0072] In this embodiment, by connecting four sets of switching components to the pins of multiple transistors one by one, dynamic switching between the collector, emitter and different connection points of each transistor is realized. This prevents the static process deviation of a single transistor from acting on the circuit in a fixed manner, but instead disperses it into high-frequency fluctuations that vary with the switching frequency. This reduces the fixed offset effect of transistor mismatch on the reference voltage. Furthermore, this dynamic connection does not interfere with the temperature compensation logic of the bandgap reference module itself.

[0073] In one embodiment of this disclosure, the first set of dynamic switching signals includes a first number of clock signals with sequentially shifted phases, configured to access the control terminals of corresponding switches in the first switching network. The first number is the same as the number of the first bipolar transistor and the second bipolar transistor, and the number of switches in each group of switching components in the first switching network.

[0074] like Figure 5 and Figure 6 As shown, in some embodiments, taking 9 transistors (Q0~Q8) and each group of switches including 9 switches as an example: the first group of dynamic switching signals are 9 clock signals with sequentially shifted phases, such as CK1. <0> ~CK1 <8> Each clock signal controls the same transistor in four sets of switches, such as CK1. <0> Corresponding to the four switches of Q0, CK1 <1> This corresponds to the four switches in Q1.

[0075] When CK1 <0> When the signal is high, the four sets of switching components corresponding to Q0 are closed, connecting the collector of Q0 to the first connection point, the emitter of Q0 to the third connection point, the collectors of Q1-Q8 to the second connection point, and the emitters of Q1-Q8 to the fourth connection point.

[0076] Similarly, the nine clock signals take turns to activate in phase offset order. Q0~Q8 will sequentially switch the connection relationship of their collector (between the first and second connection points) and emitter (between the third and fourth connection points), so that each transistor can be connected in different circuit paths in turn.

[0077] In this embodiment, by using clock signals with sequentially shifted phases to control the switching of the corresponding transistors, Q0~Q8 are switched to different circuit nodes in an orderly manner. Each time, the connection positions between two transistors are exchanged. This ensures that each transistor participates in the generation of the bandgap voltage, and also disperses the mismatch error of a single transistor into different periods and different paths. This prevents the continuous offset of the reference voltage caused by a fixed mismatch. At the same time, this periodic switching only changes the connection relationship of the transistors without destroying the temperature compensation logic. Ultimately, the accuracy of the reference voltage is improved while maintaining temperature stability.

[0078] In one embodiment of this disclosure, the mismatch device in the bandgap reference module further includes: a fourth resistor connected in series and a plurality of third resistors, with a fifth connection point between the plurality of third resistors and the fourth resistor, and one of the plurality of third resistors connected between the third connection point and the fourth connection point.

[0079] like Figure 3 As shown, in some embodiments, the fourth resistor R4 connected in series and multiple third resistors, namely R31~R36, form a voltage divider network. By allowing any of the resistors R31~R36 to be alternately placed between the third connection point VE3 and the fourth connection point VE4 to connect between the emitters of two different transistors, the voltage division of the resistors can be used to adjust the proportion of the positive temperature coefficient voltage, thereby calibrating the bandgap reference voltage to zero temperature coefficient. At the same time, by alternately switching different R31 to R36 connected between the third connection point VE3 and the fourth connection point VE4, the static process deviation of each resistor will not have a fixed impact on the voltage, but will be distributed over time, preventing the reference voltage offset caused by single resistor mismatch, and realizing accurate temperature coefficient compensation and average processing of resistor mismatch error.

[0080] The dynamic switching signal includes a second set of dynamic switching signals, which are used to sequentially configure multiple third resistors to be connected to the emitters of the first bipolar transistor and the second bipolar transistor, respectively.

[0081] In some embodiments, the second set of dynamic switching signals is a timing signal that controls the access of R31 to R36 to the third connection point VE3 and the fourth connection point VE4. It can be accessed sequentially to one of R31 to R36 in a fixed order. Combined with the first set of dynamic switching signals, it is synchronously switched to a path connected to the emitter of the first bipolar transistor or the second bipolar transistor, providing timing control logic for averaging resistance mismatch.

[0082] In this embodiment, the negative temperature coefficient Vbe and positive temperature coefficient ΔVbe generated by the bandgap reference module are divided by the fourth resistor R4 and the third resistor, and the ratio of the two is adjusted to achieve a reference voltage with zero temperature coefficient. At the same time, the second set of dynamic exchange signals sequentially switches R31 to R36 to connect to the third connection point and the fourth connection point, so that the mismatch error of each resistor periodically participates in the circuit, converting the static resistance deviation into high-frequency noise. Thus, temperature coefficient calibration can be completed through the voltage divider network, and the mismatch effect can be eliminated through the dynamic switching of resistors.

[0083] In one embodiment of this disclosure, the switch network further includes a second switch network, the second switch network comprising: A branch switching assembly is configured to, based on a second set of dynamic switching signals, sequentially connect one of the multiple third resistors to the branch between the third connection point VE3 and the fourth connection point VE4; a series path switching assembly is configured to, based on the second set of dynamic switching signals, control the portions of the multiple third resistors that are not connected to the branch to be connected in series sequentially and connected to the path between the fourth connection point VE4 and the fifth connection point VE5, as shown below. Figure 7 As shown.

[0084] In this embodiment, the configuration of the second switch network, in which the branch switching switch assembly alternately connects a single third resistor to the key voltage divider branch and the series path switch assembly maintains the series path of the remaining resistors, can achieve zero temperature coefficient calibration of the reference voltage by utilizing the voltage divider characteristics of the third resistor to ensure temperature stability. Furthermore, based on the dynamic rotation of the third resistor, the static process mismatch error of a single resistor can be dispersed into periodic small fluctuations, preventing the deviation of fixed mismatch from the reference voltage. This is beneficial to improving the output accuracy of the reference voltage while maintaining temperature performance.

[0085] In one embodiment of this disclosure, the branch switching assembly includes: a first sub-switch group configured to control a first end of a target resistor among a plurality of third resistors to be connected to a third connection point; a second sub-switch group configured to control a second end of the target resistor to be connected to a fourth connection point; and a third sub-switch group configured to connect a third resistor adjacent to the target resistor to the fourth connection point.

[0086] In one embodiment of this disclosure, the series path switching assembly includes: a fourth sub-switch group configured to control communication between a first terminal of a third resistor not connected to a branch and a second terminal of a preceding adjacent resistor; a fifth sub-switch group configured to control communication between a second terminal of a third resistor not connected to a branch and a first terminal of a subsequent adjacent resistor; a sixth sub-switch group and a seventh sub-switch group for configuring additional series paths between adjacent third resistors not connected to branches; and an eighth sub-switch group configured to control communication between the second terminal of the end resistor among a plurality of third resistors and a fifth connection point.

[0087] like Figure 8 As shown, the six switches in the first sub-switch group include: VA <5> →VE3 (corresponding to the first end of R31), VA <4> →VE3 (corresponding to the first end of R32), VA <3> →VE3 (corresponding to the first end of R33), VA <2> →VE3 (corresponding to the first end of R34), VA <1> →VE3 (corresponding to the first end of R35) and VA <0> →VE3 (corresponding to the first end of R36).

[0088] The six switches in the second sub-switch group include: VB <5> →VE4 (corresponding to the second terminal of R31), VB <4> →VE4 (corresponding to the second terminal of R32), VB <3> →VE4 (corresponding to the second end of R33), VB <2> →VE4 (corresponding to the second end of R34), VB <1> →VE4 (corresponding to the second end of R35), VB <0> →VE4 (corresponding to the second end of R36).

[0089] The six switches in the third sub-switch group include: VA <4> →VE4 (corresponding to the first end of R32 adjacent to R31), VA <5> →VE4 (corresponding to the first end of R31 adjacent to R32), VA <3> →VE4 (corresponding to the first end of R32 adjacent to R33), VA <2> →VE4 (corresponding to the first end of R33 adjacent to R34), VA <1> →VE4 (corresponding to the first end of R34 adjacent to R35), VA <0> →VE4 (corresponding to the first end of R35 adjacent to R36).

[0090] The six switches in the fourth sub-switch group include: VA <4> →VB <5> (R32 first terminal and R31 second terminal), VA <3> →VB <4> (R33 first terminal and R32 second terminal), VA <2> →VB <3> (R34 first terminal and R33 second terminal), VA <1> →VB <2> (R35 first terminal and R34 second terminal), VA <0> →VB <1> (R36 first terminal and R35 second terminal), VA <5> →VB <0> (R31 first end and R36 second end).

[0091] The six switches in the fifth sub-switch group include: VB <5> →VA <4> (R31 second terminal and R32 first terminal), VB <4> →VA <3> (R32 second terminal and R33 first terminal), VB <3> →VA <2> (R33 second terminal and R34 first terminal), VB <2> →VA <1> (R34 second terminal and R35 first terminal), VB <1> →VA <0> (R35 second terminal and R36 first terminal), VB <0> →VA <5> (R36 second terminal and R31 first terminal).

[0092] The six switches in the sixth sub-switch group include: VB <4> →VA <5> (R32 second terminal and R31 first terminal), VB <3> →VA <4> (R33 second terminal and R32 first terminal), VB <2> →VA <3> (R34 second terminal and R33 first terminal), VB <1> →VA <2> (R35 second terminal and R34 first terminal), VB <0> →VA <1> (R36 second terminal and R35 first terminal), VB <5> →VA <0> (R31 second terminal and R36 first terminal).

[0093] The six switches in the seventh sub-switch group include: VA <5> →VB <4> (R31 first terminal and R32 second terminal), VA <4> →VB <3> (R32 first terminal and R33 second terminal), VA <3> →VB <2> (R33 first terminal and R34 second terminal), VA <2> →VB <1> (R34 first terminal and R35 second terminal), VA <1> →VB <0> (R35 first terminal and R36 second terminal), VA <0> →VB <5> (R36 first end and R31 second end).

[0094] The six switches in the eighth sub-switch group include: VB <0> →VE5 (R36 second end), VB <5> →VE5 (R31 second terminal), VB <4> →VE5 (R32 second terminal), VB <3> →VE5 (R33 second terminal), VB <2> →VE5 (R34 second terminal), VB <1> →VE5 (R35 second end).

[0095] In some embodiments, the control process of the switch is to switch different third resistors in turn to the critical voltage divider branch between the third connection point VE3 and the fourth connection point VE4 according to the triggering order of the clock signal, while the remaining resistors remain in series.

[0096] In some embodiments, CK <0> When the voltage is high, the control logic acts on R31 (the two ends of R31 correspond to VA). <5> VB <5> ) switch, VA <5> Connect to VE3, VB <5> Connect to VE4, R32 (both ends correspond to VA) <4> and VB <4> ) of VA <4> Connect to VE4, R33 (both ends correspond to VA) <3> and VB <3> ) of VA <3> Connect to VB <4> R34 (both ends correspond to VA) <2> and VB <2> ) of VA <2> Connect to VB <3> R35 (both ends correspond to VA) <1> and VB <1> ) of VA <1> Connect to VB <2> R36 (both ends correspond to VA) <0> and VB <0> ) of VA <0> Connect to VB <1> VB <0> Continuing with VE5.

[0097] In some embodiments, CK <1> When the voltage is high, the control logic acts on R32 (the two ends of R32 correspond to VA). <4> VB <4> ) switch, VA <4> Connect to VE3, VB <4> Connect to VE4, R31 (both ends correspond to VA) <5> and VB <5> ) of VA <5> Connect to VE4, R33 (both ends correspond to VA) <3> and VB <3> ) of VA <3> Connect to VB <5> R34 (both ends correspond to VA) <2> and VB <2> ) of VA <2> Connect to VB <3> R35 (both ends correspond to VA) <1> and VB <1> ) of VA <1> Connect to VB <2> R36 (both ends correspond to VA) <0> and VB <0> ) of VA <0> Connect to VB <1> VB <0> Continuing with VE5.

[0098] In this embodiment, a branch switching switch assembly precisely controls the connection of a single third resistor to the critical voltage divider branch, and simultaneously connects its adjacent resistors to the auxiliary path. At the same time, a series path switching assembly is used to construct a main series path and an additional redundant series path. This not only achieves zero temperature coefficient calibration of the reference voltage by leveraging the voltage divider characteristics of the third resistor, ensuring temperature stability, but also avoids the risk of voltage divider network breakage caused by a single switch failure through the dual protection of the main and backup series paths. In addition, the dynamic rotation design of the target resistor disperses the process mismatch error of a single resistor into periodic fluctuations. Ultimately, while improving the circuit's fault tolerance, the accuracy and consistency of the reference voltage output are significantly enhanced.

[0099] In one embodiment of this disclosure, the second set of dynamic switching signals includes a second number of clock signals with sequentially shifted phases, configured to access the control terminals of corresponding switches in the second switching network, the second number being the same as the number of third resistors.

[0100] In this embodiment, the second set of dynamic switching signals is configured as clock signals with the same number of third resistors and sequentially offset phases. This allows for dynamic switching by controlling the correspondence between each third resistor and the critical branch between the third and fourth connection points through a clock control signal-to-resistance relationship. This disperses the mismatch error of individual resistors. Furthermore, the timing characteristics of the phase offset prevent circuit conflicts or voltage divider logic confusion caused by multiple switches being turned on simultaneously. At the same time, it matches the redundant path control rhythm of the series path switch components, ensuring that the second switch network achieves reference voltage and temperature calibration while also possessing stable timing control and reliable circuit fault tolerance.

[0101] In one embodiment of this disclosure, the feedback module includes: a first chopper switch, the input terminals of the first chopper switch being connected to a first resistor and a second resistor respectively, and the output terminals of the first chopper switch being connected to a first connection point and a second connection point respectively.

[0102] like Figure 9A As shown, in a chopper switch according to an embodiment of this disclosure, the CHOP signal passes through two stages of inverters to generate complementary control signals CHOPB and CHOPA, as follows: Figure 9B As shown, if CHOP=1, then CHOPA=1, CHOPB=0, IN1 is connected to OUT1 through the switch controlled by CHOPB, and IN2 is connected to OUT2 through the switch controlled by CHOPA. If CHOP=0, then CHOPA=0, CHOPB=1, IN1 is connected to OUT2 through the switch controlled by CHOPA, and IN2 is connected to OUT1 through the switch controlled by CHOPB, thus allowing the input and output to be interchanged.

[0103] like Figure 5As shown, in some embodiments, the chopping signal corresponding to the first chopper switch, i.e. the first sub-signal, is CHOP1. If the chopping signal CHOP1 is at the first level (e.g., high level), the internal channel of the first chopper switch can be forward-conducting, i.e., the first resistor R1 is connected to the first connection point VE1 and the second resistor R2 is connected to the second connection point VE2. At this time, the process mismatch between the first resistor R1 and the second resistor R2 will introduce a positive error. If the chopping signal CHOP1 is switched to the second level (e.g., low level), the internal channel of the first chopper switch is cross-conducting, i.e., the first resistor R1 is connected to the second connection point VE2 and the second resistor R2 is connected to the first connection point VE1. At this time, the mismatch direction between the first resistor R1 and the second resistor R2 is reversed, introducing a reverse error. Through the periodic alternation of the dual-level signal, the resistor mismatch error in the output exhibits periodic reverse fluctuations, rather than a fixed deviation.

[0104] In this embodiment, by using the cross-switching design of the first chopper switch at different levels, the process mismatch error between the first resistor and the second resistor is converted into a periodic reverse fluctuation signal to replace the fixed mismatch deviation. The frequency of this fluctuation signal is determined based on the period of the first sub-signal and can be matched with the cutoff frequency of the subsequent low-pass filter module to effectively filter out the resistor mismatch error, while not affecting the temperature drift complementary characteristics of the reference voltage.

[0105] In one embodiment of this disclosure, the feedback module further includes: a second chopper switch, the input terminals of which are respectively connected to the first connection point and the second connection point, and the output terminals of which are respectively connected to the first input terminal and the second input terminal of the operational amplifier; and a third chopper switch, the input terminals of which are respectively connected to the first output terminal and the second output terminal of the operational amplifier, and the output terminals of which are respectively connected to the output terminal and the positive bias voltage terminal of the operational amplifier.

[0106] Figure 10A The internal structure of the operational amplifier BG_OP is shown, where M1 is the differential input transistor used to receive the differential inputs of VIP1 and VIN1, M3 and M4 are common gate transistors used to improve the output impedance and gain of the op-amp, and VBN and VBP are bias voltages that provide stable operating current for M1 to M4 to ensure the amplification performance of the op-amp.

[0107] Where chop2=1, Von is connected to VBP and Vop is connected to Vout; chop2=0, Von is connected to Vout and Vop is connected to VBP.

[0108] like Figure 3As shown, in some embodiments, the first transistor MN1 serves as a feedback transistor, with its gate connected to the output terminal of the operational amplifier and its source connected to the common base terminal of the bipolar transistor, i.e., the VBG node. The second transistor MN2 and the first transistor form a current mirror, with the source of the second transistor connected to the common terminal of the first resistor R1 and the second resistor R2. This enables the operational amplifier output to perform negative feedback control on the current passing through the first resistor R1 and the second resistor R2, ensuring current matching of VE1=VE2.

[0109] like Figure 10B The second chopper switch shown is located at the input terminal of the operational amplifier BG_OP. The input terminals (IN1, IN2) of the second chopper switch are connected to external differential signals, corresponding to the first connection point V1 and the second connection point V2. The output terminals (OUT1, OUT2) are connected to the gates of the two input stages of BG_OP, namely M1 and M2, and are controlled by the first switch signal chop2.

[0110] Where chop2=1, VIP is connected to VIP1 and VIN is connected to VIN1; where chop2=0, VIP is connected to VIN1 and VIN is connected to VIP1.

[0111] like Figure 10C The third chopper switch shown is located at the output of the operational amplifier BG_OP. The input terminals (IN1, IN2) of the third chopper switch are connected to the output signals of BG_OP, namely the differential outputs Von and Vop of the operational amplifier. The output terminals (OUT1, OUT2) are connected to the subsequent circuits, corresponding to VBP and Vout, and are synchronously controlled with the chop2 signal shared with the input chopper.

[0112] In some embodiments, such as Figure 11A As shown, chop2=0, VIP is connected to the gate of M1, and VIN is connected to the gate of M2. The operational amplifier BG_OP works in the forward path. If there is a characteristic mismatch between M1 and M2, a fixed forward offset error will be introduced, resulting in a deviation in the op-amp output Vout.

[0113] In some embodiments, such as Figure 11B As shown, chop2=1. After chopping, VIP is connected to the gate of M2 and VIN is connected to the gate of M1. The input path of the operational amplifier BG_OP is reversed, and the direction of the mismatch effect between M1 and M2 is also reversed, making the positive offset error into the negative offset error.

[0114] In some embodiments, the input terminal of the second chopper switch is connected to the first connection point and the second connection point, and the output terminal is connected to the two input terminals of the operational amplifier. The input terminal of the third chopper switch is connected to the two output terminals of the operational amplifier, the output node, and the positive bias voltage terminal. In conjunction with the first switching signal period of the first group of chopper switches, when the chopping signal of the first group of chopper switches is at the second level, the second chopper switch connects the first connection point to the first input terminal of the operational amplifier and the second connection point to the second input terminal of the operational amplifier. The third chopper switch connects the first output terminal of the operational amplifier to the output node. When the chopping signal of the first group of chopper switches is at the first level, the connection is switched to the first connection point to the second input terminal of the operational amplifier and the second connection point to the first input terminal of the operational amplifier. The third chopper switch synchronously switches the path of the output terminal of the operational amplifier. Through the synchronous reversal of the input and output terminals, the fixed offset error of the operational amplifier is converted into a 2T periodic fluctuation signal.

[0115] In this embodiment, the negative feedback accuracy of the operational amplifier to the first and second resistor branches is enhanced by combining a feedback transistor with a current mirror, ensuring that the current flowing through the first and second resistors is equivalent. At the same time, by configuring chopper switches at both the input and output terminals of the operational amplifier and switching them synchronously, the fluctuation processing of the operational amplifier offset error is achieved. Combined with the configured chopper period, it can not only prevent timing conflicts with other chopper switches in the bandgap reference module, but also allow the operational amplifier offset error to be filtered out by the subsequent low-pass filter. Ultimately, while improving the stability of the operational amplifier's negative feedback, the output error of the reference voltage is further reduced.

[0116] In some embodiments, such as Figure 1 and Figure 3 As shown, it can be understood as Figure 1 R3 in the text is equivalent to Figure 3 R31 in the middle, and Figure 1 R4 is split into R32, R33, R34, R35, R36 and a new R4, R31=R32=R33=R34=R35=R36=R. R4 is a resistor smaller than R, used to adjust the temperature coefficient of VBG to close to 0.

[0117] In some embodiments, such as Figure 1 and Figure 3 As shown, Figure 1 In the equation, Q1 is split into Q0~Q7, and... Figure 1 Q2 is redefined as Q8, and Q0~Q8 are completely identical BJT tubes.

[0118] Timing combining chopper and DEM, such as Figure 6 As shown.

[0119] The CHOP signal controls BG_OP to perform chopping, and also controls the swapping of R1 and R2 (i.e., dynamic component matching between R1 and R2). CK <0> ~CK <5> Control R31~R36 to perform DEM, when CK <0> When the value is high, the circuit structure is as follows: Figure 3 As shown; when CK <1> When the value is high, R32 and R31 swap positions; when CK... <2> When the value is high, R33 and R31 swap positions. And so on, when CK... <5> When the value is high, R36 and R31 swap positions. CK1 <0> ~CK1 <8> DEM is performed by controlling Q0~Q8, when CK1 <0> When the value is high, the connection method for Q0~Q8 is as follows: Figure 3 As shown; when CK1 <1> When CK1 is high, Q0 and Q8 swap positions; when CK1 is high, Q0 and Q8 swap positions. <2> When CK1 is high, Q1 and Q8 swap positions. And so on, until CK1... <8> When the CHOP signal is high, Q7 and Q8 swap positions. Therefore, when the CHOP signal is high, R1 and R2 swap positions, and CK... <1> and CK1 <1> When the value is high, R31 and R32 are swapped, and Q0 and Q8 are swapped. The circuit connection is as follows: Figure 4 As shown. Figure 3 The Vref generated by filtering the VBG voltage after LPF and performing chopping and DEM can achieve very high accuracy.

[0120] In one embodiment of this disclosure, the phase offset between adjacent signals in a dynamically exchanged signal corresponds to half a period of a chopper signal.

[0121] In this embodiment, the second set of dynamic exchange signals (CK) <0> -CK <5> ), the first group of dynamic switching signals (CK1) <0> -CK1 <8> The phase offset of adjacent signals in the circuit is set to half a chopper signal period. This enables the timing of the two types of dynamic switching signals to be coupled with the chopper period. For the second group of dynamic switching signals, this offset allows multiple third resistors to be connected to the critical branch in turn during the chopper period, ensuring that the mismatch error of a single resistor is uniformly canceled in the complete chopper period. For the first group of dynamic switching signals, this offset allows the corresponding switching action to form a half-cycle alternating timing relationship with the branch switching of the second group of signals, preventing circuit conflicts caused by the simultaneous conduction of the two types of switching networks. At the same time, the modulation effect of the chopper signal covers the critical path of the entire circuit, which is beneficial to eliminating the superposition effect of mismatch errors of different networks and preventing additional ripple introduced by timing asynchrony. Ultimately, it can ensure the output accuracy and stability of the reference voltage circuit.

[0122] Table 1 shows the impact of chopping and DEM techniques on the Vref accuracy of the BG output. As shown in Table 1, when the BG does not perform DEM or chopping, the 1 sigma change in Vref is 2.128 mV; if the BG only performs DEM between R1 and R2, the 1 sigma change in Vref is 2.14 mV; if the BG only performs chopping on BG_OP, the 1 sigma change in Vref is 2.057 mV; if the BG only performs DEM on R31~R36, the 1 sigma change in Vref is 1.363 mV; if the BG only performs DEM on Q0~Q8, the 1 sigma change in Vref is 1.967 mV; if the BG_OP performs chopping, and simultaneously the resistors R31~R36 and the BJT transistors Q0~Q8 perform DEM, the 1 sigma change in Vref decreases to 86.46 uV.

[0123] In some embodiments, the fourth resistor R4 can be further split and a corresponding third switch network and a third set of dynamic switching signals can be configured to further reduce the 1 sigma of Vref variation.

[0124] In some embodiments, the error sources caused by the mismatch between R1 and R2, as well as the mismatch between Q0 and Q8, can be equivalent to the input of the op-amp. The polarities of the error sources before and after DEM are reversed, and the errors caused by the output are exactly opposite in polarity and equal in magnitude, thus canceling each other out.

[0125] The expression output by VBG is: (1) If we consider the effect of mismatch between R31 and R32 and ignore other resistors, then equation (1) becomes: (2) Assumption , Then equation (2) is transformed into: (3) After swapping the positions of R31 and R32, equation (3) is further transformed into: (4) Adding the results of the two outputs and dividing by 2 gives: (5) Error term is If no DEM was performed, the error term is: Therefore, after performing DEM, the first-order error term is eliminated, leaving only the second-order error term, which can significantly improve accuracy. The accuracy improvement factor is approximately: (6) Table 1

[0126] A DC-DC converter according to an embodiment of the present disclosure includes: a reference voltage circuit as described in any of the preceding embodiments.

[0127] In this disclosure, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0128] In the description of this disclosure, it should be understood that the terms "upper," "lower," "left," "right," "front," "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0129] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0130] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure. Other embodiments of this disclosure will be readily apparent to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A reference voltage circuit, characterized in that, include: A bandgap reference module and a feedback module are electrically connected, wherein the feedback module is configured to feed back a voltage balance signal to the bandgap reference module so that the bandgap reference module outputs an initial reference voltage based on the voltage balance signal; A dynamic element matching switch network, connected to the bandgap reference module, is configured to periodically switch the connection relationship of mismatched devices in the bandgap reference module based on the accessed dynamic switching signal. The feedback module is also configured to receive a chopper signal, which is used to modulate the offset of the feedback module to a high frequency band, and a period of the dynamic switching signal includes multiple periods of the chopper signal. A low-pass filter module is configured to connect to the initial reference voltage and perform low-pass filtering on the initial reference voltage.

2. The reference voltage circuit according to claim 1, characterized in that, The bandgap reference module and the feedback module have a first connection point and a second connection point. The feedback module includes: A first resistor and a second resistor have a common connection point, one of which is also connected to the first connection point and the other is also connected to the second connection point; An operational amplifier, wherein the two input terminals of the operational amplifier are respectively connected to the first connection point and the second connection point, the voltage balance signal includes a first current flowing through the first resistor and a second current flowing through the second resistor, and the operational amplifier is configured to make the first current and the second current equivalent based on negative feedback operation; The chopping signal is configured to switch the first resistor to the first connection point and the second resistor to the second connection point, or to switch the first resistor to the second connection point and the second resistor to the first connection point.

3. The reference voltage circuit according to claim 2, characterized in that, The bandgap reference module has a third connection point and a fourth connection point, and the mismatch device in the bandgap reference module includes: A first bipolar transistor with multiple common-emitter connections; The second bipolar transistor is connected to the common base of multiple first bipolar transistors, and the initial reference voltage is output at the common base. One of the common emitter terminals of the first bipolar transistors and the emitter terminal of the second bipolar transistor is connected to the third connection point, and the other is connected to the fourth connection point. The dynamic switching signal includes a first set of dynamic switching signals, which are used to switch the collector of the second bipolar transistor to be connected to the first connection point, and the collector of the first bipolar transistor to be connected to the second connection point, or to switch the collector of the second bipolar transistor to be connected to the second connection point, and to switch the collector of any of the first bipolar transistors to be connected to the first connection point.

4. The reference voltage circuit according to claim 3, characterized in that, The first bipolar transistor and the second bipolar transistor are configured as the same transistor.

5. The reference voltage circuit according to claim 3, characterized in that, The switching network includes a first switching network, the first switching network comprising: The first set of switching components is connected in parallel. The first end of the first set of switching components is connected to the collector of the plurality of first bipolar transistors and the collector of the second bipolar transistors in a one-to-one correspondence. The second end of the first set of switching components is connected to the first connection point. A second set of switching components connected in parallel, wherein the first end of the second set of switching components is connected one-to-one with the collectors of the plurality of first bipolar transistors and the collectors of the second bipolar transistors, and the second end of the second set of switching components is connected to the second connection point; A third set of switching components connected in parallel, wherein the first end of the third set of switching components is connected one-to-one with the emitters of the plurality of first bipolar transistors and the emitters of the second bipolar transistors, and the second end of the third set of switching components is connected to the third connection point; A fourth set of switching components is connected in parallel. The first end of the fourth set of switching components is connected to the emitter of the plurality of first bipolar transistors and the emitter of the second bipolar transistors in a one-to-one correspondence. The second end of the fourth set of switching components is connected to the fourth connection point.

6. The reference voltage circuit according to claim 5, characterized in that, The first set of dynamic switching signals includes a first number of clock signals with sequentially shifted phases, configured to be connected to the control terminal of the corresponding switch in the first switching network. The first number is the same as the number of the first bipolar transistor and the second bipolar transistor, and the number of switches in each group of switching components in the first switching network.

7. The reference voltage circuit according to claim 3, characterized in that, The mismatch device in the bandgap reference module also includes: A fourth resistor and a plurality of third resistors are connected in series, with a fifth connection point between the plurality of third resistors and the fourth resistor, and one of the plurality of third resistors is connected between the third connection point and the fourth connection point. The dynamic exchange signal includes a second set of dynamic exchange signals, which are used to sequentially configure the plurality of third resistors to be connected to the emitter of the first bipolar transistor and the emitter of the second bipolar transistor, respectively.

8. The reference voltage circuit according to claim 7, characterized in that, The switching network further includes a second switching network, the second switching network comprising: A branch switching assembly is configured to sequentially connect one of the plurality of third resistors to the branch between the third connection point and the fourth connection point based on the second set of dynamic switching signals; The series path switch assembly is configured to control the unconnected portions of the plurality of third resistors to be connected in series sequentially based on the second set of dynamic exchange signals, and to be connected to the path between the fourth connection point and the fifth connection point.

9. The reference voltage circuit according to claim 8, characterized in that, The branch switching assembly includes: The first sub-switch group is configured to control the first end of the target resistor among the plurality of third resistors to be connected to the third connection point; The second sub-switch group is configured to control the second terminal of the target resistor to be connected to the fourth connection point; The third sub-switch group is configured such that one of the third resistors adjacent to the target resistor is connected to the fourth connection point.

10. The reference voltage circuit according to claim 8, characterized in that, The series path switching assembly includes: The fourth sub-switch group is configured to control the connection between the first terminal of the third resistor that is not connected to the branch and the second terminal of the preceding adjacent resistor; The fifth sub-switch group is configured to control the connection between the second terminal of the third resistor that is not connected to the branch and the first terminal of the next adjacent resistor; The sixth and seventh sub-switch groups are used to configure additional series paths between adjacent third resistors that are not connected to a branch. The eighth sub-switch group is configured to control the connection between the second end of the end resistor of the plurality of third resistors and the fifth connection point.

11. The reference voltage circuit according to claim 8, characterized in that, The second set of dynamic switching signals includes a second number of clock signals with sequentially shifted phases, configured to be connected to the control terminals of the corresponding switches in the second switching network, the second number being the same as the number of the third resistors.

12. The reference voltage circuit according to claim 2, characterized in that, The feedback module also includes: A first chopper switch has two input terminals connected to the first resistor and the second resistor, respectively, and two output terminals connected to the first connection point and the second connection point, respectively.

13. The reference voltage circuit according to claim 2, characterized in that, The feedback module also includes: The second chopper switch has its input terminals connected to the first connection point and the second connection point, respectively, and its output terminals connected to the first input terminal and the second input terminal of the operational amplifier, respectively. The third chopper switch has its input terminals connected to the first and second output terminals of the operational amplifier, and its output terminals connected to the output terminal and the positive bias voltage terminal of the operational amplifier.

14. The reference voltage circuit according to claim 1, characterized in that, The phase offset between adjacent signals in the dynamic exchange signal corresponds to half a period of the chopper signal.

15. The reference voltage circuit according to claim 1, characterized in that, Switching the connection relationship is suitable for converting the mismatch error of the mismatched device into a first group of high-frequency noise; The offset modulation to the high-frequency band is adapted to obtain a second set of high-frequency noise, so that the first set of high-frequency noise and the second set of high-frequency noise can be filtered out by the low-pass filter module.

16. A DC-DC converter, characterized in that, include: The reference voltage circuit as described in any one of claims 1 to 15.

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