FPGA (Field Programmable Gate Array) remote updating method and related device
By dividing the Flash memory of the FPGA board into multiple regions and using remote update commands and CRC checks, batch updates of FPGA logic code were achieved, solving the problem of wasted time and manpower caused by writing code block by block in the existing technology, and improving update efficiency and reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-03-13
AI Technical Summary
In existing technologies, modifying FPGA logic code requires programming block by block, which consumes a lot of time and manpower and seriously affects the project progress.
The FPGA board's Flash memory is divided into a jump control area, a first application bit stream area, and a second application bit stream area. Batch updates of FPGA logic code are achieved through remote update commands and CRC checks.
It improves the efficiency and reliability of remote FPGA updates, reduces the error rate, and can continue to load the data from the last update in the event of an update failure without corrupting the data from the last update.
Smart Images
Figure CN121658044A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of FPGA (Field-Programmable Gate Array) remote update technology, specifically relating to an FPGA remote update method and related apparatus. Background Technology
[0002] In FPGA design, remote upgrades (also called remote updates) are a common requirement, especially in embedded systems or industrial automation systems. This capability allows for updating the FPGA's logic design even when system operation is interrupted.
[0003] In practical engineering applications, equipment chassis typically contain multiple boards with identical layouts. However, in real-world engineering applications, modifying the FPGA logic code requires programming each board individually, which consumes a significant amount of time and manpower, thus severely impacting project progress.
[0004] Therefore, a strategy for batch updating FPGAs is needed in engineering. Summary of the Invention
[0005] The purpose of this invention is to provide a method and related apparatus for remote FPGA updates, which solves the problem in the prior art that after modifying the FPGA logic code, it is necessary to burn the code block by block, which consumes a lot of time and manpower and seriously affects the progress of the project.
[0006] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a method for remotely updating an FPGA, comprising the following steps: The Flash memory of the first FPGA board is divided into several regions, including a jump control region, a first application bit stream region, and a second application bit stream region. The second FPGA board sends the remote update command to the first FPGA board; After receiving the remote update command, the first FPGA board obtains the state of the jump control area synchronization header from the jump control area, and determines which application bit stream area to update based on the state of the jump control area synchronization header. The first FPGA board erases the data in the first application bitstream region or the second application bitstream region; After the data in the first application bitstream region or the second application bitstream region is erased, the second FPGA board will update the data and transmit it to the first FPGA board. The first FPGA board reads the updated data back from the Flash memory and performs CRC verification on the read-back updated data to obtain the CRC verification result. Based on the CRC (Cyclic Redundancy Check) verification results, determine whether to complete the batch FPGA remote update.
[0007] A further improvement of the present invention is that the first FPGA board is one FPGA board or several FPGA boards.
[0008] A further improvement of this invention is that the second FPGA board sends the remote update command to the first FPGA board, specifically: The second FPGA board sends remote update commands to the first FPGA board via the backplane.
[0009] A further improvement of this invention is that determining which application bitstream region to update based on the state of the jump control region synchronization header specifically includes: If the jump control region synchronization header is read, then update the first application bit stream region; If the jump control area synchronization header is not read, then update the second application bit stream area.
[0010] A further improvement of this invention is that the second FPGA board transmits update data to the first FPGA board, specifically as follows: The second FPGA board transmits the update data to the first FPGA board via the backplane.
[0011] A further improvement of this invention is that the step of determining whether the remote update of the first FPGA board has been completed based on the CRC check result specifically involves: If the CRC check is successful and the updated area is the first application bit stream area, then erase the jump control area synchronization header and set the update completion flag. If the CRC check is successful and the updated area is the second application bit stream area, then write the jump control area synchronization header and set the update completion flag bit. If the CRC check fails, the update failure flag is set.
[0012] A further improvement of the present invention is that, based on the CRC check result, after determining whether the remote update of the first FPGA board has been completed, the second FPGA board prints the serial number of the first FPGA board that was successfully updated and the serial number of the first FPGA board that failed to be updated.
[0013] Secondly, the present invention provides an FPGA remote update system, comprising: The region partitioning module is used to divide the Flash memory of the first FPGA board into several regions, including a jump control region, a first application bit stream region, and a second application bit stream region. The command sending module is used by the second FPGA board to send remote update commands to the first FPGA board; The update region determination module is used to obtain the state of the jump control region synchronization header from the jump control region after the first FPGA board receives the remote update command, and determine which application bit stream region to update based on the state of the jump control region synchronization header; The erase module is used by the first FPGA board to erase data in the first application bit stream region or the second application bit stream region. The transmission module is used to transmit the update data from the second FPGA board to the first FPGA board after the data in the first application bit stream region or the second application bit stream region has been erased. The verification module is used by the first FPGA board to read back the updated data from the Flash memory and perform CRC verification on the read-back updated data to obtain the CRC verification result. The update module is used to determine whether the remote update of the first FPGA board has been completed based on the CRC check result.
[0014] Thirdly, the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the FPGA remote update method described above.
[0015] Fourthly, the present invention provides a storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the FPGA remote update method described above.
[0016] Compared with the prior art, the present invention has the following beneficial effects: The FPGA remote update method proposed in this invention has two aspects. First, after receiving a remote update command, the first FPGA board obtains the state of the jump control region synchronization header from the jump control region and determines which application bitstream region to update based on the state of the jump control region synchronization header. This operation can accurately locate the FPGA remote update region, avoiding the transmission and burning of all data, thereby improving the efficiency of FPGA remote update. Second, the first FPGA board reads back the update data from the Flash memory and performs CRC verification on the read-back update data to obtain the CRC verification result. This operation can not only improve the reliability of FPGA remote update but also reduce the error rate of FPGA remote update.
[0017] Furthermore, this invention discloses a method for determining whether a remote update of the first FPGA board has been completed based on the CRC check result, specifically as follows: If the CRC check is successful and the updated area is the first application bit stream area, then erase the jump control area synchronization header and set the update completion flag. If the CRC check is successful and the updated area is the second application bit stream area, then write the jump control area synchronization header and set the update completion flag bit. If the CRC check fails, the update failure flag is set.
[0018] It is evident that even if the update fails, the FPGA can continue to load the previously updated data upon the next startup without damaging the previously updated data. Attached Figure Description
[0019] Figure 1 This is a flowchart of the FPGA remote update method of the present invention; Figure 2 This is a schematic diagram of the FPGA remote update system of the present invention; Figure 3 This is a flowchart of the FPGA remote update method in Embodiment 4 of the present invention; Figure 4 This is a schematic diagram of the structure of the electronic device of the present invention. Detailed Implementation
[0020] To further understand the content of this invention, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments are merely illustrative and not limiting of the invention.
[0021] Example 1: The flowchart of the FPGA remote update method of this invention is as follows: Figure 1 As shown, the FPGA remote update method of the present invention includes the following steps: S1. Divide the Flash memory of the first FPGA board into several regions, the several regions including a jump control region, a first application bit stream region, and a second application bit stream region; S2. The second FPGA board sends the remote update command to the first FPGA board; S3. After receiving the remote update command, the first FPGA board obtains the state of the jump control area synchronization header from the jump control area, and determines which application bit stream area to update based on the state of the jump control area synchronization header; S4. The first FPGA board erases the data in the first application bitstream region or the second application bitstream region; S5. After the data erasure of the first application bit stream region or the second application bit stream region is completed, the second FPGA board will update the data and transmit it to the first FPGA board. S6. The first FPGA board reads the updated data back from the Flash memory and performs CRC verification on the read-back updated data to obtain the CRC verification result; S7. Based on the CRC check result, determine whether the remote update of the first FPGA board has been completed.
[0022] Example 2: A schematic diagram of the FPGA remote update system of this invention is shown below. Figure 2 As shown, the FPGA remote update system of the present invention includes: The region partitioning module is used to divide the Flash memory of the first FPGA board into several regions, including a jump control region, a first application bit stream region, and a second application bit stream region. The command sending module is used by the second FPGA board to send remote update commands to the first FPGA board; The update region determination module is used to obtain the state of the jump control region synchronization header from the jump control region after the first FPGA board receives the remote update command, and determine which application bit stream region to update based on the state of the jump control region synchronization header; The erase module is used by the first FPGA board to erase data in the first application bit stream region or the second application bit stream region. The transmission module is used to transmit the update data from the second FPGA board to the first FPGA board after the data in the first application bit stream region or the second application bit stream region has been erased. The verification module is used by the first FPGA board to read back the updated data from the Flash memory and perform CRC verification on the read-back updated data to obtain the CRC verification result. The update module is used to determine whether the remote update of the first FPGA board has been completed based on the CRC check result.
[0023] Example 3: The FPGA remote update method of the present invention includes the following steps: S1. Divide the Flash memory of the first FPGA board into several regions, including a jump control region, a first application bit stream region, and a second application bit stream region.
[0024] The first FPGA board can be one FPGA board or several FPGA boards.
[0025] S2. The second FPGA board sends the remote update command to the first FPGA board.
[0026] In this step, the second FPGA board sends the remote update command to the first FPGA board, specifically as follows: The second FPGA board sends remote update commands to the first FPGA board via the backplane.
[0027] S3. After receiving the remote update command, the first FPGA board obtains the status of the jump control area synchronization header from the jump control area, and determines which application bit stream area to update based on the status of the jump control area synchronization header.
[0028] This step determines which application bitstream region to update based on the state of the jump control region synchronization header, specifically including: If the jump control region synchronization header is read, then update the first application bit stream region; If the jump control area synchronization header is not read, then update the second application bit stream area.
[0029] S4. The first FPGA board erases the data in the first application bitstream region or the second application bitstream region.
[0030] S5. After the data erasure of the first application bitstream region or the second application bitstream region is completed, the second FPGA board will update the data and transmit it to the first FPGA board.
[0031] In this step, the second FPGA board will transmit update data to the first FPGA board, specifically as follows: The second FPGA board transmits the update data to the first FPGA board via the backplane.
[0032] S6. The first FPGA board reads the updated data back from the Flash memory and performs CRC verification on the read-back updated data to obtain the CRC verification result.
[0033] S7. Based on the CRC check result, determine whether the remote update of the first FPGA board has been completed.
[0034] This step determines whether the remote update of the first FPGA board has been completed based on the CRC check result. Specifically: If the CRC check is successful and the updated area is the first application bit stream area, then erase the jump control area synchronization header and set the update completion flag. If the CRC check is successful and the updated area is the second application bit stream area, then write the jump control area synchronization header and set the update completion flag bit. If the CRC check fails, the update failure flag is set.
[0035] Based on the CRC check result, after determining whether the remote update of the first FPGA board has been completed, the second FPGA board prints the serial number of the first FPGA board that was successfully updated and the serial number of the first FPGA board that failed to be updated.
[0036] Example 4: When the FPGA is powered on, it starts reading data from address 0x00 of the flash memory by default. The address increments continuously until a valid synchronization word is read. The configuration data before the synchronization word is ignored by the FPGA. In other words, the FPGA only starts receiving configuration data after synchronization.
[0037] The bitstream file is stored in three regions within the flash chip: the jump control area (also called the jump control region), which includes the switching program and the jump program; and the application bitstream 1 area (also called the first application bitstream area) and the application bitstream 2 area (also called the second application bitstream area), which are used to store the application bitstream. The switching program is the synchronization header. When the FPGA starts up, it reads the synchronization header in the jump control area and jumps to load the application bitstream 2 area according to the bitstream jump program. If the FPGA starts up and does not read the synchronization header in the jump control area, the FPGA loads the application bitstream 1 area according to the address order.
[0038] In practical engineering, multiple FPGA boards of the same type (A board, also called the first FPGA board) in a chassis interact with a B board (also called the second FPGA board) in a middle slot via a backplane. This second FPGA board performs unified program upgrades on the other boards. To control the upgrade progress of the A board, the A board feeds back its upgrade progress to the B board using a flag. During the upgrade process, the B board transmits updated data to the A board based on the A board's buffer status flag. The buffer status flag is used by the B board for data flow control.
[0039] The flowchart of the FPGA remote update method of this invention is as follows: Figure 3 As shown, the method of the present invention will be described in detail below: Step 1: The B board will remotely update and send the startup command to the A board FPGA that needs to be upgraded via the backplane. Upon receiving the startup command, the A board FPGA reads the synchronization header data information from its respective flash jump area.
[0040] Step 2: Each FPGA on board A determines the area to be updated this time based on the synchronization header status. If the jump area synchronization header has been written, the last updated area is bit stream area 2 (also called application bit stream 2 area), and the current updated area is bit stream area 1 (also called application bit stream 1 area). Alternatively, if the jump area synchronization header has been erased, the last updated area is bit stream area 1, and the current updated area is bit stream area 2.
[0041] Step 3: The FPGA on board A begins erasing either bitstream region 1 or bitstream region 2 based on the determination result. Once the flash update region erasure is complete, the FPGA on board A sets the relevant erasure completion flag. The erasure completion flag is then fed back to board B via the backplane.
[0042] Step 4: Once board B has acquired all erase completion flags, it reads the buffer status flag from board A. When the status flag is idle, board B transmits a bitstream data packet to board A via the backplane; otherwise, it pauses and waits for a period before rereading the buffer status flag. This process continues until the bitstream data transmission is complete.
[0043] Step 5: After the update data is written, the FPGA control of board A reads the update data back from the flash memory and performs CRC verification on the read-back update data to obtain the CRC verification result.
[0044] Step 6: Determine the CRC check result.
[0045] If the CRC check is successful and the updated area is application bitstream 1, then the synchronization header of the jump control area is erased and the update completion flag is set. If the CRC check is successful and the updated area is application bitstream 2, then the synchronization header of the jump control area is written and the update completion flag is set.
[0046] If the CRC check fails, the update failure flag is set (the FPGA will continue to load the previously updated data on the next startup, without corrupting the data). Both the update success flag and the update failure flag are transmitted to the B board via the backplane bus. Finally, the B board prints out the serial numbers of the A boards that successfully completed the batch update and the A boards that failed the update.
[0047] Example 5: Please see Figure 4 As shown, the present invention also provides an electronic device 100 for a remote FPGA update method; the electronic device 100 includes a memory 101, at least one processor 102, a computer program 103 stored in the memory 101 and executable on the at least one processor 102, and at least one communication bus 104.
[0048] The memory 101 can be used to store the computer program 103. The processor 102 implements the steps of the FPGA remote update method described in Embodiment 1 by running or executing the computer program stored in the memory 101 and calling the data stored in the memory 101. The memory 101 may mainly include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as sound playback function, image playback function, etc.), etc.; the data storage area may store data created according to the use of the electronic device 100 (such as audio data), etc. In addition, the memory 101 may include non-volatile memory, such as hard disk, memory, plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, at least one disk storage device, flash memory device, or other non-volatile solid-state storage device.
[0049] The at least one processor 102 may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 102 may be a microprocessor or any conventional processor. The processor 102 is the control center of the electronic device 100, connecting various parts of the electronic device 100 via various interfaces and lines.
[0050] The memory 101 in the electronic device 100 stores multiple instructions to implement the FPGA remote update method, and the processor 102 can execute the multiple instructions to achieve the following: The Flash memory of the first FPGA board is divided into several regions, including a jump control region, a first application bit stream region, and a second application bit stream region. The second FPGA board sends the remote update command to the first FPGA board; After receiving the remote update command, the first FPGA board obtains the state of the jump control area synchronization header from the jump control area, and determines which application bit stream area to update based on the state of the jump control area synchronization header. The first FPGA board erases the data in the first application bitstream region or the second application bitstream region; After the data in the first application bitstream region or the second application bitstream region is erased, the second FPGA board will update the data and transmit it to the first FPGA board. The first FPGA board reads the updated data back from the Flash memory and performs CRC verification on the read-back updated data to obtain the CRC verification result. Based on the CRC check result, determine whether the remote update of the first FPGA board has been completed.
[0051] Example 6: If the modules / units integrated in the electronic device 100 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).
[0052] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0053] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0054] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0055] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.
Claims
1. A method for remotely updating an FPGA, characterized in that, Includes the following steps: The Flash memory of the first FPGA board is divided into several regions, including a jump control region, a first application bit stream region, and a second application bit stream region. The second FPGA board sends the remote update command to the first FPGA board; After receiving the remote update command, the first FPGA board obtains the state of the jump control area synchronization header from the jump control area, and determines which application bit stream area to update based on the state of the jump control area synchronization header. The first FPGA board erases the data in the first application bitstream region or the second application bitstream region; After the data in the first application bitstream region or the second application bitstream region is erased, the second FPGA board will update the data and transmit it to the first FPGA board. The first FPGA board reads the updated data back from the Flash memory and performs CRC verification on the read-back updated data to obtain the CRC verification result. Based on the CRC check result, determine whether the remote update of the first FPGA board has been completed.
2. The FPGA remote update method according to claim 1, characterized in that, The first FPGA board can be one FPGA board or several FPGA boards.
3. The FPGA remote update method according to claim 1, characterized in that, The second FPGA board sends a remote update command to the first FPGA board, specifically as follows: The second FPGA board sends remote update commands to the first FPGA board via the backplane.
4. The FPGA remote update method according to claim 1, characterized in that, The determination of which application bitstream region to update based on the state of the jump control region synchronization header specifically includes: If the jump control region synchronization header is read, then update the first application bit stream region; If the jump control area synchronization header is not read, then update the second application bit stream area.
5. The FPGA remote update method according to claim 1, characterized in that, The second FPGA board will transmit update data to the first FPGA board, specifically as follows: The second FPGA board transmits the update data to the first FPGA board via the backplane.
6. The FPGA remote update method according to claim 1, characterized in that, The determination of whether the remote update of the first FPGA board has been completed based on the CRC check result is as follows: If the CRC check is successful and the updated area is the first application bit stream area, then erase the jump control area synchronization header and set the update completion flag. If the CRC check is successful and the updated area is the second application bit stream area, then write the jump control area synchronization header and set the update completion flag bit. If the CRC check fails, the update failure flag is set.
7. The FPGA remote update method according to claim 1, characterized in that, Based on the CRC check result, after determining whether the remote update of the first FPGA board has been completed, the second FPGA board prints the serial number of the first FPGA board that was successfully updated and the serial number of the first FPGA board that failed to be updated.
8. An FPGA remote update system, characterized in that, include: The region partitioning module is used to divide the Flash memory of the first FPGA board into several regions, including a jump control region, a first application bit stream region, and a second application bit stream region. The command sending module is used by the second FPGA board to send remote update commands to the first FPGA board; The update region determination module is used to obtain the state of the jump control region synchronization header from the jump control region after the first FPGA board receives the remote update command, and determine which application bit stream region to update based on the state of the jump control region synchronization header; The erase module is used by the first FPGA board to erase data in the first application bit stream region or the second application bit stream region. The transmission module is used to transmit the update data from the second FPGA board to the first FPGA board after the data in the first application bit stream region or the second application bit stream region has been erased. The verification module is used by the first FPGA board to read back the updated data from the Flash memory and perform CRC verification on the read-back updated data to obtain the CRC verification result. The update module is used to determine whether the remote update of the first FPGA board has been completed based on the CRC check result.
9. An electronic device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the FPGA remote update method according to any one of claims 1 to 7.
10. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the FPGA remote update method according to any one of claims 1 to 7.