32-bit processor based on RISC-V instruction set architecture

Abstract

The invention discloses a 32-bit processor based on an RISC-V instruction set architecture, and belongs to the field of computer system structures and microprocessor design. According to the technical scheme adopted by the invention, the 32-bit processor based on the RISC-V instruction set architecture comprises an instruction set extension module, two new instructions of'aggresgate 'and'disaggresgate' are introduced, an R-type coding format is adopted, and the 32-bit processor is used for realizing grouping and splitting operation of data bits; the data path unit comprises a general register group, an arithmetic logic unit ALU and a special adder and is used for executing various data operations and processing; the control unit is used for generating a control signal according to an instruction decoding result and controlling operation of the data path unit and the memory; according to the method, by adding the special instruction and optimizing the data flow control mechanism, the complex bit operation is completed in a single period, the cache pressure is reduced, and the method has the advantages of improving the bit operation efficiency, reducing the instruction cache pressure and reducing the dynamic power consumption.

Description

Technical Field

[0001] This invention belongs to the field of computer architecture and microprocessor design, specifically relating to a 32-bit processor based on the RISC-V instruction set architecture. Background Technology

[0002] In the field of computer architecture, consumer electronics computing devices place stringent demands on system efficiency, low cost, and low power consumption. Currently, the embedded and IoT markets primarily rely on x86 and ARM architecture processors, with ARM architecture excelling in performance-power balance due to its streamlined nature. RISC-V, as an open-source instruction set architecture, is gradually becoming an alternative due to its modular design and scalability. However, existing RISC-V processors still have significant shortcomings in bit manipulation, particularly for complex bit grouping and splitting operations, which often require multiple instruction combinations. This not only leads to code bloat but also increases instruction cache pressure and dynamic power consumption. Although the industry has optimized some bit operations through instruction set extensions such as the B extension, there is still a lack of dedicated instruction support for specific operations like data bit grouping and splitting. Existing solutions typically require multiple shift and logical operation instructions, resulting in low execution efficiency and significantly increased processor power consumption. Furthermore, traditional RISC-V processors also have room for optimization in data flow control, particularly in instruction execution flow and cache pressure management. These issues severely limit the performance and energy efficiency of RISC-V processors in embedded and IoT applications. Summary of the Invention

[0003] This invention provides a 32-bit processor based on the RISC-V instruction set architecture to solve at least one of the aforementioned technical problems.

[0004] The technical solution adopted in this invention is as follows: A 32-bit processor based on the RISC-V instruction set architecture includes an instruction set extension module that introduces two new instructions, "aggregate" and "disaggregate," using an R-type encoding format to implement data bit grouping and splitting operations; a data path unit containing a general-purpose register set, an arithmetic logic unit (ALU), and a dedicated adder for performing various data operations and processing; a control unit that generates control signals based on instruction decoding results to control the operation of the data path unit and memory; memory for storing instructions and data; and a bidirectional data flow control mechanism to optimize the instruction execution process and reduce instruction cache pressure.

[0005] Furthermore, this application also proposes that, when the "aggregate" instruction is executed, it groups the data bits in the source register according to a specified mask and stores them in the target register.

[0006] Furthermore, this application also proposes that, when the "disaggregate" instruction is executed, it splits the data bits in the source register according to a specified mask and stores them in the target register.

[0007] Furthermore, this application also proposes that the general-purpose register group in the data path unit consists of 32 32-bit registers.

[0008] Furthermore, this application also proposes that the arithmetic logic unit (ALU) supports arithmetic operations, logical operations, and shift operations.

[0009] Furthermore, this application also proposes that the dedicated adder is used to quickly calculate the branch target address during the execution of branch instructions.

[0010] Furthermore, this application also proposes that the control unit, during instruction decoding, identifies and processes the newly introduced "aggregate" and "disaggregate" instructions.

[0011] Furthermore, this application also proposes that the memory adopts a Harvard architecture, with the instruction memory and data memory being independent of each other.

[0012] Furthermore, this application also proposes that, in the bidirectional data flow control mechanism, the data path unit can simultaneously perform data read and write operations within one clock cycle.

[0013] Furthermore, this application also proposes that the processor adopts a single-cycle structure, and each instruction is executed within one clock cycle.

[0014] Due to the adoption of the above technical solution, the beneficial effects achieved by this invention are as follows: By introducing the new "aggregate" and "disaggregate" instructions on the RISC-V instruction set architecture and adopting a single-cycle processor architecture design, several beneficial effects have been achieved. The new instructions optimize complex bit operations to be completed in a single cycle, avoiding the instruction bloat problem caused by combining multiple instructions in traditional solutions, effectively reducing instruction cache pressure and improving instruction execution efficiency. The single-cycle structure, combined with a dedicated adder and a bidirectional data flow control mechanism, enables the processor's various functional modules to work collaboratively, reducing redundant operations in the data path. This improves processing performance in scenarios such as branch prediction and reduces dynamic power consumption. The unified bit operation primitives formed by the inverse instructions simplify the bit operation-related programming process, allowing developers to more efficiently implement data grouping and splitting operations. At the same time, this architecture design controls hardware complexity while ensuring performance improvements, making it suitable for low-cost embedded device applications and providing a superior processor solution for fields such as the Internet of Things. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the RISC-V microarchitecture in this invention; Figure 2 This is a schematic diagram of the encoding of the aggregate instruction in this invention; Figure 3 This is a schematic diagram of the disaggregate instruction encoding of the present invention.

[0016] The accompanying drawings, which are provided to further illustrate the invention and constitute a part of this invention, are illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. Detailed Implementation

[0017] To more clearly illustrate the overall concept of the present invention, a detailed description will be provided below with reference to the accompanying drawings and examples.

[0018] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0019] Furthermore, in the description of this invention, it should be understood that the terms "top," "bottom," "inner," "outer," "axial," "radial," "circumferential," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0020] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0021] In this invention, unless otherwise expressly specified and limited, the first feature "on" or "below" the second feature may be in direct contact with the first and second features, or indirect contact through an intermediate medium. In the description of this specification, references to terms such as "implementation," "example," "aspect," "specific example," or "specific example" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0022] A 32-bit processor based on the RISC-V instruction set architecture includes an instruction set extension module that introduces two new instructions, "aggregate" and "disaggregate," using an R-type encoding format to implement data bit grouping and splitting operations; a data path unit containing a general-purpose register set, an arithmetic logic unit (ALU), and a dedicated adder for performing various data operations and processing; a control unit that generates control signals based on instruction decoding results to control the operation of the data path unit and memory; memory for storing instructions and data; and a bidirectional data flow control mechanism to optimize the instruction execution process and reduce instruction cache pressure.

[0023] This application adopts a single-cycle architecture design, dividing the processor into an instruction set extension module, a data path unit, a control unit, a memory, and a bidirectional data flow control mechanism. The instruction set extension module introduces two new instructions, "aggregate" and "disaggregate," using an R-type encoding format (fun7 is 0011000 or 0010000, opcode is 1101011). Instruction parsing is achieved through the combination of opcode and function code. The data path unit contains 32 32-bit general-purpose registers (R0 to R31, R0 is hardwired to 0), an arithmetic logic unit (ALU), and a dedicated adder. The ALU performs operations based on control signals, and the dedicated adder is used for PC increment and branch address calculation. The control unit generates 7 control signals (we, memread, memwrite, func3, pcsel, bsel, slsel) based on the instruction's opcode, func3, and Inst bits to control the collaborative work of each module. The memory adopts a Harvard architecture, with independent instruction and data memory, and an actual capacity of 16KB. The bidirectional data flow control mechanism achieves dynamic switching of the data path through selection lines such as pcsel, bsel, and slsel.

[0024] Instruction set extension modules refer to newly added hardware units that modify the instruction decoding logic. These can be implemented using a separate microcode controller and are used to identify and execute the specific opcodes of the newly added instructions. The general-purpose register set in the data path unit refers to a storage array used to temporarily store operands. This can be implemented using a multi-port register file, supporting simultaneous reading and writing of multiple registers. The bidirectional data flow control mechanism refers to the path design that allows bidirectional data transfer between functional units. This can be implemented using a crossbar switch structure, enabling read and write operations to be executed in parallel within the same clock cycle.

[0025] When the processor executes a grouping instruction, the control unit parses the instruction field and activates the bit processing circuitry in the arithmetic logic unit. Data in the source register is filtered by a mask selector, and the reassembled result is directly written to the target register. In data splitting scenarios, a dedicated adder works with a shifter to perform address calculations, while the general-purpose register bank uses a multiplexer to achieve parallel data access. The memory uses independent channels to transmit instructions and data, avoiding access conflicts. The bidirectional data flow mechanism optimizes data path timing, allowing operation results to be fed back to the register bank instantly, eliminating the time interval between read and write operations in traditional architectures.

[0026] This solution achieves equivalent functionality with a single instruction. In existing architectures, register reads and writes require time-sharing of the data bus. This solution achieves zero-latency data write-back through a bidirectional transmission mechanism, significantly shortening the instruction cycle, effectively reducing the number of instructions required for bit operations, lowering the instruction cache access frequency, and reducing the number of register accesses through parallel data path design. This hardware architecture, while maintaining the simplicity of RISC-V, significantly improves the execution efficiency of bit-intensive tasks, providing a more energy-efficient processor solution for embedded devices.

[0027] In a preferred embodiment of this application, the "aggregate" instruction, when executed, groups the data bits in the source register according to a specified mask and stores them in the target register.

[0028] The "aggregate" instruction uses R-type encoding and is triggered when fun7 is 0011000 and opcode is 1101011. During instruction execution, data is read from registers rs1 and rs2. Using the value of register rs2 as a mask, the data bits corresponding to the bits with a value of 1 in the mask are grouped to the right of the result, and those with a value of 0 are grouped to the left, while the bit order within each group remains unchanged. For example, when the mask is 0b1111000010101011, the bits with a mask value of 1 in the input data (bits 2, 6, 7, etc.) are selected and shifted to the right of the result, while the data corresponding to bits with a value of 0 are shifted to the left. The final result is stored in the rd register. The control unit generates control signals we=1, pcsel=00, bsel=000, and slsel=01 to drive the ALU to perform the grouping operation. The source register refers to the register that stores the input data; it can be implemented using a 32-bit register to provide the data bits to be processed. The destination register stores the output result and can be implemented as a 32-bit register to hold the grouped data. The specified mask defines the bit pattern for grouping data bits and can be implemented using immediate values ​​or mask values ​​stored in a register; it controls the extraction and combination of data bits. The grouping operation concatenates the scattered data bits in the source register into a continuous data block according to the mask. This can be achieved using a combination of multiplexers and shifters to reduce the number of clock cycles required for instruction execution.

[0029] After the `aggregate` instruction is decoded, the control unit generates the corresponding control signal, driving the data path unit to read data from the source register. The arithmetic logic unit filters the data bits in the source register according to the mask parameters in the instruction, extracting bits that meet the mask conditions sequentially and aligning them to the specified location in the target register through a shift operation. During this process, the mask parameters can be dynamically configured, for example, through the immediate numeric field in the instruction encoding or loaded from other registers. The grouped data is written to the target register, and subsequent instructions can directly use the result without additional operations.

[0030] This solution completes the above operations with a single instruction, eliminating the need for register temporary storage of intermediate results, reducing the number of instruction executions and register access frequency. It solves the problem of increased code size and power consumption caused by the bloat of bit operation instructions in existing technologies. By reducing the number of instructions, it lowers the instruction cache pressure and reduces dynamic power consumption. Taking the radix-2 sorting algorithm as an example, after using the aggregate instruction, the number of instructions for the key sorting steps is reduced from 24 to 3, the code size is reduced by 87.5%, the instruction cache pressure is reduced, the algorithm execution time is shortened by 40%, and the energy efficiency ratio is improved by 35%.

[0031] The "disaggregate" instruction, when executed, splits the data bits in the source register according to a specified mask and stores them in the target register. The disaggregate instruction is a bit splitting operation instruction based on the R-type encoding format, specifically defined by a combination of opcode and function code fields. This instruction directly performs the bit splitting operation through hardware circuitry, avoiding multiple instruction combinations at the software level. The source register is a 32-bit register storing the data to be processed, which can be implemented using any physical register in the general-purpose register set; its contents serve as the input data source for the bit splitting operation. Data bit splitting refers to the separation operation of data bits at specific positions according to mask parameters, specifically implemented using a combination of bit selection logic circuitry and shifters. The positions of the bits to be extracted are dynamically configured through the mask parameters. The specified mask is a binary control parameter used to indicate the bit splitting rules, specifically implemented by passing it through an immediate data field or auxiliary registers; bits set to 1 in the mask correspond to the target data bits to be retained. The target register is a 32-bit register storing the splitting result, specifically implemented using an idle register in the general-purpose register set, used to store the valid data after bit splitting.

[0032] Specifically, when the processor executes the `disaggregate` instruction, the control unit identifies the opcode of the instruction through the decoding circuit and generates the corresponding control signal sequence. After receiving the raw data from the source register, the arithmetic logic unit filters the data bits according to the mask parameters carried in the instruction, retaining the bits marked as valid by the mask. The shifter then aligns the valid bits to the low-order region of the target register, automatically filling the unselected high-order regions with zero values. The entire operation is completed within one clock cycle, and the processing result is written to the target register via the internal data bus, while simultaneously updating the processor status flags. The "disaggregate" instruction is encoded as fun7=0010000, opcode=1101011, and performs the inverse operation of aggregate. Data is read from the rs1 register, and rs2 is used as a mask. Bits of the input data are filled from right to left into the corresponding bits of the result according to the mask values ​​of 1, and the corresponding data bits are filled into the positions where the mask is 0, thus achieving bit splitting. For example, when the mask is 0b1111000010101011, the input data bits are sequentially filled into the 2nd, 6th, and 7th bits of the result, and the remaining bits are filled with the corresponding data. The result is stored in the rd register. The control unit generates the same control signal, but only the ALU operation logic is reversed.

[0033] This solution directly performs bit splitting operations using dedicated instructions, compressing the operation that originally required 3-5 instructions into a single instruction, effectively reducing instruction cache usage and memory access frequency. Simultaneously, the hardware implementation utilizes existing arithmetic logic unit circuits for functional expansion, eliminating the need for additional complex logic units. This effectively solves the instruction bloat problem caused by bit splitting operations, compressing bit operations that originally required multiple cycles into single-cycle execution, significantly reducing instruction cache pressure. At the hardware level, bit selection functionality is implemented by reusing existing arithmetic logic units, and instruction decoding logic is added to the control unit. While maintaining controllable hardware complexity, this reduces the number of register accesses and shift operations during dynamic execution, thereby lowering the processor's dynamic power consumption.

[0034] As a preferred example of the above implementation, the general-purpose register set in the data path unit consists of 32 32-bit registers. When executing instructions, the general-purpose register set receives register address signals from the instruction decoder, selects source operands from the 32 registers via a multiplexer, and writes the result back to the destination register. The 32-bit width of the register set is aligned with the processor's data path, allowing a single access operation to process 32 bits of data completely. When executing bit manipulation instructions, the register set can provide multiple operands simultaneously, avoiding additional memory accesses due to insufficient register count. The data path unit contains 32 32-bit general-purpose registers (R0 to R31), employing a dual-port read, single-port write structure. R0 is hardwired to logic 0; any write operation to R0 is invalid, and read operations always return 0. The register file reads data through ports RA1 and RA2, writes data through port WD, and the WEN signal controls write enable. For example, when the ADD instruction is executed, the values ​​of registers rs1 and rs2 are read through RA1 and RA2, the result is written to register rd through WD, and WEN=1 is active.

[0035] This solution maintains a match between the number of registers and their bit width, ensuring fast operand access during bit manipulation instruction execution while keeping hardware complexity under control. This reduces instruction sequence lengthening caused by insufficient register resources. This application supports parallel reading of multi-source operands for bit manipulation instructions, reducing data transfer overhead caused by register resource limitations during instruction execution, decreasing the processor's access frequency to the memory subsystem, thereby improving instruction execution efficiency and reducing dynamic power consumption.

[0036] The arithmetic logic unit (ALU) supports arithmetic operations, logical operations, and shift operations. Arithmetic operations involve adding, subtracting, multiplying, and dividing operands, which can be implemented using a multi-level carry chain structure combined with parallel computing units for numerical computation tasks. Logical operations involve performing Boolean operations such as AND, OR, NOT, and XOR, which can be implemented using multiplexers and combinational logic circuits for logical combination operations of data bits. Shift operations involve left shifting, right shifting, or cyclic shifting of data bits, which can be implemented using a barrel shifter structure for adjusting the position of data bits or extending their sign. The ALU module supports arithmetic operations (addition and subtraction), logical operations (AND, OR, XOR), and shift operations (logical left shift, arithmetic right shift), selecting the operation based on the func3 signal output by the control unit (e.g., 000 for addition, 001 for subtraction). For example, in the ADD instruction, func3=000, the ALU performs an addition operation on the inputs RD1 and RD2; in the SLL instruction, func3=001, a logical left shift is performed on RD1, with the shift amount determined by the immediate value. The ALU also participates in the conditional judgment of branch instructions and outputs the comparison result to the control unit.

[0037] Specifically, the Arithmetic Logic Unit (ALU) integrates arithmetic, logical, and shift operation modules to complete multiple operation types within a single cycle. The operation type is selected by the control unit based on the instruction decoding result, operands are obtained from the general-purpose register set through the data path, and the operation result is directly written to the target register. For example, when performing bit operations, the shift operation module works in conjunction with the logical operation module, completing an operation sequence that would require multiple shift and logical instructions in a traditional architecture with a single instruction.

[0038] This solution extends the ALU functional module, deeply integrating shift and logic operations, thus reducing the number of instructions and register accesses required for complex bit operations. This application effectively reduces instruction bloat in bit operation scenarios, decreases dynamic power consumption, and improves instruction execution efficiency, making it particularly suitable for embedded computing scenarios requiring frequent data bit rearrangement or conditional judgments.

[0039] As a preferred example of the above implementation, the dedicated adder is used to quickly calculate the branch target address when the branch instruction is executed.

[0040] A dedicated adder is a hardware module independent of the arithmetic logic unit (ALU). It can be implemented using a carry-select adder or a carry-lookahead adder, with an optimized circuit structure to shorten critical path latency. This adder is activated during the branch instruction decoding stage and works in parallel with the ALU, avoiding the consumption of ALU resources. Fast calculation of the branch target address involves adding the current value of the program counter to the offset carried in the instruction. This can be achieved by prefetching the offset and establishing a dedicated data path, allowing the address calculation to partially overlap with the instruction decoding stage. The ALU module supports arithmetic operations (addition, subtraction), logical operations (AND, OR, XOR), and shift operations (logical left shift, arithmetic right shift). The operation is selected based on the func3 signal output by the control unit (e.g., 000 for addition, 001 for subtraction). For example, in the ADD instruction, func3=000, the ALU performs addition on the inputs RD1 and RD2; in the SLL instruction, func3=001, logical left shift is performed on RD1, with the shift number determined by the immediate value. The ALU also participates in the conditional judgment of branch instructions and outputs the comparison results to the control unit.

[0041] Specifically, when the processor executes a branch instruction, the control unit parses the immediate offset value during the decoding phase and transmits it to a dedicated adder via a dedicated data path. The current value of the program counter is latched to the input of the dedicated adder on the rising edge of the clock and added to the offset. Because the dedicated adder employs an optimized carry chain design, its computational latency is less than the main ALU's operation cycle, allowing the branch target address to be calculated before the decoding phase ends. At this time, the arithmetic logic unit can continue to perform other data operations, achieving parallel utilization of computing resources.

[0042] Compared to existing technologies, traditional RISC-V processors require two steps in the ALU to calculate the address when executing branch instructions: first, the offset is added to the zero register to extend the sign bit, and then added to the program counter value. This process not only consumes ALU resources but also adds a clock cycle delay. This solution, however, uses a dedicated adder to achieve single-cycle address calculation, eliminating ALU resource contention and avoiding pipeline stalls caused by multi-cycle operations. This application effectively solves the problems of high address calculation latency and large resource consumption during branch instruction execution. In embedded applications where conditional branches frequently occur, this design can reduce pipeline bubbles, improve instruction throughput, and reduce dynamic power consumption caused by multi-cycle operations.

[0043] The control unit identifies and processes the newly introduced "aggregate" and "disaggregate" instructions during instruction decoding. The control unit receives 32-bit instructions, parses the Opcode (bits 0-6), func3 (bits 12-14), and Inst

[30] bits, and generates 7 control signals. For the new instructions "aggregate" and "disaggregate", when Opcode=1101011 and fun7 is 0011000 or 0010000, it is identified as an extended instruction, and the corresponding pcsel=00 (sequential execution), bsel=000 (selecting rs2 as the second operand of the ALU), and slsel=01 (selecting the ALU result to be written to the register) are generated. For example, when decoding the aggregate instruction, the control unit determines that it is an R-type instruction based on the Opcode, and fun7 and func3 are determined to be group operations, and generates control signals to drive the data path.

[0044] During instruction execution, after receiving the machine code from the instruction memory, the control unit first determines whether it is an aggregate or disaggregate instruction through decoding logic. When the corresponding opcode is detected, a dedicated control signal sequence is immediately activated, including register file read / write enable, ALU function selection, and data path switching control. This process optimizes the decoding path, enabling the identification of new instructions without additional clock cycles, directly generating control signals compatible with standard R-type instructions, while maintaining the decoding parallelism with the original instruction set.

[0045] This solution, by adding dedicated decoding logic, achieves complete parsing of complex bit operation instructions within a single cycle while maintaining controllable hardware complexity, avoiding multiple register accesses and intermediate control state switching. This application effectively solves the problem of frequent control signal switching caused by instruction bloat in bit operation scenarios. By generating a complete control sequence through a single decoding operation, it reduces the number of instruction cache accesses and the frequency of control state machine jumps, thereby reducing dynamic power consumption and improving instruction execution efficiency. As a preferred example of the memory, the memory adopts a Harvard architecture, where the instruction memory and data memory are independent. A Harvard architecture refers to an architecture where the instruction memory and data memory are physically isolated. Specifically, this can be implemented using independently addressed instruction and data memory modules, accessed through separate address and data buses. The independence of the instruction and data memories means that the two types of memory have independent access channels and control logic. This can be achieved through a dual-bus interface or dual-port memory design, avoiding bus conflicts between instruction read and data access operations. The memory adopts a Harvard architecture, with independent instruction and data memories. The 32-bit address lines theoretically support a 4GB capacity, but in practice, 16KB is implemented. The instruction memory reads instructions via the PC address, while the data memory reads and writes data via the ALU output address. The memread and memwrite signals are independently controlled. For example, in the LOAD instruction, the control unit generates memread=1, and the data memory reads data according to the address calculated by the ALU; in the STORE instruction, memwrite=1, writing data to the specified address.

[0046] During processor instruction execution, the instruction memory provides the instructions to be decoded to the control unit via an independent bus, while the data memory interacts with the data path unit via another independent bus. When the arithmetic logic unit performs operations, the data memory can simultaneously respond to data access requests, and the instruction prefetch unit can fetch the next instruction to be executed from the instruction memory in parallel. This parallel access mechanism can eliminate memory access conflicts in the traditional von Neumann architecture when processing dense data streams, such as in scenarios where IoT devices simultaneously perform sensor data acquisition and real-time control instruction parsing.

[0047] Compared to existing technologies, traditional RISC-V processors mostly employ a unified addressing von Neumann architecture, where instructions and data share memory space, leading to bus contention during the instruction fetch and data access phases. This solution, however, uses a physically isolated memory structure, allowing instruction prefetching and data loading operations to be completed in parallel within a single clock cycle. This effectively avoids pipeline stalls caused by memory access conflicts, especially when processing code segments containing numerous bit manipulation instructions.

[0048] Through the above technical solution, this application solves the access efficiency bottleneck problem caused by the shared storage bandwidth of instruction stream and data stream. In the scenario of embedded device performing real-time data processing, the parallel access capability of instruction memory and data memory enables the control unit to continuously obtain subsequent instructions, while the data path unit can complete the update operation of register data in a timely manner, thereby improving the overall throughput of the processor.

[0049] In the bidirectional data flow control mechanism, the data path unit can simultaneously perform data read and write operations within one clock cycle. The bidirectional data flow control mechanism refers to a data transmission architecture built using a crossbar switch or multiplexer, specifically implemented using a combination of bidirectional buffers and priority arbitrators, enabling the data path unit to process input and output operations in parallel. This mechanism optimizes the pipeline of instruction execution flow by eliminating serial dependencies in the data path. The synchronous execution of data read and write operations means that the read and write ports of the register group are configured independently. Specifically, this can be achieved using a dual-port register group combined with time-division multiplexing control logic, allowing the arithmetic logic unit's calculation result to be directly written to the target register while the source operand of the next instruction can be read in parallel from another register. This design effectively reduces the idle wait cycles required for instruction execution by eliminating register access conflicts. The bidirectional data flow control dynamically switches the data path using the pcsel, bsel, and slsel selection lines. `pcsel` (2 bits) selects the next PC value (PC+4, branch address, jump address); `bsel` (3 bits) selects the second ALU operand (RS2 register value, immediate value `immS / immI`, etc.); `slsel` (2 bits) selects register stack write input (ALU result, memory data, etc.). For example, in the `ADD` instruction, `bsel=000` selects the RS2 register, and `slsel=01` selects the ALU result; in the `STORE` instruction, `bsel=001` selects the `immS` immediate value as the offset.

[0050] During instruction execution, while the arithmetic logic unit reads source operands from the general-purpose register set, the write operation to the target register is performed synchronously through a dedicated data channel. For example, during the execution of the "aggregate" instruction, when the mask grouping module extracts data bits from the source register, the grouping result can be directly written to the target register through a bypass channel, avoiding the timing constraints of traditional architectures that require waiting for the register to be written before subsequent operations can proceed. This mechanism, through physically isolated read / write channels and a dynamic scheduling strategy, enables the data path unit to complete the entire process of operand reading, computation execution, and result writing within a single cycle.

[0051] Traditional RISC architecture processors are limited by the von Neumann bottleneck, allowing only unidirectional data transfer operations per clock cycle. For example, ARM Cortex-M series processors require time-sharing of the data bus when performing register read / write operations, resulting in wait cycles during instruction execution. This solution overcomes the unidirectional data transmission limitation of traditional data paths by constructing independent data read / write channels and an intelligent arbitration mechanism, while maintaining a single-cycle instruction architecture.

[0052] Through the above technical solution, this application effectively solves the problem of low instruction execution efficiency caused by serial data flow in traditional processors. By eliminating register access conflicts and bus contention, it significantly reduces the bubble cycle of the instruction pipeline, and achieves simultaneous improvement in instruction throughput and energy efficiency while keeping hardware complexity under control.

[0053] As a preferred embodiment of the processor, the processor adopts a single-cycle architecture, where each instruction is executed within one clock cycle. A single-cycle architecture means that the execution process of all instructions in the processor can be completed in just one complete clock cycle. Specifically, this can be achieved by using a unified clock signal to drive the seamless connection of the five stages: instruction fetch, decode, execution, memory access, and write-back. This simplifies hardware design complexity by eliminating the status registers and cycle switching logic found in multi-cycle architectures. Execution within a clock cycle means that the entire operation process of each instruction, from instruction fetch to write-back, is completed within one clock cycle. This can be achieved by optimizing the critical path latency of the data path and reducing the depth of combinational logic levels, thereby ensuring that the timing of all instructions meets the single-cycle constraint.

[0054] The processor employs a single-cycle architecture, where all instructions complete fetch, decode, execute, memory access, and write-back within a single clock cycle. The clock cycle length is determined by the longest path (e.g., for the LOAD instruction: fetch → decode → ALU address calculation → memory access → write-back), approximately 5ns. Each stage processes in parallel: PC increment and instruction fetch occur simultaneously, control unit decoding and data path operations occur in parallel, and memory access and write-back are synchronized. For example, the ADD instruction completes register fetch, ALU operation, and result write-back within one cycle, with no pipeline overhead.

[0055] In a single-cycle architecture, the instruction execution flow is designed with a fixed timing pattern. The control unit generates static control signals based on the instruction type, and the data path unit sequentially completes register reads, arithmetic operations, and result write-back after being triggered by a unified clock edge. For example, when executing an arithmetic logic instruction, the arithmetic logic unit receives the operands and completes the calculation immediately after the rising edge of the clock, and the result is written to the target register before the falling edge of the clock. For memory access instructions, the memory access operation and register read / write are completed within a single cycle through synchronous timing control. Thus, the latency of all instructions is strictly limited to one clock cycle, eliminating the need to wait for multi-cycle switching or pipeline flushing.

[0056] Traditional multi-cycle or pipelined processors require increasing the number of clock cycles or pipeline stages to improve instruction throughput, but this introduces additional penalties for branch prediction errors, pipeline conflict handling overhead, and dynamic power consumption. Single-cycle architectures, by eliminating cycle switching and pipeline buffering mechanisms, avoid pauses and energy waste caused by instruction dependencies, making them particularly suitable for embedded scenarios with high real-time requirements and controllable instruction complexity. This application effectively solves the clock resource waste problem caused by differences in the number of instruction execution cycles in multi-cycle processors, reduces dynamic power consumption by fixing the single-cycle execution mode, simplifies control logic and timing design, reduces hardware resource consumption, and provides a more efficient instruction execution infrastructure for low-power embedded devices.

[0057] For any parts not mentioned in this invention, existing technologies can be used or referenced.

[0058] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0059] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A 32-bit processor based on the RISC-V instruction set architecture, characterized in that, include: The instruction set extension module introduces two new instructions, "aggregate" and "disaggregate," which adopt the R-type encoding format and are used to implement the grouping and splitting of data bits. The data path unit includes a general-purpose register set, an arithmetic logic unit (ALU), and a dedicated adder, which are used to perform various data operations and processing. The control unit generates control signals based on the instruction decoding results to control the operation of the data path unit and the memory. Memory, used to store instructions and data; A two-way data flow control mechanism optimizes the instruction execution process and reduces instruction cache pressure.

2. A 32-bit processor based on the RISC-V instruction set architecture according to claim 1, characterized in that, When the "aggregate" instruction is executed, it groups the data bits in the source register according to the specified mask and stores them in the target register.

3. A 32-bit processor based on the RISC-V instruction set architecture according to claim 1, characterized in that, When the "disaggregate" instruction is executed, it splits the data bits in the source register according to the specified mask and stores them in the target register.

4. A 32-bit processor based on the RISC-V instruction set architecture according to claim 1, characterized in that, The general-purpose register group in the data path unit consists of 32 32-bit registers.

5. A 32-bit processor based on the RISC-V instruction set architecture according to claim 3, characterized in that, The arithmetic logic unit (ALU) supports arithmetic operations, logical operations, and shift operations.

6. A 32-bit processor based on the RISC-V instruction set architecture according to claim 1, characterized in that, The dedicated adder is used to quickly calculate the branch target address during branch instruction execution.

7. A 32-bit processor based on the RISC-V instruction set architecture according to claim 2, characterized in that, The control unit identifies and processes the newly introduced "aggregate" and "disaggregate" instructions during instruction decoding.

8. A 32-bit processor based on the RISC-V instruction set architecture according to claim 1, characterized in that, The memory adopts a Harvard architecture, with the instruction memory and data memory being independent of each other.

9. A 32-bit processor based on the RISC-V instruction set architecture according to claim 1, characterized in that, In the bidirectional data flow control mechanism, the data path unit can perform data read and write operations simultaneously within one clock cycle.

10. A 32-bit processor based on the RISC-V instruction set architecture according to claim 1, characterized in that, The processor adopts a single-cycle architecture, and each instruction is executed within one clock cycle.

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