Main and standby board card redundancy control method and system based on ARM instruction triggering
By adopting a primary/backup board redundancy control method based on ARM instructions, combined with PCIe switching and voltage monitoring, microsecond-level switching, intelligent fault diagnosis and safety protection are achieved. This solves the problems of high latency, weak decision-making ability and insufficient resource utilization in existing technologies, and improves the real-time performance and security of the system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-26
- Publication Date
- 2026-03-13
AI Technical Summary
Existing technologies in dual-redundant control suffer from problems such as high switching latency, weak intelligent decision-making capabilities, insufficient anti-interference and security, and inadequate resource utilization, making it difficult to achieve microsecond-level hardware triggering, intelligent fault diagnosis, and safety protection.
A primary/backup board redundancy control method based on ARM instruction triggering is adopted. The serial port forwarding module detects the level signal, and the ARM controller controls the state switching of the primary/backup processing module. The PCIe switching chip and voltage monitoring module are combined for real-time monitoring and fault diagnosis. A hardware-accelerated digital signature mechanism is introduced to achieve load balancing.
It greatly reduces switching latency, improves real-time performance and intelligent decision-making capabilities, enhances anti-interference capabilities and security, enables dynamic utilization of backup resources, and improves resource utilization.
Smart Images
Figure CN121658294A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of embedded system redundancy control technology, specifically relating to a primary / standby board redundancy control method and system based on ARM instruction triggering. Background Technology
[0002] Dual redundancy control technology is a core means of ensuring high reliability and business continuity for critical equipment, and it is widely used in scenarios such as industrial PLCs, 5G base stations, and battery management systems. Current mainstream solutions mainly revolve around software protocol redundancy and basic hardware redundancy architectures.
[0003] Software protocol redundancy relies on operating system scheduling and protocol stack parsing, detecting faults through periodic heartbeat messages. Its switching latency is typically in the milliseconds or even seconds, making it difficult to meet the real-time requirements of microsecond-level switching. Furthermore, the complexity of the software stack introduces potential latency jitter and reliability risks.
[0004] Basic hardware redundancy architectures focus on physical-level backup, using relays or MOSFET circuits for switching. However, such solutions often rely on simple level signals or bus state changes for triggering, lacking intelligent assessment of the overall system health. When faced with complex common-cause faults or systemic power anomalies, simple hardware switching may be ineffective or even harmful, and it lacks security protection against command interference or malicious injection.
[0005] Furthermore, regardless of the software or basic hardware solutions, their backup units are often completely offline or in deep hibernation under normal circumstances, resulting in idle computing resources and an inability to provide performance expansion when the system is under high load.
[0006] Therefore, existing technologies suffer from common problems such as high switching latency, weak intelligent decision-making capabilities, insufficient anti-interference and security, and inadequate resource utilization. There is an urgent need for a comprehensive redundancy control solution capable of microsecond-level hardware triggering, possessing intelligent fault diagnosis and security protection mechanisms, and enabling dynamic resource allocation. Summary of the Invention
[0007] To address the aforementioned technical problems, the present invention provides the following solution:
[0008] This invention provides a primary / standby board redundancy control method based on ARM instruction triggering, characterized in that it includes:
[0009] After the system is powered on, the ARM controller in the serial port forwarding module detects the level signal on the baseboard and distinguishes the main slot and the backup slot according to the high or low level of the level signal.
[0010] The ARM controller sends instructions to control the main processing module located in the main slot to enter the working state, and to control the backup processing module located in the backup slot to enter the standby state.
[0011] Control the PCIe switching chip to establish a communication link between the main processing module and the data communication module;
[0012] The voltage monitoring module monitors the voltage status of multiple modules on the board in real time.
[0013] When an abnormal voltage is detected on the board where the main processing module is located, the ARM controller sends a switching command to control the main processing module to enter standby mode and control the backup processing module to exit standby mode and start. At the same time, the PCIe switching chip switches the communication link to the backup processing module.
[0014] Furthermore, when the backup processing module is in standby mode, the following preparatory steps are performed:
[0015] In standby mode, the backup processing module has its operating system or underlying firmware loaded and running in low-power monitoring mode, suspending business processing, but maintaining synchronous monitoring with the main processing module in the shared memory area or communication bus.
[0016] The core power supply and memory power supply of the backup processing module are kept on, and the PCIe link layer and data link layer it manages are kept in an initialized state.
[0017] The physical link in the PCIe switching chip leading to the backup processing module has been pre-trained and synchronized.
[0018] Furthermore, the method also includes an intelligent fault diagnosis mode;
[0019] When the main processing module is in operation, if the voltage monitoring module detects an abnormal voltage on its board, the ARM controller performs correlation analysis based on the voltage values received from multiple boards and executes the following steps:
[0020] If the correlation analysis determines that a local fault has occurred, a primary / standby switchover command is triggered.
[0021] If the correlation analysis determines that the fault is a system-level fault, then the master / slave switchover command is suppressed and a system-level fault alarm is triggered.
[0022] Furthermore, the voltage anomaly includes overvoltage and undervoltage;
[0023] The logic for detecting voltage anomalies includes an invalid signal filtering mechanism based on a de-jitter delay window to ensure that the detected anomaly is a persistent level fault.
[0024] Furthermore, the correlation analysis is based on a preset fault arbitration strategy;
[0025] The local fault was arbitrated as a unit-level fault that only affected the main processing module;
[0026] The system-level failure was arbitrated as a domain-level failure occurring simultaneously on multiple boards marked as critical paths within the associated time window.
[0027] Furthermore, if the correlation analysis determines that a domain-level fault has occurred and the fault type is overvoltage, then the ARM controller invokes a preset global power management strategy.
[0028] The execution of the global power management strategy includes: suppressing primary / standby switching, triggering the highest priority system integrity alarm, and initiating a controlled emergency power-down sequence to the power management unit.
[0029] Furthermore, the method also includes a security enhancement mechanism;
[0030] Before sending the instruction or the switching instruction, the ARM controller performs the following steps:
[0031] A digital signature that performs hardware cryptographic acceleration on the instruction;
[0032] Send the instruction carrying the digital signature to the target processing module;
[0033] Upon receiving the instruction, the target processing module first verifies the validity of the digital signature, and only executes the operation indicated by the instruction after the signature verification is successful.
[0034] Furthermore, the method also includes a load balancing mode;
[0035] When the main processing module is in working state and the backup processing module is in standby state, if the ARM controller detects that the load parameter of the main processing module exceeds a first load threshold, the following steps are executed:
[0036] The ARM controller controls the standby processing module to exit the standby state and start up, entering the collaborative working state;
[0037] Control the PCIe switching chip to establish an auxiliary communication link between the backup processing module and the data communication module;
[0038] Some of the computing tasks of the main processing module are migrated to the backup processing module, and the two processing modules jointly handle the business.
[0039] Furthermore, the load parameters include at least one of the following:
[0040] The CPU utilization rate of the main processing module continuously exceeds the preset ratio;
[0041] The available memory capacity of the main processing module is lower than the preset capacity;
[0042] The number of tasks piled up in the main processing module exceeds the preset number.
[0043] A second aspect of the present invention provides a primary / standby board redundancy control system based on ARM instruction triggering, characterized in that the system comprises:
[0044] Base plate, used to install various modules;
[0045] At least two processing modules are mounted on the base plate;
[0046] At least one data communication module is mounted on the base plate and is communicatively connected to the processing module;
[0047] At least one serial port forwarding module is mounted on the base plate and is communicatively connected to the processing module;
[0048] The voltage monitoring module is mounted on the board of the processing module and the data communication module, and is connected to the serial port forwarding module via the I2C bus.
[0049] The ARM controller is configured to perform the steps of the method according to any one of claims 1 to 9.
[0050] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0051] 1. Significantly reduced switching latency and improved real-time performance: By bypassing the ARM instruction-level hardware triggering of the operating system and protocol stack, and combining the pre-synchronization mechanism of the PCIe link, the master-slave switching time is shortened from milliseconds to microseconds in traditional software solutions, solving the problem of high switching latency.
[0052] 2. Significantly enhances the system's intelligent decision-making and reliability: Through correlation analysis based on multi-source voltage and fault arbitration strategy, it can intelligently distinguish between local unit faults and global domain-level faults, thereby performing precise switching or suppressing switching and issuing alarms, effectively avoiding malfunctions under system-level faults and solving the defect of weak intelligent decision-making ability.
[0053] 3. Built-in hardware-level security protection enhances anti-interference capabilities: By introducing a hardware-accelerated digital signature and verification mechanism, the integrity and legitimacy of control commands are ensured, fundamentally preventing malicious command injection and interference, and overcoming the bottleneck of insufficient anti-interference and security.
[0054] 4. Dynamic utilization of backup resources has been achieved, improving resource utilization: Through load balancing mode, the standby processing module in standby state can take over some computing tasks when the main module is under high load, turning idle standby into performance expansion, and thoroughly improving the current situation of insufficient resource utilization. Attached Figure Description
[0055] Figure 1 This is a block diagram of the overall system architecture described in this invention;
[0056] Figure 2 This is a schematic diagram illustrating the connection and control of the PCIe switching chip described in this invention;
[0057] Figure 3 This is a flowchart illustrating the logical judgment process of the intelligent fault diagnosis mode described in this invention.
[0058] Figure 4 This is a flowchart illustrating the workflow of the load balancing mode described in this invention. Detailed Implementation
[0059] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0060] Example 1: System Basic Architecture and Workflow
[0061] This invention provides a primary / standby board redundancy control system based on ARM instruction triggering, the core components of which include:
[0062] A VPX system connection backplane, compliant with the VITA46 standard, provides power distribution, management bus, and PCIe data paths. This backplane features multiple VPX-compliant slots, with two specific processing module slots using different hardware routing for identification. Specifically, the GA0 management pin of the primary slot is permanently connected to a high level via a pull-up resistor, while the GA0 management pin of the secondary slot is permanently connected to a low level via a pull-down resistor. This hardware routing provides a reliable physical identification mechanism for the system.
[0063] Two identical processing modules are single-board computers compliant with the 6UVPX standard. The core components of each module include: a Loongson 3A5000 central processing unit, a 7A1000 bridge chip, and an ARM Cortex A53 coprocessor as an independent management unit. This ARM controller runs dedicated management firmware, responsible for executing the control logic of this invention, and has programmable GPIO pins for hardware control.
[0064] A data communication module, whose core uses a Xilinx Kintex7 series FPGA chip, is programmed to implement communication protocol conversion and data processing functions for 1188B high-speed bus, 1553B bus, and CAN bus. This module exchanges high-speed data with the processing module via a PCIe x4 link.
[0065] A serial port forwarding module adopts an FPGA+ARM architecture. The ARM controller communicates with the baseboard management controller of each processing module through the UART serial port, and at the same time, it uses the I2C bus as a master device to collect monitoring data from each board in the system.
[0066] The distributed voltage monitoring network consists of IPMB intelligent platform management submodules located on each board. Specifically, it uses ADI's ADM1276 hot-swap control and power monitoring chip to collect the voltage values of key power rails such as +12V, +5V, and +3.3V on this board in real time, with an accuracy of ±1%.
[0067] The system also includes a key PCIe switching chip, the Pericom PI3PCIe3412, which is a 4-channel, 2-port PCIe 3.0 switch. Its channel selection is directly controlled by the GPIO pins of the ARM controller of the serial port forwarding module.
[0068] The basic workflow after the system is powered on is as follows:
[0069] 1. Power-on and Identification: After all modules are powered on, the ARM controller of the serial port forwarding module first reads the GA0 pin level of its respective slot. The ARM controller of the processing module installed in the main slot detects a high level and identifies itself as the main processing module; the ARM controller of the processing module installed in the backup slot detects a low level and identifies itself as the backup processing module. This identification process is completed at the hardware level, with no software delay.
[0070] 2. Initial State Setup: The ARM controller of the serial port forwarding module sends IPMI 2.0 compliant instructions to the BMCs of both the main processing module and the backup processing module simultaneously via the UART serial port. It sends a PowerOn instruction to the main processing module to enable it to boot the operating system normally; and sends a PowerOff instruction to the backup processing module, which, combined with specific parameters, puts it into our defined hardware standby state.
[0071] 3. Communication Link Establishment: The ARM controller of the serial port forwarding module outputs a high level by configuring its GPIO8 pin. This signal is directly connected to the SEL pin of the PCIe switching chip, controlling it to connect the PCIe x4 link of the data communication module to the PCIe slot of the main processing module.
[0072] 4. Routine Monitoring and Switching: During system operation, each IPMB submodule transmits voltage data to the serial port forwarding module via the I2C bus at a frequency of 100Hz. The management firmware in the ARM controller presets the normal operating range for each voltage (e.g., the normal range for +12V is 11.4V~12.6V). When the +12V voltage of the main processing module is detected to be below 11.4V for 10 milliseconds, it is determined to be a voltage anomaly. Subsequently, the ARM controller executes switching instructions sequentially:
[0073] (1) Send a PowerOff command to the main processing module (BMC);
[0074] (2) Send the PowerOn command to the backup processing module (BMC);
[0075] (3) Change the GPIO8 pin level to low level to control the PCIe switching chip to switch the data link from the main processing module to the backup processing module. The entire switching process is completed in microseconds.
[0076] Example 2: Preparatory Steps for Quick Switching
[0077] This embodiment describes in detail the specific preparation measures of the backup processing module in standby mode, which is the key technology for achieving microsecond-level switching:
[0078] The hardware standby state is specifically the S3 (Sleep) sleep state defined by the ACPI standard. In this state, the Loongson CPU of the standby processing module suspends instruction execution, but its complete operating context (including all register states and memory data) is preserved in continuously powered DDR4 memory. The operating system kernel is in a state of suspended business processing but ready to load.
[0079] Synchronous monitoring is achieved through two mechanisms: First, a circular buffer is established in the shared memory area of the primary and backup processing modules. The primary processing module writes key status data (such as task queue pointer, network connection status, etc.) into this area every 1 millisecond. The memory controller of the backup processing module can still monitor access to this area in standby mode to maintain data synchronization. Second, the two maintain a 1kHz heartbeat communication through the management Ethernet bus of the backplane to ensure logical state synchronization.
[0080] The core power supply and memory power supply of the standby processing module are kept on by a dedicated power management IC in standby mode, while only the power domains of non-essential peripherals such as the display controller and USB controller are turned off, ensuring that the wake-up time from standby is less than 100 microseconds.
[0081] The PCIe link layer and data link layer it manages have completed full link training before entering standby mode and remain in a low-power L1 state, maintaining bit locking and symbol locking. At the same time, the physical link port in the PCIe switching chip leading to the standby processing module has completed link training during the system startup phase and remains in the L1 state, which is equivalent to a "paved but not yet open" highway, ensuring that there is no link training delay during switching.
[0082] Example 3: Intelligent Fault Diagnosis Mode
[0083] This embodiment details the system's intelligent decision-making capabilities, demonstrating its essential difference from traditional simple switching solutions.
[0084] The correlation analysis performed by the ARM controller is based on a pre-defined fault arbitration strategy. This strategy is implemented in the management firmware, and its logical flow is as follows:
[0085] 1. When an abnormal voltage is detected in the main processing module, the ARM controller immediately queries the voltage status of other boards (including the data communication module and the serial port forwarding module itself) marked as critical paths within the most recent 100-millisecond associated time window.
[0086] 2. Judgment and Arbitration:
[0087] If, within the relevant time window, only the main processing module reports undervoltage (voltage value below 11.4V for 10 milliseconds) or overvoltage (voltage value above 12.6V for 10 milliseconds), then the arbitration is considered a unit-level fault (i.e., a partial fault). At this time, the system triggers a standard primary / standby switchover command.
[0088] If the data communication module also reports undervoltage within the relevant time window, the arbitration is classified as a domain-level fault (i.e., a system-level fault). In this case, the system determines that the entire chassis's +12V input power supply has a common cause fault (such as a central power module failure), and switching to a backup board that also relies on this power supply is meaningless. Therefore, the ARM controller will suppress the triggering of the primary / backup switchover command and instead report a "CriticalPowerSupplyFailure" system integrity alarm to the remote management terminal via the IPMIOverLAN interface of the baseboard management controller.
[0089] As a more extreme form of protection, if the arbitration result is a domain-level fault and the fault type is overvoltage, this indicates that the central power module may be out of control, posing a risk of burning out all hardware. In this case, while executing the aforementioned suppression and alarm functions, the ARM controller will initiate a controlled emergency power-down sequence to the chassis's power management unit via the IPMI's PowerOff instruction. This sequence includes: first, notifying the operating system to save the emergency log; and then, forcibly cutting off power to the entire system within 10 milliseconds, achieving the highest level of safety protection.
[0090] 3. Anti-jitter mechanism: All the above-mentioned "voltage anomaly" judgments are based on the anti-jitter delay window. The management firmware performs digital filtering on the original voltage sampling data, requiring that the abnormal signal must continue to exceed the preset delay threshold (typically 10 milliseconds) to be confirmed as valid, thereby filtering out invalid interference signals caused by power supply ripple, instantaneous load changes, etc.
[0091] Example 4: Security Enhancement Mechanism
[0092] This embodiment details the hardware-level security measures introduced to prevent malicious instruction injection or interference.
[0093] Before sending any critical management commands, the ARM controller of the serial port forwarding module performs the following security procedures:
[0094] 1. Signature: The management firmware calls the hardware cryptographic acceleration engine built into the ARM chip to perform a hash operation on the plaintext instruction, timestamp, and 4-byte random number to generate a 32-byte digest. It then uses a private key pre-stored in the secure storage area to perform a digital signature, generating 256 bytes of signature data.
[0095] 2. Sending: Encapsulate the plaintext instruction, timestamp, random number, and digital signature together into an IPMI format data packet and send it to the BMC of the target processing module via the UART serial port.
[0096] 3. Verification: Upon receiving the instruction, the target BMC first verifies the validity of the digital signature using its pre-installed, paired public key, and simultaneously checks the freshness of the timestamp. Only if the signature verification passes and the timestamp is valid, proving that the instruction originated from a trustworthy source and has not been tampered with, will the BMC execute the instruction. Otherwise, the instruction will be immediately discarded, and an "AUTHENTICATIONFAILURE" security event will be recorded in the BMC's SEL.
[0097] Example 5: Load Balancing Mode
[0098] This embodiment demonstrates an innovative operating mode that improves system performance in a non-faulty state.
[0099] To fully utilize spare resources, the system supports load balancing mode. In this mode:
[0100] Triggering condition: The ARM controller of the serial port forwarding module periodically (twice per second) acquires the load parameters of the main processing module via the IPMI "SensorDataRecord" command. These parameters are provided by an agent program in the main processing module's operating system and include:
[0101] CPU utilization: Calculated using / proc / stat data, based on a preset percentage that exceeds 80% for 30 consecutive seconds.
[0102] Available memory capacity: obtained via / proc / meminfo, less than 15% of the total capacity (i.e., approximately 1.2GB of available memory).
[0103] Task queue backlog: The loadaverage (1-minute average) of the Linux system is consistently above 10.0.
[0104] Execution steps: When any parameter exceeds the first load threshold, the ARM controller executes the load balancing process:
[0105] 1. Send a PowerOn command to the standby processing module (BMC) to control it to exit standby mode and start normally into the operating system.
[0106] 2. Configure the GPIO8 pin to a specific level sequence (high-low-high). This sequence is interpreted by the PCIe switching chip as a "dual-active mode" command, enabling it to establish an auxiliary communication link between the backup processing module and the data communication module. At this point, the system forms a dual-active architecture, allowing both processing modules to access the data communication module simultaneously.
[0107] 3. Through the upper-layer Kubernetes cluster management software, after detecting the addition of a new node (backup processing module) to the cluster, it automatically migrates about 30%-50% of the computing tasks (such as specific NginxPods or database instances) on the main processing module to the backup processing module online through the kubectldrain and kubectlschedule commands. The two processing modules then jointly handle the business, thereby smoothly distributing the load and improving the overall throughput of the system.
[0108] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A method for controlling redundancy of primary and backup boards based on ARM instruction triggering, characterized in that, include: After the system is powered on, the ARM controller in the serial port forwarding module detects the level signal on the baseboard and distinguishes the main slot and the backup slot according to the high or low level of the level signal. The ARM controller sends instructions to control the main processing module located in the main slot to enter the working state, and to control the backup processing module located in the backup slot to enter the standby state. Control the PCIe switching chip to establish a communication link between the main processing module and the data communication module; The voltage monitoring module monitors the voltage status of multiple modules on the board in real time. When an abnormal voltage is detected on the board where the main processing module is located, the ARM controller sends a switching command to control the main processing module to enter standby mode and control the backup processing module to exit standby mode and start. At the same time, the PCIe switching chip switches the communication link to the backup processing module.
2. The method according to claim 1, characterized in that, When the backup processing module is in standby mode, the following preparatory steps are performed: In standby mode, the backup processing module has its operating system or underlying firmware loaded and running in low-power monitoring mode, suspending business processing, but maintaining synchronous monitoring with the main processing module in the shared memory area or communication bus. The core power supply and memory power supply of the backup processing module are kept on, and the PCIe link layer and data link layer it manages are kept in an initialized state. The physical link in the PCIe switching chip leading to the backup processing module has been pre-trained and synchronized.
3. The method according to claim 1, characterized in that, The method also includes an intelligent fault diagnosis mode; When the main processing module is in operation, if the voltage monitoring module detects an abnormal voltage on its board, the ARM controller performs correlation analysis based on the voltage values received from multiple boards and executes the following steps: If the correlation analysis determines that a local fault has occurred, a primary / standby switchover command is triggered. If the correlation analysis determines that the fault is a system-level fault, then the master / slave switchover command is suppressed and a system-level fault alarm is triggered.
4. The method according to claim 3, characterized in that, The voltage anomalies include overvoltage and undervoltage; The logic for detecting voltage anomalies includes an invalid signal filtering mechanism based on a de-jitter delay window to ensure that the detected anomaly is a persistent level fault.
5. The method according to claim 3, characterized in that, The correlation analysis is based on a preset fault arbitration strategy; The local fault was arbitrated as a unit-level fault that only affected the main processing module; The system-level failure was arbitrated as a domain-level failure occurring simultaneously on multiple boards marked as critical paths within the associated time window.
6. The method according to claim 3, characterized in that, If the correlation analysis determines that a domain-level fault has occurred and the fault type is overvoltage, then the ARM controller invokes a preset global power management strategy. The execution of the global power management strategy includes: suppressing primary / standby switching, triggering the highest priority system integrity alarm, and initiating a controlled emergency power-down sequence to the power management unit.
7. The method according to claim 1, characterized in that, The method also includes a security enhancement mechanism; Before sending the instruction or the switching instruction, the ARM controller performs the following steps: A digital signature that performs hardware cryptographic acceleration on the instruction; Send the instruction carrying the digital signature to the target processing module; Upon receiving the instruction, the target processing module first verifies the validity of the digital signature, and only executes the operation indicated by the instruction after the signature verification is successful.
8. The method according to claim 1, characterized in that, The method also includes a load balancing mode; When the main processing module is in working state and the backup processing module is in standby state, if the ARM controller detects that the load parameter of the main processing module exceeds a first load threshold, the following steps are executed: The ARM controller controls the standby processing module to exit the standby state and start up, entering the collaborative working state; Control the PCIe switching chip to establish an auxiliary communication link between the backup processing module and the data communication module; Some of the computing tasks of the main processing module are migrated to the backup processing module, and the two processing modules jointly handle the business.
9. The method according to claim 8, characterized in that, The load parameters include at least one of the following: The CPU utilization rate of the main processing module continuously exceeds the preset ratio; The available memory capacity of the main processing module is lower than the preset capacity; The number of tasks piled up in the main processing module exceeds the preset number.
10. A primary / standby board redundancy control system based on ARM instruction triggering for implementing the method as described in any one of claims 1 to 9, characterized in that, The system includes: Base plate, used to install various modules; At least two processing modules are mounted on the base plate; At least one data communication module is mounted on the base plate and is communicatively connected to the processing module; At least one serial port forwarding module is mounted on the base plate and is communicatively connected to the processing module; The voltage monitoring module is mounted on the board of the processing module and the data communication module, and is connected to the serial port forwarding module via the I2C bus. The ARM controller is configured to perform the steps of the method according to any one of claims 1 to 9.