A clock shift circuit, serializer, deserializer, and electronic device

Abstract

The application provides a clock shift circuit, a serializer, a deserializer and an electronic device. An input end of a delay unit is used for connecting an analog sampling clock. Output ends of the delay unit are respectively connected with control ends of a first shift unit and a second shift unit and a control end of a decision device. The output ends of the delay unit are also used for connecting a digital sending module. An input end of the first shift unit is used for connecting a first reference clock. An input end of the second shift unit is used for connecting a second reference clock. An output end of the first shift unit is connected with a first input end of the decision device. An output end of the second shift unit is connected with a second input end of the decision device. An output end of the decision device is connected with the control end of the delay unit. Even if the timing relationship is changed due to the changes of the temperature and voltage in the chip during the data transmission process, the timing relationship between the analog sampling clock and the data sending clock can be adjusted in real time, so that the data can be correctly sampled.

Description

Technical Field

[0001] This invention relates to the field of communications, and more specifically, to a clock shifter circuit, a serializer, a deserializer, and an electronic device. Background Technology

[0002] SERDES, short for SERializer and DESerializer, is a mainstream time-division multiplexing (TDM) point-to-point serial communication technology. At the transmitting end, multiple low-speed parallel signals are converted into high-speed serial signals, transmitted through a medium (optical fiber or copper wire), and finally converted back into low-speed parallel signals at the receiving end. This fully utilizes the channel capacity of the transmission medium, reduces the number of required transmission channels and device pins, increases signal transmission speed, and thus significantly reduces communication costs.

[0003] In a SERDES system, an analog transmission module is required to sample data from a digital transmission module. Specifically, after the SERDES data is sent by the digital transmission module, it is transmitted from the digital transmission path to the analog transmission module, and then sent out by the analog transmission module. The analog transmission module needs to sample the digital data at the digital-analog interface using an analog sampling clock. To ensure the accuracy of the sampling results, the analog sampling clock and the data transmission clock of the digital transmission module need to meet the set timing requirements. This has become one of the challenges that has attracted the attention of those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a clock shift circuit, a serializer, a deserializer, and an electronic device to improve the above-mentioned problems.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0006] In a first aspect, embodiments of the present invention provide a clock shifting circuit, the clock shifting circuit comprising: a delay unit, a first shifting unit, a second shifting unit, and a decision unit;

[0007] The input terminal of the delay unit is used to connect to the analog sampling clock, and the output terminal of the delay unit is connected to the control terminal of the first shift unit, the control terminal of the second shift unit, and the control terminal of the decision unit. The output terminal of the delay unit is also used to connect to the digital transmission module.

[0008] The input terminal of the first shift unit is used to connect to the first reference clock, and the input terminal of the second shift unit is used to connect to the second reference clock. The pulse width of the first reference clock and the pulse width of the second reference clock are the same as the pulse width of the analog sampling clock. The phase of the first reference clock lags behind the analog sampling clock, and the phase of the second reference clock lags behind the first reference clock.

[0009] The output of the first shift unit is connected to the first input of the decision unit, the output of the second shift unit is connected to the second input of the decision unit, and the output of the decision unit is connected to the control terminal of the delay unit.

[0010] The clock shift circuit can adjust the timing relationship between the analog sampling clock and the data transmission clock in real time. Even if the timing relationship changes due to on-chip temperature or voltage variations during data transmission, the correct data sampling can be ensured by adjusting the timing relationship between the analog sampling clock and the data transmission clock in real time.

[0011] Optionally, the delay unit is used to perform a shift operation on its input clock according to the shift signal output by the decision unit, and transmit the obtained data transmission clock to the digital transmission module, the first shift unit, the second shift unit and the decision unit;

[0012] The first shift unit is used to sample the first reference clock under the control of the data transmission clock, and send the obtained first sampling result to the decision unit after N cycles;

[0013] The second shift unit is used to sample the second reference clock under the control of the data transmission clock, and after N cycles, send the obtained second sampling result to the decision unit;

[0014] The decision unit is used to analyze the received first and second sampling results under the control of the data transmission clock to obtain the shift signal.

[0015] In each clock cycle, the first and second sampling results are analyzed to obtain the corresponding shift signal, and the timing relationship between the analog sampling clock and the data transmission clock is adjusted in real time.

[0016] Optionally, the decision unit is configured to output a shift signal indicating a left shift when both the first sampling result and the second sampling result are low;

[0017] The decision unit is used to output a shift signal indicating that the position remains unchanged when the first sampling result is low and both of the second sampling results are high.

[0018] The decision unit is used to output a shift signal indicating a right shift when the first sampling result is high.

[0019] By generating a corresponding shift signal for each digital clock cycle, the timing relationship between the analog sampling clock and the data transmission clock can be adjusted in real time.

[0020] Optionally, the clock shift circuit further includes a selector, which has M input terminals and two output terminals;

[0021] The m-th input terminal of the selector is used to receive the m-th clock signal, where 1≤m≤M, 2≤M, the pulse width of the M clock signals is the same as the pulse width of the analog sampling clock, and the phase lag of the M clock signals relative to the analog sampling clock increases sequentially.

[0022] The first output terminal of the selector is connected to the input terminal of the first shift unit, and the second output terminal of the selector is connected to the input terminal of the second shift unit.

[0023] The selector is used to switch its internal conduction relationship, transmitting the first reference clock to the first shift unit and the second reference clock to the second shift unit;

[0024] Wherein, the first reference clock is the clock signal connected to the input terminal of the selector that is connected to the first output terminal, and the second reference clock is the clock signal connected to the input terminal of the selector that is connected to the second output terminal.

[0025] It should be understood that by selecting clock signals with different phase lag levels as reference clocks, the adjustment accuracy of the clock shift circuit can be changed. When the phase lag is small, the adjustment accuracy is higher and the change frequency of the delay unit is higher; conversely, when the phase lag is large, the adjustment accuracy is lower, the change frequency of the delay unit is lower, and the energy consumption is lower.

[0026] Secondly, embodiments of the present invention provide a serializer, the serializer including the clock shift circuit described above.

[0027] Thirdly, embodiments of the present invention provide a deserializer, which includes the clock shift circuit described above.

[0028] Fourthly, embodiments of the present invention provide an electronic device, the electronic device including the serializer and / or deserializer described above.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is one of the structural schematic diagrams of a clock shift circuit provided in an embodiment of the present invention.

[0032] Figure 2 A clock signal timing diagram provided for an embodiment of the present invention.

[0033] Figure 3 This is a second schematic diagram of the clock shift circuit provided in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0036] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this invention, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0037] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0038] Please refer to Figure 1 , Figure 1This is one of the schematic diagrams of a clock shift circuit provided in an embodiment of the present invention. The clock shift circuit includes: a delay unit, a first shift unit, a second shift unit, and a decision unit. Both the first and second shift units include N cascaded D flip-flops, where N is greater than or equal to 2.

[0039] The input terminal of the delay unit is used to connect to the analog sampling clock. The output terminal of the delay unit is connected to the control terminal of the first shift unit, the control terminal of the second shift unit, and the control terminal of the decision unit. The output terminal of the delay unit is also used to connect to the digital transmission module (in the SERDES system).

[0040] The input terminal of the first shift unit is used to connect to the first reference clock, and the input terminal of the second shift unit is used to connect to the second reference clock. The pulse width of the first reference clock and the pulse width of the second reference clock are the same as the pulse width of the analog sampling clock. The phase of the first reference clock lags behind the analog sampling clock, and the phase of the second reference clock lags behind the first reference clock. The phase difference between any two of the analog sampling clock, the first reference clock, and the second reference clock can be 45° or 30°.

[0041] The output of the first shift unit is connected to the first input of the decision unit, the output of the second shift unit is connected to the second input of the decision unit, and the output of the decision unit is connected to the control terminal of the delay unit.

[0042] In the clock shift circuit provided in this embodiment of the invention, the timing relationship between the analog sampling clock and the data transmission clock can be adjusted in real time. Even if the timing relationship changes due to variations in on-chip temperature and voltage during data transmission, the data can still be correctly sampled by adjusting the timing relationship between the analog sampling clock and the data transmission clock in real time.

[0043] It can also reduce the complexity of extracting timing libraries in digital backend implementations.

[0044] Optionally, the delay unit is used to shift the input clock according to the shift signal output by the decision unit, and transmit the obtained data transmission clock to the digital transmission module, the first shift unit, the second shift unit, and the decision unit.

[0045] The digital transmission module is used to transmit digital data according to the data transmission clock, and the analog transmission module is used to sample the digital data according to the analog sampling clock.

[0046] It should be understood that the input clock of the delay unit (tx_dig_clk_shift shown in the figure) and the analog sampling clock (tx_ana_clk_0) are from the same source, but there is a certain phase difference between them due to the difference in the transmission path.

[0047] The shift operation can be left shift, right shift, or remain unchanged. It should be understood that during the first N cycles, the decision unit has no valid output, and the delay unit does not need to perform a shift operation on its input clock.

[0048] The first shift unit is used to sample the first reference clock under the control of the data transmission clock, and after N cycles (the cycle of the data transmission clock), the obtained first sampling result is sent to the decision unit.

[0049] The second shift unit is used to sample the second reference clock under the control of the data transmission clock, and after N cycles (the cycle of the data transmission clock), the obtained second sampling result is sent to the decision unit.

[0050] The decision unit is used to analyze the received first and second sampling results under the control of the data transmission clock (tx_dig_clk) to obtain the shift signal.

[0051] It should be understood that the first and second sampling results are analyzed in each clock cycle to obtain the corresponding shift signal, and the timing relationship between the analog sampling clock and the data transmission clock is adjusted in real time.

[0052] Optionally, the decision unit is used to output a shift signal indicating a left shift when both the first and second sampling results are low (0). The shift signal indicating a left shift can be represented as -1 in the figure.

[0053] The decision unit is used to output a shift signal that indicates that the first sampling result is low (0) and the second sampling result is high (1). The shift signal that indicates that the second sampling result is high (1) can be represented as 0 in the figure.

[0054] The decision unit is used to output a shift signal indicating a right shift when the first sampling result is high (1), regardless of whether the second sampling result is high (1) or low (0). The shift signal indicating a right shift can be represented as +1 in the figure.

[0055] Please refer to Figure 2 , Figure 2 A clock signal timing diagram provided for an embodiment of the present invention. Figure 2In this context, tx_ana_clk_0 represents the analog sampling clock, tx_dig_clk_shift represents the input clock of the delay unit, tx_dig_clk_shift and tx_ana_clk_0 are from the same source, but there is a slight phase lag or lead, tx_dig_clk represents the shifted digital transmission clock, tx_ana_clk_45 represents the first reference clock, tx_ana_clk_90 represents the second reference clock, the phase difference between tx_ana_clk_45 and tx_ana_clk_0 is 45°, and the phase difference between tx_ana_clk_90 and tx_ana_clk_45 is 45°.

[0056] It should be understood that when the digital transmission module sends digital data (data) according to tx_dig_clk_shift, and the analog transmission module samples according to tx_ana_clk_0, there may be insufficient sampling time, leading to inaccurate data. Therefore, a delay unit is introduced to perform a shift operation on tx_dig_clk_shift to obtain tx_dig_clk. The digital transmission module sends digital data (data) according to tx_dig_clk, and the analog transmission module samples according to tx_ana_clk_0, which improves data accuracy. However, changes in chip temperature or voltage may alter the timing relationship between tx_ana_clk_0 and tx_dig_clk, requiring real-time adjustments using tx_ana_clk_45 and tx_ana_clk_90.

[0057] Please continue to refer to this. Figure 2 At point A in the diagram, both the first and second sampling results are 1, and the decision unit outputs a shift signal (+1) indicating a right shift, requiring an increase in the phase lag of the digital transmission clock tx_dig_clk. At point B, both the first and second sampling results are 0, and the decision unit outputs a shift signal (0) indicating no change, requiring the phase of the digital transmission clock tx_dig_clk to remain unchanged. At point C, both the first and second sampling results are 0, and the decision unit outputs a shift signal (-1) indicating a left shift, requiring a decrease in the phase lag of the digital transmission clock tx_dig_clk.

[0058] Optionally, the first shift unit is used to sample the first reference clock on the rising edge of the data transmission clock, and send the obtained first sampling result to the decision unit after N cycles;

[0059] The second shift unit is used to sample the second reference clock on the rising edge of the data transmission clock, and after N cycles, sends the obtained second sampling result to the decision unit.

[0060] The decision unit is used to analyze the received first and second sample results on the rising edge of the data transmission clock to obtain the shift signal.

[0061] Please continue to refer to this. Figure 1 The first shift unit includes a first D flip-flop, a second D flip-flop, and a third D flip-flop.

[0062] The input of the first D flip-flop serves as the input of the first shift unit (used to connect to the first reference clock). The output of the first D flip-flop is connected to the input of the second D flip-flop. The output of the second D flip-flop is connected to the input of the third D flip-flop. The output of the third D flip-flop serves as the output of the first shift unit (connected to the first input of the decision unit).

[0063] The clock inputs of the first D flip-flop, the second D flip-flop, and the third D flip-flop serve as the control terminals of the first shift unit (connected to the data transmission clock tx_dig_clk).

[0064] D flip-flops are used to identify the signal at their input terminals when triggered by the rising edge of the data transmission clock, and output the identification result (high 1 or low 0) for a duration equal to the period of the data transmission clock. The identification process repeats on the next rising edge. It should be understood that there are N D flip-flops in the shift unit, and each D flip-flop identifies the signal. Therefore, when the first D flip-flop obtains its identification result, the Nth D flip-flop will output its result to the decision circuit after N cycles.

[0065] Please continue to refer to this. Figure 1 The second shift unit includes a fourth D flip-flop, a fifth D flip-flop, and a sixth D flip-flop;

[0066] The input of the fourth D flip-flop serves as the input of the second shift unit (used to connect to the first reference clock). The output of the fourth D flip-flop is connected to the input of the fifth D flip-flop. The output of the fifth D flip-flop is connected to the input of the sixth D flip-flop. The output of the sixth D flip-flop serves as the output of the second shift unit (connected to the first input of the decision unit).

[0067] The clock inputs of the fourth, fifth, and sixth D flip-flops serve as the control terminals of the second shift unit (connected to the data transmission clock tx_dig_clk).

[0068] Please refer to Figure 3 , Figure 3This is a second schematic diagram of the clock shift circuit provided in an embodiment of the present invention. In an optional embodiment, the clock shift circuit further includes a selector, which has M input terminals and two output terminals.

[0069] The m-th input of the selector is used to receive the m-th clock signal, where 1≤m≤M, 2≤M, and the pulse width of each of the M clock signals is the same as the pulse width of the analog sampling clock. The phase lag of the M clock signals relative to the analog sampling clock increases sequentially.

[0070] M clock signals include, but are not limited to, Figure 3 The phase lag of tx_ana_clk_45, tx_ana_clk_90, tx_ana_clk_135, tx_ana_clk_180, tx_ana_clk_225, tx_ana_clk_270 and tx_ana_clk_315 shown in the figure increases by 45° in sequence.

[0071] The first output of the selector is connected to the input of the first shift unit, and the second output of the selector is connected to the input of the second shift unit.

[0072] The selector is used to switch its internal conduction relationship, transmitting the first reference clock to the first shift unit and the second reference clock to the second shift unit.

[0073] Wherein, the first reference clock is the clock signal connected to the input terminal of the selector that is connected to the first output terminal, and the second reference clock is the clock signal connected to the input terminal of the selector that is connected to the second output terminal.

[0074] It should be understood that by selecting clock signals with different phase lag levels as reference clocks, the adjustment accuracy of the clock shift circuit can be changed. When the phase lag is small, the adjustment accuracy is higher and the change frequency of the delay unit is higher; conversely, when the phase lag is large, the adjustment accuracy is lower, the change frequency of the delay unit is lower, and the energy consumption is lower.

[0075] The present invention also provides a serializer, which includes the clock shift circuit described above.

[0076] This invention also provides a deserializer, which includes the clock shift circuit described above.

[0077] This invention also provides an electronic device, which includes the serializer and / or deserializer described above.

[0078] In summary, the clock shift circuit, serializer, deserializer, and electronic device provided by this invention have the following features: The input of a delay unit is connected to an analog sampling clock; the output of the delay unit is connected to the control terminals of a first shift unit, a second shift unit, and a decision unit, respectively; the output of the delay unit is also connected to a digital transmission module. The input of the first shift unit is connected to a first reference clock, and the input of the second shift unit is connected to a second reference clock. The pulse widths of both the first and second reference clocks are the same as the pulse width of the analog sampling clock. The phase of the first reference clock lags behind the analog sampling clock, and the phase of the second reference clock lags behind the first reference clock. The output of the first shift unit is connected to the first input of the decision unit, the output of the second shift unit is connected to the second input of the decision unit, and the output of the decision unit is connected to the control terminal of the delay unit. Even if the timing relationship changes due to variations in on-chip temperature and voltage during data transmission, the timing relationship between the analog sampling clock and the data transmission clock can be adjusted in real time to ensure that the data is correctly sampled.

[0079] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0080] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A clock shifting circuit, characterized in that, The clock shift circuit includes: a delay unit, a first shift unit, a second shift unit, and a decision unit; The input terminal of the delay unit is used to connect to the analog sampling clock, and the output terminal of the delay unit is connected to the control terminal of the first shift unit, the control terminal of the second shift unit, and the control terminal of the decision unit. The output terminal of the delay unit is also used to connect to the digital transmission module. The input terminal of the first shift unit is used to connect to the first reference clock, and the input terminal of the second shift unit is used to connect to the second reference clock. The pulse width of the first reference clock and the pulse width of the second reference clock are the same as the pulse width of the analog sampling clock. The phase of the first reference clock lags behind the analog sampling clock, and the phase of the second reference clock lags behind the first reference clock. The output of the first shift unit is connected to the first input of the decision unit, the output of the second shift unit is connected to the second input of the decision unit, and the output of the decision unit is connected to the control terminal of the delay unit. The delay unit is used to shift the input clock according to the shift signal output by the decision unit, and transmit the obtained data transmission clock to the digital transmission module, the first shift unit, the second shift unit and the decision unit; The first shift unit is used to sample the first reference clock under the control of the data transmission clock, and send the obtained first sampling result to the decision unit after N cycles; The second shift unit is used to sample the second reference clock under the control of the data transmission clock, and after N cycles, send the obtained second sampling result to the decision unit; The decision unit is used to analyze the received first and second sampling results under the control of the data transmission clock to obtain the shift signal; The decision unit is used to output a shift signal indicating a left shift when both the first sampling result and the second sampling result are low. The decision unit is used to output a shift signal indicating that the position remains unchanged when the first sampling result is low and both of the second sampling results are high. The decision unit is used to output a shift signal indicating a right shift when the first sampling result is high.

2. The clock shifting circuit as described in claim 1, characterized in that, The first shift unit is used to sample the first reference clock at the rising edge of the data transmission clock, and send the obtained first sampling result to the decision unit after N cycles; The second shift unit is used to sample the second reference clock at the rising edge of the data transmission clock, and after N cycles, send the obtained second sampling result to the decision unit; The decision unit is used to analyze the received first and second sampling results on the rising edge of the data transmission clock to obtain the shift signal.

3. The clock shifting circuit as described in claim 1, characterized in that, The first shift unit includes a first D flip-flop, a second D flip-flop, and a third D flip-flop; The input terminal of the first D flip-flop serves as the input terminal of the first shift unit, the output terminal of the first D flip-flop is connected to the input terminal of the second D flip-flop, the output terminal of the second D flip-flop is connected to the input terminal of the third D flip-flop, and the output terminal of the third D flip-flop serves as the output terminal of the first shift unit. The clock input terminals of the first D flip-flop, the second D flip-flop, and the third D flip-flop serve as the control terminals of the first shift unit.

4. The clock shifting circuit as described in claim 1, characterized in that, The second shift unit includes a fourth D flip-flop, a fifth D flip-flop, and a sixth D flip-flop; The input terminal of the fourth D flip-flop serves as the input terminal of the second shift unit, the output terminal of the fourth D flip-flop is connected to the input terminal of the fifth D flip-flop, the output terminal of the fifth D flip-flop is connected to the input terminal of the sixth D flip-flop, and the output terminal of the sixth D flip-flop serves as the output terminal of the second shift unit. The clock input terminals of the fourth D flip-flop, the fifth D flip-flop, and the sixth D flip-flop serve as the control terminals of the second shift unit.

5. The clock shifting circuit as described in claim 1, characterized in that, The clock shift circuit also includes a selector, which has M input terminals and two output terminals; The m-th input terminal of the selector is used to receive the m-th clock signal, where 1≤m≤M, 2≤M, the pulse width of the M clock signals is the same as the pulse width of the analog sampling clock, and the phase lag of the M clock signals relative to the analog sampling clock increases sequentially. The first output terminal of the selector is connected to the input terminal of the first shift unit, and the second output terminal of the selector is connected to the input terminal of the second shift unit. The selector is used to switch its internal conduction relationship, transmitting the first reference clock to the first shift unit and the second reference clock to the second shift unit; Wherein, the first reference clock is the clock signal connected to the input terminal of the selector that is connected to the first output terminal, and the second reference clock is the clock signal connected to the input terminal of the selector that is connected to the second output terminal.

6. A serializer, characterized in that, The serializer includes the clock shift circuit according to any one of claims 1-5.

7. A deserializer, characterized in that, The deserializer includes the clock shift circuit according to any one of claims 1-5.

8. An electronic device, characterized in that, The electronic device includes the serializer of claim 6 and / or the deserializer of claim 7.

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