Modeling method for SPICE (Single Event Effect) model of storage unit
By establishing a SPICE model of single-event effects in memory cells, neutron transport and transistor transient currents are simulated, solving the problem of predicting and locating the single-event effect of neutrons in SRAM chips. This provides guidance for radiation hardening design of SRAM chips and improves chip reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-27
- Publication Date
- 2026-03-13
AI Technical Summary
Existing technologies cannot effectively predict and locate the weak points of the single-event upset effect in SRAM chips, thus failing to guide radiation hardening design.
A SPICE model of single-event effect in a storage cell was established. Neutron transport was simulated using the Monte Carlo simulation software Geant4 to obtain the LET value of neutron secondary particles. The single-event transient current of the transistor was characterized by combining the TCAD model and the SPICE model and injected into the storage cell circuit model to realize the transmission of radiation damage from the microscopic to the macroscopic.
It enables the physical prediction of neutron single-event upset (SONE) effects in SRAM chips and the location of weak points, guiding the hardened design to resist SONE effects and improving the accuracy and reliability of circuit design.
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Figure CN121659862A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of radiation effect technology, and in particular to a modeling method for a storage cell single-event effect SPICE model. Background Technology
[0002] The aerospace field has brought great convenience to mankind in communication, navigation, and other fields. However, the environment in space is often extremely harsh. Without the shielding of the Earth's magnetic field and atmosphere, spacecraft are subjected to a large amount of radiation, which can lead to failure or crashes in severe cases. In a particle radiation environment, single-event effects are a typical effect that aerospace electronic equipment may encounter. SEUs caused by single-event effects can cause malfunctions in aerospace electronic equipment.
[0003] Static Random-Access Memory (SRAM) is widely used in various electronic circuits or integrated circuits because it has the characteristics of high operating speed and constant data retention without refresh when powered on, either as a standalone memory or embedded in digital and logic integrated circuits such as MCUs, CPUs, DSPs, and FPGAs.
[0004] Considering the cost and time required for iterative experiments in chip radiation hardening, there is a growing tendency to use radiation effect simulation analysis to design and implement radiation hardening for SRAM chips. However, current simulations cannot physically predict the neutron single-event upset (SOME) effect in SRAM chips, nor can they pinpoint the weak points that cause SOME to occur, which hinders the design of SRAM chips with neutron SOME resistance based on failure physics. Summary of the Invention
[0005] The purpose of this application is to provide a modeling method for the SPICE model of single-event effect in memory cells. This method can simulate and obtain the threshold value of single-event flip (LET) in memory cells, realize the physical prediction of neutron single-event flip effect in SRAM chips, and guide the hardening design of SRAM chips against neutron single-event flip effect based on failure physics.
[0006] This application provides a modeling method for a single-event effect (SPICE) model of a memory cell. The method includes: establishing a neutron transport model of a semiconductor material to obtain information about neutron secondary particles; establishing a mapping relationship between neutrons and neutron secondary particles to obtain the LET value of neutron secondary particles; using the LET value of neutron secondary particles as input parameters for TCAD simulation to obtain the single-event transient current of the transistor; characterizing the single-event transient current of the transistor in the form of an exponential current source; and injecting the exponential current source into the memory node in the memory cell SPICE circuit model to establish a single-event effect SPICE model of the memory cell.
[0007] In an optional implementation of this application, a neutron transport model for semiconductor materials is established using the Monte Carlo simulation software Geant4.
[0008] In an optional embodiment of this application, when establishing a neutron transport model of a semiconductor material using the Monte Carlo simulation software Geant4, the interaction between neutrons and the semiconductor material involves elastic scattering, inelastic scattering, and ejection processes; wherein, the ejection processes include (n, α), (n, p), neutron capture reactions, and nuclear fission reactions.
[0009] In an optional embodiment of this application, the neutron secondary particles include an initial recoil atom and a secondary recoil atom.
[0010] In an optional implementation of this application, if the LET value of the neutron secondary particle itself is greater than 5 times the critical LET value of the SRAM chip process node flip, then the neutron secondary particle is taken as a new incident particle, and the secondary recoil atoms generated by the new incident particle are counted.
[0011] In an optional implementation of this application, the LET value of the neutron secondary particle is obtained using SRIM software.
[0012] In an optional embodiment of this application, the method for obtaining the single-event transient current of a transistor includes: based on the normal transistor model, introducing a carrier mobility model, an SRH recombination model, and a heavy ion model to establish a transistor single-event effect TCAD model, using the LET value of neutron secondary particles as input parameters, and simulating to obtain the single-event transient current of the transistor.
[0013] In an optional implementation of this application, the normal transistor model is a three-dimensional TCAD model of an NMOS transistor and a PMOS transistor.
[0014] In an optional embodiment of this application, the method of characterizing the single-event transient current of a transistor by means of an exponential current source includes: using an exponential current source to simulate the transient current generated by the single-event effect of a transistor, and realizing the transient current injection corresponding to different LET values by modifying the magnitude of the final current.
[0015] In an optional embodiment of this application, the method for establishing a storage cell single-event effect SPICE model includes: using SPICE software to build a storage cell circuit netlist based on the storage cell circuit structure, simulating the normal operation of the storage cell circuit by adding excitation, and establishing a storage cell normal operation SPICE circuit model; injecting an exponential current source into the storage node in the storage cell normal operation SPICE circuit model to establish a storage cell single-event effect SPICE model.
[0016] The modeling method for the single-event effect SPICE model of memory cells provided in this application has at least the following advantages:
[0017] The SPICE modeling method for single-event effect in memory cells provided in this application is based on the physical process of radiation damage transmission from the microscopic to the macroscopic level. It uses a high-level model to proxy the low-level model, realizing the transmission and proxying of single-event irradiation damage level by level from the "material level - transistor level - unit circuit level". It can simulate and obtain the LET value threshold of single-event flip in memory cells, realize the physical prediction of neutron single-event flip effect in SRAM chips, trace and locate the weak link that causes single-event flip effect in SRAM chips caused by neutrons, and understand the physical nature of neutron single-event flip effect. It can be used to guide the design of SRAM chips to resist neutron single-event flip effect based on failure physics. Attached Figure Description
[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.
[0019] Figure 1 A flowchart of the modeling method for the single-event effect SPICE model of the storage cell provided in this application.
[0020] Figure 2 A simplified material model diagram for a 130nm transistor.
[0021] Figure 3 A statistical diagram showing the secondary particle information of one million 14MeV neutrons incident on silicon material.
[0022] Figure 4 Three-dimensional device model diagrams for PMOS and NMOS.
[0023] Figure 5 The IdVg characteristic curve of the MOS transistor in TCAD and its calibration diagram with the SPICE model are shown.
[0024] Figure 6 The diagram shows the single-event transient current of the NMOS drain under different LET values for incident particles.
[0025] Figure 7 The diagram shows the single-event transient current of the PMOS source under different LET values for the incident particle.
[0026] Figure 8 This is the core code diagram of the exponential current source introduced from the Q node by the single-event transient current in SPICE.
[0027] Figure 9 This is a circuit diagram of a six-transistor SRAM memory cell.
[0028] Figure 10 The figure shows the simulation results of each node in the SRAM six-transistor memory cell under normal conditions in SPICE.
[0029] Figure 11 The figure shows the simulation results of the single-event effect when the injected charge is 8.05fC.
[0030] Figure 12 The figure shows the simulation results of the single-event effect when the injected charge is 9.69fC.
[0031] Figure 13 The figure shows the simulation results of the single-event effect when the injected charge is 9.87fC.
[0032] Figure 14 The figure shows the simulation results of the single-event effect when the injected charge is 10.8fC. Detailed Implementation
[0033] During their research, the inventors discovered that current single-event effect (SEE) simulations lack a unified modeling framework that seamlessly couples material properties, transistor physical behavior, and memory cell logic functions. This prevents the modeling of radiation effects across the "material-transistor-cell circuit" hierarchy, allowing radiation damage to propagate from the microscopic to the macroscopic level. Particularly at the nanoscale, material-level factors such as interface states and doping fluctuations significantly influence charge collection behavior but are difficult to effectively transfer to the circuit-level model. This limits the accuracy of predicting macroscopic electrical performance degradation of circuits based on material-level micro-irradiation damage, hindering the improvement of physics-based radiation hardening technologies. Therefore, accurately locating the physical weaknesses of SRAM chips in SEE through simulation analysis can more effectively guide the design and implementation of SEE-resistant hardening.
[0034] To address the aforementioned problems, this application provides a modeling method for a storage cell single-event effect SPICE model, the method comprising:
[0035] A neutron transport model for semiconductor materials is established to obtain information about neutron secondary particles; a mapping relationship between neutrons and neutron secondary particles is established to obtain the LET value of neutron secondary particles; the LET value of neutron secondary particles is used as the input parameter for TCAD simulation to obtain the single-event transient current of transistors; the single-event transient current of transistors is characterized by an exponential current source; the exponential current source is injected into the storage node in the SPICE circuit model of the storage cell to establish the SPICE model of single-event effect of storage cell.
[0036] The modeling method for the single-event effect SPICE model of memory cells provided in this application is based on the physical process of radiation damage transmission from the microscopic to the macroscopic level. It uses the idea of a high-level model to proxy the low-level model, realizing the transmission and proxying of single-event irradiation damage level by level from the "material level - transistor level - unit circuit level".
[0037] Specifically, at the material level, information about neutron secondary particles is obtained by calculating the particle transport process of neutrons in semiconductor materials; the information about neutron secondary particles is used as input to obtain the LET value of neutron secondary particles, which is then used as input for the subsequent transistor single-event effect TCAD model.
[0038] At the transistor level, the LET value of neutron secondary particles is used as the input parameter for transistor single-event effect TCAD simulation to obtain the transistor single-event transient current caused by neutron secondary particles. The transistor single-event transient current is characterized in the form of an exponential current source, laying the foundation for SPICE modeling of single-event effects in memory cells.
[0039] At the unit circuit level, an exponential current source is injected into the storage node in the storage cell SPICE circuit model, thereby establishing the storage cell single-event effect SPICE model.
[0040] Therefore, by using the provided SPICE modeling method for single-event effect (SEE) of memory cells, the LET (Left-Oriented Event) value threshold of single-event flip (SEE) in memory cells can be simulated and obtained. The SPICE modeling method for SEE of memory cells provided in this application can not only evaluate the SEE effect in SRAM chips, but also locate the weak points of the SEE effect in SRAM chips, and trace the physical mechanism of the SEE effect in SRAM chips. This guides the hardening design of SRAM chips to resist SEE, and after expanding to other chip applications, it enables circuit designers to understand the chip operating boundaries caused by device process dispersion.
[0041] Figure 1 For a flowchart of the modeling method for the single-event effect SPICE model of the memory cell provided in this application, please refer to [link / reference]. Figure 1 The modeling method for the SPICE model of single-event effects in storage cells specifically includes the following steps:
[0042] S110, establish a neutron transport model for semiconductor materials to obtain information on neutron secondary particles.
[0043] The information obtained about neutron secondary particles is used as input for subsequent transistor single-event effect simulations.
[0044] S111, a neutron transport model for semiconductor materials was established using the Monte Carlo simulation software Geant4.
[0045] In some optional embodiments of this application, when establishing a neutron transport model of semiconductor materials using the Monte Carlo simulation software Geant4, the interactions between neutrons and semiconductor materials involved include: elastic scattering, inelastic scattering, and ejection processes; wherein, the ejection processes include (n, α), (n, p), neutron capture reactions, and nuclear fission reactions.
[0046] S112 obtains information about secondary neutron particles based on the neutron transport model of semiconductor materials.
[0047] In some optional embodiments of this application, if the LET value of the neutron secondary particle itself is greater than 5 times the critical LET value of the SRAM chip process node flip, then the neutron secondary particle is used as a new incident particle and continues to have a series of subsequent collisions with other surrounding atoms. In this continuous collision process, more secondary recoil atoms will be generated, and the secondary recoil atoms generated by the new incident particle will be counted.
[0048] In this case, the neutron secondary particles include the initial recoil atom (PKA) and the secondary recoil atom (SKA), and the obtained PKA and SKA information is used as input for subsequent transistor single-event effect simulations.
[0049] Furthermore, in some optional embodiments of this application, the critical LET value for the SRAM chip process node flip is determined by memory cell TCAD simulation.
[0050] S120 establishes a mapping relationship between neutrons and neutron secondary particles, and obtains the LET value of neutron secondary particles.
[0051] A mapping relationship between neutrons and neutron secondary particles was established to obtain the LET values of different neutron secondary particles. The LET values of neutron secondary particles were used to represent material-level irradiation damage information, which can then be used as input for subsequent transistor single-event effect TCAD models, laying the foundation for subsequent transistor single-event effect simulations.
[0052] In some optional embodiments of this application, the LET value of the neutron secondary particle is obtained using SRIM software. The LET value and range of the neutron secondary particle in the semiconductor material are calculated using SRIM and used as input for subsequent transistor single-event effect TCAD models.
[0053] In other feasible embodiments of this application, the LET value of the neutron secondary particle can also be obtained through other LET value calculation software.
[0054] S130 uses the LET value of the neutron secondary particle as the input parameter for TCAD simulation to obtain the transistor single-particle transient current.
[0055] By using the LET value of neutron secondary particles as the input parameter for TCAD simulation, the single-event transient current of the transistor is obtained, thus realizing the use of the single-event transient current of the transistor to substitute for the charge collection process in the transistor.
[0056] In some optional embodiments of this application, the method for obtaining the single-event transient current of a transistor includes: based on the normal TCAD model of the transistor, introducing a carrier mobility model, an SRH recombination model, and a heavy ion model to establish a single-event effect TCAD model of the transistor, using the LET value of the neutron secondary particle as an input parameter, and simulating to obtain the single-event transient current of the transistor.
[0057] Furthermore, in some optional embodiments of this application, the normal TCAD model of the transistor is a three-dimensional TCAD model of an NMOS transistor and a PMOS transistor.
[0058] In some optional embodiments of this application, the transistor normal state SPICE model is first verified based on the transistor normal state TCAD model provided by the process manufacturer, mainly by comparing the transfer characteristic curves of the two, with an error of less than 10%. Based on the transistor normal state TCAD model, a carrier mobility model, an SRH recombination model, and a heavy ion model are introduced, and the LET value of neutron secondary particles is used as input to establish a transistor single-event effect TCAD model, and the transistor single-event transient current caused by neutron secondary particles is simulated to obtain the result.
[0059] S140 characterizes the single-particle transient current of a transistor in the form of an exponential current source.
[0060] In some optional embodiments of this application, the method of characterizing transistor single-event transient current in the form of an exponential current source includes: using an exponential current source to simulate the transient current generated by the transistor single-event effect, and achieving transient current injection (i.e., different integrated charges) corresponding to different LET values by modifying the magnitude of the final current.
[0061] S150, inject an exponential current source into the storage node in the storage cell SPICE circuit model to establish the storage cell single-event effect SPICE model.
[0062] The obtained SPICE model of single-event effect in memory cells can be used to simulate and obtain the threshold value of single-event flip (LET) in memory cells, thus realizing the physical prediction of single-event flip effect in SRAM chips.
[0063] In some optional embodiments of this application, the method for establishing a storage cell single-event effect SPICE model includes: using SPICE software to build a storage cell circuit netlist based on the storage cell circuit structure, simulating the normal operation of the storage cell circuit by adding excitation, and establishing a storage cell normal operation SPICE circuit model; injecting an exponential current source into the storage node in the storage cell normal operation SPICE circuit model to establish a storage cell single-event effect SPICE model.
[0064] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall apply. Reagents or instruments whose manufacturers are not specified are all conventional products that can be purchased commercially.
[0065] Example
[0066] This embodiment provides a modeling method for a storage cell single-event effect SPICE model.
[0067] Taking 130nm SRAM chips as an example, existing research has shown that the weak link in the single-event effect of SRAM memory lies in the six-transistor memory cell structure used for information storage. Therefore, the essence of modeling the single-event effect in SRAM chips is to analyze whether the voltage of the memory cell node in the SRAM chip flips. The specific modeling process is as follows:
[0068] (1) A simplified three-dimensional material model of a 130nm transistor was established using the Monte Carlo simulation software Geant4 to analyze neutron transport processes, such as... Figure 2 As shown, the top layer is the encapsulation cover plate (Kovar alloy (Au)). 80 Sn 20 The internal materials of the chip, from top to bottom, are Si3N4 (400nm), SiO2 (800nm), Al (3μm), W (1.3μm), SiO2 (600nm), and Si. For ease of analysis, the volume of the Si sensitive region is set to 1μm. 3The radiation source is a unidirectional planar neutron source with a radius of 1 μm. The physical processes involved in the interaction between neutrons and semiconductor materials in the simulation mainly include elastic scattering, inelastic scattering, and ejection processes (including (n, α), (n, p), neutron capture reactions, and nuclear fission reactions). The neutron secondary particle information is recorded through the statistical module in the simulation software. If the LET value of the neutron secondary particle itself is greater than the LET value of the SRAM chip process node flip (determined through TCAD simulation of the memory cell, the flip-out critical LET value of the 130nm transistor is 1.18 MeV·cm⁻¹), the simulation results are considered. 2 If the initial recoil atom (PKA) is 5 times larger than that of 0.0262 pC / μm, it is treated as a new incident particle and continues to undergo a series of subsequent collisions with other surrounding atoms, producing secondary recoil atoms (SKA). The information of the initial recoil atom (PKA) and the secondary recoil atom (SKA) is used as the information of the neutron secondary particles, which is then used as the input for subsequent transistor single-event effect simulations.
[0069] The general-purpose materials neutron transport model simulation can obtain 1 million 14MeV neutrons incident orthogonally into a 1μm*1μm*1μm sensitive silicon material region from a 1μm radius planar source. Neutron secondary particle product information is as follows: Figure 3 As shown, there are 61 main secondary particle products.
[0070] (2) Using the information on neutron secondary products obtained from the Geant4 calculation as input, SRIM was used to calculate the LET values and ranges of Al-27, Al-28, α, Mg-24, Mg-25, Si-28, Si-29, and Si-30 with different energies. The simulation results are shown in Table 1. The results were compared by checking whether the neutron secondary particle energies were within the range where the LET value was greater than 1.18 MeV·cm⁻¹. 2 Within the range of / mg or 0.0262pC / μm (the critical LET value for single-event flip in SRAM chips), it can be seen that 21 secondary particle products resulting from the interaction of neutrons with semiconductor materials can cause SRAM flipping. The above work establishes the relationship between incident neutrons and neutron secondary products that cause SRAM flipping, that is, a mapping between 1 million neutrons and 21 neutron secondary particle products.
[0071] Table 1. SRIM calculation results of secondary particles in silicon materials subjected to 14MeV neutron incidence.
[0072]
[0073]
[0074] (3) Establish three-dimensional TCAD models of 130nm process NMOS transistors and PMOS transistors, such as Figure 4As shown, the transistor adopts an "H"-type gate structure, and the highest doping concentration of the source and drain is 2e⁻. 20 cm -3 (Using Gaussian doping), substrate doped with 6e 16 cm -3 The top silicon film thickness is 0.2 μm, the gate length is 0.13 μm, the gate width is 0.15 μm, and the substrate thickness below the buried oxide layer is 0.4 μm. After calibration, the electrical characteristic curves of the transistor's 3D TCAD model are consistent with the electrical characteristics of the standard transistor SPICE circuit model provided by the process manufacturer. A comparison of the Id-Vg characteristic curves of NMOS and PMOS transistors is shown below. Figure 5 As shown.
[0075] Based on the normal transistor model, a carrier mobility model, an SRH recombination model, and a heavy ion model are introduced to establish a transistor single-event transient current (TCAD) model. The LET value of neutron secondary particles is used as an input parameter to simulate and obtain the transistor's single-event transient current. The influence of incident particle LET on the drain transient current of NMOS and PMOS transistors is shown in the figure. Figure 6 and Figure 7 As shown.
[0076] (4) Based on the transistor single-event effect simulation results under different LET values, an exponential current source is used in SPICE to simulate the transient current generated by the single-event effect (ensuring that the pulse width, peak current, and total charge of the single-event transient current are equivalent in both simulations; at the SPICE simulation level, single-event flips only have a critical charge, which is the amount of charge generated by the memory cell under the LET value). The relevant code is as follows: Figure 8 As shown, the initial current is 0A, the final current is 3.4mA, introduced at 35ns with a rise time constant of 2ps, and begins to decrease at 35.001ns with a fall time constant of 5ps. Different amplitude transient current injections (i.e., different integrated charges) are achieved by modifying the magnitude of the final current.
[0077] (5) Based on SPICE, such as Figure 9 The circuit structure shown establishes a netlist for a six-transistor SRAM memory cell. Appropriate excitation signals are added to the SRAM memory cells to ensure normal operation, i.e., Q is 1.2V and QN is 0V. This establishes a normal SPICE model of the memory cell, and the simulation results are as follows. Figure 10 As shown, the voltage at the BL terminal is set to DC 1.2V, BLB to 0V, and WL is turned on at 5ns to write a high level of 1.2V to Q. WL is then turned off at 15ns, keeping Q at a high level of 1.2V and QN at a low level of 0V. Therefore, the SRAM memory cell circuit model works correctly.
[0078] Figure 9In the diagram, M1, M2, M5, and M6 are NMOS transistors, while M3 and M4 are PMOS transistors.
[0079] Based on the above work, an exponential current source of the equivalent transistor single-event effect is injected into the normal SPICE model of the memory cell to establish a SPICE model of the single-event effect of the memory cell. The single-event flip (LET) value threshold of the memory cell is obtained by simulation, and the physical prediction of the single-event flip effect of the SRAM chip is realized. Figure 11 , Figure 12 , Figure 13 and Figure 14 This section describes the single-event transient and flip-flop (SET) results of a six-transistor SRAM memory cell simulated using SPICE. Current is injected at the drain of transistor M1 (an off-state NMOS transistor), i.e., the Q-node, with a positive amplitude. When the integral of the injected transient current is 8.05 fC or 9.69 fC, the Q-node potential of the SRAM only shows a brief dip before returning to normal, while the QN-node potential exhibits the opposite behavior. However, when the integral of the transient current reaches 9.87 fC or higher, the Q-node potential changes from approximately 1.2 V to around 0 V, and the QN-node potential changes from around 0 V to 1.2 V, indicating a single-event flip. The single-event flip threshold charge is approximately 9.87 fC.
[0080] In summary, the SPICE modeling method for single-event effect of memory cells provided in this application can not only predict the single-event flip effect of neutrons in SRAM chips, but also trace and locate the weak links that cause the single-event flip effect of SRAM chips caused by neutrons, grasp the physical nature of the single-event flip effect of neutrons, and support the realization of SRAM chip hardening design based on failure physics.
[0081] The embodiments described above are some, but not all, of the embodiments of this application. The detailed description of the embodiments of this application is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
Claims
1. A modeling method for a single-event effect SPICE model of a storage cell, characterized in that, include: Establish a neutron transport model for semiconductor materials to obtain information about secondary neutron particles; Establish a mapping relationship between neutrons and the neutron secondary particles, and obtain the LET value of the neutron secondary particles; The LET value of the neutron secondary particle is used as the TCAD simulation input parameter to obtain the transistor single-particle transient current. The single-particle transient current of the transistor is characterized by an exponential current source. The exponential current source is injected into the storage node in the storage cell SPICE circuit model to establish the storage cell single-event effect SPICE model.
2. The modeling method for the single-event effect SPICE model of the memory cell according to claim 1, characterized in that, A neutron transport model for the semiconductor material was established using the Monte Carlo simulation software Geant4.
3. The modeling method for the single-event effect SPICE model of the memory cell according to claim 2, characterized in that, When using the Monte Carlo simulation software Geant4 to establish the neutron transport model of the semiconductor material, the interactions between neutrons and semiconductor materials involved include: elastic scattering, inelastic scattering, and the bounce process; The bomb removal process includes (n, α), (n, p), neutron capture reaction, and nuclear fission reaction.
4. The modeling method for the single-event effect SPICE model of the storage cell according to claim 1, characterized in that, The neutron secondary particles include initial recoil atoms and secondary recoil atoms.
5. The modeling method for the single-event effect SPICE model of the storage cell according to claim 4, characterized in that, If the LET value of the neutron secondary particle itself is greater than 5 times the critical LET value of the SRAM chip process node flip, then the neutron secondary particle is taken as a new incident particle, and the secondary recoil atoms generated by the new incident particle are counted.
6. The modeling method for the single-event effect SPICE model of memory cells according to any one of claims 1 to 5, characterized in that, The LET value of the neutron secondary particle was obtained using SRIM software.
7. The modeling method for the single-event effect SPICE model of memory cells according to any one of claims 1 to 5, characterized in that, The method for obtaining the single-event transient current of the transistor includes: Based on the normal TCAD model of the transistor, a carrier mobility model, an SRH recombination model, and a heavy ion model are introduced to establish a single-event effect TCAD model of the transistor. The LET value of the neutron secondary particle is used as the input parameter to simulate and obtain the single-event transient current of the transistor.
8. The modeling method for the single-event effect SPICE model of the memory cell according to claim 7, characterized in that, The standard TCAD model of the transistor is a three-dimensional TCAD model of NMOS transistor and PMOS transistor.
9. The modeling method for the single-event effect SPICE model of memory cells according to any one of claims 1 to 5, characterized in that, The method for characterizing the single-event transient current of the transistor in the form of the exponential current source includes: The exponential current source is used to simulate the transient current generated by the single-event effect of a transistor, and the transient current injection corresponding to different LET values is achieved by modifying the magnitude of the final current.
10. The modeling method for the single-event effect SPICE model of memory cells according to any one of claims 1 to 5, characterized in that, The method for establishing the single-event effect SPICE model of the memory cell includes: SPICE software is used to build a storage cell circuit netlist based on the storage cell circuit structure. By adding excitation, the normal operation simulation of the storage cell circuit is realized, and a normal SPICE circuit model of the storage cell is established. The exponential current source is injected into the storage node in the normal SPICE circuit model of the storage cell to establish a single-event effect SPICE model of the storage cell.