Memory, operation method of memory, memory system and chip

Abstract

The invention discloses a memory, an operation method of the memory, a memory system and a chip, and relates to the technical field of memory. The memory comprises a memory array and a peripheral circuit; a peripheral circuit configured to: in response to receiving the power-on signal, read a plurality of revised parameter copies from the memory array using a first read parameter, the plurality of revised parameter copies being copies stored for the revised parameter; the multiple correction parameter copies are corrected, correction parameters are output, the correction parameters are used for adjusting the first read parameters, and second read parameters are obtained when the storage array is read. The multiple read parameter copies are corrected through the multi-modular redundancy circuit, so that correction parameters which are more accurate and small in error probability are determined, after default reading parameters are adjusted through the correction parameters, reading parameters for reading other operating parameters are obtained, the reading accuracy of the operating parameters is improved, and the reading efficiency of the operating parameters is improved. And the problem of low reading reliability of the OTP memory in the power-on stage is avoided.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a memory, a method for operating the memory, a storage system, and a chip. Background Technology

[0002] Memory typically includes a memory array, which contains memory cells used to store data. During data retrieval from a memory, read parameters, such as reference voltage and reference current, are usually obtained first, and then used to read the data stored in the memory cell.

[0003] The data reading process of a memory typically includes steps such as address selection, address decoding, memory cell selection, data reading, and data output. Summary of the Invention

[0004] This application provides a memory, a method for operating the memory, a storage system, and a chip. The technical solution is as follows:

[0005] On the one hand, a non-volatile memory is provided, the non-volatile memory comprising: a memory array and peripheral circuitry;

[0006] The peripheral circuit is configured as follows:

[0007] In response to receiving a power-on signal, a plurality of correction parameter copies are read from the storage array using a first read parameter, the plurality of correction parameter copies being copies of the correction parameter storage;

[0008] The plurality of correction parameter copies are corrected, and the correction parameters are output. The correction parameters are used to adjust the first read parameters to obtain the second read parameters when reading the storage array.

[0009] In an optional embodiment, the non-volatile memory includes a one-time programmable (OTP) memory.

[0010] In an optional embodiment, the peripheral circuitry includes multi-mode redundancy sub-circuits;

[0011] The peripheral circuit is also configured as follows:

[0012] The multiple copies of the correction parameters are corrected by the multi-mode redundancy sub-circuit, and the correction parameters are output.

[0013] In an optional embodiment, the multi-mode redundancy sub-circuit includes a voter;

[0014] The peripheral circuit is also configured as follows:

[0015] The correction parameter is determined from the plurality of copies of the correction parameter by the voter in the multi-mode redundancy sub-circuit.

[0016] In an optional embodiment, each modified parameter copy includes n first read sub-addresses, and the parameter value of the i-th modified parameter copy is a combination of values ​​read from the n first read sub-addresses corresponding to the i-th parameter copy;

[0017] The peripheral circuit is also configured as follows:

[0018] Obtain the values ​​read from the kth first read sub-address of each correction parameter copy to obtain multiple values. Determine the value that appears most frequently from the multiple values ​​as the value of the kth bit of the correction parameter, where i, n and k are positive integers and k≤n.

[0019] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0020] Obtain multiple first read addresses, where the i-th first read address is used to indicate the location where the i-th copy of the correction parameter is stored in the memory array, and i is a positive integer;

[0021] The first read parameter is used to read the plurality of first read addresses in the storage array.

[0022] In an optional embodiment, the number of copies of the correction parameter corresponding to the correction parameter corresponds to the number of modules performing voting in the multimode redundancy subcircuit.

[0023] In an optional embodiment, the peripheral circuitry further includes: a register unit;

[0024] The peripheral circuit is also configured as follows:

[0025] Multiple copies of the m-th correction parameter are read from the storage array using the first read parameter, where m is a positive integer;

[0026] Correct multiple copies of the m-th correction parameter, output the m-th correction parameter; store the m-th correction parameter in the register unit to obtain the first m correction parameters;

[0027] If the correction parameters are not fully read, read multiple copies of the (m+1)th correction parameter from the storage array;

[0028] The multiple copies of the correction parameter for the (m+1)th correction parameter are corrected, and the (m+1)th correction parameter is output; the (m+1)th correction parameter is stored in the register unit to obtain the first (m+1)th correction parameters; until all correction parameters have been read.

[0029] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0030] The first read parameter is adjusted using the correction parameter to obtain the second read parameter;

[0031] The second read parameter is used to read the operating parameters in the memory array, which are data stored in the memory used to indicate chip operation.

[0032] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0033] Obtain a second read address, which indicates the location where the operating parameters are stored in the storage array;

[0034] The operating parameters are read from the second read address in the storage array using the second read parameter.

[0035] On the other hand, a volatile memory is provided, which is coupled to a non-volatile memory, and the volatile memory includes: a memory array and peripheral circuitry;

[0036] The peripheral circuit is configured as follows:

[0037] After the volatile memory is powered on, a power-on signal is sent to the non-volatile memory. The power-on signal is used to instruct the non-volatile memory to read multiple copies of correction parameters from the storage array of the non-volatile memory using a first read parameter, to correct the multiple copies of correction parameters, to output correction parameters, and to determine a second read parameter based on the correction parameters, and then to read the operating parameters through the second read parameter.

[0038] Receive the operating parameters sent by the non-volatile memory;

[0039] The storage array is read based on the operating parameters.

[0040] In an optional embodiment, the peripheral circuitry is coupled to the peripheral circuitry of the non-volatile memory;

[0041] The peripheral circuit is also configured as follows:

[0042] After the volatile memory is powered on, the power-on signal is sent to the peripheral circuitry of the non-volatile memory.

[0043] In an optional embodiment, the peripheral circuitry is further configured as follows:

[0044] The storage array is read based on the read voltage, read current, and time delay in the operating parameters.

[0045] In an optional embodiment, the non-volatile memory coupled to the volatile memory is implemented as a one-time programmable (OTP) memory.

[0046] On the other hand, a method for operating a non-volatile memory is provided, the method comprising:

[0047] In response to receiving a power-on signal, a plurality of correction parameter copies are read from the storage array using a first read parameter, the plurality of correction parameter copies being copies of the correction parameter storage;

[0048] The plurality of correction parameter copies are corrected, and the correction parameters are output. The correction parameters are used to adjust the first read parameters to obtain the second read parameters when reading the storage array.

[0049] In an optional embodiment, the non-volatile memory includes a one-time programmable (OTP) memory.

[0050] In an optional embodiment, reading multiple copies of correction parameters from the first storage array of the memory using the first read parameter includes:

[0051] Obtain multiple first read addresses, where the i-th first read address is used to indicate the location where the i-th copy of the correction parameter is stored in the memory array, and i is a positive integer;

[0052] Read from the plurality of first read addresses in the storage array using the first read parameter.

[0053] In an optional embodiment, each modified parameter copy includes n first read sub-addresses, and the parameter value of the i-th modified parameter copy is a combination of values ​​read from the n first read sub-addresses corresponding to the i-th parameter copy;

[0054] The step of correcting the plurality of copies of the correction parameters and outputting the correction parameters includes:

[0055] Obtain the value read from the kth first read sub-address of each copy of the correction parameter, and obtain multiple values;

[0056] The value that appears most frequently among the plurality of values ​​is determined as the value of the k-th bit of the correction parameter, where i, n, and k are positive integers and k ≤ n.

[0057] In an optional embodiment, the non-volatile memory includes a multi-mode redundancy sub-circuit, and the number of copies of the correction parameter stored corresponds to the number of modules performing voting in the multi-mode redundancy sub-circuit.

[0058] In an optional embodiment, the method further includes:

[0059] Multiple copies of the m-th correction parameter are read from the storage array using the first read parameter, where m is a positive integer;

[0060] Correct multiple copies of the m-th correction parameter and output the m-th correction parameter; store the m-th correction parameter to obtain the first m correction parameters;

[0061] If the correction parameters are not fully read, read multiple copies of the (m+1)th correction parameter from the storage array;

[0062] The multiple copies of the correction parameter of the (m+1)th correction parameter are corrected, and the (m+1)th correction parameter is output; the (m+1)th correction parameter is stored to obtain the first (m+1)th correction parameters; until all correction parameters have been read.

[0063] In an optional embodiment, after the output correction parameter, the following is further included:

[0064] The first read parameter is adjusted using the correction parameter to obtain the second read parameter;

[0065] The second read parameter is used to read the operating parameters in the storage array, which are data stored in the non-volatile memory used to indicate chip operation.

[0066] In an optional embodiment, reading the operating parameters in the storage array using the second read parameter includes:

[0067] Obtain a second read address, which indicates the location where the operating parameters are stored in the storage array;

[0068] The operating parameters are read from the second read address in the storage array using the second read parameter.

[0069] On the other hand, a storage system is provided, the storage system comprising:

[0070] One or more non-volatile memories or volatile memories as described in the above embodiments, and,

[0071] A memory controller coupled to the non-volatile memory or volatile memory and configured to control the non-volatile memory or volatile memory.

[0072] On the other hand, a chip is provided, the chip comprising:

[0073] One or more non-volatile or volatile memories as described in the above embodiments.

[0074] The technical solution provided in this application may include the following beneficial effects:

[0075] When performing a power-on reset read of the memory, the correction parameters related to the read operation are first read using the default read parameters. These correction parameters are stored as multiple copies during storage. These multiple copies are then read and corrected using a multi-mode redundancy circuit to determine more accurate correction parameters with a lower probability of error. After adjusting the default read parameters using these correction parameters, the read parameters for reading other operating parameters are obtained, improving the accuracy of reading operating parameters and avoiding the problem of low reliability in reading the OTP memory during the power-on phase. Attached Figure Description

[0076] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0077] Figure 1 This is a schematic diagram of the structure of an OTP memory provided in an illustrative embodiment of this application;

[0078] Figure 2 This is a schematic diagram of a reading process provided by an exemplary embodiment of this application;

[0079] Figure 3 This is a flowchart illustrating an exemplary embodiment of the present application of a method for operating a non-volatile memory;

[0080] Figure 4 Based on Figure 3 A schematic diagram of a multimode redundancy circuit provided in the illustrated embodiment;

[0081] Figure 5 Based on Figure 3 A schematic diagram of OTP current control provided in the illustrated embodiment;

[0082] Figure 6 This is a flowchart of an operation method for a non-volatile memory provided in another exemplary embodiment of this application;

[0083] Figure 7 Based on Figure 6 The illustrated embodiment provides a schematic diagram of the reading process;

[0084] Figure 8 This is a flowchart of an operation method for a non-volatile memory provided in another exemplary embodiment of this application;

[0085] Figure 9 This is a schematic diagram of the structure of a memory provided in an exemplary embodiment of this application;

[0086] Figure 10 This is a schematic diagram of the structure of a storage system provided in an exemplary embodiment of this application;

[0087] Figure 11 This is a schematic diagram of the structure of a memory provided in another exemplary embodiment of this application. Detailed Implementation

[0088] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0089] First, the terms used in the embodiments of this application will be introduced.

[0090] One-Time Programmable (OTP) memory is a type of non-volatile memory with at least the following characteristics: 1. Programmability: OTP memory can be programmed during the manufacturing process, and once programmed, its contents cannot be changed. Programming can be achieved through methods such as electron injection or burning out connectors. 2. Non-Volatile: OTP memory is a non-volatile memory, meaning it retains data even after power failure or restart. 3. High Reliability: Because the stored data cannot be changed after programming, OTP memory has high reliability. It is not affected by electromagnetic interference, temperature changes, or power failures. 4. Low Power Consumption: OTP memory typically has low power consumption because it does not require an external power supply to maintain the stored data.

[0091] The working principle of OTP memory is relatively simple. During the programming process of OTP memory, electron injection or burning out of the connector changes the electrical characteristics of the memory cell, making it logically represent a specific data bit. These data bits can be read, but cannot be changed again.

[0092] In summary, OTP memory is a non-volatile memory that can only be programmed once. It is widely used in many applications, such as security authentication, key storage, and firmware code storage.

[0093] Multi-mode redundancy circuit: It can be implemented as a triple modular redundancy (TMR) circuit, a quadruple modular redundancy (QMR) circuit, etc. The embodiments of this application do not limit the number of modules that perform voting in the multi-mode redundancy circuit.

[0094] Multimode redundancy circuits improve system reliability by adding redundant components or modules. In this embodiment, the multimode redundancy circuit includes multiple voting modules. These modules correct the correction parameters to obtain corrected parameters, which are then used to adjust the read parameters. Based on these adjusted parameters, the data stored in the memory array is read, thereby improving the accuracy of reading from the memory array and avoiding errors caused by process voltage and temperature (PVT) during power-on. This improves the accuracy and efficiency of data reading.

[0095] Power-on reset read (POR_READ): refers to the behavior of reading and accessing non-volatile memory during system power-on reset.

[0096] The memory reading method provided in this application embodiment can be applied to non-volatile memory. This non-volatile memory can be an OTP memory.

[0097] In this embodiment, the non-volatile memory is implemented as an OTP memory as an example for explanation. Figure 1 This is a schematic diagram of the structure of an OTP memory provided in an illustrative embodiment of this application.

[0098] An OTP memory includes peripheral circuitry and a storage array. The peripheral circuitry controls the operation of the OTP memory, while the storage array stores data.

[0099] like Figure 1 As shown, it mainly illustrates a schematic diagram of a storage array 100 in an OTP memory, which includes multiple storage cells arranged in an array.

[0100] The memory cells in an OTP memory mainly include control grid (CG) cells and memory grid (MG) cells. The MG cell is a thick gate oxide device that can be broken down by high voltage. The MG cell is programmable; when programming is successful, the MG cell will be permanently enabled.

[0101] The OTP memory's storage array is implemented as a two-dimensional storage array, including rows and columns, wherein... Figure 1 Taking the illustrated memory array 100 as an example, the column direction of the memory cells is coupled to the bit line (BL), and the row direction of the memory cells is coupled to the control gate CG or the memory gate MG. The row direction of the control gate cells is coupled to the CG, and the row direction of the memory gate cells is coupled to the MG. A specific memory cell in the memory array can be located using the CG, MG, and BL.

[0102] like Figure 1 As shown, the selected positioning line BL <3> Select control gate CG <1> and selected storage gate MG <1> Then, the storage units 101 and 102 are located and read.

[0103] During POR_READ reading, the decoder receives position data and decodes it to obtain CG, MG, and BL coupled to the storage unit, thereby locating the storage unit to be read and obtaining the reading path based on the storage unit to be read. The reading path includes a sensing amplifier, which inputs 1 or 0 depending on whether the storage unit is broken down.

[0104] The decoder and sensing amplifier mentioned above are implemented as sub-circuits in the peripheral circuit.

[0105] In related technologies, POR_READ reading is performed by directly executing the read phase after power-on reset. (Illustrative example) Figure 2 A schematic diagram of a reading process provided by an exemplary embodiment of this application is shown. The reading process includes the following step 210.

[0106] Step 210: Read the addresses 1, 2, ..., M corresponding to the multiple parameters.

[0107] In other words, the system reads the addresses corresponding to multiple parameters from the OTP memory array using the default read parameters after power-on reset, and then reads the parameters from those addresses. Specifically, address 1 reads parameter 1, address 2 reads parameter 2, and address M reads parameter M, where M is a positive integer. There is a one-to-one correspondence between the addresses and the parameters.

[0108] The default read parameters are the uncorrected read parameters used by the OTP memory during the power-on reset phase. That is, regardless of the chip's process technology, voltage, or temperature, the default read parameters are used for reading.

[0109] OTP memory typically stores the operating parameters of the chip, such as chip configuration parameters and operating code. During the power-on reset (POR) read operation of the OTP memory, since the power has just been turned on, the default read parameters programmed in the metal layer are used to read the data stored in the OTP memory.

[0110] However, due to the influence of process voltage and temperature (PVT), the default read parameters are biased, which leads to low accuracy of power-on reset read results for OTP memory.

[0111] In this embodiment, the peripheral circuit also includes a multi-mode redundancy sub-circuit. During parameter reading in the POR_READ stage, multiple copies of corrected parameters are first read, and then the multi-mode redundancy circuit is used to correct these copies to obtain corrected parameters. The read parameters for reading the OTP storage array are adjusted using the corrected parameters to obtain the corrected read parameters, and the OTP storage array is then read based on these corrected read parameters.

[0112] Figure 3 This application provides an exemplary embodiment of an operation method for a non-volatile memory, which can be executed by peripheral circuitry of the non-volatile memory. The method includes at least the following steps.

[0113] Step 320: In response to receiving a power-on signal, read multiple copies of correction parameters from the storage array using the first read parameters.

[0114] Multiple copies of the correction parameter are copies of the correction parameter storage.

[0115] In some embodiments, when there are multiple correction parameters, each correction parameter corresponds to multiple correction parameter copies. For example, assuming each correction parameter corresponds to three correction parameter copies, correction parameter a corresponds to correction parameter copy a', correction parameter copy a”, and correction parameter copy a”'; correction parameter b corresponds to correction parameter copy b', correction parameter copy b”, and correction parameter copy b”'.

[0116] In some embodiments, the correction parameter copy is data written to the memory cell during the programming phase of the non-volatile memory. Multiple correction parameter copies are written for each correction parameter during the programming phase. When writing correction parameter copies, multiple copies are written according to the value of the correction parameter. This can be understood as multiple correction parameter copies having the same value when written.

[0117] In some embodiments, each correction parameter corresponds to a different PVT condition. Schematic, there exists a correction parameter a corresponding to process 1, voltage 5V and temperature 40°, and correction parameter a has correction parameter copies a', a”, and a”' stored in the storage array; there exists a correction parameter b corresponding to process 1, voltage 10V and temperature 50°, and correction parameter b has correction parameter copies b', b”, and b”' stored in the storage array.

[0118] Optionally, after receiving the power-on signal, the non-volatile memory first obtains the currently running PVT information and obtains the storage location of the correction parameter with the highest matching degree with the PVT information. The storage location refers to the location of the multiple copies of the correction parameter corresponding to the correction parameter in the storage cell of the storage array, and then reads the copy of the correction parameter of the correction parameter from the storage array based on the storage location.

[0119] Optionally, the power-on signal includes the PVT information, or the non-volatile memory reads the PVT information from a preset storage space based on the power-on signal. Schematic, the non-volatile memory reads the PVT information from a register of a chip (e.g., a volatile memory) coupled to the non-volatile memory based on the power-on signal, or the non-volatile memory reads the PVT information from a register of its own peripheral circuitry based on the power-on signal. This application does not limit the method of obtaining the PVT information.

[0120] In some embodiments, the running program of the non-volatile memory includes a correspondence between PVT information and the storage location of the correction parameter copy. The storage location of the correction parameter copy is located from the correspondence based on the read PVT information, thereby reading multiple correction parameter copies.

[0121] In this embodiment, the aforementioned non-volatile memory includes a one-time programmable (OTP) memory. This OTP memory is coupled to other chips. Schematic, the OTP memory is coupled to a Dynamic Random Access Memory (DRAM) to store the DRAM's operating parameters; illustratively, the OTP memory stores data such as the DRAM's process parameters, model parameters, operating voltage, and operating current. Alternatively, the OTP memory is coupled to a Central Processing Unit (CPU) to store data such as the CPU's process parameters, model parameters, and running programs. This application does not limit the chips coupled to the OTP memory.

[0122] Taking the coupling of OTP memory and DRAM memory as an example, when the DRAM memory is powered on, the peripheral circuit of the DRAM memory sends a power-on signal to the peripheral circuit of the OTP memory; the peripheral circuit of the OTP memory receives the power-on signal and reads multiple copies of correction parameters from the OTP memory array through the first read parameter. Among them, the first read parameter is the default read parameter after the OTP memory is powered on.

[0123] Indicatively, the first read parameters include the first read voltage, the first read current, and the first time delay. The first read voltage is the reference voltage sensed during the read process; the first read current is the reference current during the read process; and the first time delay refers to the time delay set during the read process, necessary to first select the memory cell to be read, to accommodate the moment when the sensing amplifier is activated to read precise values. For illustrative purposes, please refer to [reference needed]. Figure 4 In OTP memory, if a large number of memory cells are programmed, the circuit will generate a large current. A reference current is used to limit the current throughout the process. Furthermore, adjusting the reference current helps to make the read results more accurate. Figure 4 In the middle, the current module 410 (current_ref) is used to provide a stable current during the reading process, and ctl1 / 2 / 3 can adjust the ratio of the current mirror individually.

[0124] It is worth noting that this embodiment uses the above three parameters as an example to illustrate the first reading parameters. The first reading parameters may also include more or fewer parameters, and this embodiment does not limit this.

[0125] The first read parameter is the default read parameter preset in the OTP memory, which can be understood as a general read parameter. However, due to the influence of PVT, the first read parameter may be inaccurate when reading from the memory array, leading to data reading errors. For illustration, the first read voltage is the default reference voltage. However, due to the influence of PVT, the actual reference voltage is slightly higher than the first read voltage. Therefore, when reading data 0 stored in the memory cell using the first read voltage, there is a possibility that the memory cell actually stores data 1, which is not read because the actual reference voltage is higher.

[0126] In this embodiment, when the chip coupled to the OTP memory is powered on, multiple copies of correction parameters are first read from the memory array using a first read parameter. These multiple copies of correction parameters are multiple copies stored based on the correction parameters and are used to correct the read correction parameters. Since multiple copies of correction parameters all point to the same correction parameter, and errors occurring when reading data stored in the memory array using the first read parameter are sporadic events, correcting the correction parameters using multiple copies of correction parameters reduces the probability of errors occurring when reading the correction parameters.

[0127] Step 340: Correct multiple copies of the correction parameters and output the correction parameters. The correction parameters are used to adjust the first read parameters to obtain the second read parameters when reading the first storage array.

[0128] In some embodiments, multiple copies of the correction parameter are corrected according to a majority rule to output the correction parameter. Each correction parameter has at least three copies; that is, the correction parameter is determined from at least three copies using a majority rule.

[0129] To illustrate, taking the example of each correction parameter storing three copies of the correction parameter, when the first read parameter is used to read that there are at least two copies of the correction parameter as the first value, the first value is determined as the value of the correction parameter; similarly, when the first read parameter is used to read that there are at least two copies of the correction parameter as the second value, the second value is determined as the value of the correction parameter.

[0130] Optionally, in some embodiments, the value of each copy of the correction parameter is a value obtained by combining the values ​​of multiple data bits, and the correction parameter is obtained in at least one of the following ways:

[0131] 1. Read the values ​​of multiple data bits of each correction parameter copy; combine the values ​​of multiple data bits to obtain the value of each correction parameter copy, such as: combining the values ​​of multiple data bits of correction parameter copy a' to obtain correction parameter copy a', combining the values ​​of multiple data bits of correction parameter copy a” to obtain correction parameter copy a”, and so on.

[0132] The values ​​of the multiple copies of the correction parameter are read and then adjusted as a whole to determine the value of the correction parameter from the values ​​of the multiple copies of the correction parameter.

[0133] By performing overall correction on the values ​​of the correction parameter copies, the correction efficiency of the correction parameter copies is improved, and the amount of computational resources required during the correction process is reduced.

[0134] 2. Correct the values ​​of the data bits in units of data bits.

[0135] For example: correct the first data bit of the correction parameter copy a', the first data bit of the correction parameter copy a"", and the first data bit of the correction parameter copy a"' to obtain the value of the first data bit of the correction parameter; correct the second data bit of the correction parameter copy a', the second data bit of the correction parameter copy a"", and the second data bit of the correction parameter copy a"' to obtain the value of the second data bit of the correction parameter.

[0136] Repeat the above operation until the values ​​of all data bits of the correction parameter are obtained, and the numerical value of the correction parameter is obtained.

[0137] By correcting the value of each data bit sequentially, the accuracy of the correction parameter is improved, and the correctness of the correction parameter reading is ensured by using data bits as the unit.

[0138] In some embodiments, the peripheral circuit includes a multi-mode redundancy sub-circuit, which is used to correct multiple copies of the correction parameter and output the correction parameter.

[0139] By setting up a multi-mode redundant sub-circuit to correct multiple copies of the correction parameter, the efficiency and accuracy of correction after reading the correction parameter copy are improved, thus improving the reading efficiency of the correction parameter.

[0140] Optionally, the multi-mode redundancy subcircuit includes a voter, which determines the correction parameters from multiple copies of the correction parameters. This multi-mode redundancy subcircuit can be implemented as a three-mode redundancy subcircuit, a four-mode redundancy subcircuit, etc. In this embodiment, a three-mode redundancy subcircuit is used as an example. Here, "three-mode" refers to the number of modules in the subcircuit used for voting; similarly, "four-mode" refers to the number of modules in the subcircuit used for voting.

[0141] By using a voter in the multi-mode redundancy sub-circuit to vote on whether the copies of the read correction parameters are the same, the value with the higher percentage of values ​​among the multiple correction parameter copies is selected as the value of the correction parameter based on the voting results, thereby improving the reading accuracy of the correction parameters.

[0142] Optionally, the number of copies of the correction parameter corresponding to the correction parameter corresponds to the number of modules performing voting in the multi-mode redundancy sub-circuit, wherein the number of copies of the correction parameter corresponding to the same correction parameter corresponds to the number of modules performing voting in the multi-mode redundancy sub-circuit. For example, if correction parameter 'a' corresponds to three copies of the correction parameter, then the peripheral circuit includes three multi-mode redundancy sub-circuits that perform voting to correct the three copies of the correction parameter.

[0143] In some embodiments, the number of copies of the correction parameter corresponding to the correction parameter is equal to the number of modules performing voting in the multimode redundancy subcircuit; or, the number of modules performing voting in the multimode redundancy subcircuit is greater than the number of copies of the correction parameter. In this embodiment, taking the number of copies of the correction parameter being equal to the number of modules performing voting in the multimode redundancy subcircuit as an example, each copy of the correction parameter is input into at least two modules in the multimode redundancy subcircuit and compared with other copies of the correction parameter.

[0144] The voting unit in the triple redundancy subcircuit includes three modules for performing voting. Figure 5This is a schematic diagram of a multimode redundancy circuit provided in an exemplary embodiment of this application. Figure 5 The multi-mode redundancy circuit shown is a three-mode redundancy sub-circuit 500.

[0145] The triple-modular redundancy sub-circuit 500 includes a voter 510, which includes three modules 511, 512 and 513 for performing voting.

[0146] After reading the three copies of the correction parameters using the first read parameter, the three copies of the correction parameters are respectively input into module 511 of the voter 510. For example... Figure 5 As shown, correction parameter copy 1 and correction parameter copy 2 are input into the first module 511; correction parameter copy 1 and correction parameter copy 3 are input into the second module 512; correction parameter copy 2 and correction parameter copy 3 are input into the third module 513.

[0147] Voting device 510 uses modules 511, 512 and 513 to determine whether the correction parameter copy 1, correction parameter copy 2 and correction parameter copy 3 are the same or different, and then outputs the majority value from the three correction parameter copies according to whether they are the same or different.

[0148] Schematic illustration: Module 511 determines whether correction parameter copy 1 and correction parameter copy 2 are the same, outputting 1 if they are the same and 0 if they are different; module 512 determines whether correction parameter copy 1 and correction parameter copy 3 are the same, outputting 1 if they are the same and 0 if they are different; module 513 determines whether correction parameter copy 2 and correction parameter copy 3 are the same, outputting 1 if they are the same and 0 if they are different. Since the value of the correction copy parameter includes either the first value or the second value, such as 0 or 1, if there are different values ​​among correction parameter copy 1, correction parameter copy 2, and correction parameter copy 3, the majority value can be determined by the output values ​​of modules 511, 512, and 513, and the value of the correction parameter can then be output.

[0149] For example, if the value read by correction parameter copy 1 is 1, the value read by correction parameter copy 2 is 0, and the value read by correction parameter copy 3 is 1, then the value output by module 511 is 0, the value output by module 512 is 1, and the value output by module 513 is 0. Thus, it is determined that the value of correction parameter copy 2 is different from the values ​​of the two correction parameter copies, that is, the values ​​of correction parameter copy 1 and correction parameter copy 3 are the same. Therefore, the values ​​of correction parameter copy 1 and correction parameter copy 3 are obtained as the value of the correction parameter, or the value of a certain data bit in the parameter.

[0150] Multimode redundancy (MMBD) is a fault-tolerant technique. Taking a triple MDBD circuit as an example, three modules perform the same operation, and a majority voting system is used to determine the correct output. When the three input signals are ready, the CLK (Clock) signal is switched, and the output will then match the majority of the inputs. Because these three modules are independent of each other, the probability of all three failing is very small, thus improving the reliability of the result.

[0151] In some embodiments, each read parameter copy corresponds to a different first read address, so multiple first read addresses are obtained, wherein the i-th first read address is used to indicate the location where the i-th correction parameter copy is stored in the storage array, and i is a positive integer; the multiple first read addresses in the storage array are read using the first read parameters.

[0152] In some embodiments, each correction parameter copy includes n first read sub-addresses, and the parameter value of the i-th correction parameter copy is a combination of the values ​​read from the n first read sub-addresses corresponding to the i-th parameter copy. Then, the values ​​read from the k-th first read sub-address of each correction parameter copy are obtained, resulting in multiple values. The value that appears most frequently among these multiple values ​​is determined as the value of the k-th bit of the correction parameter, where i, n, and k are positive integers, and k ≤ n.

[0153] That is, if the correction parameter includes n data bits, then each copy of the correction parameter also includes n data bits. Each data bit is stored in a first read sub-address, and the values ​​read from the n first read sub-addresses are combined to obtain the copy of the correction parameter.

[0154] Schematic illustration: the correction parameter indicates a reference voltage of 4V, expressed as 0100. 0100 occupies four data bits, and these four data bits are combined to obtain the correction parameter 0100. Each of the three correction parameter copies occupies four data bits to represent 0100. Each data bit is stored in a first read sub-address. Correction parameter copy a' is stored in four first read sub-addresses, used to store data 0, data 1, data 0, and data 0 respectively. Similarly, correction parameter copy a” is also stored in four first read sub-addresses.

[0155] Obtain the values ​​read from the first first read sub-address of each correction parameter copy, resulting in multiple values. Determine the value that appears most frequently from among these values ​​as the value of the first bit of the correction parameter. Obtain the values ​​read from the second first read sub-address of each correction parameter copy, resulting in multiple values. Determine the value that appears most frequently from among these values ​​as the value of the second bit of the correction parameter, and so on.

[0156] In summary, the method provided in this application, when performing a power-on reset read of a non-volatile memory, first reads the correction parameters related to the read operation using default read parameters. These correction parameters are stored as multiple parameter copies during storage. The multiple parameter copies are then read and corrected to determine more accurate correction parameters with a lower probability of error. After adjusting the default read parameters using these correction parameters, read parameters for reading other operating parameters are obtained, improving the accuracy of operating parameter reading and avoiding the problem of low reliability in reading OTP memory during the power-on phase.

[0157] In an optional embodiment, the correction parameters to be read include multiple ones, and each correction parameter corresponds to multiple copies of the correction parameter stored.

[0158] Figure 6 This application provides an exemplary embodiment of an operation method for a non-volatile memory, which can be executed by peripheral circuitry of the non-volatile memory. The method includes at least the following steps.

[0159] Step 601: Use the first read parameter to read multiple copies of the k-th correction parameter from the storage array, where k is a positive integer.

[0160] Multiple copies of the correction parameters corresponding to each correction parameter are pre-stored in non-volatile memory. When the value of k is greater than 1, the k-th correction parameter is the correction parameter that is read after the copies of the first k-1 correction parameters have been read, corrected, and stored.

[0161] When reading multiple copies of the kth correction parameter, the first storage address corresponding to the kth correction parameter is first obtained. Since the kth correction parameter corresponds to multiple copies of the correction parameter, multiple first storage addresses corresponding to the kth correction parameter are obtained. Each first storage address corresponds to the storage location of a copy of the correction parameter in the storage array.

[0162] In some embodiments, the first storage address is address data stored at a preset storage location in the non-volatile memory, such as: the first storage address is pre-stored in a register of the non-volatile memory. The first storage address is then retrieved from the register and input to the decoder for decoding to obtain path data for the first storage address. This path data is used to locate the storage cell corresponding to the first storage address in the storage array. Data stored in the storage cell is read from the storage array according to the path data using the first read parameter. Specifically, reading data stored in the storage cells corresponding to the multiple first storage addresses corresponding to the k-th correction parameter using the first read parameter constitutes multiple copies of the k-th correction parameter.

[0163] Step 602: Correct the multiple copies of the correction parameter of the kth correction parameter, and output the kth correction parameter; store the kth correction parameter in the register unit to obtain the first k correction parameters.

[0164] Multiple copies of the k-th correction parameter are input into the multi-mode redundancy sub-circuit to correct the multiple copies of the correction parameter, thereby obtaining the k-th correction parameter.

[0165] The multi-mode redundancy sub-circuit is used to determine the value with the largest percentage from multiple copies of the correction parameter, based on the majority rule, as the value of the correction parameter. In other words, the multi-mode redundancy sub-circuit votes on the values ​​of multiple copies of the correction parameter and selects the majority value as the correction parameter value.

[0166] After determining the k-th correction parameter, the k-th correction parameter is stored in the register unit to obtain the first k correction parameters.

[0167] Step 603: Determine whether the correction parameters have been read completely.

[0168] If the correction parameters have not been fully read, set k = k + 1 and continue executing step 601 until the correction parameters have been fully read.

[0169] This is illustrative; please refer to it. Figure 7 This illustrates a schematic diagram of a correction parameter reading process provided in an exemplary embodiment of this application. Figure 7 As shown, when the power-on signal is received and reading begins, k = 0 is set, and reading starts from the 0th parameter.

[0170] Taking the example of each correction parameter storing three copies, when reading the k-th correction parameter, the k-th correction parameter is stored as three copies, and each copy corresponds to a storage address. For example... Figure 7 As shown, the correction parameter k is read sequentially from address 1, address 2 and address 3. Address 1 reads the correction parameter copy k', address 2 reads the correction parameter copy k", and address 3 reads the correction parameter copy k”'.

[0171] The correction parameter copies k', k”, and k”' are input to the three-mode redundancy circuit 710, which corrects the three correction parameter copies and determines the value with the highest percentage of values ​​from the correction parameter copies k', k”, and k”', which is then used as the value of the correction parameter k.

[0172] The value of the correction parameter k is stored in the register unit, and it is determined whether k is equal to M. M refers to the total number of correction parameters, that is, there are M correction parameters in total, and each correction parameter includes 3 correction parameter copies.

[0173] Triple-modular redundancy sub-circuits are added to the peripheral circuitry. Each correction parameter corresponds to three copies of the correction parameter. The entire POR_READ process is divided into two parts. The first part requires accessing and reading the addresses of the relevant correction parameter copies and loading the final result via TMR. The second part reads the running parameters through the read parameters after correction.

[0174] In summary, the method provided in this application, when performing a power-on reset read of the memory, first reads the correction parameters related to the read operation through the default read parameters. The correction parameters are stored as multiple parameter copies during storage, and then the multiple parameter copies are read and corrected to determine more accurate correction parameters with a smaller error probability. After adjusting the default read parameters through the correction parameters, the read parameters for reading other operating parameters are obtained, which improves the accuracy of reading operating parameters and avoids the problem of low read reliability of OTP memory during the power-on phase.

[0175] The method provided in this application reads copies of multiple correction parameters in sequence and stores them into a register unit, thereby improving the accuracy and efficiency of reading correction parameters.

[0176] In some embodiments, the non-volatile memory is used to store operating parameters corresponding to the chip coupled thereto. Figure 8 This is another exemplary embodiment of the present application providing a method for operating a non-volatile memory, which can be executed by the peripheral circuitry of the non-volatile memory. The method described above... Figure 3 The steps following step 340 shown include at least the following steps.

[0177] Step 820: Adjust the first read parameter by correcting the parameter to obtain the second read parameter.

[0178] In some embodiments, when adjusting the first read parameter by modifying the parameter, at least one of the following adjustment methods is included:

[0179] 1. The correction parameters stored in the non-volatile memory are read parameter data corresponding to PVT. Therefore, after directly reading the correction parameters according to PVT, the correction parameters corresponding to PVT are used as the second read parameters.

[0180] In other words, the correction parameter is a read parameter stored in the memory according to the correspondence with PVT. For example, correction parameter a corresponds to process 1, voltage 5V and temperature 40°. Correction parameter a includes reference voltage, voltage current and time delay data. Therefore, after reading correction parameter a according to PVT, correction parameter a is directly used as the second read parameter.

[0181] 2. The correction parameters stored in the non-volatile memory are the adjustment parameters corresponding to PVT. Therefore, after obtaining the correction parameters, the second read parameters are obtained by adjusting the parameters according to the correction parameters based on the first read parameters.

[0182] In other words, the correction parameters are adjustment parameters stored in the memory according to the characteristics corresponding to PVT. For example, if the correction parameter b corresponds to process 1, voltage 5V and temperature 40°, and the correction parameter b indicates that the reference voltage is increased by 0.2, then after reading the correction parameter b according to PVT, the reference voltage in the first read parameter is directly multiplied by 1.2 and used as the reference voltage in the second read parameter. The reference current and time delay in the first read parameter are directly used as the reference current and time delay in the second read parameter.

[0183] It is worth noting that the above-mentioned method of obtaining the second reading parameter is only an illustrative example, and the embodiments of this application do not limit it.

[0184] Step 840: Use the second read parameter to read the operating parameters in the storage array.

[0185] Among them, the operating parameters are data stored in non-volatile memory used to indicate the operation of the chip.

[0186] In some embodiments, the non-volatile memory described above is implemented as an OTP memory, which is coupled to other chips and is used to provide operating parameters to other chips upon power-on reset.

[0187] After adjusting the first read parameter to obtain the second read parameter, which is a calibrated read parameter superior to the first read parameter, the operating parameters in the storage array can be read directly through the second read parameter.

[0188] Optionally, a second read address is obtained, which indicates the location where the running parameters are stored in the storage array, and the running parameters are read from the second read address in the storage array using the second read parameters.

[0189] Operating parameters refer to the configuration and setting parameters required for the operation of a chip or system. These parameters may include the chip's operating frequency, voltage threshold, clock settings, calibration data, calibration curves, etc. Operating parameters are typically set during device manufacturing or system initialization; once set, they are not modified and are therefore stored in OTP memory.

[0190] In summary, the method provided in this application, when performing a power-on reset read of the memory, reads the correction parameters, corrects the first read parameters using the correction parameters, obtains the second read parameters, and then reads the operating parameters of the chip using the second read parameters, thereby improving the accuracy of reading the operating parameters.

[0191] This application embodiment also provides a volatile memory coupled to a non-volatile memory, the volatile memory including: a memory array and peripheral circuitry;

[0192] The peripheral circuitry is configured as follows:

[0193] After the volatile memory is powered on, a power-on signal is sent to the non-volatile memory. The power-on signal is used to instruct the non-volatile memory to read multiple copies of correction parameters from the storage array of the non-volatile memory using the first read parameter, to correct the multiple copies of correction parameters, output the correction parameters, and after determining the second read parameter based on the correction parameter, read the operating parameters through the second read parameter.

[0194] Receive operating parameters sent by non-volatile memory;

[0195] The storage array is read based on the operating parameters.

[0196] In an optional embodiment, the peripheral circuitry of the volatile memory is coupled to the peripheral circuitry of the non-volatile memory.

[0197] The peripheral circuitry is configured to send the power-on signal to the peripheral circuitry of the non-volatile memory after the volatile memory is powered on.

[0198] In an optional embodiment, the peripheral circuitry is further configured to read the memory array based on the read voltage, read current, and time delay in the operating parameters.

[0199] In an optional embodiment, the non-volatile memory coupled to the volatile memory is implemented as a one-time programmable (OTP) memory.

[0200] Figure 9 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. For example... Figure 9 As shown, the DRAM memory is coupled to the OTP memory.

[0201] The OTP memory includes a first peripheral circuit 920 and a first storage array 930, while the DRAM memory includes a second peripheral circuit 940 and a second storage array 950.

[0202] The OTP memory is used to provide operating parameters to the DRAM memory during operation. The first peripheral circuit 920 includes a triple-modular redundancy sub-circuit TMR and a register. The first storage array 930 stores copies of the operating parameters and the corrected parameters used by the OTP memory during the power-on reset read phase.

[0203] When the DRAM memory is powered on, the second peripheral circuit 940 sends a power-on signal to the first peripheral circuit 920 of the OTP memory through the input / output circuit 916.

[0204] After receiving the power-on signal, the OTP memory obtains the first read address of the correction parameter copy, and reads multiple correction parameter copies from the first read address of the first storage array 930 using the first read parameter. The multiple correction parameter copies are then corrected by the TMR to obtain the correction parameters, which are then stored in the register.

[0205] After the correction parameters are read, the first read parameters are adjusted based on the correction parameters to obtain the second read parameters, and the operating parameters stored in the first storage array 930 are read based on the second read parameters. The read operating parameters are then sent to the second peripheral circuit 940.

[0206] The second peripheral circuit 940 is used to write data to the second storage array 950 and to read data from the second storage array 950.

[0207] The second peripheral circuitry 940 includes: a data input / output buffer 902, a sensing amplifier 904, a column decoder 906, and a row decoder 908. It should be understood that in some examples, it may also include... Figure 9 Additional secondary peripheral circuits, such as registers and data buses, not shown in the diagram.

[0208] The sense amplifier 904 can be configured to read data from and program (write) data to the second memory array 950 according to control signals. In one example, the sense amplifier 904 can store a page of programming data (write data) to be programmed into a page of the second memory array 950. In another example, the sense amplifier 904 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to a selected word line. In yet another example, the sense amplifier 904 can also sense a low-power signal from a bit line representing a data bit stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation.

[0209] The column decoder 906 can be configured to select one or more memory strings by applying bit line voltages.

[0210] The row decoder 908 can be configured to select / deselect blocks of the second memory array 950 and select / deselect word lines of the blocks. The row decoder 908 can also be configured to use word line voltage (V). WL The row decoder 908 drives the word lines. In some embodiments, the row decoder 908 can also select / deselect and drive the source select gate line and the drain select gate line. Illustratively, the row decoder 908 is configured to perform an erase operation on memory cells coupled to one or more selected word lines.

[0211] It should be emphasized that the second peripheral circuit 940 is configured to perform the memory operation method provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0212] Figure 10 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application, such as... Figure 10 As shown, the storage system 1000 includes: one or more memories 1010, and a memory controller 1020 coupled to the memories 1010 and configured to control the memories 1010.

[0213] The storage system 1000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0214] Optionally, the storage system 1000 may include a host and a storage subsystem, the storage subsystem having one or more memories 1010 and a memory controller 1020. The host may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to the memory 1010. Alternatively, the host may be configured to receive data from the memory 1010.

[0215] According to some implementations, the memory controller 1020 is also coupled to a host. The memory controller 1020 can manage data stored in the memory 1010 and communicate with the host.

[0216] In some implementations, the memory controller 1020 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, CompactFlash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0217] In some implementations, the memory controller 1020 is designed to operate in a high duty cycle environment in a solid state disk (SSD) or an embedded multi media card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0218] The memory controller 1020 can be configured to control the operation of the memory 1010, such as read, erase, and program operations. The memory controller 1020 can also be configured to manage various functions related to data stored or to be stored in the memory 1010, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1020 is also configured to process error correcting codes (ECCs) regarding data read from or written to the memory 1010.

[0219] The memory controller 1020 can also perform any other suitable functions, such as formatting the memory 1010. The memory controller 1020 can communicate with external devices according to a specific communication protocol.

[0220] The memory controller 1020 and one or more memories 1010 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 1000 can be implemented and packaged into different types of end electronic products.

[0221] Schematic illustration: The memory controller 1020 and a single memory 1010 can be integrated into a memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards, SD cards, UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host computer.

[0222] Schematic, the memory controller 1020 and multiple memories 1010 may be integrated into a solid-state drive (SSD). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0223] It is understood that the memory controller 1020 can perform memory operation methods as provided in any embodiment of this disclosure.

[0224] The memory 1010 described above can be implemented as the volatile memory involved in the embodiments of this application, or it can be implemented as the non-volatile memory involved in the embodiments of this application.

[0225] This application provides a control circuit, which includes programmable logic circuits and / or program instructions. The control circuit can be used to implement the operation method of the non-volatile memory provided in the foregoing embodiments of this application.

[0226] Indicative, such as Figure 11 As shown, the non-volatile memory includes peripheral circuitry 1100 and a memory array 1110;

[0227] The peripheral circuit 1100 is configured as follows:

[0228] In response to receiving a power-on signal, a plurality of correction parameter copies are read from the storage array 1110 using a first read parameter, the plurality of correction parameter copies being copies of the correction parameter storage;

[0229] The plurality of correction parameter copies are corrected, and the correction parameters are output. The correction parameters are used to adjust the first read parameters to obtain the second read parameters when reading the storage array 1110.

[0230] In an optional embodiment, the non-volatile memory includes a one-time programmable (OTP) memory.

[0231] In an optional embodiment, the peripheral circuit 1100 includes a multi-mode redundant sub-circuit;

[0232] The peripheral circuit 1100 is also configured as follows:

[0233] The multiple copies of the correction parameters are corrected by the multi-mode redundancy sub-circuit, and the correction parameters are output.

[0234] In an optional embodiment, the multi-mode redundancy sub-circuit includes a voter;

[0235] The peripheral circuit 1100 is also configured as follows:

[0236] The correction parameter is determined from the plurality of copies of the correction parameter by the voter in the multi-mode redundancy sub-circuit.

[0237] In an optional embodiment, each modified parameter copy includes n first read sub-addresses, and the parameter value of the i-th modified parameter copy is a combination of values ​​read from the n first read sub-addresses corresponding to the i-th parameter copy;

[0238] The peripheral circuit 1100 is also configured as follows:

[0239] Obtain the values ​​read from the kth first read sub-address of each correction parameter copy to obtain multiple values. Determine the value that appears most frequently from the multiple values ​​as the value of the kth bit of the correction parameter, where i, n and k are positive integers and k≤n.

[0240] In an optional embodiment, the peripheral circuit 1100 is further configured to:

[0241] Obtain multiple first read addresses, wherein the i-th first read address is used to indicate the location where the i-th copy of the correction parameter is stored in the storage array 1110, and i is a positive integer;

[0242] The first read parameter is used to read the plurality of first read addresses in the storage array 1110.

[0243] In an optional embodiment, the number of copies of the correction parameter corresponding to the correction parameter corresponds to the number of modules performing voting in the multimode redundancy subcircuit.

[0244] In an optional embodiment, the peripheral circuit 1100 further includes: a register unit;

[0245] The peripheral circuit 1100 is also configured as follows:

[0246] Multiple copies of the m-th correction parameter are read from the storage array 1110 using the first read parameter, where m is a positive integer;

[0247] Correct multiple copies of the m-th correction parameter, output the m-th correction parameter; store the m-th correction parameter in the register unit to obtain the first m correction parameters;

[0248] If the correction parameters are not fully read, multiple copies of the (m+1)th correction parameter are read from the storage array 1110;

[0249] The multiple copies of the correction parameter for the (m+1)th correction parameter are corrected, and the (m+1)th correction parameter is output; the (m+1)th correction parameter is stored in the register unit to obtain the first (m+1)th correction parameters; until all correction parameters have been read.

[0250] In an optional embodiment, the peripheral circuit 1100 is further configured to:

[0251] The first read parameter is adjusted using the correction parameter to obtain the second read parameter;

[0252] The second read parameter is used to read the operating parameters in the storage array 1110, which are data stored in the memory used to indicate chip operation.

[0253] In an optional embodiment, the peripheral circuit 1100 is further configured to:

[0254] Obtain a second read address, which indicates the location where the operating parameters are stored in the storage array 1110;

[0255] The operating parameters are read from the second read address in the storage array 1110 using the second read parameter.

[0256] This application provides an electronic device, the electronic device comprising:

[0257] One or more non-volatile memories or volatile memories as described in any of the above embodiments, and,

[0258] A memory controller coupled to the non-volatile memory or volatile memory and configured to control the non-volatile memory or volatile memory.

[0259] This application provides a computer-readable storage medium storing instructions that, when executed on a control circuit, implement the memory programming method provided in the foregoing embodiments of this application.

[0260] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0261] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0262] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A non-volatile memory, characterized in that, The non-volatile memory includes: a memory array and peripheral circuitry; The peripheral circuit is configured as follows: In response to receiving a power-on signal, a plurality of correction parameter copies are read from the storage array using a first read parameter, the plurality of correction parameter copies being copies of the correction parameter storage; The plurality of correction parameter copies are corrected, and the correction parameters are output. The correction parameters are used to adjust the first read parameters to obtain the second read parameters when reading the storage array.

2. The memory according to claim 1, characterized in that, The non-volatile memory includes a one-time programmable (OTP) memory.

3. The memory according to claim 1, characterized in that, The peripheral circuit includes a multi-mode redundancy sub-circuit; The peripheral circuit is also configured as follows: The multiple copies of the correction parameters are corrected by the multi-mode redundancy sub-circuit, and the correction parameters are output.

4. The memory according to claim 3, characterized in that, The multi-mode redundancy sub-circuit includes a voting unit; The peripheral circuit is also configured as follows: The correction parameter is determined from the plurality of copies of the correction parameter by the voter in the multi-mode redundancy sub-circuit.

5. The memory according to claim 1, characterized in that, Each modified parameter copy includes n first read sub-addresses, and the parameter value of the i-th modified parameter copy is a combination of the values ​​read from the n first read sub-addresses corresponding to the i-th parameter copy; The peripheral circuit is also configured as follows: Obtain the values ​​read from the kth first read sub-address of each correction parameter copy to obtain multiple values. Determine the value that appears most frequently from the multiple values ​​as the value of the kth bit of the correction parameter, where i, n and k are positive integers and k≤n.

6. The memory according to any one of claims 1 to 5, characterized in that, The peripheral circuit is also configured as follows: Obtain multiple first read addresses, where the i-th first read address is used to indicate the location where the i-th copy of the correction parameter is stored in the memory array, and i is a positive integer; The first read parameter is used to read the plurality of first read addresses in the storage array.

7. The memory according to any one of claims 3 to 5, characterized in that, The number of copies of the correction parameter corresponds to the number of modules performing voting in the multi-mode redundancy sub-circuit.

8. The memory according to any one of claims 1 to 5, characterized in that, The peripheral circuit also includes: a register unit; The peripheral circuit is also configured as follows: Multiple copies of the m-th correction parameter are read from the storage array using the first read parameter, where m is a positive integer; Correct multiple copies of the m-th correction parameter, output the m-th correction parameter; store the m-th correction parameter in the register unit to obtain the first m correction parameters; If the correction parameters are not fully read, read multiple copies of the (m+1)th correction parameter from the storage array; The multiple copies of the correction parameter for the (m+1)th correction parameter are corrected, and the (m+1)th correction parameter is output; the (m+1)th correction parameter is stored in the register unit to obtain the first (m+1)th correction parameters; until all correction parameters have been read.

9. The memory according to any one of claims 1 to 5, characterized in that, The peripheral circuit is also configured as follows: The first read parameter is adjusted using the correction parameter to obtain the second read parameter; The second read parameter is used to read the operating parameters in the memory array, which are data stored in the memory used to indicate chip operation.

10. The memory according to claim 9, characterized in that, The peripheral circuit is also configured as follows: Obtain a second read address, which indicates the location where the operating parameters are stored in the storage array; The operating parameters are read from the second read address in the storage array using the second read parameter.

11. A volatile memory, characterized in that, The volatile memory is coupled to the non-volatile memory, and the volatile memory includes: a memory array and peripheral circuitry; The peripheral circuit is configured as follows: After the volatile memory is powered on, a power-on signal is sent to the non-volatile memory. The power-on signal is used to instruct the non-volatile memory to read multiple copies of correction parameters from the storage array of the non-volatile memory using a first read parameter, to correct the multiple copies of correction parameters, to output correction parameters, and to determine a second read parameter based on the correction parameters, and then to read the operating parameters through the second read parameter. Receive the operating parameters sent by the non-volatile memory; The storage array is read based on the operating parameters.

12. The memory according to claim 11, characterized in that, The peripheral circuit is coupled to the peripheral circuit of the non-volatile memory; The peripheral circuit is also configured as follows: After the volatile memory is powered on, the power-on signal is sent to the peripheral circuitry of the non-volatile memory.

13. The memory according to claim 11, characterized in that, The peripheral circuit is also configured as follows: The storage array is read based on the read voltage, read current, and time delay in the operating parameters.

14. The memory according to claim 11, characterized in that, The non-volatile memory coupled to the volatile memory is implemented as a one-time programmable (OTP) memory.

15. A method for operating a non-volatile memory, characterized in that, The method includes: In response to receiving a power-on signal, a plurality of correction parameter copies are read from the storage array using a first read parameter, the plurality of correction parameter copies being copies of the correction parameter storage; The plurality of correction parameter copies are corrected, and the correction parameters are output. The correction parameters are used to adjust the first read parameters to obtain the second read parameters when reading the storage array.

16. The method according to claim 15, characterized in that, The non-volatile memory includes a one-time programmable (OTP) memory.

17. The method according to claim 15, characterized in that, The step of reading multiple copies of correction parameters from the storage array using the first read parameter includes: Obtain multiple first read addresses, where the i-th first read address is used to indicate the location where the i-th copy of the correction parameter is stored in the memory array, and i is a positive integer; Read from the plurality of first read addresses in the storage array using the first read parameter.

18. The method according to claim 15, characterized in that, Each modified parameter copy includes n first read sub-addresses, and the parameter value of the i-th modified parameter copy is a combination of the values ​​read from the n first read sub-addresses corresponding to the i-th parameter copy; The step of correcting the plurality of copies of the correction parameters and outputting the correction parameters includes: Obtain the value read from the kth first read sub-address of each copy of the correction parameter, and obtain multiple values; The value that appears most frequently among the plurality of values ​​is determined as the value of the k-th bit of the correction parameter, where i, n, and k are positive integers and k ≤ n.

19. The method according to any one of claims 15 to 18, characterized in that, The non-volatile memory includes a multi-mode redundancy sub-circuit, and the number of copies of the correction parameter stored corresponds to the number of modules performing voting in the multi-mode redundancy sub-circuit.

20. The method according to any one of claims 15 to 18, characterized in that, The method further includes: Multiple copies of the m-th correction parameter are read from the storage array using the first read parameter, where m is a positive integer; Correct multiple copies of the m-th correction parameter and output the m-th correction parameter; store the m-th correction parameter to obtain the first m correction parameters; If the correction parameters are not fully read, read multiple copies of the (m+1)th correction parameter from the storage array; The multiple copies of the correction parameter of the (m+1)th correction parameter are corrected, and the (m+1)th correction parameter is output; the (m+1)th correction parameter is stored to obtain the first (m+1)th correction parameters; until all correction parameters have been read.

21. The method according to any one of claims 15 to 18, characterized in that, Following the output correction parameters, the following is also included: The first read parameter is adjusted using the correction parameter to obtain the second read parameter; The second read parameter is used to read the operating parameters in the storage array, which are data stored in the non-volatile memory used to indicate chip operation.

22. The method according to claim 21, characterized in that, The step of reading the operating parameters in the storage array using the second read parameter includes: Obtain a second read address, which indicates the location where the operating parameters are stored in the storage array; The operating parameters are read from the second read address in the storage array using the second read parameter.

23. A storage system, characterized in that, The storage system includes: One or more non-volatile memories as described in any one of claims 1 to 10, or one or more volatile memories as described in any one of claims 11 to 14, and, A memory controller coupled to the non-volatile memory or volatile memory and configured to control the non-volatile memory or volatile memory.

24. A chip, characterized in that, The chip includes: One or more non-volatile memories as described in any one of claims 1 to 10, or one or more volatile memories as described in any one of claims 11 to 14.

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