Multi-layer focus ring for plasma semiconductor processing

Abstract

The present invention generally relates to plasma semiconductor processing and related components and tools. In an example, a focus ring includes a first annular layer and a second annular layer. The upper surface of the second annular layer is configured to support the first annular layer by contacting the lower surface of the first annular layer with the upper surface. The lower surface and the upper surface are of a periodic structure in the circumferential direction and have the same periodic length. At least one of the lower surface and the upper surface includes a first protruding radial line (PRL), a second PRL, and a recessed radial line (RRL) disposed between the first PRL and the second PRL. The cycle length is from the first PRL to the second PRL. The lower surface and / or the upper surface is continuous from the first PRL to the RRL, and the lower surface and / or the upper surface is continuous from the RRL to the second PRL. The second annular layer is rotatably movable relative to the first annular layer.

Description

[0001] This application is a divisional application of patent application No. 2022800353877, filed on August 25, 2022, entitled "Multilayer Focusing Ring for Plasma Semiconductor Processing". Background Technology

[0002] Plasma processing has become ubiquitous in the semiconductor industry. Plasma semiconductor processing is used for etching materials, depositing materials, and more. It has been found that this plasma processing provides improved processing quality or result characteristics on the semiconductor substrates on which the processing is performed compared to previous methods. For example, plasma-enhanced chemical vapor deposition (PECVD) has been found to have advantages over previous chemical vapor deposition (CVD) processes, including lower deposition temperatures, increased material purity, and improved step coverage. However, the introduction of plasma has also brought various challenges. Summary of the Invention

[0003] The first example described herein is a component for semiconductor processing. The component includes a focusing ring configured to laterally surround a semiconductor substrate during plasma semiconductor processing. The focusing ring includes a first annular layer having a lower surface and a second annular layer having an upper surface. The upper surface is configured to support the first annular layer by contacting the upper surface with the lower surface. The lower and upper surfaces are periodically arranged in the circumferential direction. The lower and upper surfaces have the same period length at the same first radial distance from the center of the focusing ring. At least one of the lower and upper surfaces includes a first protruding radial line, a first recessed radial line, and a second protruding radial line. The first recessed radial line is laterally arranged between the first and second protruding radial lines. The period length at the first radial distance is from the first protruding radial line to the second protruding radial line. At least one of the lower and upper surfaces is continuous from the first protruding radial line to the first recessed radial line. At least one of the lower and upper surfaces is continuous from the first recessed radial line to the second protruding radial line. While the upper surface supports the first annular layer, the second annular layer is laterally and rotatably movable relative to the first annular layer.

[0004] A second example is a processing tool for semiconductor processing. The processing tool includes a chamber, a substrate support, and a focusing ring rotation assembly. The chamber has an internal volume within the chamber. The substrate support is disposed within the internal volume of the chamber. The substrate support has a support surface configured to support a semiconductor substrate. The substrate support includes a flange configured to support a focusing ring laterally surrounding the support surface. The focusing ring rotation assembly is at least partially disposed within the internal volume of the chamber. The focusing ring rotation assembly is configured to laterally rotate at least a portion of the focusing ring about an axis perpendicular to the support surface. The focusing ring rotation assembly includes a frame configured to laterally rotate about an axis perpendicular to the support surface.

[0005] The third example is a method for semiconductor processing. The method includes adjusting the height of a focusing ring. The focusing ring is arranged laterally around a semiconductor substrate in a chamber of a processing tool. The focusing ring includes a first annular layer and a second annular layer. Adjusting the height of the focusing ring includes rotating the second annular layer relative to the first annular layer. The first annular layer has a lower surface. The second annular layer has an upper surface. The lower surface is disposed on and in contact with the upper surface. The lower and upper surfaces are periodically structured in the circumferential direction. The lower and upper surfaces have the same period length at the same first radial distance from the center of the focusing ring. At least one of the lower and upper surfaces includes a first protruding radial line, a first recessed radial line, and a second protruding radial line. The first recessed radial line is laterally disposed between the first and second protruding radial lines. The period length at the first radial distance is from the first protruding radial line to the second protruding radial line. At least one of the lower and upper surfaces is continuous from the first protruding radial line to the first recessed radial line. At least one of the lower and upper surfaces is continuous from the first recessed radial line to the second protruding radial line. The method involves generating plasma within a processing volume of a chamber while the focusing ring is arranged laterally around the semiconductor substrate. The semiconductor substrate is exposed to the plasma.

[0006] The fourth example is a method for semiconductor processing. The method includes performing a plasma semiconductor process on a plurality of first substrates using a processing tool, having first processing conditions. The processing tool includes a substrate support configured to support the substrates during the plasma semiconductor process. During the plasma semiconductor process, a focusing ring is arranged laterally around the substrates. The focusing ring has a first annular layer and a second annular layer that supports and contacts the first annular layer. The height of the focusing ring can be adjusted by rotating the second annular layer relative to the first annular layer. The first processing condition corresponds to a first rotation amount by which the second annular layer rotates relative to the first annular layer during the plasma semiconductor process to achieve a first height of the focusing ring. The method includes measuring a corresponding first characteristic of the plurality of first substrates near a corresponding center of the plurality of first substrates. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a corresponding second characteristic of the plurality of first substrates near a corresponding edge of the plurality of first substrates. The second characteristic is formed by the plasma semiconductor process. The method includes determining, using a processor-based system, second processing conditions to be applied when performing the plasma semiconductor process on the plurality of second substrates, based on the first and second characteristics. The second processing condition corresponds to a second rotation amount by which the second annular layer rotates relative to the first annular layer during the plasma semiconductor process to achieve a second height of the focusing ring. The method includes performing a plasma semiconductor process with second processing conditions on a plurality of second substrates using a processing tool.

[0007] The foregoing summary has broadly outlined various features of the examples of this disclosure in order to provide a better understanding of the detailed embodiments described below. Other features and advantages of these examples will be described below. The described examples can be readily used as the basis for modifications or designs of other examples within the scope of the appended claims. Attached Figure Description

[0008] To gain a detailed understanding of the above features, please refer to the following specific embodiments in conjunction with the accompanying drawings.

[0009] Figure 1 These are schematic diagrams of processing tools for semiconductor processing, based on some examples.

[0010] Figure 2A It is a layout diagram of the focus ring based on some examples.

[0011] Figure 2B It is based on some examples Figure 2A A cross-sectional view of the focusing ring.

[0012] Figure 2C It is based on some examples Figure 2A A cross-sectional view of the focusing ring.

[0013] Figure 2D It is based on some examples Figure 2C The layout diagram of the cross-section of the focusing ring.

[0014] Figure 3 and Figure 4 The following are examples. Figures 2A to 2D The height of the focusing ring is adjusted.

[0015] Figure 5 This is a simplified cross-sectional view of a focusing ring rotating assembly based on some examples.

[0016] Figure 6 It is based on some examples Figure 5 A perspective view of the focusing ring rotating assembly.

[0017] Figure 7A , Figure 7B and Figure 7C These are, respectively, a layout diagram, a first cross-sectional view, and a second cross-sectional view of a focusing ring on the flange of a substrate support member based on some examples.

[0018] Figure 8A and Figure 8B These are layout and cross-sectional views of the focusing ring on the flange of a substrate support, based on some examples.

[0019] Figure 9 and Figure 10 The concept illustrates how the height of the focusing ring, based on some examples, can contribute to plasma control.

[0020] Figure 11 It is based on some examples of processor-based systems.

[0021] Figure 12 It is a flowchart of a semiconductor processing method based on some examples.

[0022] Figure 13 It is a flowchart of a method for semiconductor processing based on some examples.

[0023] Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 It is a cross-sectional view of the corresponding focusing ring based on some examples.

[0024] The accompanying drawings and detailed embodiments are provided to illustrate the features of the various examples, and not to limit the scope of the appended claims. The examples shown in the drawings and described in the appended detailed embodiments can readily serve as the basis for modifications or designs of other examples within the scope of the appended claims. Where possible, the same reference numerals may be used to denote common elements in the drawings. The drawings are drawn to clearly illustrate relevant elements or features, and are not necessarily drawn to scale. Detailed Implementation

[0025] Various features are described below with reference to the accompanying drawings. Examples may not possess all the aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and may be practiced in any other example even if not so shown or so explicitly described. Furthermore, the methods described herein may be described with a particular order of operations, but other methods according to other examples may be implemented with various other orders of operations (e.g., different serial or parallel executions of various operations).

[0026] This disclosure relates to plasma semiconductor processing, and specifically to components and processing tools for plasma semiconductor processing. Some examples described herein include a focusing ring having multiple layers. Typically, a first annular layer (e.g., a top layer) of the focusing ring has a lower surface, and a second annular layer (e.g., a bottom layer) has an upper surface. The upper surface is configured to contact and support the lower surface of the first annular layer. The upper and lower surfaces are configured such that rotation of the second annular layer relative to the first annular layer adjusts the height of the focusing ring. In some examples, continuous rotation of the second annular layer relative to the first annular layer results in oscillations in the height of the focusing ring without requiring a hard reset of either the first or second annular layer for height adjustment.

[0027] Some examples described herein include processing tools in which such a focusing ring can be used. The processing tool includes a focusing ring rotation assembly configured to rotate the second annular layer. The processing tool may also include a substrate support including a mechanism to prevent significant rotation of the first annular layer as the second annular layer rotates. Such a mechanism may include a stop pin extending from the substrate support and engaging with the first annular layer to prevent significant rotation of the first annular layer.

[0028] For example, other examples described herein include semiconductor processing methods using such a focusing ring and processing tool. Further examples include methods for semiconductor processing that determine the height of the focusing ring to be achieved in subsequent processing of a semiconductor substrate based on the results of previous semiconductor processing.

[0029] Additionally, in some examples, the focusing ring may include electrodes on which a voltage (such as a radio frequency (RF) signal) can be applied. The processing tool may include components that apply such a voltage to the electrodes of the focusing ring. Plasma semiconductor processing may include applying such a voltage to the electrodes.

[0030] Plasma inhomogeneities in semiconductor processing can lead to the manufacture of defective integrated circuit (IC) chips. Plasma inhomogeneities have been observed between the center of a semiconductor substrate (e.g., a wafer) and near its edges. Since a large number of IC chips are manufactured near the edges of semiconductor substrates, plasma inhomogeneities at the substrate edges can result in significant yield losses.

[0031] Structural differences at the edges of a semiconductor substrate compared to its center can lead to plasma inhomogeneities between the two locations. For example, the structure controlling or defining the plasma at the edges of the substrate may differ from that at the center. At the center, the plasma is controlled or defined by a flat lateral surface of the semiconductor surface, while at the edge, with its vertical sides, the plasma is structurally different from the flat lateral surface. A focusing ring surrounding the semiconductor substrate can be used to reduce this structural difference; however, gaps may exist between the focusing ring and the semiconductor substrate due to manufacturing tolerances. The plasma sheath may bend into these gaps near the edges, potentially causing the angle of ion bombardment near the edges to differ from that at the center.

[0032] Furthermore, the physical structure of the processing tool can at least partially determine the electromagnetic field used to generate plasma. The structure of the electrodes in which plasma is generated can determine the electromagnetic field. At the center of the electrodes, the electromagnetic field can be modeled as being generated by an infinite plane with little or no edge effects. Near the edges of the electrodes, edge effects become more pronounced, which can reduce and / or alter the directionality of the electromagnetic field. As a result, the plasma density at the edges of the semiconductor substrate can differ from that at the center. Moreover, the edges of the electrodes are closer to the cavity walls of the processing tool, which can create low-resistivity electromagnetic loops, leading to a difference in plasma density and ion energy between the center and the edges.

[0033] Some examples can address and / or mitigate some of these challenges associated with plasma semiconductor processing. By adjusting the height of the focusing ring, the plasma sheath can be tuned to produce a more uniform ion bombardment angle at the edges of the semiconductor substrate relative to the center. Additionally, by applying a voltage to the electrodes of the focusing ring, the electromagnetic field can be controlled to produce a more uniform ion bombardment angle at the edges relative to the center. Other advantages or benefits can be achieved using the various aspects described herein.

[0034] Figure 1 This is a schematic diagram of a processing tool 100 for semiconductor processing, based on some examples. Figure 1 The XYZ axes are included to facilitate the description of various orientations, and these axes are reproduced in other figures according to the orientation. Figure 1The processing tool 100 is shown simply so as not to obscure the various aspects described herein. Other aspects of the processing tool 100 will be readily understood by those skilled in the art. In this example, the processing tool 100 is shown as a capacitively coupled plasma (CCP) processing tool. In other examples, the processing tool 100 may be configured as an inductively coupled plasma (ICP) processing tool, an electron cyclotron resonance (ECR) processing tool, or other processing tools. The various aspects described herein applicable to these other processing tools will be readily understood by those skilled in the art. The processing tool 100 can be used to perform plasma semiconductor processing, such as sputtering, physical vapor deposition (PVD), modified dual plasma (MDP), plasma-enhanced chemical vapor deposition (PECVD), ion beam etching (IBE), reactive ion etching (RIE), and other semiconductor processing.

[0035] The processing tool 100 includes a chamber 102. The chamber 102 has an internal volume 104 defined by its inner walls. The processing tool 100 includes a substrate support 106 disposed within the internal volume 104 of the chamber 102. The substrate support 106 includes an electrostatic chuck (ESC) 108, an intermediate plate 110, and a base plate 112. In the illustrated configuration, the intermediate plate 110 is disposed above and over the base plate 112, and the ESC 108 is disposed above and over the intermediate plate 110. The substrate support 106 is disposed on and supported by a base 114. The base plate 112 is disposed above and over the base 114.

[0036] The substrate support 106 has a support surface 116 configured to support a semiconductor substrate 120 during semiconductor processing. During semiconductor processing, the semiconductor substrate 120 is disposed on the support surface 116 of the substrate support 106. In the example shown, the support surface 116 is the top surface of ESC 108. Figure 1 In the illustration, the supporting surface 116 is in the xy plane.

[0037] ESC 108 includes an adsorption electrode 122. The adsorption electrode 122 is configured to be subjected to a direct current (DC) voltage for adsorbing the semiconductor substrate 120 onto a support surface 116. ESC 108 may include a dielectric material coated on the adsorption electrode 122 to provide electrical isolation from direct contact with the adsorption electrode 122. ESC 108 also has a flange 126 at its lateral periphery. The flange 126 is configured to support a focusing ring 130 laterally surrounding the semiconductor substrate 120 during plasma semiconductor processing. The flange 126 may be formed from the dielectric material coated on the adsorption electrode 122. The dielectric material may be or include any non-conductive material, such as aluminum oxide (Al2O3), yttrium oxide (Y2O3), silicon oxide (SiO2), etc., or combinations thereof. In some examples, ESC 108 may include a resistance heating element configured to allow current to flow through it, which can generate heat energy conducted to the semiconductor substrate 120.

[0038] As described in detail below, the focusing ring 130 includes a bottom layer 130a and a top layer 130b on the bottom layer 130a. The bottom layer 130a is supported by a flange 126 of ESC 108, and the top layer 130b is supported by the bottom layer 130a. The bottom layer 130a is rotatable about a vertical axis (e.g., the z-axis). During rotation, the bottom layer 130a slides or travels along the surface of the flange 126 that supports the focusing ring 130. The top layer 130b typically cannot rotate significantly. When the bottom layer 130a rotates, the construction of the upper surface of the bottom layer 130a and the lower surface of the top layer 130b causes the top layer 130b to translate in a vertical direction (e.g., the z-direction). The translation of the top layer 130b results in a change in the height of the focusing ring 130 relative to the semiconductor substrate 120.

[0039] Intermediate plate 110 includes RF electrode 132. RF electrode 132 may have a dielectric material to provide electrical isolation between RF electrode 132 and other components in direct contact. In some examples, intermediate plate 110 includes a fluid channel configured to allow fluid (e.g., liquid) to flow through it to remove and dissipate heat from semiconductor substrate 120. The fluid channel may be referred to as a cooler.

[0040] The base plate 112 includes a bias electrode 136. The bias electrode 136 is configured to be subjected to a bias signal (e.g., an RF signal) to facilitate the drivability of the RF electrode 132. The bias electrode 136 may have a dielectric material to provide electrical isolation between the bias electrode 136 and direct contact with other components.

[0041] Processing tool 100 includes a focus ring rotation assembly. The focus ring rotation assembly includes a rotatable frame 138 and a rotating pin 140 projecting vertically from the rotatable frame 138. The rotatable frame 138 projects laterally from a base 114. The rotating pin 140 is supported by and extends vertically from the rotatable frame 138. The rotating pin 140 extends through a slot formed through a flange 126 of ESC 108 and is mechanically coupled to a focus ring 130 (e.g., a bottom layer 130a). The rotatable frame 138 is rotatable about a vertical axis (e.g., the z-axis), and rotation of the rotatable frame 138 causes the bottom layer 130a to rotate about the vertical axis. Further details of the focus ring rotation assembly will be described subsequently.

[0042] The processing tool 100 also includes a gas distribution plate 142 and a gas nozzle 144 disposed in the internal volume 104 of the chamber 102. The gas distribution plate 142 has an opening therethrough, and the gas nozzle 144 has an opening therethrough. The gas distribution plate 142 and the gas nozzle 144 are electrically connected to a grounding node (e.g., electrically grounded). The chamber 102 has a gas inlet 146 fluidly connected to a gas supply system 148 and a gas outlet 150 fluidly connected to an exhaust system 152. The gas distribution plate 142 and the gas nozzle 144 are positioned relative to the substrate support 106 in the internal volume 104 of the chamber 102 such that, during semiconductor processing, gas flows from the gas supply system 148 through the gas inlet 146, through the opening formed through the gas distribution plate 142, and then through the opening formed through the gas nozzle 144, to the processing volume 154 in the internal volume 104. The processing volume 154 is arranged between the gas nozzle 144 and the substrate support 106, and is typically the location where plasma is generated during semiconductor processing (using the gas flowing into the processing volume 154). During semiconductor processing, the semiconductor substrate 120 disposed on the support surface 116 of the substrate support 106 is exposed to the plasma in the processing volume 154. The gas can then flow through the gas outlet 150 to the exhaust system 152 to be discharged from the internal volume 104 of the chamber 102.

[0043] The processing tool 100 includes a direct current (DC) power supply 160 and an isolation filter 162. The DC power supply 160 is configured to generate and output a DC voltage. Output nodes of the DC power supply 160 (e.g., positive and negative output nodes) are electrically connected to input nodes of the isolation filter 162, and output nodes of the isolation filter 162 are electrically connected to corresponding adsorption electrodes 122. The isolation filter 162 may be, for example, a low-pass filter. The DC power supply 160 can be selectively switched on and off to adsorb and release the semiconductor substrate 120.

[0044] Processing tool 100 includes an RF power supply 164 and an RF signal control circuit 166. The RF power supply 164 may include an RF power generator and an RF matching network, and is configured to generate and output an RF signal at its output node, which may be a continuous RF signal and / or a pulsed RF signal. The output node of the RF power supply 164 is electrically connected to the input node of the RF signal control circuit 166. The RF signal control circuit 166 can be controlled to generate a regulated RF signal based on the RF signal received from the RF power supply 164. The regulated RF signal generated by the RF signal control circuit 166 may have a regulated amplitude of the received RF signal (e.g., through the gain of the RF signal control circuit 166, which may have a magnitude greater than, equal to, or less than 1) and / or may have a phase shift relative to the received RF signal. The gain and / or phase shift may be selected from a set of gains and / or phase shifts implemented by the RF signal control circuit 166. The RF signal control circuit 166 has an output node electrically connected to an RF electrode 132 of an intermediate board 110. The RF signal control circuit 166 is configured to output a regulated RF signal at the output node, so that the regulated RF signal can be applied to the RF electrode 132. The RF signal output by the RF signal control circuit 166 can be used to generate and / or control plasma in the processing volume 154.

[0045] Processing tool 100 includes an RF power supply 168 and an RF bias control circuit 172. The RF power supply 168 may include an RF power generator and an RF matching network, and is configured to generate and output an RF signal at its output node, which may be a continuous RF signal and / or a pulsed RF signal. The output node of the RF power supply 168 is electrically connected to the input node of the RF bias control circuit 172. Similar to the RF signal control circuit 166, the RF bias control circuit 172 can be controlled to generate a regulated RF signal based on the RF signal received from the RF bias control circuit 172. The regulated RF signal generated by the RF bias control circuit 172 may have a regulated amplitude of the received RF signal (e.g., through the gain of the RF bias control circuit 172, which may have a magnitude greater than, equal to, or less than 1) and / or may have a phase shift relative to the received RF signal. The gain and / or phase shift may be selected from a set of gains and / or phase shifts implemented by the RF bias control circuit 172, respectively. The RF bias control circuit 172 has an output node that is electrically connected to the bias electrode 136 on the base plate 112.

[0046] In this example, the base plate 112 can be strongly capacitively connected to the RF electrode 132 in the intermediate plate 110. Therefore, according to some examples, the base plate 112 is biased by an RF signal output from the RF bias control circuit 172 to increase the drivability of the RF electrode 132, thereby generating plasma. The RF bias control circuit 172 outputs an RF signal during operation that has a target amplitude and a target phase offset relative to the RF signal applied to the RF electrode 132. Applying this RF signal to the bias electrode 136 of the base plate 112 can improve the drivability of the RF electrode 132 to generate and control plasma.

[0047] Processing tool 100 includes an RF power supply 180 and an RF signal control circuit 182. The RF power supply 180 may include an RF power generator and an RF matching network, and is configured to generate and output an RF signal at its output node, which may be a continuous RF signal and / or a pulsed RF signal. The output node of the RF power supply 180 is electrically connected to the input node of the RF signal control circuit 182. The RF signal control circuit 182 can be controlled to generate a regulated RF signal based on the RF signal received from the RF power supply 180. The regulated RF signal generated by the RF signal control circuit 182 may have a regulated amplitude of the received RF signal (e.g., through the gain of the RF signal control circuit 182, which may have a magnitude greater than, equal to, or less than 1) and / or may have a phase shift relative to the received RF signal. The gain and / or phase shift may be selected from a set of gains and / or phase shifts implemented by the RF signal control circuit 182. The RF signal control circuit 182 has an output node that is electrically connected to an external electrical connector 186 of the bottom layer 130a of the focusing ring 130. The RF signal control circuit 182 is configured to output a regulated RF signal at the output node, thus allowing the regulated RF signal to be applied to the bottom layer 130a. The RF signal output by the RF signal control circuit 182 can be used to control the plasma located near the edge of the semiconductor substrate 120 in the processing volume 154.

[0048] Processing tool 100 includes a controller 190. The controller 190 can be or includes any processor-based system, which can be or includes a hardened processor architecture, a soft processor (e.g., implemented on a programmable structure of a field-programmable gate array (FPGA), or a combination thereof. For example, the controller 190 can be or includes a computer, a server, a programmable logic controller (PLC), etc., or a combination thereof. The controller 190 can control the operation of processing tool 100 and can be programmed to implement the operation of processing tool 100 as described herein. The controller 190 is communicatively coupled to RF signal control circuitry 166, RF bias control circuitry 172, and RF signal control circuitry 182. The controller 190 can be programmed to implement various setpoints for controlling RF signal control circuitry 166, 182, and RF bias control circuitry 182. These setpoints can be implemented in RF signal control circuitry 166, 182, and RF bias control circuitry 172 to implement and / or selectively configure the corresponding control circuitry to achieve corresponding gain and / or phase shift.

[0049] Although reference Figure 1 The processing tool 100 describes a focusing ring 130 implemented to control the plasma in chamber 102; however, the focusing ring 130 can be implemented in other processing tools, such as ICP processing tools. The aspects described herein can be applied to other tools and configurations for controlling plasma.

[0050] Figure 2A It is a layout diagram of the focus ring 130 based on some examples. Figure 2A It shows Figure 2B The section 2B-2B in the xz plane is shown, and the relationship with... Figure 2C The section 2C-2C corresponds to the outer periphery of the focusing ring 130 (which is approximately in the yz plane).

[0051] refer to Figure 2BA top layer 130b is situated on and supported by a bottom layer 130a. The bottom layer 130a includes an electrode 202. The electrode 202 is electrically coupled to an external electrical connector 186, which is configured to be electrically coupled to an RF signal control circuit 182. A dielectric material 204 is coated on the electrode 202 and also forms a flange 206 that projects vertically (e.g., along the z-direction) along the outer edge of the bottom layer 130a and externally onto the top layer 130b. The dielectric material 204 provides electrical isolation from direct electrical contact between the electrode 202 and other components. The flange 206 of the bottom layer 130a provides lateral restraint of the top layer 130b relative to the bottom layer 130a. As described above, the bottom layer 130a can rotate relative to the top layer 130b. When such rotation occurs, the flange 206 can laterally restrain the top layer 130b within the lateral boundary of the bottom layer 130a to facilitate proper engagement between the bottom layer 130a and the top layer 130b.

[0052] The top layer 130b may be formed of dielectric material 208 or any other material resistant to plasma semiconductor processing (e.g., etching) exposed to the focusing ring 130. Exemplary dielectric materials 204, 208 for the bottom layer 130a and top layer 130b include any non-conductive material, such as aluminum oxide (Al2O3), yttrium oxide (Y2O3), silicon oxide (SiO2), etc., or combinations thereof. Electrode 202 may be formed of any conductive material (e.g., metal), such as aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), etc., or combinations thereof.

[0053] The bottom layer 130a has an inner vertical sidewall 212, and the top layer 130b has an inner vertical sidewall 214. A radial distance 216 is the distance from the inner vertical sidewall 212 of the bottom layer 130a to the center 210 of the focusing ring 130. A radial distance 218 is the distance from the inner vertical sidewall 214 of the top layer 130b to the center 210 of the focusing ring 130. The radial distance 218 is less than the radial distance 216. The top layer 130b extends further inward toward the center 210 of the focusing ring 130 than the bottom layer 130a. This further inward extension of the top layer 130b allows a particle trap 220 to be formed along the inner vertical sidewall 212 of the bottom layer 130a below the inwardly extended portion of the top layer 130b. The particle trap 220 can be a region where particles accumulate. Particles accumulating in particle trap 220 can be generated by the surfaces of bottom layer 130a and top layer 130b rubbing together during the relative rotation of bottom layer 130a. Particle trap 220 can prevent particle contamination of plasma semiconductor processing.

[0054] The bottom layer 130a has an upper surface 230a, and the top layer 130b has a lower surface 230b. The lower surface 230b of the top layer 130b is disposed on, in contact with, and supported by the upper surface 230a of the bottom layer 130a. Section 2C-2C intersects the upper surface 230a and the lower surface 230b. Figure 2C Section 2C-2C is shown, which is a circumferential section of a portion of the focusing ring 130. Figure 2C In the example shown, the upper surface 230a and the lower surface 230b are complementary to each other, and in other examples, as shown in the following figures, the upper and lower surfaces may not be complementary to each other.

[0055] The upper surface 230a and the lower surface 230b are arranged in a periodic structure around the focusing ring 130 in the circumferential direction, and at a given radial distance 260 from the center 210 of the focusing ring 130. Figure 2A The radial lines 240, 242, and 244 of the upper and lower surfaces 230a and 230b have the same period length. These radial lines are shown at a radial distance of 260 with a period length of 250. The radial lines 240, 242, and 244 are respectively the protruding, recessed, and protruding radial lines of the upper surface 230a, and respectively the recessed, protruding, and recessed radial lines of the lower surface 230b. The period length 250 is shown between the radial lines 240 and 244. The period length 250 is symmetrical about the centerline of the period length 250 (e.g., the recessed / protruding radial line 242).

[0056] exist Figure 2D In the layout diagram of the corresponding portion of the focusing ring 130, protruding / recessed radial lines 240, 242, and 244 are shown. Figure 2D The layout diagram illustrates the radial characteristics of radial lines 240, 242, and 244. Additionally, the period of the focusing ring is typically combined with radial characteristics. For example, for a given period, the period length along the outer circumference of the focusing ring 130 is greater than the period length along the inner circumference of the focusing ring 130 for the same given period.

[0057] The upper surface 230a and the lower surface 230b are continuous surfaces between adjacent pairs of protruding and recessed radial lines. For example, the upper surface 230a is continuous from the protruding / recessed radial line 240 to the recessed / protruding radial line 242, and the upper surface 230a is continuous from the recessed / protruding radial line 242 to the protruding / recessed radial line 244. Similarly, the lower surface 230b is continuous from the protruding / recessed radial line 240 to the recessed / protruding radial line 242, and the lower surface 230b is continuous from the recessed / protruding radial line 242 to the protruding / recessed radial line 244. In the example shown, both the upper surface 230a and the lower surface 230b are continuous surfaces between adjacent pairs of protruding and recessed radial lines, and in other examples, as shown in the following figures, one of the upper and lower surfaces is a continuous surface between adjacent pairs of protruding and recessed radial lines.

[0058] In the example shown, the upper surface 230a and the lower surface 230b are continuous surfaces at the protruding radial lines and recessed radial lines (e.g., at the protruding / recessed radial lines 240, 242, and 240). However, in other examples, the upper surface 230a and the lower surface 230b may be discontinuous at the protruding and recessed radial lines. For example, as shown in the following figures, the upper surface 230a and / or the lower surface 230b may be discontinuous at the vertex lines (e.g., the vertex lines of a triangular prism).

[0059] In the example shown, the upper surface 230a and the lower surface 230b are sinusoidal surfaces, but other examples consider other continuous surfaces with periodic structures. In further examples, the upper surface 230a and the lower surface 230b are repeating triangular surfaces or other surfaces that are discontinuous at protruding and recessed radial lines.

[0060] Figure 3 and Figure 4 The height adjustment of the focus ring 130 is shown according to some examples. (Refer to...) Figure 3 The focusing ring 130 has a height 302. Height 302 is the minimum height the focusing ring 130 can have. For ease of reference, height 302 is designated as height h0. At height h0, the protruding radial line of the upper surface 230a contacts the corresponding recessed radial line of the lower surface 230b, and similarly, the recessed radial line of the upper surface 230a contacts the corresponding protruding radial line of the lower surface 230b. In order to... Figure 3 For reference in the positioning, the protruding radial line 304 of the upper surface 230a and the protruding radial line 306 of the lower surface 230b are shown.

[0061] exist Figure 4In the focal ring 130, the focusing ring 130 has a height of 402. Height 402 is the maximum height the focusing ring 130 can have. Height 402 is height h0 plus twice the amplitude of the periodic structure of the upper surface 230a and lower surface 230b. At height 402, the protruding radial line of the upper surface 230a contacts the corresponding protruding radial line of the lower surface 230b. In order to... Figure 4 For reference in the positioning, the protruding radial line 304 of the upper surface 230a and the protruding radial line 306 of the lower surface 230b are also shown.

[0062] The rotation 404 of the bottom layer 130a relative to the top layer 130b is half the period length of the upper surface 230a and the lower surface 230b. The bottom layer 130a rotates continuously relative to the top layer 130b for one complete cycle and then returns to its original position. Figure 3 The focusing ring 130 has a height of 302. The continuous rotation of the bottom layer 130a relative to the top layer 130b causes the height of the focusing ring 130 to oscillate between height 302 and height 402, without the need for hard reset of the bottom layer 130a or the top layer 130b for height adjustment.

[0063] Figure 5 It is a simplified cross-sectional view of a focusing ring rotating assembly based on some examples, and Figure 6 This is a perspective view of the focusing ring rotating assembly. Figure 5 and Figure 6 The content shows the semiconductor substrate 120 and the focusing ring 130, and Figure 5 A substrate support 106, a base 114, and a controller 190 are shown. The focus ring rotation assembly also includes a motor 502 with a drive shaft 504. In some examples, the motor 502 is a stepper motor, and in other examples, the motor 502 may be another type of motor. The motor 502 is configured to rotate the drive shaft 504 about a vertical axis 508 (e.g., the z-direction) perpendicular to the top surface and / or support surface 116 of the semiconductor substrate 120. A rotatable frame 138 is mechanically attached to and supported by the drive shaft 504. As previously described, a rotating pin 140 is supported by and extends vertically from the rotatable frame 138. The rotating pin 140 extends through a corresponding slot formed through a flange 126 of the ESC 108 and engages with the bottom layer 130a of the focus ring 130. The motor 502 is communicatively coupled to the controller 190, and the controller 190 is configured to control the operation of the motor 502.

[0064] In operation, motor 502 causes drive shaft 504 to rotate 506 about a vertical axis 508, which in this example corresponds to the axis of drive shaft 504. The rotation 506 of drive shaft 504 causes rotatable frame 138 to rotate about vertical axis 508. As rotatable frame 138 rotates about vertical axis 508, the mechanical connection between rotatable frame 138 and the bottom layer 130a of focusing ring 130, achieved via rotating pin 140, causes the bottom layer 130a to rotate about vertical axis 508.

[0065] The substrate support 106 (e.g., ESC 108) supporting the focusing ring 130 also includes a stop mechanism that prevents rotation of the top layer 130b of the focusing ring 130 when the bottom layer 130a of the focusing ring 130 rotates. In some examples, the stop mechanism includes a pin extending laterally from a sidewall of the substrate support 106 (e.g., ESC 108) into the top layer 130b. In some examples, the stop mechanism includes a pin extending vertically from the upper surface of the substrate support 106 (e.g., ESC 108) supporting the focusing ring 130.

[0066] Figure 7A This is a layout diagram of a focusing ring 130 on flange 126 of ESC 108 according to some examples. In this example, the stop mechanism includes a stop pin 702 that extends laterally from the vertical sidewall of substrate support 106 (e.g., ESC 108) into a corresponding slot 704 in top layer 130b. Figure 7A The example includes three stop pins 702, but other numbers of stop pins can be used. Figure 7A Also shown is a rotating pin 140, which extends vertically through a corresponding circumferential slot 710 formed through the flange 126 of the ESC 108 to engage a corresponding recess 712 in the bottom layer 130a of the focusing ring 130. Figure 7A The example includes three rotating pins 140, although other numbers of pins can be used (e.g., as shown in the previous figure). Figure 7A Section 7B through the stop pin 702 and section 7C through the rotating pin 140 are shown. Figure 7B Section 7B is shown in more detail, and Figure 7C Section 7C is shown in more detail.

[0067] As mentioned earlier, for Figures 7A to 7C The semiconductor substrate 120 is disposed on and supported by a support surface 116 of a substrate support 106 (e.g., ESC 108), and the ESC 108 includes a flange 126 on which a focusing ring 130 is disposed. The focusing ring 130, including a bottom layer 130a and a top layer 130b, is arranged to laterally surround the semiconductor substrate 120.

[0068] refer to Figure 7A and Figure 7B For each stop pin 702, ESC 108 includes an actuator 706 extending above flange 126 on its sidewall. The actuator 706 is mechanically coupled to the stop pin 702 to extend and retract the stop pin 702. In the retracted position, the stop pin 702 does not engage with slot 704 in the top layer 130b of the focusing ring 130. Figure 7B As shown, in the extended position, the stop pin 702 engages with the slot 704. The slot 704 has a lateral depth (e.g., along the inner sidewall of the top layer 130b of the focusing ring 130) measured from the inner sidewall of the top layer 130b of the focusing ring 130. Figure 7B The lateral depth is sufficient to accommodate the stop pin 702 in its extended position. The lateral depth extends radially from the center of the focusing ring 130 to the edge of the focusing ring 130 that intersects with the slot 704. The slot 704 has a lateral width (e.g., along the y-direction) that approximately corresponds to the lateral width of the stop pin 702 (e.g., plus any tolerance). Figure 7B The lateral width lies in a plane parallel to the support surface 116 and perpendicular to the radial direction from the center of the focusing ring 130 to the edge of the focusing ring 130 intersecting the slot 704. The slot 704 has a vertical length (e.g., along the x-direction). Figure 7B The vertical length (in the z-direction) roughly corresponds to the vertical travel distance that the top layer 130b can vertically translate due to the rotation of the bottom layer 130a. The vertical length lies in a plane perpendicular to the support surface 116 and in the radial direction from the center point of the focusing ring 130 to the edge of the focusing ring 130 that intersects with the slot 704.

[0069] Reference Figure 7A and Figure 7CFor each rotating pin 140, the rotating pin 140 extends vertically through a corresponding circumferential slot 710 formed through the flange 126 to engage a corresponding recess 712 in the bottom surface of the bottom layer 130a of the focusing ring 130. The circumferential slot 710 has a lateral circumferential length (e.g., in the xy plane) corresponding to the allowable rotational travel distance of the rotating pin 140 and the bottom layer 130a. The lateral circumferential length is along an arc perpendicular to the corresponding radial direction (which intersects the arc). The circumferential slot 710 has a lateral width (e.g., in the radial direction) that corresponds approximately to the lateral width of the rotating pin 140 (e.g., plus any tolerance). The recess 712 has a vertical depth (e.g., in the z-direction) measured from the bottom surface of the bottom layer 130a. The bottom surface of the bottom layer 130a contacts and is supported by the upper surface of the flange 126. The vertical depth of the recess 712 is sufficient to accommodate the rotating pin 140 that engages with the recess 712, without, for example, causing the rotating pin 140 to vertically support the bottom layer 130a. The recess 712 has a lateral dimension (e.g., in the x and y directions) that is typically the corresponding lateral dimension of the rotating pin 140 (e.g., plus any tolerances).

[0070] In operation, rotation of the rotatable frame 138 (as previously described) causes the rotating pin 140 to translate circumferentially within the circumferential slot 710. This translation of the rotating pin 140, which engages with the recess 712 in the bottom layer 130a, causes the bottom layer 130a to rotate about the axis of rotation of the rotatable frame 138, which may correspond to the center of the support surface 116. With the stop pin 702 in the extended position and engaged with the slot 704, significant rotation of the top layer 130b together with the bottom layer 130a is prevented, and therefore, the bottom layer 130a rotates relative to the top layer 130b (and ESC 108). As the bottom layer 130a rotates relative to the top layer 130b, the top layer 130b can translate vertically, allowing the stop pin 702 to travel vertically within the slot 704. See reference... Figure 3 and Figure 4 The relative rotation of the bottom layer 130a and the vertical movement of the top layer 130b can change the height of the focusing ring 130.

[0071] Figure 8A This is a layout diagram of the focusing ring 130 on the flange 126 of the ESC 108 according to some examples. In this example, the stop mechanism includes a stop pin 802 that extends vertically from the upper surface of the flange 126 through a corresponding circumferential slot 804 formed through the bottom layer 130a and into a corresponding recess 806 in the top layer 130b. Figure 8A The example includes three stop pins 802, but other numbers of stop pins can be used. Figure 8A It also shows something similar to Figure 7ARotary pin 140. Figure 8A Section 8B through the stop pin 802 and section 7C through the swivel pin 140 are shown. Figure 8B Section 8B is shown in more detail, and as described above. Figure 7C Section 7C is shown. For the sake of brevity, details regarding [the section on section 7C] are omitted here. Figure 8A and Figure 8B The middle and above about Figures 7A to 7C The description of the same features as those described above.

[0072] Reference Figure 8A and Figure 8B The stop pin 802 extends vertically from the upper surface of the flange 126, which contacts and supports the focusing ring 130 (e.g., the bottom layer 130a). Figure 8A and Figure 8B In the example, the stop pin 802 can be static. The circumferential slot 804 has a lateral circumferential length (e.g., in the xy plane) corresponding to the allowable lateral rotational travel distance of the bottom layer 130a relative to the flange 126. The lateral circumferential length is along an arc perpendicular to the corresponding radial direction (which intersects the arc). The circumferential slot 804 has a lateral width (e.g., in the radial direction) that corresponds approximately to the lateral width of the stop pin 802 (e.g., plus any tolerance). The recess 806 has a vertical depth (e.g., in the z-direction) measured from the lower surface 230b of the top layer 130b. The vertical depth of the recess 806 is sufficient to accommodate the stop pin 802 engaging with the recess 806 as the top layer 130b is vertically translated between different heights of the focusing ring 130. Additionally, the stop pin 802 has a vertical height that extends sufficiently through the circumferential slot 804 in the bottom layer 130a and engages with a recess 806 in the top layer 130b at each height achievable by the focusing ring 130 (this achievable height may be limited by, for example, the travel distance of a structure connecting the upper surface 230a and the lower surface 230b via a rotating pin 140). The recess 806 has a lateral dimension (e.g., in the x and y directions) that substantially corresponds to the lateral dimension (e.g., plus any tolerances) of the stop pin 802.

[0073] In operation, rotation of the rotatable frame 138 (as previously described) causes the rotating pin 140 to translate circumferentially within the circumferential slot 710. This translation of the rotating pin 140, which engages with the recess 712 in the bottom layer 130a, causes the bottom layer 130a to rotate about the axis of rotation of the rotatable frame 138, which may correspond to the center of the support surface 116. With the stop pin 802 engaged with the recess 806, significant rotation of the top layer 130b together with the bottom layer 130a is prevented, and therefore, the bottom layer 130a rotates relative to the top layer 130b (and the flange 126 of ESC 108). As the bottom layer 130a rotates relative to the top layer 130b, the top layer 130b can translate vertically, causing the recess 806 to translate vertically relative to the stop pin 802. See reference Figure 3 and Figure 4 The relative rotation of the bottom layer 130a and the vertical movement of the top layer 130b can change the height of the focusing ring 130.

[0074] Figure 9 and Figure 10 The concept illustrates how the height of the focusing ring 130, according to some examples, can contribute to plasma control. Figure 9 and Figure 10 It is the semiconductor substrate 120 and the focusing ring 130 (as arranged in...) Figure 1 The cross-sectional view (in the processing tool 100). For example, in Figure 9 In the middle, the focusing ring 130 has Figure 3 The height is 302, and in Figure 10 In the middle, the focusing ring 130 has Figure 4 The height is 402. (Refer to...) Figure 9 The plasma sheath 902 descends in the gap between the edge of the semiconductor substrate 120 and the focusing ring 130. The plasma sheath 902 is generally flat at the center of the semiconductor substrate 120, and therefore, ion bombardment 904 from the plasma at the center of the semiconductor substrate 120 can generally be perpendicular to the top surface of the semiconductor substrate 120. At the edge of the semiconductor substrate 120, the plasma sheath 902 bends due to its descent in the gap, and therefore, ion bombardment 906 from the plasma at the edge of the semiconductor substrate 120 may generally deviate from the normal to the top surface of the semiconductor substrate 120 (e.g., at an angle to the normal). Reference Figure 10 Increasing the height of the focusing ring 130 allows the plasma sheath 1002 to extend more flatly beyond the edge of the semiconductor substrate 120. Therefore, both the ion bombardment 1004 at the center of the semiconductor substrate 120 and the ion bombardment 1006 at the edge of the semiconductor substrate 120 can be substantially perpendicular to the top surface of the semiconductor substrate 120.

[0075] Figure 11A processor-based system 1100 is illustrated according to some examples. The processor-based system 1100 may be or include a computer, server, PLC, etc., or a combination thereof. The processor-based system 1100 may be implemented as a controller 190 or any other processor-based system that implements any of the operations described herein. The processor-based system 1100 includes one or more processors 1102, a memory system 1112, a communication bus 1122, one or more input / output (I / O) interfaces 1132, and a network interface 1142.

[0076] Each processor 1102 may include one or more processor cores 1104. Each processor 1102 and / or processor core 1104 may be, for example, a hardened processor, such as a central processing unit (CPU), a reduced instruction set computing (RISC) processor, a complex instruction set computing (CISC) processor, a graphics processing unit (GPU), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), or a combination thereof, or a soft processor implemented on programmable logic, such as an FPGA.

[0077] Memory system 1112 includes one or more memory controllers 1114 and memory 1116. Memory controller 1114 is configured to control read and / or write access to a particular memory 1116 or a subset of memory 1116. Memory 1116 may include main memory, disk storage, or any suitable combination thereof. Memory 1116 may include any type of volatile or non-volatile memory, such as dynamic random access memory (DRAM), static random access memory (SRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, solid-state storage devices, etc. Memory 1116 is a non-transitory machine-readable storage medium. Instructions 1118 are stored in memory 1116. Instructions 1118 may be machine-executable code (e.g., machine code) and may include firmware, software, programs, applications, or other machine-executable code. Instructions 1118 may, for example, embody software module 1120, which, when executed by one or more processors 1102, performs the various functions and operations described herein.

[0078] One or more I / O interfaces 1132 are configured to be electrically and / or communicatively connected to one or more I / O devices 1134. I / O device 1134 includes RF signal control circuitry 166, RF bias control circuitry 172, RF signal control circuitry 182, and motor 502. RF signal control circuitry 166, RF bias control circuitry 172, RF signal control circuitry 182, and motor 502 can receive their respective setpoints via I / O interface 1132. Other example I / O devices 1134 include keyboards, mice, display devices, printers, etc. One or more I / O interfaces 1132 may include connectors or connection circuitry, such as industrial application connections, Universal Serial Bus (USB) connections, High Definition Multimedia Interface (HDMI) connections, Bluetooth® circuitry, etc.

[0079] Network interface 1142 is configured to communicatively connect to network 1144. Network interface 1142 may include circuitry for wired communication, such as an Ethernet connection, and / or may include circuitry for wireless communication, such as circuitry for Wi-Fi® communication. For example, one or more computers and / or servers communicatively connected to network 1144 may send recipes, processing conditions, etc., to processor-based system 1100 via network 1144 and network interface 1142.

[0080] Communication bus 1122 is communicatively connected to one or more processors 1102, memory system 1112, one or more I / O interfaces 1132, and network interface 1142. The components can communicate with each other via communication bus 1122. Communication bus 1122 can control the communication flow, for example, by including an arbitrator to arbitrate communication.

[0081] Figure 12This is a flowchart of a semiconductor processing method 1200 according to some examples. Method 1200 can be implemented using the processing tool 100 previously described. Operation of method 1200 can be initiated and / or controlled by controller 190 (e.g., by executing instructions 1118 by one or more processors 1102). At block 1202, a semiconductor substrate 120 is transferred into the chamber 102 of the processing tool 100 and onto a substrate support 106 (e.g., ESC 108) within the chamber 102. When the semiconductor substrate 120 is transferred into the chamber 102, a focusing ring 130 can be arranged on the flange 126 of the ESC 108. The focusing ring 130 can be at a minimum height h0. The semiconductor substrate 120 can be secured to the ESC 108 by applying a DC voltage to the adsorption electrode 122 (e.g., to adsorb the semiconductor substrate 120). The DC voltage can be generated by a DC power supply 160 and applied to the adsorption electrode 122. With the semiconductor substrate 120 being transferred into the chamber 102 and arranged on the support surface 116, the focusing ring 130 is arranged to laterally surround the semiconductor substrate 120.

[0082] At frame 1204, the height of the focusing ring 130 is adjusted. This height can be adjusted to a target height for targeted plasma control. As described above, the height can be adjusted by rotating the bottom layer 130a relative to the top layer 130b. Controller 190 can cause motor 502 to rotate the rotatable frame 138, which rotates the bottom layer 130a relative to the top layer 130b. This, in turn, adjusts the height of the focusing ring 130.

[0083] At block 1206, a plasma semiconductor process is performed in chamber 102 of the processing tool 100. The plasma semiconductor process can be, for example, an etching process, a deposition process, or any other suitable process. Exemplary plasma semiconductor processes include sputtering, PVD, MDP, PECVD, IBE, and RIE. Block 1206 includes, at block 1208, the generation of plasma in a processing volume 154 of chamber 102. Semiconductor substrate 120 may be exposed to the plasma in processing volume 154. The plasma can be generated by flowing gas into chamber 102 (e.g., from gas supply system 148 through gas inlet 146, gas distribution plate 142, and gas nozzle 144) and applying an RF signal to RF electrode 132. The plasma can be generated by an RF signal on RF electrode 132 and a grounded gas nozzle 144. Block 1206 also includes controlling the plasma at the periphery of semiconductor substrate 120 at block 1210. Although described separately for simplicity, blocks 1208 and 1210 can be implemented by the same operation. The plasma can be controlled by an RF signal applied to the RF electrode 132. (See reference...) Figure 9 and Figure 10As described, a focusing ring 130 can be used to control the plasma at the periphery based on the height of the focusing ring. Additionally, an RF signal can be applied to the electrode 202 of the bottom layer 130a of the focusing ring 130 to control the plasma at the periphery of the semiconductor substrate 120. An RF power supply 180 can generate an RF signal output to an RF signal control circuit 182, and the RF signal control circuit 182 can adjust the RF signal (adjusting it to an adjusted amplitude and / or phase) and output the adjusted RF signal. The RF signal output by the RF signal control circuit 182 is applied to the electrode 202 of the bottom layer 130a. The RF signal on the electrode 202 can partially control the electromagnetic field at the periphery of the semiconductor substrate 120 to control the plasma at the periphery. Furthermore, applying a bias voltage to the bias electrode 136 can be performed during blocks 1208 and 1210. Applying the bias voltage can include applying an RF bias signal to the bias electrode 136.

[0084] At frame 1212, the plasma semiconductor processing ends, and the semiconductor substrate 120 is conveyed out of the chamber 102 of the processing tool 100. At the end of the plasma semiconductor processing, the RF signal can be stopped from being applied to the RF electrode 132 and the electrode 202 of the focusing ring 130 (e.g., by turning off the RF power supplies 164, 180), and the gas supply to the chamber 102 can be stopped and the gas can be discharged from the chamber 102. Additionally, the RF bias signal can be stopped from being applied to the bias electrode 136. The focusing ring 130 can then be adjusted back to its minimum height h0. The DC voltage can also be stopped (e.g., by turning off the DC power supply 160) to release the semiconductor substrate 120 from ESC 108. Afterward, the semiconductor substrate 120 can be conveyed out of the chamber 102.

[0085] Figure 13 This is a flowchart of a method 1300 for semiconductor processing, based on some examples. At block 1302, processing tool 100 is used to perform the following process on a plurality of first semiconductor substrates (e.g., a batch or more of semiconductor substrates): Figure 12 The plasma semiconductor processing is as described. Plasma semiconductor processing is performed under first processing conditions. These first processing conditions include settings for the RF signal control circuit 182 and the motor 502. Based on these settings, an RF signal is applied to the electrodes 202 of the focusing ring 130 during plasma semiconductor processing, and the height of the focusing ring 130 is set for the plasma semiconductor processing.

[0086] At block 1304, a corresponding first characteristic of a plurality of first semiconductor substrates near their respective centers is measured, and at block 1306, a corresponding second characteristic of a plurality of first semiconductor substrates near their respective edges is measured. The first and second characteristics may be the same feature or component; the terms "first" and "second" are used for ease of reference. Measurements may be performed using metrological tools. In some examples, the first and second characteristics may be or include the profile angle of a recess etched by a plasma semiconductor process. In some examples, the first and second characteristics may be or include the depth of a recess etched by a plasma semiconductor process. In some examples, the first and second characteristics may be or include the thickness of a film deposited by a plasma semiconductor process. Other characteristics may be measured. Variations between the first and second characteristics may indicate plasma inhomogeneity in the plasma semiconductor process when processing the plurality of first substrates.

[0087] At block 1308, using one or more processor-based systems, second processing conditions to be applied in the processing tool when performing plasma semiconductor processing on multiple second semiconductor substrates are determined. The second processing conditions are determined based on first and second characteristics (such as the difference between the first and second characteristics) measured in blocks 1304 and 1306. The second processing conditions are processing conditions of the same type as the first processing conditions, although the values ​​or data of the first and second processing conditions may differ. As an example, a processor-based system running an advanced process control (APC) algorithm can determine the RF signal (including amplitude and phase) to be applied to the electrode 202 of the focusing ring 130, and can determine the height of the focusing ring 130. The processor-based system running the APC algorithm can then determine the setpoints for setting the RF signal control circuit 182 and the motor 502.

[0088] At block 1310, a second processing condition is applied to the processing tool performing the plasma semiconductor processing. For example, a processor-based system running an APC algorithm can send the second processing condition (e.g., via network 1144) to controller 190. Controller 190 can reset the plasma semiconductor processing procedure to have the second processing condition and can send the second processing condition (e.g., a set value) to RF signal control circuitry 182, which allows RF signal control circuitry 182 to be selectively configured based on the second processing condition, and send the second processing condition to motor 502 to adjust the height of focusing ring 130.

[0089] At frame 1312, a plasma semiconductor process is performed on a plurality of second semiconductor substrates using a processing tool 100. The plasma semiconductor process is performed under second processing conditions. Based on the settings of the second processing conditions, a motor 502 rotates the bottom layer 130a relative to the top layer 130b to achieve the height of the focusing ring 130, and an RF signal is applied to the electrode 202 during the plasma semiconductor process.

[0090] Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 These are cross-sectional views based on the corresponding focus rings 1430, 1530, 1630, 1730, and 1830 of some examples. The cross-sections of these views are along... Figure 2A The cross section is 2C-2C. Focusing rings 1430, 1530, 1630, 1730, and 1830 may be similar to the previously described focusing ring 130, except for the upper surface of the bottom layer and / or the lower surface of the top layer of the corresponding focusing rings 1430, 1530, 1630, 1730, and 1830.

[0091] Reference Figure 14 The focusing ring 1430 has a bottom layer 1430a with an upper surface 1440a and a top layer 1430b with a lower surface 1440b. The lower surface 1440b of the top layer 1430b is disposed on, in contact with, and supported by the upper surface 1440a of the bottom layer 1430a. The upper surface 1440a and the lower surface 1440b are complementary to each other. The upper surface 1440a and the lower surface 1440b are arranged in a periodic structure around the focusing ring 1430 in the circumferential direction and have the same period length at a given radial distance from the center of the focusing ring 1430. At a given radial distance from the center of the focusing ring 1430, protruding / recessed radial lines 1450, recessed / protruding radial lines 1452 and 1454 of the upper surface 1440a and the lower surface 1440b are shown in the period length 1460. The protruding / recessed radial lines 1450, 1452, and 1454 are respectively the protruding radial line, recessed radial line, and protruding radial line of the upper surface 1440a, and respectively the recessed radial line, protruding radial line, and recessed radial line of the lower surface 1440b. A period length 1460 is shown between the protruding / recessed radial lines 1450 and 1454. The period length 1460 is symmetrical about the centerline of the period length 1460 (e.g., the recessed / recessed radial line 1452).

[0092] The upper surface 1440a and the lower surface 1440b are continuous surfaces between adjacent pairs of protruding and recessed radial lines. For example, the upper surface 1440a is continuous from the protruding / recessed radial line 1450 to the recessed / protruding radial line 1452, and the upper surface 1440a is continuous from the recessed / protruding radial line 1452 to the protruding / recessed radial line 1454. Similarly, the lower surface 1440b is continuous from the protruding / recessed radial line 1450 to the recessed / protruding radial line 1452, and the lower surface 1440b is continuous from the recessed / protruding radial line 1452 to the protruding / recessed radial line 1454.

[0093] In the example shown, the upper surface 1440a and the lower surface 1440b are discontinuous surfaces at protruding radial lines and recessed radial lines (e.g., protruding / recessed radial line 1450, recessed / protruding radial line 1452, and protruding / recessed radial line 1450). In the example shown, the upper surface 1440a and the lower surface 1440b are surfaces of repeating triangular prisms.

[0094] Reference Figure 15 As previously described, the focusing ring 1530 has a bottom layer 130a with an upper surface 230a. The top layer 1530b has a lower surface 1540b. The lower surface 1540b of the top layer 1530b is disposed on, in contact with, and supported by the upper surface 230a of the bottom layer 130a. The lower surface 1540b is generally a flat surface, from which a protrusion 1542 extends. The lower surface 1540b is not complementary to the upper surface 230a. The upper surface 230a of the bottom layer 130a has a periodic structure and has a protruding radial line 1550, a recessed radial line 1552, and a protruding radial line 1554 at a given radial distance from the center of the focusing ring 1530, within a period length 1560. The protrusions 1542 of the lower surface 1540b of the top layer 1530b are circumferentially positioned around the focusing ring 1530 at a given radial distance from the center of the focusing ring 1530 with the same period length 1560. The period length 1560 in the lower surface 1540b is symmetrical about the radial lines intersecting the corresponding protrusions 1542. In this example, the lower surface 1540b is discontinuous between adjacent pairs of protruding radial lines and recessed radial lines (e.g., for an arbitrarily positioned recessed radial line on a flat surface, the lower surface 1540b is discontinuous with two adjacent protruding radial lines on either lateral side of the recessed radial line).

[0095] Reference Figure 16As previously described, the focusing ring 1630 has a top layer 130b with a lower surface 230b. The bottom layer 1630a has an upper surface 1640a. The lower surface 230b of the top layer 130b is disposed on, in contact with, and supported by the upper surface 1640a of the bottom layer 1630a. The upper surface 1640a is generally a flat surface from which the protrusion 1642 extends. The upper surface 1640a is not complementary to the lower surface 230b. The lower surface 230b of the top layer 130b has a periodic structure and has a protruding radial line 1650, a recessed radial line 1652, and a protruding radial line 1654 at a given radial distance from the center of the focusing ring 1530, within a period length 1660. The protrusions 1642 of the upper surface 1640a of the bottom layer 1630a are circumferentially positioned around the focusing ring 1630 at a given radial distance from the center of the focusing ring 1530 with the same period length 1660. The period length 1660 in the upper surface 1640a is symmetrical about the radial lines intersecting the corresponding protrusions 1642. In this example, the upper surface 1640a is discontinuous between adjacent pairs of protruding radial lines and recessed radial lines (e.g., for an arbitrarily positioned recessed radial line on a flat surface, the upper surface 1640a is discontinuous with two adjacent protruding radial lines on either lateral side of the recessed radial line).

[0096] Reference Figure 17 As previously described, the focusing ring 1730 has a bottom layer 1430a with an upper surface 1440a. The top layer 1730b has a lower surface 1740b. The lower surface 1740b of the top layer 1730b is disposed on, in contact with, and supported by the upper surface 1440a of the bottom layer 1430a. The lower surface 1740b is generally a flat surface, from which the protrusion 1742 extends. The lower surface 1740b is not complementary to the upper surface 1440a. The upper surface 1440a of the bottom layer 1430a has a periodic structure and has a protruding radial line 1750, a recessed radial line 1752, and a protruding radial line 1754 at a given radial distance from the center of the focusing ring 1530, within a period length 1760. The protrusions 1742 of the lower surface 1740b of the top layer 1730b are circumferentially positioned around the focusing ring 1730 at a given radial distance from the center of the focusing ring 1530 with the same period length 1760. The period length 1760 in the lower surface 1740b is symmetrical about the radial lines intersecting the corresponding protrusions 1742. In this example, the lower surface 1740b is discontinuous between adjacent pairs of protruding radial lines and recessed radial lines (e.g., for an arbitrarily positioned recessed radial line on a flat surface, the lower surface 1740b is discontinuous with two adjacent protruding radial lines on either lateral side of the recessed radial line).

[0097] Reference Figure 18 As previously described, the focusing ring 1830 has a top layer 1430b with a lower surface 1440b. The bottom layer 1830a has an upper surface 1840a. The lower surface 1440b of the top layer 1430b is disposed on, in contact with, and supported by the upper surface 1840a of the bottom layer 1830a. The upper surface 1840a is generally a flat surface, from which a protrusion 1842 extends. The upper surface 1840a is not complementary to the lower surface 1440b. The lower surface 1440b of the top layer 1430b has a periodic structure and has a protruding radial line 1850, a recessed radial line 1852, and a protruding radial line 1854 within a period length 1860 at a given radial distance from the center of the focusing ring 1530. The protrusions 1842 of the upper surface 1840a of the bottom layer 1830a are positioned circumferentially around the focusing ring 1830 at a given radial distance from the center of the focusing ring 1530 with the same period length 1860. The period length 1860 in the upper surface 1840a is symmetrical about the radial lines intersecting the corresponding protrusions 1842. In this example, the upper surface 1840a is discontinuous between adjacent pairs of protruding radial lines and recessed radial lines (e.g., for an arbitrarily positioned recessed radial line on a flat surface, the upper surface 1840a is discontinuous with two adjacent protruding radial lines on either lateral side of the recessed radial line).

[0098] Various upper and lower surfaces of the bottom and top layers of the focusing ring have been provided as examples. Further modifications and configurations can be made to the upper and lower surfaces of the bottom and top layers of the focusing ring based on other examples.

[0099] The first example is a component for semiconductor processing. The component includes a focusing ring configured to laterally surround a semiconductor substrate during plasma semiconductor processing. The focusing ring includes a first annular layer having a lower surface and a second annular layer having an upper surface. The upper surface is configured to support the first annular layer by contacting the upper surface with the lower surface. The lower and upper surfaces are periodically arranged in the circumferential direction. The lower and upper surfaces have the same period length at the same first radial distance from the center of the focusing ring. At least one of the lower and upper surfaces includes a first protruding radial line, a first recessed radial line, and a second protruding radial line. The first recessed radial line is laterally arranged between the first and second protruding radial lines. The period length at the first radial distance is from the first protruding radial line to the second protruding radial line. At least one of the lower and upper surfaces is continuous from the first protruding radial line to the first recessed radial line. At least one of the lower and upper surfaces is continuous from the first recessed radial line to the second protruding radial line. While the upper surface supports the first annular layer, the second annular layer can be laterally and rotatably moved relative to the first annular layer.

[0100] In the component of the first example, at least one of the lower surface and the upper surface may be continuous at each of the first protruding radial line, the first recessed radial line, and the second protruding radial line.

[0101] In the component of the first example, at least one of the lower surface and the upper surface may be discontinuous at each of the first protruding radial line, the first recessed radial line, and the second protruding radial line.

[0102] In the component of the first example, the period length from the first protruding radial line to the second protruding radial line at the first radial distance can be symmetrical about the first recessed radial line.

[0103] In the component of the first example, at least one of the lower surface and the upper surface may be a sinusoidal surface. The first protruding radial line, the first recessed radial line, and the second protruding radial line may each be in a sinusoidal surface.

[0104] In the component of the first example, the other of the lower and upper surfaces may include a second recessed radial line, a third protruding radial line, and a third recessed radial line. The third protruding radial line may be arranged laterally between the second and third recessed radial lines. The period length at the first radial distance may extend from the second recessed radial line to the third recessed radial line. The other of the lower and upper surfaces may be continuous from the second recessed radial line to the third protruding radial line. Alternatively, the other of the lower and upper surfaces may be continuous from the third protruding radial line to the third recessed radial line. Furthermore, in the aforementioned component, the other of the lower and upper surfaces is continuous at each of the second recessed radial line, the third protruding radial line, and the third recessed radial line. Alternatively, in the aforementioned component, the other of the lower and upper surfaces is discontinuous at each of the second recessed radial line, the third protruding radial line, and the third recessed radial line.

[0105] In the component of the first example, both the lower and upper surfaces can be sinusoidal surfaces. The upper surface can be complementary to the lower surface.

[0106] In the component of the first example, the first annular layer may be a non-conductive material.

[0107] In the component of the first example, the second annular layer may include conductive electrodes.

[0108] In the components of the first example, the second annular layer may include a vertically projecting flange, and the flange may be configured to laterally constrain the first annular layer.

[0109] In the component of the first example, the inner vertical surface of the first annular layer may be located at a second radial distance from the center of the focusing ring. The inner vertical surface of the second annular layer may be located at a third radial distance from the center of the focusing ring. The inner vertical surface of the second annular layer may be configured to support the first annular layer on its lower surface while being located below the first annular layer. The second radial distance may be less than the third radial distance.

[0110] In the component of the first example, the second annular layer may have a bottom surface, and a recess may be located in the second annular layer from the bottom surface. The recess may be configured to engage with a corresponding pin.

[0111] In the component of the first example, the first annular layer may have an inner sidewall. A slot may be formed in the first annular layer extending deep into the inner sidewall (to a certain depth within the first annular layer). The slot may be configured to engage with a corresponding pin. The slot may also be configured to allow the corresponding pin to travel vertically within the slot relative to the first annular layer.

[0112] In the component of the first example, the second annular layer may have a slot extending through the second annular layer. This slot may be configured to allow a corresponding pin to travel laterally within the slot relative to the second annular layer. The first annular layer may have a recess located within the first annular layer from its lower surface. The recess may be configured to engage with a corresponding pin. The recess may also be configured to allow the corresponding pin to travel vertically within the recess relative to the first annular layer.

[0113] A second example is a processing tool for semiconductor processing. The processing tool includes a chamber, a substrate support, and a focusing ring rotation assembly. The chamber has an internal volume within the chamber. The substrate support is disposed within the internal volume of the chamber. The substrate support has a support surface configured to support a semiconductor substrate. The substrate support includes a flange configured to support a focusing ring laterally surrounding the support surface. The focusing ring rotation assembly is at least partially disposed within the internal volume of the chamber. The focusing ring rotation assembly is configured to laterally rotate at least a portion of the focusing ring about an axis perpendicular to the support surface. The focusing ring rotation assembly includes a frame configured to laterally rotate about an axis perpendicular to the support surface.

[0114] In the processing tool of the second example, the substrate support may include a stop pin located on a vertical sidewall of the substrate support and above a flange. The stop pin may extend laterally from the vertical sidewall in an extended position. The stop pin is retractable. The stop pin may be configured to engage a corresponding slot in the inner sidewall of a focusing ring. Additionally, the substrate support may include actuators, each configured to retract and extend a corresponding stop pin.

[0115] In the processing tool of the second example, the substrate support may include a stop pin extending vertically from the flange. The stop pin may be configured to engage with a corresponding recess in the lower surface of the focusing ring. Alternatively, the stop pin may be fixed.

[0116] In the processing tool of the second example, the focusing ring rotating assembly may further include a rotating pin. The rotating pin may be mechanically coupled to and protrude from the frame. The rotating pin may extend through a corresponding slot formed through a flange and may project vertically above the flange configured to engage a corresponding recess in the bottom surface of the focusing ring.

[0117] In the processing tool of the second example, the focusing ring rotating assembly may also include a motor mechanically coupled to the frame and configured to rotate the frame laterally.

[0118] The processing tool in the second example may also include an electrical connector configured to be electrically connected to the focusing ring.

[0119] The processing tool of the second example may further include a power supply and control circuitry. The power supply may be configured to output a voltage at its output node. The control circuitry may have an input node electrically connected to the output node of the power supply and may have an output node configured to be electrically connected to a focusing ring. The control circuitry can be controlled to adjust the amplitude, phase, or a combination thereof of the voltage, and output a corresponding adjusted voltage at its output node. Additionally, the processing tool may include a controller. The controller may include one or more processors and a non-transitory memory. The non-transitory memory may include stored instructions that, when executed by one or more processors, cause the one or more processors to control the circuitry to adjust the amplitude, phase, or a combination thereof.

[0120] The third example is a method for semiconductor processing. The method includes adjusting the height of a focusing ring. The focusing ring is arranged laterally around a semiconductor substrate in a chamber of a processing tool. The focusing ring includes a first annular layer and a second annular layer. Adjusting the height of the focusing ring includes rotating the second annular layer relative to the first annular layer. The first annular layer has a lower surface. The second annular layer has an upper surface. The lower surface is disposed on and in contact with the upper surface. The lower and upper surfaces are periodically structured in the circumferential direction. The lower and upper surfaces have the same period length at the same first radial distance from the center of the focusing ring. At least one of the lower and upper surfaces includes a first protruding radial line, a first recessed radial line, and a second protruding radial line. The first recessed radial line is laterally disposed between the first and second protruding radial lines. The period length at the first radial distance is from the first protruding radial line to the second protruding radial line. At least one of the lower and upper surfaces is continuous from the first protruding radial line to the first recessed radial line. At least one of the lower and upper surfaces is continuous from the first recessed radial line to the second protruding radial line. The method involves generating plasma within a processing volume of a chamber while arranging a focusing ring laterally around the semiconductor substrate. The semiconductor substrate is exposed to the plasma.

[0121] In the method of the third example, at least one of the lower surface and the upper surface may be continuous at each of the first protruding radial line, the first recessed radial line and the second protruding radial line.

[0122] In the method of the third example, at least one of the lower surface and the upper surface may be discontinuous at each of the first protruding radial line, the first recessed radial line, and the second protruding radial line.

[0123] In the method of the third example, the period length from the first protruding radial line to the second protruding radial line at the first radial distance can be symmetrical about the first recessed radial line.

[0124] In the method of the third example, at least one of the lower surface and the upper surface can be a sinusoidal surface. The first protruding radial line, the first recessed radial line, and the second protruding radial line can each be in a sinusoidal surface.

[0125] In the method of the third example, the other of the lower and upper surfaces may include a second recessed radial line, a third protruding radial line, and a third recessed radial line. The third protruding radial line may be arranged laterally between the second and third recessed radial lines. The period length at the first radial distance may extend from the second recessed radial line to the third recessed radial line. The other of the lower and upper surfaces may be continuous from the second recessed radial line to the third protruding radial line. The other of the lower and upper surfaces may be continuous from the third protruding radial line to the third recessed radial line. In this method, the other of the lower and upper surfaces may be continuous at each of the second recessed radial line, the third protruding radial line, and the third protruding radial line. In this method, the other of the lower and upper surfaces may be discontinuous at each of the second recessed radial line, the third protruding radial line, and the third recessed radial line.

[0126] In the method of the third example, both the lower and upper surfaces can be sinusoidal surfaces. The upper surface can be complementary to the lower surface.

[0127] In the method of the third example, the first annular layer can be a non-conductive material.

[0128] In the third example method, the second annular layer may include conductive electrodes. Additionally, the method may also include applying a voltage to the conductive electrodes while the plasma is in the processing volume.

[0129] In the method of the third example, the second annular layer may include a vertically projecting flange. The flange may be configured to laterally constrain the first annular layer.

[0130] In the method of the third example, the inner vertical surface of the first annular layer can be located at a second radial distance from the center of the focusing ring, and the inner vertical surface of the second annular layer can be located at a third radial distance from the center of the focusing ring. The inner vertical surface of the second annular layer can be configured to support the first annular layer on its lower surface while being located below the first annular layer. The second radial distance can be less than the third radial distance.

[0131] In the third example method, a semiconductor substrate may be disposed on a substrate support within a chamber of a processing tool. The substrate support may include a flange. A focusing ring may be disposed on the flange. A focusing ring rotation assembly may rotate a second annular layer relative to a first annular layer. Additionally, in this method, the focusing ring rotation assembly may include a frame and a rotating pin mechanically coupled to and projecting from the frame. The rotating pin may extend through a corresponding slot formed through the flange and engage with a corresponding recess in the bottom surface of the focusing ring. Rotating the second annular layer relative to the first annular layer may include a rotating frame. Furthermore, in this method, the focusing ring rotation assembly may include a motor, and the motor may rotate the frame.

[0132] In this method, the substrate support may include a stop pin located on a vertical sidewall of the substrate support and above a flange. Rotating the second annular layer relative to the first annular layer may include engaging the stop pin in a corresponding slot in the inner sidewall of the first annular layer. Additionally, in this method, the stop pin is retractable.

[0133] In this method, the substrate support may include a stop pin extending vertically from the flange. Rotating the second annular layer relative to the first annular layer may include extending the stop pin through a corresponding slot formed through the second annular layer and engaging the stop pin in a corresponding recess in the lower surface of the first annular layer. Alternatively, in this method, the stop pin may be fixed.

[0134] The fourth example is a method for semiconductor processing. The method includes performing a plasma semiconductor process on a plurality of first substrates using a processing tool, having first processing conditions. The processing tool includes a substrate support configured to support the substrates during the plasma semiconductor process. During the plasma semiconductor process, a focusing ring is arranged laterally around the substrates. The focusing ring has a first annular layer and a second annular layer supporting and contacting the first annular layer. The height of the focusing ring can be adjusted by rotating the second annular layer relative to the first annular layer. The first processing condition corresponds to a first rotation amount by which the second annular layer rotates relative to the first annular layer during the plasma semiconductor process to achieve a first height of the focusing ring. The method includes measuring a corresponding first characteristic of the plurality of first substrates near a corresponding center of the plurality of first substrates. The first characteristic is formed by the plasma semiconductor process. The method includes measuring a corresponding second characteristic of the plurality of first substrates near a corresponding edge of the plurality of first substrates. The second characteristic is formed by the plasma semiconductor process. The method includes determining, using a processor-based system, second processing conditions to be applied when performing the plasma semiconductor process on the plurality of second substrates, based on the first and second characteristics. The second processing condition corresponds to a second rotation amount by which the second annular layer rotates relative to the first annular layer during the plasma semiconductor process to achieve a second height of the focusing ring. The method includes performing a plasma semiconductor process with second processing conditions on a plurality of second substrates using a processing tool.

[0135] In the method of the fourth example, for each of the plurality of first substrates, the first characteristic may include a first profile angle of a recess etched into the respective substrate near the respective center of the respective substrate, and for each of the plurality of first substrates, the second characteristic may include a second profile angle of a recess etched into the respective substrate near the respective edge of the respective substrate.

[0136] In the method of the fourth example, for each of the plurality of first substrates, the first characteristic may include a first depth of a recess etched into the respective substrate near the respective center of the respective substrate, and for each of the plurality of first substrates, the second characteristic may include a second depth of a recess etched into the respective substrate near the respective edge of the respective substrate.

[0137] In the method of the fourth example, for each of the plurality of first substrates, a first characteristic may be a first thickness of a film deposited on the respective substrate near the respective center of the respective substrate, and for each of the plurality of first substrates, a second characteristic may include a second thickness of a film near the respective edge of the respective substrate.

[0138] In the fourth example method, performing a plasma semiconductor process with first processing conditions on a plurality of first substrates may further include a third processing condition. The third processing condition may correspond to a first amplitude and a first phase of a signal applied to the electrodes of the focusing ring during the plasma semiconductor process. Determining the second processing condition may further include determining a fourth processing condition to be applied when performing the plasma semiconductor process on the plurality of second substrates based on first and second characteristics. The fourth processing condition may correspond to a second amplitude and a second phase of a signal applied to the electrodes of the focusing ring during the plasma semiconductor process. Performing a plasma semiconductor process with second processing conditions on a plurality of second substrates may further include a fourth processing condition.

[0139] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations may be made therein without departing from the scope defined by the appended claims.

Claims

1. A focusing ring configured to laterally surround a semiconductor substrate, the focusing ring comprising: The first annular layer has a lower surface; as well as A second annular layer has an upper surface configured to support the first annular layer by contacting the upper surface with the lower surface, wherein: The shapes of the lower surface and the upper surface are periodic in the circumferential direction; The lower surface and the upper surface have the same period length at the same first radial distance from the center of the focusing ring; At least one of the lower surface and the upper surface includes a first protruding radial line, a first recessed radial line and a second protruding radial line, wherein the first recessed radial line is arranged laterally between the first protruding radial line and the second protruding radial line. The period length at the first radial distance is from the first protruding radial line to the second protruding radial line; At least one of the lower surface and the upper surface is continuous from the first protruding radial line to the first recessed radial line; At least one of the lower and upper surfaces is continuous from the first recessed radial line to the second protruding radial line; and While the upper surface supports the first annular layer, the second annular layer moves laterally and rotatably relative to the first annular layer.

2. The focusing ring according to claim 1, wherein, At least one of the lower surface and the upper surface is continuous at each of the first protruding radial line, the first recessed radial line, and the second protruding radial line.

3. The focusing ring according to claim 1, wherein, At least one of the lower surface and the upper surface is discontinuous at each of the first protruding radial line, the first recessed radial line, and the second protruding radial line.

4. The focusing ring according to claim 1, wherein, The period length from the first protruding radial line to the second protruding radial line at the first radial distance is symmetrical about the first recessed radial line.

5. The focusing ring according to claim 1, wherein, At least one of the lower surface and the upper surface is a sinusoidal surface, wherein the first protruding radial line, the first recessed radial line and the second protruding radial line are each in the sinusoidal surface.

6. The focusing ring according to any one of claims 1 to 5, wherein: The other of the lower surface and the upper surface includes a second recessed radial line, a third protruding radial line, and a third recessed radial line, the third protruding radial line being arranged laterally between the second recessed radial line and the third recessed radial line; The period length at the first radial distance is from the second concave radial line to the third concave radial line; The other of the lower and upper surfaces is continuous from the second recessed radial line to the third protruding radial line; and The other of the lower and upper surfaces is continuous from the third protruding radial line to the third recessed radial line.

7. The focusing ring according to claim 6, wherein, The other of the lower and upper surfaces is continuous at each of the second recessed radial line, the third protruding radial line, and the third recessed radial line.

8. The focusing ring according to claim 6, wherein, The other of the lower and upper surfaces is discontinuous at each of the second recessed radial line, the third protruding radial line, and the third recessed radial line.

9. The focusing ring according to any one of claims 1 to 5, wherein, The upper surface and the lower surface are complementary.

10. The focusing ring according to any one of claims 1 to 5, wherein, One of the lower surface and the upper surface includes the first protruding radial line, the first recessed radial line, and the second protruding radial line, and the other of the lower surface and the upper surface includes a protrusion, and the protrusion is circumferentially positioned around the focusing ring at the first radial distance with the period length.

11. The focusing ring according to claim 10, wherein, The period length is symmetrical about the radial line intersecting the protrusion.

12. The focusing ring according to any one of claims 1 to 5, wherein, The second annular layer includes a vertically projecting flange configured to laterally constrain the first annular layer.

13. The focusing ring according to any one of claims 1 to 5, wherein: The inner vertical surface of the first annular layer is a second radial distance from the center of the focusing ring; The inner vertical surface of the second annular layer is a third radial distance from the center of the focusing ring, and the inner vertical surface of the second annular layer is configured to support the first annular layer on the lower surface while being located below the first annular layer; and The second radial distance is less than the third radial distance.

14. The focusing ring according to any one of claims 1 to 5, wherein, The second annular layer has a bottom surface, and a recess is located in the second annular layer from the bottom surface, the recess being configured to engage with a corresponding pin.

15. The focusing ring according to any one of claims 1 to 5, wherein, The first annular layer has an inner sidewall, in which a slot is formed extending deep from the inner sidewall of the first annular layer. The slot is configured to engage with a corresponding pin, and the slot is also configured to allow the corresponding pin to travel vertically relative to the first annular layer within the slot.

16. The focusing ring according to any one of claims 1 to 5, wherein: The second annular layer has a slot through the second annular layer, the slot being configured to allow a corresponding pin to travel laterally relative to the second annular layer within the slot; and The first annular layer has a recess located in the first annular layer from the lower surface, the recess being configured to engage with the corresponding pin, and the recess being further configured to allow the corresponding pin to travel vertically relative to the first annular layer within the recess.

17. A processing tool for semiconductor processing, the processing tool comprising: A chamber having an internal volume within the chamber; A substrate support is disposed in the internal volume of the chamber, the substrate support having a support surface configured to support a semiconductor substrate, the substrate support including a flange configured to support a focusing ring that laterally surrounds the support surface. as well as A focusing ring rotation assembly, at least partially disposed within the internal volume of the chamber, the focusing ring rotation assembly being configured to allow at least a portion of the focusing ring to rotate laterally about an axis perpendicular to the support surface, the focusing ring rotation assembly including a frame located below the substrate support, the frame being configured to rotate laterally about the axis perpendicular to the support surface.

18. The processing tool according to claim 17, wherein, The substrate support includes a stop pin located on the vertical sidewall of the substrate support and above the flange. In an extended position, the stop pin extends laterally from the vertical sidewall. The stop pin is retractable and is configured to engage with a corresponding slot in the inner sidewall of the focusing ring.

19. The processing tool according to claim 18, wherein, The substrate support includes actuators, each configured to retract and extend a corresponding stop pin in the stop pin.

20. The processing tool according to claim 17, wherein, The substrate support includes a stop pin extending vertically from the flange, the stop pin being configured to engage with a corresponding recess in the lower surface of the focusing ring.

21. The processing tool according to claim 20, wherein, The stop pin is fixed.

22. The processing tool according to any one of claims 17 to 21, wherein, The focusing ring rotation assembly also includes a rotating pin mechanically connected to and protruding from the frame, the rotating pin extending through a corresponding slot formed through the flange and protruding vertically above the flange, the rotating pin being configured to engage with a corresponding recess in the bottom surface of the focusing ring.

23. The processing tool according to claim 22, wherein, The corresponding slot of the flange has a lateral circumferential length corresponding to the allowable rotational travel distance of at least a portion of the rotating pin and the focusing ring, the lateral circumferential length extending along an arc perpendicular to the corresponding radial direction.

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