Transient enhancement circuit of constant-on-time switching converter

Abstract

On the basis of a constant on-time switching converter comprising a PWM comparator, an adder, a ripple generation circuit, a constant on-time generation circuit, a PWM control logic circuit, an NMOS tube M1, an NMOS tube M2, an inductor L, a resistor RFB1, a resistor RFB2, a resistor ESR, a resistor RLOAD and a capacitor COUT, an output current sampling circuit is additionally arranged, and the ripple generation circuit is improved into a controllable ripple generation circuit. The output current sampling circuit comprises a sampling resistor and a sampling amplifier, the controllable ripple generation circuit comprises a transient identification circuit and an RC ripple circuit, output current information is collected in real time through the sampling resistor and fed back to the transient identification circuit in the controllable ripple generation circuit, and output current changes are identified and include light load switching to heavy load switching and heavy load switching to light load switching. And finally, the controllable ripple generation circuit is controlled to reduce the ripple or keep the ripple at 0 when load switching occurs, so that the transient response speed can be greatly improved.

Description

Technical Field

[0001] This invention relates to switching power supplies, and more particularly to a transient enhancement circuit for constant on-time (COT) switching converters. Background Technology

[0002] As the power of switching converters increases and the number of load switching scenarios increases, the requirements for transient response also become more stringent. In addition, the application of constant on-time (COT) architecture switching converters is becoming more widespread. When the load current ILOAD quickly switches from a light load to a heavy load, the output voltage VOUT will drop and then recover; when the load quickly switches from a heavy load to a light load, the output voltage VOUT will overshoot and then recover.

[0003] Figure 1 The circuit structure of a constant on-time (COT) switching converter in the prior art includes a PWM comparator, an adder, a ripple generation circuit, a constant on-time generation circuit, a PWM control logic circuit, NMOS transistors M1 and M2, an inductor L, resistors RFB1 and RFB2, a resistor ESR, a resistor RLOAD, and a capacitor COUT. A reference voltage VREF is connected to the non-inverting input of the PWM comparator, the VC signal output from the adder is connected to the inverting input of the PWM comparator, the CMP signal output from the PWM comparator is connected to the set input of the PWM control logic circuit, the output of the constant on-time generation circuit is connected to the on-time input of the PWM control logic unit, and the HG signal output from the PWM control logic unit is connected to the gate of NMOS transistor M1. The LG signal output from the PWM control logic unit is connected to the gate of NMOS transistor M2. The drain of NMOS transistor M1 is connected to the power supply VIN. The source of NMOS transistor M2 is grounded to GND. The source of NMOS transistor M1 and the drain of NMOS transistor M2 are interconnected and output a SW signal, which is connected to one end of inductor L and the input of the ripple generation circuit, respectively. The VRAMP signal output from the ripple generation circuit is connected to one input of the adder. The other end of inductor L is connected to one end of resistor ESR, one end of resistor RFB2, and one end of resistor RLOAD. The other end of resistor RFB2 is interconnected with one end of resistor RFB1 and outputs a voltage divider feedback signal FB, which is connected to the other input of the adder. The other end of resistor ESR is grounded to GND through capacitor COUT, and the other end of resistor RLOAD is grounded to GND.

[0004] Figure 2 yes Figure 1The existing circuit used in the ripple generation circuit includes resistors R1 and R2, and capacitors C1 and C2. One end of resistor R1 serves as the input terminal of the ripple generation circuit and is connected to the SW signal. The other end of resistor R1 is connected to one end of resistor R2 and one end of capacitor C1 and outputs the signal +VP. The other end of resistor R2 is connected to one end of capacitor C2 and outputs the signal -VN. The other ends of capacitors C1 and C2 are both grounded to GND. The differential signal VRAMP = VP - VN.

[0005] when Figure 1 When a load transient occurs in the circuit, the waveform is as follows: Figure 3 As shown, when switching from light load to heavy load, FB decreases and VC decreases, resulting in an increase in duty cycle. This causes VRAMP = VP - VN to also increase in envelope. At the same time, VC = VRAMP + VFB. The rate of VC decrease is slowed down by the VRAMP signal. The same principle applies when switching from heavy load to light load. Summary of the Invention

[0006] To overcome the shortcomings of existing technologies, this invention provides a transient enhancement circuit for a constant on-time (COT) switching converter, with the goal of reducing the output voltage VOUT drop and overshoot amplitude while accelerating recovery.

[0007] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: a transient enhancement circuit for a constant on-time switching converter, the constant on-time switching converter comprising a PWM comparator, an adder, a ripple generation circuit, a constant on-time generation circuit, a PWM control logic circuit, and NMOS transistors M1 and M2, inductor L, resistors RFB1 and RFB2, resistor ESR, resistor RLOAD, and capacitor COUT; a reference voltage VREF is connected to the non-inverting input of the PWM comparator, the adder output signal VC is connected to the inverting input of the PWM comparator, the PWM comparator output signal CMP is connected to the set input of the PWM control logic unit, the output of the constant on-time generation unit is connected to the on-time input of the PWM control logic unit, and the PWM control logic unit output signal HG is connected to the NMOS transistor M1, NMOS transistor M2, inductor L, resistor RFB1, resistor RFB2, resistor ESR, resistor RLOAD, and capacitor COUT; the ... constant on-time generation unit output is connected to the on-time input of the PWM control logic unit, and The gate of MOSFET M1 and the output signal LG of the PWM control logic unit are connected to the gate of NMOS transistor M2. The drain of NMOS transistor M1 is connected to the power supply VIN. The source of NMOS transistor M2 is grounded to GND. The source of NMOS transistor M1 and the drain of NMOS transistor M2 are interconnected and output signal SW is connected to one end of inductor L and the input of the ripple generation circuit. The differential signal VRAMP output by the ripple generation circuit is connected to one input of the adder. The other end of inductor L is connected to one end of resistor ESR, one end of resistor RFB2 and one end of resistor RLOAD. The other end of resistor RFB2 is interconnected with one end of resistor RFB1 and outputs a voltage divider feedback signal FB, which is connected to the other input of the adder. The other end of resistor ESR is grounded to GND through capacitor COUT, and the other end of resistor RLOAD is grounded to GND. The ripple generation circuit includes resistors R1 and R2, and capacitors C1 and C2. One end of resistor R1 serves as the input terminal of the ripple generation circuit and is connected to the SW signal. The other end of resistor R1 is connected to one end of resistor R2 and one end of capacitor C1 and outputs the signal +VP. The other end of resistor R2 is connected to one end of capacitor C2 and outputs the signal -VN. The other ends of capacitors C1 and C2 are both grounded to GND. The differential signal VRAMP = VP - VN. Its features include: adding an output current sampling circuit and improving the ripple generation circuit to a controllable ripple generation circuit; the output current sampling circuit includes a sampling resistor RSENSE and a sampling amplifier, one end of the sampling resistor RSENSE is connected to the connection point of inductor L, resistor ESR and resistor RFB2 and connected to the non-inverting input terminal of the sampling amplifier, the other end of the sampling resistor RSENSE is connected to the non-grounded terminal of resistor RLOAD and connected to the inverting input terminal of the sampling amplifier, and the sampling amplifier outputs a VSEN signal; The controllable ripple generation circuit retains the same SW signal input and differential signal VRAMP output as the original ripple generation circuit, and adds a load current information input connected to the sampling amplifier output signal VSEN. The controllable ripple generation circuit includes a transient detection circuit and an RC ripple circuit. The transient identification circuit includes inverters INV1, INV2, INV3, and INV4, PMOS transistors MP2, MP3, MP4, and MP5, NMOS transistors MN2, MN3, and MN4, as well as a current bias IB, capacitor C3, resistor R3, and NOR gate NOR1. The source of PMOS transistor MP2 is connected to the power supply VCC along with the sources of PMOS transistors MP3, MP4, and MP5. The gate of PMOS transistor MP2 is interconnected with the gates of PMOS transistors MP3, MP4, and MP5 and connected to the drain of PMOS transistor MP2 and the current bias IB. The drain of PMOS transistor MP5 is connected to the input of inverter INV1 and the drain of NMOS transistor MN3. The source of NMOS transistor MN2 is connected to the source and grounded to GND. The gate of NMOS transistor MN3 is connected to the gate of NMOS transistor MN4, one end of resistor R3 and one end of capacitor C3 are connected to node VG. The other end of capacitor C3 is connected to the VSEN signal output by the sampling amplifier. The other end of resistor R3 is connected to the drain of NMOS transistor MN2 and the drain of PMOS transistor MP3. The source of PMOS transistor MP4 is grounded to GND. The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN4 and the input of inverter INV3. The output signal A of inverter INV3 is connected to one input of NOR gate NOR1. The other input of NOR gate NOR1 is connected to the signal B output of inverter INV2. The input of inverter INV2 is connected to the output of inverter INV1. The output signal D of NOR gate NOR1 is connected to the input of inverter INV4. Inverter INV4 outputs signal C. The RC ripple circuit adds a transmission gate composed of PMOS transistor MP1 and NMOS transistor MN1 to the ripple generation circuit, which includes resistors R1 and R2 and capacitors C1 and C2. The transmission gate is connected between the connection point of resistors R1 and R2 and capacitor C1. The gate of PMOS transistor MP1 is connected to the C signal output by inverter INV4 in the transient identification circuit. The source of PMOS transistor MP1 is interconnected with the source of NMOS transistor MN1 and connected to resistor R1. The drain of PMOS transistor MP1 is interconnected with the drain of NMOS transistor MN1 and connected to the connection point of resistor R2 and capacitor C1. The gate of NMOS transistor MN1 is connected to the D signal output by NOR1 in the transient identification circuit.

[0008] Furthermore, in the transient identification circuit, latches latch1 and latch2 can be added between the output of inverter INV3 and the input of NOR gate NOR1. The output of inverter INV3 is connected to the set input of latch1. The clock signal CLK / PWM is connected to the clock inputs of latch1 and latch2 respectively. The set input of latch2 is connected to the output of inverter INV2. The output of latch1 is connected to one input of NOR gate NOR1, and the output of latch2 is connected to the other input of NOR gate NOR1. The CLK / PWM signal serves as the clock input of the latches and can come from the clock output of the internal oscillator, the PWM periodic signal, or any periodic signal within the system.

[0009] Furthermore, in the transient identification circuit, inverters INV2, INV3, INV4, and NOR1 can be omitted; in the RC ripple circuit, the transmission gate connected between the connection point of resistor R1 and resistor R2 and capacitor C1 is composed of NMOS transistors MN5 and MN6. The drain of NMOS transistor MN6 is connected to resistor R1, the source of NMOS transistor MN6 is interconnected with the drain of NMOS transistor MN5, the source of NMOS transistor MN5 is connected to the connection point of resistor R2 and capacitor C1, the gate of NMOS transistor MN6 is connected to the interconnection terminal between the drain of PMOS transistor MP4 and the drain of NMOS transistor MN4 in the transient identification circuit, and the gate of NMOS transistor MN5 is connected to the output terminal of inverter INV1.

[0010] Furthermore, in the RC ripple circuit, the transmission gate composed of PMOS transistor MP1 and NMOS transistor MN1 can be moved from the connection point between resistor R1 and resistor R2 and capacitor C1 to the connection point between capacitor C2 and ground GND. The source of PMOS transistor MP1 is interconnected with the drain of NMOS transistor MN1 and connected to capacitor C2. The drain of PMOS transistor MP1 is interconnected with the source of NMOS transistor MN1 and connected to ground GND. The gate of PMOS transistor MP1 is connected to the C signal output by inverter INV4 in the transient identification circuit. The gate of NMOS transistor MN1 is connected to the D signal output by NOR gate NOR1 in the transient identification circuit.

[0011] Furthermore, in the RC ripple circuit, the transmission gate composed of PMOS transistor MP1 and NMOS transistor MN1 can be moved from the connection point between resistor R1 and resistor R2 and capacitor C1 to a point across resistor R2. The source of PMOS transistor MP1 is interconnected with the drain of NMOS transistor MN1 and then connected to the connection point of resistor R2, resistor R1 and capacitor C1. The drain of PMOS transistor MP1 is interconnected with the source of NMOS transistor MN1 and then connected to the non-grounded GND terminal of capacitor C2.

[0012] Furthermore, the size ratio of NMOS transistor MN4 to NMOS transistor MN2 is X:1, X>1, and the size ratio of NMOS transistor MN3 to NMOS transistor MN2 is X1:1, X1<1, preferably X=3, X1=1 / 3.

[0013] Furthermore, the PMOS transistors MP2, MP3, MP4, and MP5 form a current mirror with a size ratio of 1:1:1:1.

[0014] The advantages and significant effects of this invention are as follows: By collecting output current information and feeding it back to the transient identification circuit in the controllable ripple generation circuit, the output current change is identified through capacitive coupling, including light load to heavy load and heavy load to light load. Finally, the ripple generation circuit is controlled to reduce the ripple or keep it at 0 when load switching occurs, which can greatly improve the transient response speed. Attached Figure Description

[0015] Figure 1 It is a circuit structure of a constant on-time (COT) switching converter in the prior art; Figure 2 yes Figure 1 A type of ripple generation circuit; Figure 3 yes Figure 1 Waveform diagram of the circuit switching from light load to heavy load; Figure 4 This is the circuit diagram of the present invention; Figure 5 yes Figure 4 An implementation circuit of a transient identification circuit and an RC ripple circuit; Figure 6 yes Figure 4 , 5 Waveform diagram of the circuit switching from light load to heavy load; Figure 7 yes Figure 4 , 5 Waveform diagram when the circuit switches from heavy load to light load; Figure 8 yes Figure 5 Another implementation circuit for transient detection circuitry in a circuit; Figure 9 yes Figure 5 Another implementation circuit for transient identification circuit and RC ripple circuit in the circuit; Figure 10 yes Figure 5 Another implementation circuit for a transmission gate in a circuit; Figure 11 yes Figure 5 Another implementation circuit of a transmission gate in a circuit. Detailed Implementation

[0016] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0017] like Figure 4 The present invention is based on the prior art Figure 1 Based on the previous design, an output current sampling circuit was added, and the ripple generation circuit was improved to a controllable ripple generation circuit. The output current sampling circuit includes a sampling resistor RSENSE and a sampling amplifier. The current sampling circuit collects the output current information (i.e., the differential signal across the resistor RSENSE) in real time through the sampling resistor RSENSE, which is then amplified by the sampling amplifier to output the VSEN signal. The controllable ripple generation circuit retains the same SW signal input terminal and differential signal VRAMP output terminal as the ripple generation circuit, and adds a load current information input terminal connected to the sampling amplifier output signal VSEN.

[0018] Controllable ripple generation circuits include transient recognition circuits and RC ripple circuits, such as... Figure 5 When the output current changes abruptly, the transient information of the VSEN signal is coupled to VG through C3, which then controls MN4 and MN2 to pull down respectively. Finally, the output signals A and B are output to the transmission gate after passing through the NOR gate NOR1 and the inverter INV4. When a transient response occurs, the transmission gate composed of MP1 and MN1 will disconnect R1 from C1, that is, the charge of capacitor C1 is maintained, and the differential signal VRAMP=VP-VN also remains 0.

[0019] Figure 6 For the present invention Figure 4 , 5 The waveform diagram shows the circuit switching from light load to heavy load. When switching from light load to heavy load, i.e., when the load current ILOAD jumps from low to high, the output signal VSEN of the sampling amplifier jumps from low to high. VG is coupled up and then discharged back to its original level. The gate of MN4 is raised, causing the A signal to output a high level. The transmission gate composed of MP1 and MN1 is closed. Capacitor C1 retains its charge. VRAMP = VP - VN, and the ripple differential voltage remains unchanged. FB drops, and VC = VRAMP + VFB, so it drops and the drop amplitude is equal to the amplitude of FB. Therefore, SW immediately runs at the maximum duty cycle, which greatly improves the system response speed.

[0020] Figure 7 For the present invention Figure 4 , 5 Waveform diagram of circuit switching from heavy load to light load. When switching from heavy load to light load, i.e., when the load current ILAOD jumps from high to low, VSEN jumps from high to low. VG is coupled low and then recovers to its original level. The gate of MN3 is pulled low and then recovers, causing the B signal to output a high level. The transmission gate composed of MP1 and MN1 is closed. Capacitor C1 retains its charge. VRAMP = VP - VN. The ripple differential voltage remains unchanged. FB overshoots. VC = VRAMP + VFB also overshoots and the overshoot amplitude is equal to the amplitude of FB. Therefore, SW immediately pauses ripple until FB recovers, which greatly improves the system response speed.

[0021] Figure 8 yes Figure 5 Another implementation of the transient detection circuit in the circuit holds the transient detection signal for a certain period of time through a clocked latch. The CLK / PWM signal serves as the clock input to the latch. CLK / PWM can come from the clock output of the internal oscillator, a PWM periodic signal, or any periodic signal within the system. A latch is added before the two inputs of the NOR1 gate to broaden the transient detection signal. The original signal is a pulse signal that transitions from low to high and then back to low. The latch broadens the width of this pulse signal, and the broadening time is determined by the clock input and the latch setting. This allows for free setting of the pulse signal width, meaning the closing time of the control transmission gate can be freely set, improving the applicability of this transient enhancement structure.

[0022] Figure 9 yes Figure 5 Another implementation circuit for the transient detection circuit and RC ripple circuit in the circuit. The transient detection circuit controls the two series-connected transmission gates, NM5 and NM6, with the transient detection signal controlling the gate's output. When any one of the series-connected NMOS transmission gates is low (off), that transmission gate is closed. When the VSEN signal steps high, the VG signal is coupled high and then recovers, causing the drain output of NM4 to be pulled low and then back to high. This signal directly controls MN6 to turn off and then back on. When the VSEN signal steps low, the VG signal is coupled low and then recovers, causing MN3 to turn off and then back on. The drain output of MN3 is pulled high and then back to low, then pulled low and back to high after passing through an inverter. This signal controls MN5 to turn off and then back on. These two cases achieve the goal of closing the entire transmission gate by controlling the individual closing of one of the series-connected NMOS transmission gates.

[0023] The types of transmission gates are not limited to Figure 5It consists of NMOS and PMOS, or a single NMOS and a single PMOS, or other types. This is common knowledge and will not be elaborated further.

[0024] Figure 10 yes Figure 5 Another implementation of the transmission gate in the RC ripple circuit, wherein the transmission gate's on / off state is related to... Figure 5 The transmission gates are consistent: the C signal is connected to the gate of MP1, and the D signal is connected to the gate of MN1.

[0025] Figure 11 yes Figure 5 Another implementation circuit in the RC ripple circuit is the transmission gate, whose on / off state is related to... Figure 5 In the opposite transmission gate configuration, the D signal is connected to the gate of MP1, and the C signal is connected to the gate of MN1.

Claims

1. A transient enhancement circuit for a constant on-time switching converter, the constant on-time switching converter comprising a PWM comparator, an adder, a ripple generation circuit, a constant on-time generation circuit, a PWM control logic circuit, and NMOS transistors M1 and M2, inductor L, resistors RFB1 and RFB2, resistor ESR, resistor RLOAD, and capacitor COUT; a reference voltage VREF is connected to the non-inverting input of the PWM comparator, the adder output signal VC is connected to the inverting input of the PWM comparator, the PWM comparator output signal CMP is connected to the set input of the PWM control logic unit, the output of the constant on-time generation unit is connected to the on-time input of the PWM control logic unit, and the PWM control logic unit output signal HG is connected to the gate of NMOS transistor M1. The PWM control logic unit output signal LG is connected to the gate of NMOS transistor M2, the drain of NMOS transistor M1 is connected to the power supply VIN, the source of NMOS transistor M2 is grounded to GND, the source of NMOS transistor M1 and the drain of NMOS transistor M2 are interconnected and output signal SW is connected to one end of inductor L and the input of ripple generation circuit respectively. The ripple generation circuit outputs differential signal VRAMP signal connected to one input of adder. The other end of inductor L is connected to one end of resistor ESR, one end of resistor RFB2 and one end of resistor RLOAD. The other end of resistor RFB2 is interconnected with one end of resistor RFB1 and outputs voltage divider feedback signal FB connected to the other input of adder. The other end of resistor ESR is grounded to GND through capacitor COUT, and the other end of resistor RLOAD is grounded to GND. The ripple generation circuit includes resistors R1 and R2, and capacitors C1 and C2. One end of resistor R1 serves as the input terminal of the ripple generation circuit and is connected to the SW signal. The other end of resistor R1 is connected to one end of resistor R2 and one end of capacitor C1 and outputs the signal +VP. The other end of resistor R2 is connected to one end of capacitor C2 and outputs the signal -VN. The other ends of capacitors C1 and C2 are both grounded to GND. The differential signal VRAMP = VP - VN. Its features are: An output current sampling circuit was added, and the ripple generation circuit was improved into a controllable ripple generation circuit. The output current sampling circuit includes a sampling resistor RSENSE and a sampling amplifier. One end of the sampling resistor RSENSE is connected to the connection point of inductor L, resistor ESR and resistor RFB2 and is connected to the non-inverting input of the sampling amplifier. The other end of the sampling resistor RSENSE is connected to the non-grounded end of resistor RLOAD and is connected to the inverting input of the sampling amplifier. The sampling amplifier outputs the VSEN signal. The controllable ripple generation circuit retains the same SW signal input terminal and differential signal VRAMP output terminal as the ripple generation circuit, and adds a load current information input terminal connected to the sampling amplifier output signal VSEN; the controllable ripple generation circuit includes a transient recognition circuit and an RC ripple circuit; The transient identification circuit includes inverters INV1, INV2, INV3, and INV4, PMOS transistors MP2, MP3, MP4, and MP5, NMOS transistors MN2, MN3, and MN4, as well as a current source IB, capacitor C3, resistor R3, and NOR gate NOR1. The source of PMOS transistor MP2 is connected to the power supply VCC, and the sources of PMOS transistors MP3, MP4, and MP5 are interconnected and connected to the drain of PMOS transistor MP2 and the current bias IB. The drain of PMOS transistor MP5 is connected to the input of inverter INV1 and the drain of NMOS transistor MN3. The source of NMOS transistor MN2 is connected to the source and grounded to GND. The gate of NMOS transistor MN3 is connected to the gate of NMOS transistor MN4, one end of resistor R3 and one end of capacitor C3 are connected to node VG. The other end of capacitor C3 is connected to the VSEN signal output by the sampling amplifier. The other end of resistor R3 is connected to the drain of NMOS transistor MN2 and the drain of PMOS transistor MP3. The source of PMOS transistor MP4 is grounded to GND. The drain of PMOS transistor MP4 is connected to the drain of NMOS transistor MN4 and the input of inverter INV3. The output signal A of inverter INV3 is connected to one input of NOR gate NOR1. The other input of NOR gate NOR1 is connected to the signal B output of inverter INV2. The input of inverter INV2 is connected to the output of inverter INV1. The output signal D of NOR gate NOR1 is connected to the input of inverter INV4. Inverter INV4 outputs signal C. The RC ripple circuit adds a transmission gate composed of PMOS transistor MP1 and NMOS transistor MN1 to the ripple generation circuit, which includes resistors R1 and R2 and capacitors C1 and C2. The transmission gate is connected between the connection point of resistors R1 and R2 and capacitor C1. The gate of PMOS transistor MP1 is connected to the C signal output by inverter INV4 in the transient identification circuit. The source of PMOS transistor MP1 is interconnected with the source of NMOS transistor MN1 and connected to resistor R1. The drain of PMOS transistor MP1 is interconnected with the drain of NMOS transistor MN1 and connected to the connection point of resistor R2 and capacitor C1. The gate of NMOS transistor MN1 is connected to the D signal output by NOR1 in the transient identification circuit.

2. The transient enhancement circuit of the constant on-time switching converter according to claim 1, characterized in that: In the transient identification circuit, latches latch1 and latch2 are added between the output of inverter INV3 and the input of NOR1. The output of inverter INV3 is connected to the set input of latch1. The clock signal CLK / PWM is connected to the clock input of latch1 and latch2 respectively. The set input of latch2 is connected to the output of inverter INV2. The output of latch1 is connected to one input of NOR1, and the output of latch2 is connected to the other input of NOR1.

3. The transient enhancement circuit of the constant on-time switching converter according to claim 1, characterized in that: In the transient identification circuit, inverters INV2, INV3, INV4, and NOR1 are omitted. In the RC ripple circuit, the transmission gate connected between resistor R1 and the connection point of resistor R2 and capacitor C1 is composed of NMOS transistors MN5 and MN6. The drain of NMOS transistor MN6 is connected to resistor R1, the source of NMOS transistor MN6 is interconnected with the drain of NMOS transistor MN5, the source of NMOS transistor MN5 is connected to the connection point of resistor R2 and capacitor C1, the gate of NMOS transistor MN6 is connected to the interconnection terminal between the drain of PMOS transistor MP4 and the drain of NMOS transistor MN4 in the transient identification circuit, and the gate of NMOS transistor MN5 is connected to the output terminal of inverter INV1.

4. The transient enhancement circuit of the constant on-time switching converter according to claim 1, characterized in that: In the RC ripple circuit, the transmission gate composed of PMOS transistor MP1 and NMOS transistor MN1 is moved from the connection point between resistor R1 and resistor R2 and capacitor C1 to the connection point between capacitor C2 and ground GND. The source of PMOS transistor MP1 is interconnected with the drain of NMOS transistor MN1 and connected to capacitor C2. The drain of PMOS transistor MP1 is interconnected with the source of NMOS transistor MN1 and connected to ground GND. The gate of PMOS transistor MP1 is connected to the C signal output by inverter INV4 in the transient identification circuit. The gate of NMOS transistor MN1 is connected to the D signal output by NOR gate NOR1 in the transient identification circuit.

5. The transient enhancement circuit of the constant on-time switching converter according to claim 1, characterized in that: In the RC ripple circuit, the transmission gate formed by PMOS transistor MP1 and NMOS transistor MN1 is moved from the connection point between resistor R1 and resistor R2 and capacitor C1 to a point across resistor R2. The source of PMOS transistor MP1 is interconnected with the drain of NMOS transistor MN1 and then connected to the connection point of resistor R2, resistor R1 and capacitor C1. The drain of PMOS transistor MP1 is interconnected with the source of NMOS transistor MN1 and then connected to the non-grounded GND terminal of capacitor C2.

6. The transient enhancement circuit of the constant on-time switching converter according to claim 1, 2, 3, 4, or 5, characterized in that: The size ratio of NMOS transistor MN4 to NMOS transistor MN2 is X:1, where X>1, and the size ratio of NMOS transistor MN3 to NMOS transistor MN2 is X1:1, where X1<1.

7. The transient enhancement circuit of the constant on-time switching converter according to claim 6, characterized in that: The preferred values ​​are X=3 and X1=1 / 3.

8. The transient enhancement circuit of the constant on-time switching converter according to claim 1, 2, 3, 4, or 5, characterized in that: The PMOS transistors MP2, MP3, MP4, and MP5 form a current mirror with a size ratio of 1:1:1:1.

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