Circuit with transmission line-based signal attenuator

Abstract

The invention relates to a circuit with a signal attenuator based on a transmission line. More specifically, an electronic device may include a signal path that transmits a signal. The device may include an attenuator located on the signal path that attenuates the signal. The attenuator may not include a series switch located on the signal path. The attenuator may include transmission line segments coupled in series between an input and an output of the attenuator. The transmission line segment may extend from a first terminal to a second terminal. A first adjustable resistor may couple the first terminal to ground. A second adjustable resistor may couple the second terminal to ground. The transmission line segment may have a length configured to perform impedance matching on the attenuator. A controller can control the attenuation level of the signal attenuator by adjusting the size of the adjustable resistor. The controller may include a servo loop surrounding an operational amplifier to mitigate process, voltage, and temperature variations in the attenuator.

Description

[0001] This application claims priority to U.S. Patent Application No. 18 / 883,998, filed September 12, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates generally to electronic devices, and more specifically to electronic devices having communication circuitry. Background Technology

[0003] Electronic devices often possess communication capabilities. Electronic devices with communication capabilities have communication circuits, which have signal paths for transmitting signals.

[0004] Ensuring that a signal is transmitted along the signal path at the desired signal level can be challenging. Summary of the Invention

[0005] Electronic devices may include signal paths that transmit signals at a certain wavelength. The device may include signal attenuators disposed along the signal path. The signal attenuators can attenuate the signal. The signal attenuators may not contain series switches located along the signal path.

[0006] A signal attenuator may include a transmission line segment connected in series between the input and output terminals of the signal attenuator. This transmission line segment may extend from a first terminal to a second terminal. A first adjustable resistor may couple this first terminal to ground. A second adjustable resistor may couple this second terminal to ground. The transmission line segment may have a length configured to perform impedance matching on the attenuator. As just three examples, the length may be one-quarter, one-half, or one-eighth of the wavelength. A controller can control the attenuation level of the signal attenuator by adjusting the value of this adjustable resistor. The controller may include a servo loop around an operational amplifier to help mitigate process, voltage, and temperature variations within the attenuator.

[0007] One aspect of this disclosure provides a circuit. The circuit may include a signal path configured to transmit a radio frequency (RF) signal. The circuit may include an adjustable attenuator disposed on the signal path and configured to attenuate the RF signal. The adjustable attenuator has an input terminal and an output terminal. The adjustable attenuator may include: a transmission line segment connected in series between the input terminal and the output terminal; a first adjustable resistor coupled between a first terminal of the transmission line segment and a reference potential; and a second adjustable resistor coupled between a second terminal of the transmission line segment and a reference potential.

[0008] One aspect of this disclosure provides a radio frequency (RF) signal attenuator disposed on a signal line. The RF signal attenuator may include a transmission line extending from a first terminal to a second terminal, the first terminal being coupled to an input terminal of the RF signal attenuator and the second terminal being communicatively coupled to an output terminal of the RF signal attenuator. The RF signal attenuator may include a first adjustable resistor coupling the first terminal to a ground. The RF signal attenuator may also include a second adjustable resistor coupling the second terminal to a ground, wherein the transmission line has a length from the first terminal to the second terminal configured to match the input impedance of the RF signal attenuator to the impedance of the signal line.

[0009] One aspect of this disclosure provides an electronic device. The electronic device may include a signal path configured to transmit radio frequency (RF) signals. The electronic device may include an attenuator disposed on the signal path, wherein the attenuator is configured to attenuate RF signals and includes a first adjustable shunt resistor and a second adjustable shunt resistor. The electronic device may include a controller configured to adjust the magnitudes of the first and second adjustable shunt resistors. The controller may include an operational amplifier having outputs communicatively coupled to the first and second adjustable shunt resistors. The controller may include a set of transistors having gate terminals communicatively coupled to the outputs of the operational amplifier. The controller may include a servo loop extending around the operational amplifier from its outputs through the set of transistors to a first input of the operational amplifier. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of an exemplary electronic device with wireless circuitry according to some implementation schemes.

[0011] Figure 2 This is a schematic diagram of an exemplary wireless circuit according to some implementation schemes.

[0012] Figure 3 This is a diagram illustrating an exemplary signal path, including a signal attenuator, based on some implementation schemes.

[0013] Figure 4 This is an illustration of an exemplary signal path in which signal attenuators may be placed at one or more locations along the signal path, according to some implementation schemes.

[0014] Figure 5 This is an illustrative circuit diagram of a signal attenuator based on a quarter-wavelength transmission line, based on some implementation schemes.

[0015] Figure 6 It is based on some implementation plans. Figure 5The Smith chart illustrating the type of signal attenuator based on a quarter-wavelength transmission line is shown.

[0016] Figure 7 This is an illustrative circuit diagram of a signal attenuator based on an eighth-wavelength transmission line, according to some implementation schemes.

[0017] Figure 8 This is an illustrative circuit diagram of a signal attenuator based on a half-wavelength transmission line, based on some implementation schemes.

[0018] Figure 9 This is a circuit diagram of an exemplary controller for a transmission line-based signal attenuator, based on some implementation schemes.

[0019] Figure 10 This illustrates some implementation schemes. Figure 9 The graphs show how an exemplary controller of this type can minimize process, voltage, and temperature variations for a transmission line-based signal attenuator.

[0020] Figure 11 This is a diagram illustrating how an exemplary transmission line segment can be implemented as a lumped LC circuit according to some implementation schemes. Detailed Implementation

[0021] Figure 1 The electronic device 10 may be: a computing device, such as a laptop computer, desktop computer, computer monitor containing an embedded computer, tablet computer, cellular phone, media player, or other handheld or portable electronic device; a smaller device, such as a wristwatch, a hanging device, a headset or handset, a device embedded in glasses, goggles, a helmet, or other equipment worn on the user's head (e.g., an augmented, virtual, or mixed reality head-mounted display device), or another wearable or micro device; a television set, a computer monitor that does not contain an embedded computer, a gaming device, a navigation device, an embedded system (such as a system in which electronic equipment with a display is installed in an information kiosk or a car), a voice-controlled speaker connected to the wireless Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that enables the functions of two or more of these devices; or other electronic equipment.

[0022] like Figure 1As illustrated in the schematic diagram, device 10 may include components located on or within an electronic device housing, such as housing 12. Housing 12 (sometimes referred to as a shell) may be formed of plastic, glass, ceramic, fiber composite material, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations thereof. In some cases, housing 12 may be partially or entirely formed of a dielectric or other low-conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, housing 12, or at least some of the structures constituting housing 12, may be formed of metallic elements.

[0023] Device 10 may include control circuitry 14. Control circuitry 14 may include storage devices, such as storage device circuitry 16. Storage device circuitry 16 may include hard disk drive storage devices, non-volatile memory (e.g., flash memory configured to form a solid-state drive or other electrically programmable read-only memory), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage device circuitry 16 may include storage devices and / or removable storage media integrated within device 10.

[0024] Control circuitry 14 may include processing circuitry, such as processing circuitry 18. Processing circuitry 18 may be used to control the operation of device 10. Processing circuitry 18 may include one or more processors, such as a microprocessor, microcontroller, digital signal processor, host processor, baseband processor integrated circuit, application-specific integrated circuit, central processing unit (CPU), graphics processing unit (GPU), etc. Control circuitry 14 may be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 may be stored on storage device circuitry 16 (e.g., storage device circuitry 16 may include a non-transitory (tangible) computer-readable storage medium storing the software code). This software code may sometimes be referred to as program instructions, software, data, commands, or code. The software code stored on storage device circuitry 16 may be executed by processing circuitry 18.

[0025] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, Voice over Internet Protocol (VoIP) telephone calling applications, email applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include Internet Protocol, Wireless Local Area Network (WLAN) protocols (e.g., IEEE 802.11 protocol—sometimes referred to as...). Protocols for other short-range wireless communication links, such as The protocol may include other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 3GPP fifth-generation (5G) new radio (NR) protocols, sixth-generation (6G) protocols, sub-THz protocols, THz protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., Global Positioning System (GPS) protocols, Global Navigation Satellite System (GLONASS) protocols, etc.), antenna-based spatial ranging protocols, optical communication protocols, or any other desired communication protocol. Each communication protocol may be associated with a corresponding radio access technology (RAT), which specifies the physical connection method used to implement the protocol.

[0026] Device 10 may include input-output circuitry 20. Input-output circuitry 20 may include input-output devices 22. Input-output devices 22 may be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 may include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 may include touch sensors, displays, light-emitting components such as displays without touch sensor capability, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touchpads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, monitors, pointing devices such as touchpads, mice and joysticks, and other input-output devices can be coupled to device 10 using wired or wireless connections (e.g., some input-output devices in input-output devices 22 may be peripherals coupled to the main processing unit or other parts of device 10 via wired or wireless links).

[0027] Input-output circuitry 20 may include wireless circuitry 24 to support wireless communication. Wireless circuitry 24 (sometimes referred to herein as wireless communication circuitry 24) may include one or more antennas. Wireless circuitry 24 may also include baseband processor circuitry, transceiver circuitry, amplifier circuitry, filter circuitry, switching circuitry, RF transmission lines, RF front-end circuitry, and / or any other circuitry for transmitting and / or receiving RF signals using antennas.

[0028] Wireless circuit 24 can transmit and / or receive wireless signals within a corresponding frequency band of the electromagnetic spectrum (sometimes referred to herein as the communication band or simply the "band"). The frequency band processed by wireless circuit 24 may include the wireless local area network (WLAN) band (e.g., (IEEE 802.11) or other WLAN communication bands, such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz), 7-band and / or other Frequency bands (e.g., 1875MHz to 5160MHz); Wireless Personal Area Network (WPAN) frequency bands such as 2.4GHz Frequency bands or other WPAN communication bands; cellular phone bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, etc.); other centimeter or millimeter wave bands between 10 GHz and 100 GHz; sub-THz bands between approximately 100 GHz and 10 THz (e.g., 6G bands); near field communication (NFC) bands (e.g., 13.56 MHz); satellite navigation bands (e.g., GPS bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) bands, BeiDou Navigation Satellite System (BDS) bands, etc.); in IEEE Ultra-wideband frequencies operating under the 802.15.4 protocol and / or other ultra-wideband (UWB) communication protocols; communication frequencies under the 3GPP wireless communication standard family; communication frequencies under the IEEE 802.XX standard family; and / or any other desired frequency bands of interest.

[0029] Figure 2 This is a diagram showing exemplary components within wireless circuit 24. (Example...) Figure 2 As shown, wireless circuitry 24 may include one or more processors such as processor 26, radio frequency (RF) transceiver circuitry such as RF transceiver 28, RF front-end circuitry such as RF front-end module (FEM) 40, and antenna 42. Processor 26 may include baseband circuitry (e.g., one or more baseband processors), application processor, digital signal processor, microcontroller, microprocessor, central processing unit (CPU), programmable device, combinations and / or of these circuits. Figure 1 One or more processors are located within the processing circuitry 18. Processor 26 can be configured to generate digital (transmit or baseband) signals. Processor 26 can be coupled to transceiver 28 via path 34 (sometimes referred to as the baseband path). Transceiver 28 can be coupled to antenna 42 via an RF transmission line path. If desired, one or more RF front-end modules (such as RF front-end module 40) can be disposed between transceiver 28 and antenna 42 along RF transmission line path 36.

[0030] Wireless circuit 24 may include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 may be an antenna with a resonant element, formed from a loop antenna structure, patch antenna structure, inverted F-shaped antenna (IFA) structure, slot antenna structure, planar inverted F-shaped antenna (PIFA) structure, helical antenna structure, monopole antenna, dipole, dielectric resonator antenna (DRA) structure, waveguide antenna structure, bowtie antenna structure, or a combination of these designs. If desired, two or more antennas 42 may be arranged in one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter-wave frequencies). If desired, parasitic elements may be included in antenna 42 to adjust antenna performance. If desired, antenna 42 may be provided with a conductive cavity that supports the antenna resonant element of antenna 42 (e.g., antenna 42 may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0031] exist Figure 2 In the example, for clarity, wireless circuit 24 is illustrated as including only a single processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. Generally, wireless circuit 24 may include any desired number of processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each processor 26 may be coupled to one or more transceivers 28 via a corresponding path 34. Each transceiver 28 may include transmitter circuitry configured to output uplink signals to antenna 42, may include receiver circuitry configured to receive downlink signals from antenna 42, and may be coupled to one or more antennas 42 via a corresponding RF transmission line path 36. Each RF transmission line path 36 may have a corresponding front-end module 40 disposed thereon. If desired, two or more front-end modules 40 may be disposed on the same RF transmission line path 36. If desired, one or more RF transmission lines 36 in wireless circuit 24 may be implemented without any front-end modules disposed thereon.

[0032] The front-end module (FEM) 40 may include radio frequency front-end circuitry that operates on radio frequency signals transmitted (transmitted and / or received) through radio frequency transmission line path 36. The front-end module may include, for example, front-end module (FEM) components such as radio frequency filter circuitry 44 (e.g., low-pass filter, high-pass filter, notch filter, band-pass filter, multiplexing circuitry, duplexer circuitry, dual-signal circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio frequency switches), radio frequency amplifier circuitry 48 (e.g., one or more power amplifiers and one or more low-noise amplifiers), impedance matching circuitry (e.g., circuitry that helps match the impedance of antenna 42 to the impedance of radio frequency transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of antenna 42), radio frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on the radio frequency signals transmitted and / or received by antenna 42. Each front-end module component can be mounted on a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit board substrate. If needed, the various front-end module components can also be integrated into a single integrated circuit chip.

[0033] Filter circuit 44, switching circuit 46, amplifier circuit 48, and other circuits may be disposed along RF transmission line path 36, may be incorporated into FEM 40, and / or may be incorporated into antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) may be adjusted (e.g., using control circuit 14) to adjust the frequency response and wireless performance of antenna 42 over time.

[0034] The RF transmission line path 36 may be coupled to an antenna feed section on the antenna 42. The antenna feed section may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The RF transmission line path 36 may have a positive transmission line signal path coupled to the positive antenna feed terminal on the antenna 42. The RF transmission line path 36 may also have a ground transmission line signal path coupled to the ground antenna feed terminal on the antenna 42. This example is illustrative, and in general, the antenna 42 may be fed using any desired antenna feeding scheme. If desired, the antenna 42 may have multiple antenna feed sections coupled to one or more RF transmission line paths 36.

[0035] RF transmission line path 36 may include a means for connecting device 10 ( Figure 1The RF transmission line 36 is one or more transmission lines that route RF signals within the device. The transmission lines in device 10 may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, and combinations of these types of transmission lines. Multiple transmission lines in RF transmission line path 36 may be coupled to each other using RF connectors, RF signal couplers, RF signal splitters, and / or impedance matching circuits.

[0036] As used herein, "transmission line path" or "RF transmission line path" may refer to and is defined herein as one or more transmission lines coupled between at least a first node and a second node. The transmission line path transmits high-frequency electromagnetic signals (e.g., RF signals with frequencies greater than or equal to about 20 kHz) between at least the first and second nodes with signal loss below a threshold level. The transmission line path is typically terminated by one or more load and / or impedance matching networks (e.g., at at least the first and second nodes) to prevent signal reflection and reduce signal interference, degradation / distortion, and power loss (e.g., to help match the impedance of at least the first and second nodes at RF to the impedance of the transmission line path (such as a 50-ohm impedance).

[0037] Transmission lines in device 10 (such as those in RF transmission line path 36) may be integrated into rigid and / or flexible printed circuit boards. In a suitable embodiment, the RF transmission line path (such as RF transmission line path 36) may also include transmission line conductors integrated within a multilayer laminate structure (e.g., layers of conductive materials (such as copper) and dielectric materials (such as resin) laminated together without the intervention of adhesives). If desired, the multilayer laminate structure may be folded or bent in multiple dimensions (e.g., two-dimensional or three-dimensional) and may retain its bent or folded shape after bending (e.g., the multilayer laminate structure may be folded into a specific three-dimensional structural shape for wiring around other device components and may be rigid enough to retain its shape after folding without the need for reinforcements or other structures to hold it in place). All the multiple layers of the laminate structure may be laminated together in batches without adhesives (e.g., in a single pressing process) (e.g., in contrast to performing multiple pressing processes to laminate multiple layers together with adhesives).

[0038] Transceiver 28 may include a frequency band for processing wireless local area network (WLAN) communications (e.g., (IEEE 802.11) or other WLAN communication bands, such as the 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), the 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), 6E band (e.g., 5925MHz to 7125MHz) and / or others WLAN transceiver circuitry covering a frequency band (e.g., 1875MHz to 5160MHz); handling 2.4GHz. WPAN transceiver circuits for frequency bands or other wireless personal area network (WPAN) communication bands; cellular transceiver circuits for processing cellular telephone frequency bands (e.g., bands from approximately 600 MHz to approximately 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) band below 10 GHz, 5G New Radio Frequency Range 2 (FR2) band between 20 GHz and 60 GHz, 6G bands above 100 GHz, etc.); NFC transceiver circuits for processing near field communication (NFC) frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuits for processing satellite navigation frequency bands (e.g., GPS band from 1565 MHz to 1610 MHz, GLONASS band, BeiDou Navigation Satellite System (BDS) band, etc.); and circuits using IEEE... UWB transceiver circuitry for handling communications using the 802.15.4 protocol and / or other ultra-wideband (UWB) communication protocols; and / or any other desired radio frequency transceiver circuitry for covering any other desired communication frequency band of interest.

[0039] As used herein, the term "transmit radio frequency signal" means the transmission and / or reception of radio frequency signals (e.g., for performing one-way and / or two-way wireless communication with external wireless communication equipment). During wireless transmission, processor 26 may provide digital signals to transceiver 28 via path 34. Transceiver 28 may also include circuitry for converting baseband signals received from processor 26 into corresponding intermediate frequency (IF) or radio frequency (RF) signals. For example, transceiver 28 may include mixer circuitry 45 that upconverts (or modulates) the baseband signal to an IF (e.g., as an IF signal), upconverts the baseband signal to a higher IF (e.g., as a radio frequency (RF) signal), and / or upconverts the IF signal to RF, before transmitting it via antenna 42. Transceiver 28 may also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between the digital and analog domains. Transceiver 28 may include amplifier circuitry 41 (e.g., one or more power amplifiers) for amplifying the RF signal for transmission. Additionally or alternatively, one or more power amplifiers in amplifier circuit 48 may amplify the radio frequency signal for transmission. Transceiver 28 may include a transmitter that transmits the radio frequency signal via antenna 42 through radio frequency transmission line path 36 and front-end module 40. Antenna 42 may transmit the radio frequency signal to external wireless equipment by radiating the radio frequency signal into free space (or through a dielectric overlay on device 10).

[0040] During wireless reception, antenna 42 may receive radio frequency (RF) signals from external wireless equipment (e.g., from free space). The received RF signals may be transmitted to transceiver 28 via RF transmission line path 36 and front-end module 40. One or more low-noise amplifiers in amplifier circuit 41 and / or amplifier circuit 48 may amplify the received signals. Transceiver 28 may include circuitry for converting the received RF signals into corresponding intermediate frequency (IF) or baseband signals. For example, transceiver 28 may use mixer circuitry 45 to downconvert (or demodulate) the received RF signals to an IF, downconvert the received RF signals to a baseband frequency (e.g., as a baseband signal or baseband data), and / or downconvert the IF signal to a baseband frequency, and then transmit the received signals to processor 26 via path 34. Mixer circuitry 45 may include local oscillator circuitry, such as local oscillator (LO) circuitry 43. The local oscillator circuit 43 can generate an oscillator signal, which the mixer circuit 45 uses to modulate the transmitted signal from the baseband frequency to the radio frequency and / or demodulate the received signal from the radio frequency to the baseband frequency.

[0041] Electronic devices, such as device 10, may include signal transmission circuitry that transmits electrical signals along a signal path. Figure 3 This is a diagram illustrating an exemplary signal path 50 in device 10. Signal path 50 is sometimes also referred to herein as signal transmission path 50, transmission path 50, or transmit path 50. For example... Figure 3 As shown, signal path 50 can be coupled between input node 52 and output node 54. Device 10 may include a signal source (not shown) communicatively coupled to input node 52. Device 10 may also include an output load communicatively coupled to output node 54.

[0042] Signal path 50 can transmit electrical signals, such as the signal sig, from input node 52 to output node 54. If needed, signal path 50 can be formed in wireless circuit 24. Figure 1 In this context, the signal sig can be either a radio frequency (RF) signal or a baseband signal, as two examples. The specific implementation of the RF signal sig is described herein as an example. If desired, the signal sig can carry wireless data (e.g., the signal sig can be modulated and / or encoded to carry streams of radio symbols, packets, frames, datagrams, etc., which are transmitted to, received from, or transferred between two components of device 10). Furthermore, the signal sig can carry spatial ranging waveforms (such as radar waveforms), reference signal waveforms, or any other desired waveform.

[0043] In the specific implementation where the signal sig is a radio frequency signal, the signal path 50 may include the radio frequency transmission line path 36 ( Figure 2 The signal path 50 is, in whole or in part, and is sometimes referred to herein as radio frequency signal path 50, radio frequency path 50, radio frequency transmission path 50, or radio frequency transmit path 50. The signal path 50 may couple the FEM 40 to the antenna 42, may couple the FEM 40 to the transceiver circuit 28, may couple the transceiver circuit 28 to the processor 26, may be disposed on the FEM 40 and may extend between two components of the FEM 40, and / or may be disposed on the transceiver circuit 28 and may extend between two components of the transceiver circuit 28.

[0044] The signal source coupled to input node 52 may include transceiver circuit 28. Figure 2 The transmitter in transceiver circuit 28, the receiver in transceiver circuit 28, the baseband circuit in processor 26, the amplifier in amplifier circuit 41, the amplifier in amplifier circuit 48, the switch in switching circuit 46, the filter in filter circuit 44, the antenna 42, the signal generator, the synthesizer, the mixer in mixer circuit 45, the mixer in FEM 40, and / or any other desired signal source. Conversely, the output load coupled to output node 54 may include transceiver circuit 28 ( Figure 2 The transmitter in ) the receiver in transceiver circuit 28, the baseband circuit in processor 26, the amplifier in amplifier circuit 41, the amplifier in amplifier circuit 48, the switch in switching circuit 46, the filter in filter circuit 44, the antenna 42, the signal generator, the synthesizer, the mixer in mixer circuit 45, the mixer in FEM 40 and / or any other desired output load.

[0045] This example is illustrative and not limiting, and in general, signal path 50 can be any desired signal path in device 10, and signal sig can be at any desired frequency. If desired, signal path 50 can transmit signal sig within or between different boards, packages, nodes, chips, integrated circuits, processors, components, accessories, devices (such as device 10), etc.

[0046] Signal path 50 can receive signals at input power level P. in The signal sig. Signal path 50 can output at the output power level P. outThe signal path 50 may include a set of M circuit components 56 arranged along the signal path (e.g., first component 56-1, second component 56-2, Mth component 56-M, etc.). M may be any desired integer greater than or equal to zero. Components 56 may be components configured to adjust the signal level (e.g., voltage level, magnitude, amplitude, power level, etc.) of the signal sig propagating along the signal path 50. Components 56 may include, for example, amplifiers (e.g., power amplifiers (PA), low-noise amplifiers (LNA), gain stages, amplifier stages, etc.), signal splitters, signal combiners, signal couplers, mixers, transformers, DC-DC converters, and / or any other components that adjust the signal level of the signal sig.

[0047] In implementation, it may be desirable to tune the amplitude of the signal sig after the signal has been operated by component 56 (e.g., to tune the signal level to match a desired level that component 56 cannot achieve on its own) and / or before providing the signal sig to component 56 (e.g., to tune the signal level to match the optimal range of the input level associated with that component 56). Therefore, signal path 50 may include a set of N signal attenuators 58 (e.g., first signal attenuator 58-1, second signal attenuator 58-2, Nth signal attenuator 58-N, etc.) located between input node 52 and output node 54. N can be any desired integer greater than or equal to one.

[0048] Signal attenuators 58 can be coupled to the input of a corresponding component 56, the input of signal path 50 (see, for example, signal attenuator 58-1 coupled between the input of component 56-1 and input node 52), the output of a corresponding component 56, the output of signal path 50 (see, for example, signal attenuator 58-N coupled between the output of component 56-M and output node 54), and / or between the first component 56 and the second component 56 (see, for example, signal attenuator 58-2 coupled between component 56-1 and component 56-2). Each signal attenuator 58 can receive a signal sig and attenuate (reduce) the signal level of signal sig (e.g., voltage level, magnitude, amplitude, power level, etc.) by a desired amount (attenuation level). If desired, one or more signal attenuators 58 can be adjustable to change the amount of attenuation produced by the signal attenuator over time. The N signal attenuators 58 and M components 56 on signal path 50 can collectively reduce the signal sig from the input power level P at input node 52. in Converted to the output power level P at output node 54 out .

[0049] Figure 4This is a circuit diagram illustrating an exemplary embodiment of signal path 50, wherein components 56 on signal path 50 include at least three amplifiers 60-1, 60-2, and 60-3, a signal combiner (adder) 62, and a mixer 64. Figure 4 As shown, amplifier 60-1 can be disposed on signal path 50 between amplifier 60-2 and input node 56. Amplifier 60-2 can be disposed on signal path 50 and signal combiner 62. Amplifiers 60-1 and 60-2 can each amplify the signal sig received at input node 56.

[0050] An additional signal path 50' can be coupled to signal path 50 via signal combiner 62. Signal combiner 62 increases the power of signal sig propagating along signal path 50 by combining the power from signal path 50' to signal path 50. Amplifier 60-3 can be disposed on signal path 50 between signal combiner 62 and mixer 64. Amplifier 60-3 can further amplify signal sig. Before outputting signal sig at output node 54, mixer 64 can upconvert signal sig (e.g., from baseband to intermediate frequency or radio frequency, or from intermediate frequency to radio frequency), or downconvert signal sig (e.g., from radio frequency to intermediate frequency or baseband, or from intermediate frequency to baseband).

[0051] In this specific implementation, one or more signal attenuators 58 ( Figure 3 A signal attenuator can be positioned at any desired number of nodes 66 on the signal path 50 (e.g., between input node 56 and the input of amplifier 60-1, between the output of amplifier 60-1 and the input of amplifier 60-2, between the output of amplifier 60-2 and the signal combiner 62, between the signal combiner 62 and the input of amplifier 60-3, between the output of amplifier 60-3 and the input of mixer 64, and / or between the output of mixer 64 and the output node 54) to adjust or fine-tune the power level of signal sig before it is supplied to amplifier 60-1, amplifier 60-2, signal combiner 62, amplifier 60-3, mixer 64, and / or output node 54. The signal attenuator at node 66 can, for example, facilitate gain tuning, amplitude equalization, isolation, and / or matching of signal sig. Figure 4 The examples are illustrative and not limiting. In general, signal path 50 may include any desired component 56 and any desired signal attenuator 58 at any desired location along the signal path.

[0052] In some cases, the signal attenuator 58 is implemented as a resistive step attenuator. Resistive step attenuators include π-type attenuators and T-type attenuators. In a π-type attenuator, an adjustable series resistor is disposed on the signal path 50 and connected in series between the input and output nodes of the attenuator. The signal sig flows through the adjustable series resistor. A first adjustable shunt resistor and a second adjustable shunt resistor are coupled between the end of the adjustable series resistor and ground. In a T-type attenuator, a first adjustable series resistor and a second adjustable series resistor are disposed on the signal path 50 and connected in series between the input and output nodes of the attenuator. The signal sig flows through the first and second adjustable series resistors. The adjustable shunt resistor couples the nodes on the signal path between the first and second adjustable series resistors and ground.

[0053] The adjustable resistor in T-type and π-type attenuators includes a switch that is adjusted to tune the resistance of the adjustable resistor. This changes the relative amount of incident signal shunt to ground and thus the level of attenuation performed by the attenuator. However, the switching components coupled in series along the signal path 50 (such as the adjustable series resistor in π-type and T-type attenuators) always introduce non-zero insertion loss (e.g., at least 1 dB insertion loss) to the signal sig transmitted along the signal path 50, which can degrade the performance of wireless communication using the signal sig. Furthermore, resistive step attenuators exhibit a relatively limited tuning range (e.g., a limited range of attenuation levels).

[0054] To reduce the amount of insertion loss generated by the signal attenuator, to increase the tuning (attenuation) range of the signal attenuator, and to maximize the flexibility of implementing the signal attenuator on the substrate in device 10, the signal attenuator 58 in the signal path 50 may include a transmission line-based signal attenuator. Therefore, the signal attenuator 58 is sometimes referred to herein as a transmission line-based signal attenuator 58, or more simply as a transmission line attenuator 58.

[0055] Figure 5 This is a circuit diagram of an illustrative transmission line-based signal attenuator 58. (See diagram for example.) Figure 5 As shown, the transmission line-based signal attenuator 58 may have an input node 70 and an output node 72 disposed along the signal path 50. The input node 70 is sometimes referred to herein as the input terminal 70 or input port 70 of the transmission line-based signal attenuator 58. The output node 72 is sometimes referred herein as the output terminal 72 or output port 72 of the transmission line-based signal attenuator 58.

[0056] The transmission line-based signal attenuator 58 may alternatively include a transmission line segment 68 connected in series between the input node 70 and the output node 72, instead of an adjustable resistor (as in a resistive step attenuator) connected in series between the input node 70 and the output node 72. The transmission line segment 68 may have a first terminal 82 communicatively coupled to the input node 70. The transmission line segment 68 may have an opposite second terminal 84 communicatively coupled to the output node 72. The transmission line segment 68 may extend from terminal 82 to terminal 84 and may have a length L measured from terminal 82 to terminal 84. Terminals 82 and 84 are sometimes also referred to herein as nodes 82 and 84.

[0057] Transmission segment 68 is sometimes simply referred to herein as transmission line 68. Transmission line 68 can be formed using any desired transmission line structure (e.g., one or more coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, twisted-pair cables, slotted wires, waveguides, etc.). Transmission lines such as transmission segment 68 include at least a first conductor (e.g., a signal conductor) and a second conductor (e.g., a ground or reference conductor) extending between at least a first node and a second node, such as terminals 82 and 84 (e.g., where the first and second conductors propagate electromagnetic waves at radio frequency between at least the first and second nodes). Transmission lines may include one or more shielding structures that provide electrical isolation from nearby circuitry and / or facilitate the propagation of electromagnetic energy at radio frequency between at least the first and second nodes. Not all signal lines are transmission lines. For example, general-purpose signal lines carrying digital and / or analog signals at frequencies below about 20 kHz, not optimized for minimum signal loss at radio frequency and / or not properly terminated at radio frequency are not “transmission lines” or “transmission segments” as defined herein.

[0058] The transmission line-based signal attenuator 58 may also include adjustable shunt resistors, such as adjustable resistor R1 and adjustable resistor R2. Adjustable resistor R1 may be coupled between terminal 82 of transmission line segment 68 and a reference potential such as ground 78. Adjustable resistor R2 may be coupled between terminal 84 of transmission line segment 68 and a reference potential such as ground 78. The transmission line segment 68 couples adjustable resistor R1 to adjustable resistor R2 via a portion of the signal path 50 (e.g., a portion formed by transmission line segment 68 may couple adjustable resistor R1 to adjustable resistor R2), which does not contain any adjustable resistors or switches (i.e., there are no switches or adjustable resistors along the entire length of transmission line segment 68 from terminal 82 to terminal 84). Adjustable resistors R1 and R2 are sometimes also referred to herein as adjustable resistors, adjustable shunt resistors, or adjustable shunt resistors.

[0059] Adjustable resistors R1 and R2 can be controlled from controller 86 via one or more control paths 88 (e.g., forming...). Figure 1 The controller (a part of the control circuit 14) receives a control signal. The control signal can be a digital control signal or an analog control signal. The control signal can set adjustable resistors R1 and R2 to a desired value and / or can adjust adjustable resistors R1 and R2 between different values ​​over time. During the transmission of signal sig along signal path 50, the values ​​of adjustable resistors R1 and R2 determine the amount of signal sig shunted from signal path 50 to ground 78, thereby effectively reducing (attenuating) the power of signal sig from the input power level P1 at input node 70 to the output power level P2 at output node 72. When the transmission line-based signal attenuator 58 is configured not to perform any attenuation on signal sig, the output power level P2 can be less than or equal to the input power level P1. The attenuation level of the transmission line-based signal attenuator 58 can be given, for example, by the difference between the output power level P2 and the input power level P1. The controller 86 can use control signals provided via control path 88 to set the attenuation level of the transmission line-based signal attenuator 58 by setting the adjustable resistors R1 and R2 to appropriate values. The controller 86 can also use control signals to change the attenuation level of the transmission line-based signal attenuator 58 over time by varying the values ​​of the adjustable resistors R1 and / or R2.

[0060] Adjustable resistors R1 and R2 can be implemented using any desired adjustable resistors and / or resistive components. As an example, adjustable resistor R1 may include one or more transistors such as transistor 80, and adjustable resistor R2 may include one or more transistors such as transistor 82. The terms "source" and "drain" terminals used to refer to current-carrying terminals in transistors are used interchangeably and are sometimes referred to as "source-drain" terminals. Therefore, the drain terminal of transistor 80 may sometimes be referred to as the first source-drain terminal, and the source terminal of transistor 80 may be referred to as the second source-drain terminal (or vice versa).

[0061] Transistor 80 may have a first source-drain terminal coupled to terminal 82 of transmission line segment 68. Transistor 80 may have a second source-drain terminal coupled to ground portion 78. Transistor 80 may have a gate terminal coupled to a control circuit such as controller 86 via one or more control paths 88. Transistor 82 may have a first source-drain terminal coupled to terminal 84 of transmission line segment 68. Transistor 82 may have a second source-drain terminal coupled to ground portion 78. Transistor 82 may have a gate terminal coupled to controller 86 via one or more control paths 88.

[0062] The controller 86 may, for example, supply analog control signals to the gate terminals of transistors 80 and 82. The control signals may supply a gate voltage to transistor 80, which sets a desired source-drain voltage between the first and second source-drain terminals of transistor 80. This also sets the magnitude of the adjustable resistor R1 and the amount of signal sig shunted from signal path 50 through the adjustable resistor R1. Simultaneously, the control signals may supply a gate voltage to transistor 82, which sets a desired source-drain voltage between the first and second source-drain terminals of transistor 82. This also sets the magnitude of the adjustable resistor R2 and the amount of signal sig shunted from signal path 50 through the adjustable resistor R2 (e.g., to configure the transmission line-based signal attenuator 58 to exhibit a desired attenuation level, or equivalently, to configure the transmission line-based signal attenuator 58 to output signal sig at output power level P2 given its input power level P1).

[0063] For example, the adjustable resistor R1 can be implemented using a first set of transistors, and the adjustable resistor R2 can be implemented using a second set of transistors. In this example, the controller 86 can supply digital control signals to the gate terminals of each set of transistors to set the magnitude of the adjustable resistance exhibited by the transistor sets. The digital control signals can be asserted, for example, at a logic high level to turn on the corresponding transistor in each set (e.g., to make the transistor exhibit a transconductance greater than a threshold level between its source and drain terminals, an impedance less than a threshold impedance between its source and drain terminals, and / or to allow current to flow between its source and drain terminals), and can be deasserted (e.g., provided at a logic low level) to turn off the corresponding transistor in each set (e.g., to make the transistor exhibit a transconductance less than a threshold level between its source and drain terminals, an impedance greater than a threshold impedance between its source and drain terminals, and / or to stop the current flow between its source and drain terminals), so that each set collectively exhibits an adjustable resistance of the desired magnitude. These examples are illustrative, and in general, adjustable resistors R1 and R2 can be implemented using any desired resistive components, switching components, transistors, etc.

[0064] In some configurations, the adjustable resistor R1 can be set to the same value as the adjustable resistor R2. In these embodiments, the adjustable resistors R1 and R2 are symmetrically applied to the transmission line segment 68 (e.g., equal amounts are applied at terminals 82 and 84). This configures the transmission line-based signal attenuator 58 to form a symmetrical transmission line-based signal attenuator. In other configurations, the adjustable resistor R1 can be set to exhibit a different value than the adjustable resistor R2. In these embodiments, the adjustable resistors R1 and R2 are asymmetrically applied to the transmission line segment 68 (e.g., different amounts are applied at terminals 82 and 84). This configures the transmission line-based signal attenuator 58 to form an asymmetrical transmission line-based signal attenuator.

[0065] like Figure 5 As shown, an arbitrary input load 76 with an impedance Z0 (e.g., 50 ohms) coupled between input node 70 and ground 78 may exist. An arbitrary output load 74 with an impedance Z0 coupled between output node 72 and ground 78 may also exist. The transmission line-based signal attenuator 58 may exhibit an input impedance Zin (e.g., away from input node 70 and towards terminal 82 of transmission line segment 68) and an output impedance Zout (e.g., away from terminal 84 of transmission line segment 68 and towards output node 72). Given the settings (sizes) of adjustable resistors R1 and R2, the length L of transmission line segment 68 is selected to perform appropriate impedance matching between the input impedance Zin and the output impedance Zout. The length L may, for example, be approximately equal to one-quarter (e.g., within 15% of one-quarter of the wavelength) of the signal sig propagating along the signal path 50 between input node 70 and output node 72. When configured in this way, the transmission line segment 68 is sometimes referred to as a quarter-wavelength impedance transformer, and the transmission line-based signal attenuator 58 is sometimes referred to herein as a quarter-wavelength transmission line-based signal attenuator 58.

[0066] Figure 6 The Smith chart 90 illustrates how transmission line segment 68 can perform matching for transmission line-based signal attenuator 58 in an example where adjustable resistors R1 and R2 have the same size (e.g., when the transmission line-based signal attenuator 58 is configured to form a symmetrical quarter-wavelength transmission line-based signal attenuator 58).

[0067] Point 92 at the center of the Smith chart 90 represents a nominal (50 ohms) resistance (e.g., that experienced by the signal sig, which propagates along signal path 50 and is incident on the attenuator at input node 70). An adjustable resistor R1 shifts the signal away from point 92, as indicated by arrow 94. The signal sig can propagate along transmission segment 68 for one-quarter of its wavelength. Therefore, transmission segment 68 effectively shifts the phase of the signal sig by one-quarter of its wavelength. This shifts the signal away from the tip of arrow 94, as indicated by arrow 96. Finally, in this example, an adjustable resistor R2, having the same size as the adjustable resistor R1, shifts the signal from the tip of arrow 96 back to point 92, as indicated by arrow 98, which has the same size and orientation as arrow 94 (e.g., matching the nominal impedance of the signal along signal path 50 before reaching the input node 70 of the attenuator).

[0068] return Figure 5 The propagation of signal sig through transmission line-based signal attenuator 58 can be characterized by corresponding complex scattering parameters (sometimes referred to as S-parameters). The scattering parameters include a first scattering parameter S11 (sometimes referred to as the reflection coefficient at the input of transmission line-based signal attenuator 58), which characterizes the amount of incident signal sig reflected from input node 70 away from transmission line-based signal attenuator 58 and returning towards input node 70 (e.g., due to the impedance discontinuity between input impedance Zin and impedance Z0). The scattering parameters also include a second scattering parameter S22 (sometimes referred to as the reflection coefficient at the output of transmission line-based signal attenuator 58), which characterizes the amount of signal sig reflected from output node 72 away from transmission line-based signal attenuator 58 and returning to output node 72 (e.g., due to the impedance non-discontinuity between input impedance Zout and impedance Z0). The scattering parameters also include a third scattering parameter S21 (sometimes referred to as the forward or transmission coefficient of the transmission line-based signal attenuator 58), which characterizes the amount of signal sig incident on the input node 70, which is transmitted to the output node 72 via the transmission line-based signal attenuator 58. Generally, when the attenuation level of the transmission line-based signal attenuator 58 is set relatively high, the scattering parameter S21 will exhibit a relatively low magnitude, and when the attenuation level of the transmission line-based signal attenuator 58 is set relatively low, the scattering parameter will exhibit a relatively high magnitude.

[0069] Generally speaking, when implemented as a symmetrical transmission line-based signal attenuator, the operation of the transmission line-based signal attenuator 58 can be characterized by the factor g = Z0 / R, where R is equal to the magnitudes of both adjustable resistors R1 and R2. Input impedance Z in It is a function of Z0 and the factor g, as shown in the formula Z. in=Z0*[(1 / (1+g)+g] -1 ≈Z0*[1-g+g] -1 =Given by Z0. The magnitude of the scattering parameter S21, |S21|, is given by the formula |S21|=2 / [(1+g) / 2]. 2 +1] is given.

[0070] When configured in this manner, the magnitude of the scattering parameter S11 is minimized (e.g., less than -17 dB) at the frequency of the signal sig in the frequency band from frequency FA (e.g., 35 GHz) to frequency FB (e.g., 50 GHz) across all sizes of the adjustable resistors R1 and R2. In other words, the impedance matching performed by transmission line segment 68 effectively minimizes the amount of signal reflected back from input node 70. The magnitude of the scattering parameter S22 is also minimized (e.g., less than -17 dB) at the frequency of the signal sig in the frequency band from frequency FA to frequency FB. In other words, the impedance matching performed by transmission line segment 68 effectively minimizes the amount of signal reflected back from output node 72. The magnitude of the scattering parameter S21 corresponds to the amount of signal attenuation performed by the attenuator. The transmission line-based signal attenuator 58 can exhibit a relatively wide gain range (e.g., up to 5 dB to 6 dB) between its lowest and highest attenuation levels.

[0071] Meanwhile, the transmission line-based signal attenuator 58 contributes less insertion loss to the attenuated signal sig than a resistive step attenuator (e.g., when configured to exhibit its lowest attenuation level) because the transmission line-based signal attenuator 58 comprises only a transmission line segment 68 series-coupled between the input node 70 and the output node 72, and does not include any adjustable resistors or switches series-coupled between the input node 70 and the output node 72. Furthermore, the transmission line segment 68 can be implemented using transmission line wiring already present on the signal path 54, and can be flexibly placed and routed on its corresponding substrate (e.g., reducing the footprint of the transmission line-based signal attenuator 58 compared to a resistive step attenuator).

[0072] Consider another example where the transmission line-based signal attenuator 58 is configured to form an asymmetric quarter-wavelength transmission line-based signal attenuator. In this example, the transmission line segment 68 has a length L = λ / 4, an adjustable resistor R1 is set to exhibit a first size RA, and an adjustable resistor R2 is set to exhibit a second size RB different from the size RA of the adjustable resistor R1. The transmission line-based signal attenuator 58 can exhibit an additional input impedance Z from the output node 72 toward the transmission line segment 68. in2 .

[0073] In this configuration, the operation of the transmission line-based signal attenuator 58 can be characterized by a first factor g1 = Z0 / RA and a second factor g2 = Z0 / RB. Input impedance Z in From formula Z in =Z0*[(1 / (1+g2)+g1] -1 Given, and Z in2 From formula Z in2 =Z0*[(1 / (1+g1)+g2] -1 The magnitude of the scattering parameter S21, |S21|, is given by the formula |S21|=2 / [(1+g1)*(1+g2)+1]. If g2=g1 / (1-g1) or RB=RA-Z0, then Z in =Z0 and |S21| = 1-g1. If the input matching at the deep back can be relaxed on one side, especially in specific implementations where matching on only one side of the attenuator is important, the attenuation range of the transmission line-based signal attenuator 58 can be further extended (e.g., beyond the attenuation range when implemented as a symmetrical quarter-wavelength transmission line-based signal attenuator).

[0074] In these configurations, across all sizes R of the adjustable resistors R1 and R2, the magnitude of the scattering parameter S11 is minimized (e.g., less than -17 dB) at the frequency of the signal sig in the frequency band from frequency FA to frequency FB. In other words, the impedance matching performed by transmission line segment 68 effectively minimizes the amount of signal reflected back from input node 70. Across all sizes R of the adjustable resistors R1 and R2, the magnitude of the scattering parameter S22 is relatively low (e.g., less than -5.4 dB) at the frequency of the signal sig in the frequency band from frequency FA to frequency FB. In other words, the impedance matching performed by transmission line segment 68 effectively limits the amount of signal reflected back from output node 72. The transmission line-based signal attenuator 58 can exhibit a relatively wide gain range 138 (e.g., up to 11 dB to 12 dB) between its lowest and highest attenuation levels.

[0075] Figure 5 The example of transmission segment 68 having a length L = λ / 4 is illustrative and not limiting. Transmission segment 68 may have other lengths (e.g., shorter or longer lengths) if desired. For instance, the length L may be approximately equal to one-eighth of the wavelength λ (e.g., within 15% of one-eighth of the wavelength). When configured in this way, transmission segment 68 is sometimes referred to as an eighth-wavelength impedance transformer, and transmission line-based signal attenuator 58 is sometimes referred to herein as an eighth-wavelength transmission line-based signal attenuator 58.

[0076] Figure 7This is a circuit diagram illustrating an example in which the transmission line-based signal attenuator 58 is implemented as a signal attenuator based on an eighth-wavelength transmission line. Figure 7 As shown, transmission line segment 68 may have a length L = λ / 8. To help offset the impedance effect of reducing the length L of transmission line segment 68, the transmission line-based signal attenuator 58 may include an additional capacitor C coupled between terminal 82 and ground 78. Implementing the transmission line-based signal attenuator 58 in this way as a signal attenuator based on an eighth-wavelength transmission line can, for example, allow the transmission line-based signal attenuator 58 to be integrated into a segment of the signal path 50 (e.g., in...). Figure 3 (between adjacent components 56), this segment is shorter than when it is implemented as a signal attenuator based on a quarter-wavelength transmission line.

[0077] For example, the transmission line-based signal attenuator 58 can be implemented as a half-wavelength transmission line-based signal attenuator. Figure 8 This is a circuit diagram illustrating an example in which the transmission line-based signal attenuator 58 is implemented as a half-wavelength transmission line-based signal attenuator. Figure 8 As shown, the transmission line-based signal attenuator 58 may include a first transmission line segment 68-1 of length L = λ / 4 and a second transmission line segment 68-2 of length L = λ / 4, which are connected in series between the input node 70 and the output node 72.

[0078] Transmission segment 68-1 may extend from terminal 82 to terminal 84. Transmission segment 68-2 may extend from terminal 84 to the opposite terminal 146. The transmission line-based signal attenuator 58 may include an additional adjustable resistor R3 coupled between terminal 146 and ground. The adjustable resistor R3 may be implemented using a transistor such as transistor 144 or using any other desired component. Transistor 144 may have a first source-drain terminal coupled to terminal 146 and a second source-drain terminal coupled to ground. The gate terminal of transistor 144 may be coupled to controller 86 via control path 88.

[0079] The controller 86 can set the attenuation level of the transmission line-based signal attenuator 58 by setting the values ​​of adjustable resistors R1, R2, and R3. If needed, the controller 86 can configure the transmission line-based signal attenuator 58 to form a symmetrical half-wavelength transmission line-based signal attenuator by setting the values ​​of adjustable resistors R1 and R3 to be equal to a first value RA and by setting the value of adjustable resistor R2 to be equal to a second value RB.

[0080] When configured in this way, the input impedance Z of the transmission line-based signal attenuator 58 is... in From formula Z in=Z0*[(1 / (1 / (1+g1)+g2)+g1] -1 The scattering parameter S21 is given, and the magnitude of |S21| is given by the formula |S21|=2 / [(1+g1)*(2+g2+g1*g2)]. If g2=2*g1 / (1-g1) 2 ) or 2*RB=RA-Z0 2 / RA, then Z in =Z in2 =Z0 and |S21| = (1-g1) / (1+g1).

[0081] In this specific implementation, across all sizes R of the adjustable resistors R1 and R2, the magnitude of the scattering parameter S11 is minimized (e.g., less than -16 dB) at the frequency of the signal sig in the frequency band from frequency FA to frequency FB. In other words, the impedance matching performed by transmission line segment 68 effectively minimizes the amount of signal reflected back from input node 70. Simultaneously, across all sizes R of the adjustable resistors R1 and R2, the magnitude of the scattering parameter S22 is minimized (e.g., less than -16 dB) at the frequency of the signal sig in the frequency band from frequency FA to frequency FB. In other words, the impedance matching performed by transmission line segment 68 effectively limits the amount of signal reflected back from output node 72. Furthermore, the transmission line-based signal attenuator 58 can exhibit a very wide gain range (e.g., up to 26 dB) between its lowest and highest attenuation levels. If desired, transmission line segment 68 can have other lengths (e.g., corresponding impedance adjustment between terminals 82 and 84 and ground).

[0082] The controller 86 can be implemented using any desired control circuit. Figure 9 This is a circuit diagram illustrating an example of a control circuit that can be used to form controller 86. (Example) Figure 9 As shown, the controller 86 may include an operational amplifier 178, a set of transistors 170 (e.g., NMOS transistors), a first current source 182, a second current source 180, and a resistor R0.

[0083] Current source 182 can be coupled to ground via a first current path, such as reference line 184. Resistor R0 can be connected in series on reference line 184 between current source 182 and ground. Current source 180 can be coupled to transistor 170 via a second current path, such as reference line 186. The source-drain terminals of transistor 170 can be connected in series between ground and reference line 186. The gate terminal of transistor 170 can be coupled to gate line 168.

[0084] Operational amplifier 178 may have a first (e.g., positive) input terminal coupled to a node on reference line 186 between resistor R0 and current source 182. Operational amplifier 178 may have a second (e.g., negative) input terminal coupled to a node on reference line 184 between current source 180 and transistor 170. The output terminal of operational amplifier 178 may be coupled to gate line 168. A control path 80 for controlling adjustable resistors R1, R2, and / or R3 may be coupled to gate line 168.

[0085] Current source 182 can output a first current to reference line 184. The first current can be equal to the bandgap voltage divided by the resistance R0. The bandgap voltage can be very stable across process, voltage, and temperature (PVT) variations in device 10. The reference voltage VREF can be generated on reference line 184 and can be supplied to the second input of operational amplifier 178. Current source 180 can output a second current I0 to reference line 186. Current source 180 can be a constant current source, and current I0 can be a constant current that varies across the PVT (e.g., as tailored for device 10).

[0086] Operational amplifier 178 can amplify the difference between its first and second input terminals to generate an output voltage, such as a regulated voltage VG on gate line 168. The regulated voltage VG can drive the gate terminal of transistor 170 on gate line 168, causing current to flow through the source-drain terminals of transistor 170 until the effective resistance Ron of the source-drain terminals of transistor 170 (e.g., where Ron equals the source-drain voltage VDS of the transistor divided by I0) equals the resistance R0. This effectively forms a servo loop 185 (e.g., an Ron servo loop or regulation loop) around operational amplifier 178 (e.g., from the output of operational amplifier 178 through gate line 168, transistor 170, and reference line 186 to the positive input of the operational amplifier). The servo loop allows the operational amplifier to output the regulated voltage VG to control path 80 (for driving an adjustable resistor of a signal attenuator), the regulated voltage VG being constant across the PVT variation in device 10.

[0087] In this way, controller 86 can help mitigate PVT variations in device 10 that could otherwise affect signal attenuation performed by transmission line-based signal attenuator 58. During implementation, the adjustable resistors are highly sensitive to PVT variations. In the absence of servo loop 184, PVT variations can affect the adjustable resistors R1, R2, and / or R3 in transmission line-based signal attenuator 58 more than transmission line segment 68, resulting in an uncompensated mismatch between the attenuator's shunt path and series path. Adjusting the output of controller 86 using servo loop 184 helps mitigate this uncompensated mismatch to optimize the performance of transmission line-based signal attenuator 58. This is exemplary, and in general, controller 86 can have other architectures.

[0088] Figure 10 This is a graph of the gain of the transmission line-based signal attenuator 58 as a function of attenuation code (e.g., the setting of the adjustable resistor in the attenuator). Curve 200 plots the gain of the transmission line-based signal attenuator 58 at different PVT levels (e.g., across PVT variations) in the absence of servo loop 185. Curve 202 plots the gain of the transmission line-based signal attenuator 58 at different PVT levels when the adjustable resistor is driven using servo loop 185. As indicated by arrows 206 and 204, servo loop 185 can be used to significantly reduce the variation in gain of the transmission line-based signal attenuator 58 across PVT variations (e.g., by a factor of eight or more).

[0089] Figure 5 , Figure 7 and Figure 8 The examples illustrate transmission segment 68 as a distributed transmission line (sometimes referred to as a "real" transmission line). This is illustrative and not limiting. Any of the transmission segments 68 described herein can be implemented using a lumped LC circuit (sometimes referred to as a lumped LC transmission line) if desired. In these specific implementations, a transmission segment 68 with a length L = λ / 4 can be implemented using a 90-degree phase shift between the input and output of a lumped LC circuit.

[0090] Figure 11Examples of non-limiting lumped LC circuits 220 for forming a 90-degree phase shift between terminals 82 and 84 of signal attenuator 58 are illustrated. As a first example, the 90-degree phase shift can be formed using lumped LC circuit 220-1 (e.g., a three-element π-lumped bus) having a series inductor coupled between terminals 82 and 84 and a shunt capacitor coupled to either end of the series inductor. As a second example, the 90-degree phase shift can be formed using lumped LC circuit 220-2 (e.g., a three-element T-lumped bus) having two series inductors coupled between terminals 82 and 84 and a shunt capacitor coupled between the series inductors. As a third example, the 90-degree phase shift can be formed using lumped LC circuit 220-3 (e.g., a three-element π-lumped bus) having a series capacitor coupled between terminals 82 and 84 and a shunt inductor coupled to either end of the series capacitor. As a fourth example, a 90-degree phase shift can be formed using a lumped LC circuit 220-4 (e.g., a three-element T-lumped bus) having two series capacitors coupled between terminals 82 and 84 and a shunt inductor coupled between the series capacitors. These examples are illustrative and not limiting, and in general, the lumped LC circuit 220 can include any desired inductors and capacitors coupled together in any desired manner. The absence of resistive components in the lumped LC circuit 220 prevents the transmission segment 68 from introducing non-zero insertion losses that would otherwise be generated by a resistive T or π circuit.

[0091] As used herein, the term "simultaneous" means at least partially overlapping in time. In other words, the first and second events are referred to herein as "simultaneous" if at least some of the first events occur simultaneously with at least some of the second events (e.g., if at least some of the first events occur during, concurrently with, or when at least some of the second events occur). The first and second events can be simultaneous if they are synchronized (e.g., if the entire duration of the first event overlaps with the entire duration of the second event in time), but they can also be simultaneous if they are asynchronous (e.g., if the first event begins before or after the second event, ends before or after the second event, or if they do not partially overlap in time). As used herein, the term "at the time of" is synonymous with "simultaneous."

[0092] The methods and operations described above can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). The software code used to perform these operations can be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1 The storage device circuitry 16). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., Figure 1 The processing circuitry (e.g., 18) performs the execution. The processing circuitry may include a microprocessor, a central processing unit (CPU), an application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0093] As is widely recognized, the use of personally identifiable information should comply with privacy policies and practices that are generally accepted to meet or exceed industry or governmental requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and the nature of authorized use should be clearly explained to users.

[0094] According to one embodiment, the circuit includes: a signal path configured to transmit a radio frequency (RF) signal; and an adjustable attenuator disposed on the signal path and configured to attenuate the RF signal, wherein the adjustable attenuator has an input terminal and an output terminal and includes a transmission line segment series coupled between the input terminal and the output terminal, a first adjustable resistor coupled between a first terminal of the transmission line segment and a reference potential, and a second adjustable resistor coupled between a second terminal of the transmission line segment and the reference potential.

[0095] According to another embodiment, the transmission segment may optionally extend from the first terminal to the second terminal and have a length equal to one-quarter of the wavelength of the radio frequency signal.

[0096] According to another embodiment, the adjustable attenuator is optionally configured to attenuate the radio frequency signal when the first adjustable resistor has a first maximum value and when the second adjustable resistor also has the first maximum value.

[0097] According to another embodiment, the adjustable attenuator is optionally configured to attenuate the radio frequency signal when the first adjustable resistor has a first maximum value and when the second adjustable resistor simultaneously has a second maximum value different from the first value.

[0098] According to another embodiment, the circuit may optionally further include an additional transmission line segment coupled in series with the transmission line segment between the input terminal and the output terminal, wherein the additional transmission line segment extends from the third terminal to the fourth terminal, the third terminal being coupled to the second terminal and the second adjustable resistor.

[0099] According to another embodiment, the circuit may optionally also include a third adjustable resistor coupled between the fourth terminal and the reference potential.

[0100] According to another embodiment, the additional transmission segment may optionally have an additional length equal to one-quarter of the wavelength of the radio frequency signal.

[0101] According to another embodiment, the adjustable attenuator is optionally configured to attenuate the radio frequency signal when the first adjustable resistor has a first maximum value, the second adjustable resistor has a second maximum value different from the first value, and the third adjustable resistor has the first maximum value.

[0102] According to another embodiment, the transmission segment may optionally extend from the first terminal to the second terminal and have a length equal to one-eighth of the wavelength of the radio frequency signal.

[0103] According to another embodiment, the circuit may optionally further include a first capacitor coupled between the first terminal and a reference potential, and a second capacitor coupled between the second terminal and the reference potential.

[0104] According to another embodiment, the first adjustable resistor optionally includes a first transistor having a first source-drain terminal coupled to a first terminal and a second source-drain terminal coupled to a reference potential, the second adjustable resistor includes a second transistor having a third source-drain terminal coupled to a second terminal and a fourth source-drain terminal coupled to a reference potential, and the circuit further includes a controller configured to apply one or more voltages to the first gate terminal of the first transistor and the second gate terminal of the second transistor.

[0105] According to another embodiment, the controller optionally includes: a first current source; a second current source; a first conductive line coupling the first current source to a reference potential; a resistor disposed on the first conductive line; a set of transistors; a second conductive line coupled to the second current source, wherein the source-drain terminals of the set of transistors are connected in series between the second conductive line and the reference potential; a third conductive line coupled to the gate terminal of the set of transistors; an operational amplifier having a first input terminal coupled to a node on the first conductive line located between the resistor and the first current source, a second input terminal coupled to the second conductive line, and an output terminal coupled to the third conductive line; and a control path coupling the third conductive line to the first gate terminal and the second gate terminal, wherein the operational amplifier is configured to output a voltage to the third conductive line, the voltage setting the first adjustable resistor and the second adjustable resistor to one or more magnitudes.

[0106] According to another implementation, the transmission line segment may optionally not include any switches or adjustable resistors.

[0107] According to one embodiment, a radio frequency (RF) signal attenuator disposed on a signal line includes: a transmission line extending from a first terminal to a second terminal, the first terminal being coupled to an input terminal of the RF signal attenuator and the second terminal being communicatively coupled to an output terminal of the RF signal attenuator; a first adjustable resistor coupling the first terminal to a ground; and a second adjustable resistor coupling the second terminal to the ground, wherein the transmission line has a length from the first terminal to the second terminal, the length being configured to match the input impedance of the RF signal attenuator to the impedance of the signal line.

[0108] According to another embodiment, the radio frequency signal attenuator may optionally be configured to transmit radio frequency signals at a wavelength equal to one-quarter of the wavelength.

[0109] According to another embodiment, the RF signal attenuator may optionally further include: an additional transmission line extending from a third terminal to a fourth terminal, wherein the third terminal is coupled to a second terminal, the fourth terminal is coupled to the output of the RF signal attenuator, and the additional transmission line has an additional length equal to one-quarter of the wavelength; and a third adjustable resistor coupling the fourth terminal to a ground.

[0110] According to another embodiment, the radio frequency signal attenuator is optionally configured to transmit a radio frequency signal at a wavelength equal to one-eighth of the wavelength, and the radio frequency signal attenuator further includes a first capacitor that couples a first terminal to a ground and a second capacitor that couples a second terminal to a ground.

[0111] According to one embodiment, an electronic device includes: a signal path configured to transmit a radio frequency (RF) signal; an attenuator disposed on the signal path, wherein the attenuator is configured to attenuate the RF signal and includes a first adjustable shunt resistor and a second adjustable shunt resistor; and a controller configured to adjust the magnitudes of the first adjustable shunt resistor and the second adjustable shunt resistor, wherein the controller includes: an operational amplifier having an output terminal communicatively coupled to the first adjustable shunt resistor and the second adjustable shunt resistor; a set of transistors having gate terminals communicatively coupled to the output terminal of the operational amplifier; and a servo loop extending around the operational amplifier from the output terminal of the operational amplifier through the set of transistors to a first input terminal of the operational amplifier.

[0112] According to another embodiment, the controller may optionally further include: a first current source; a first conductive line that couples the first current source to a ground; a resistor disposed on the first conductive line, wherein a node on the first conductive line located between the first current source and the resistor is coupled to a second input terminal of the operational amplifier; a second current source; and a second conductive line that couples the second current source to the group of transistors, wherein the second conductive line is coupled to a first input terminal of the operational amplifier.

[0113] According to another embodiment, in an electronic device, the attenuator optionally includes a transmission line that does not contain a switch and an adjustable resistor and is coupled in series along the signal path, wherein a first adjustable shunt resistor is coupled to a first end of the transmission line and a second adjustable shunt resistor is coupled to a second end of the transmission line opposite to the first end.

[0114] The foregoing is illustrative and various modifications can be made to the described implementation scheme. The foregoing implementation scheme can be implemented individually or in any combination.

Claims

1. A circuit, the circuit comprising: A signal path configured to transmit radio frequency signals; and An adjustable attenuator, disposed on the signal path and configured to attenuate the radio frequency signal, wherein the adjustable attenuator has an input terminal and an output terminal and includes... A transmission line segment, wherein the transmission line segment is connected in series between the input terminal and the output terminal. A first adjustable resistor is coupled between a first terminal of the transmission line segment and a reference potential. A second adjustable resistor is coupled between the second terminal of the transmission line segment and the reference potential.

2. The circuit of claim 1, wherein the transmission line segment extends from the first terminal to the second terminal and has a length equal to one-quarter of the wavelength of the radio frequency signal.

3. The circuit of claim 2, wherein the adjustable attenuator is configured to attenuate the radio frequency signal when the first adjustable resistor has a first maximum value and when the second adjustable resistor also has the first maximum value.

4. The circuit of claim 2, wherein the adjustable attenuator is configured to attenuate the radio frequency signal when the first adjustable resistor has a first maximum value and when the second adjustable resistor simultaneously has a second maximum value different from the first maximum value.

5. The circuit according to claim 2, further comprising: An additional transmission line segment is connected in series with the transmission line segment between the input terminal and the output terminal, wherein the additional transmission line segment extends from the third terminal to the fourth terminal, and the third terminal is coupled to the second terminal and the second adjustable resistor.

6. The circuit according to claim 5, further comprising: A third adjustable resistor is coupled between the fourth terminal and the reference potential.

7. The circuit of claim 6, wherein the additional transmission segment has an additional length equal to one-quarter of the wavelength of the radio frequency signal.

8. The circuit of claim 7, wherein the adjustable attenuator is configured to attenuate the radio frequency signal when the first adjustable resistor has a first maximum value, when the second adjustable resistor has a second maximum value different from the first value, and when the third adjustable resistor has the first maximum value.

9. The circuit of claim 1, wherein the transmission line segment extends from the first terminal to the second terminal and has a length equal to one-eighth of the wavelength of the radio frequency signal.

10. The circuit according to claim 9, further comprising: A first capacitor is coupled between the first terminal and the reference potential; and A second capacitor is coupled between the second terminal and the reference potential.

11. The circuit according to claim 1, wherein: The first adjustable resistor includes a first transistor having a first source-drain terminal coupled to the first terminal and a second source-drain terminal coupled to the reference potential; The second adjustable resistor includes a second transistor having a third source-drain terminal coupled to the second terminal and a fourth source-drain terminal coupled to the reference potential; and The circuit also includes a controller configured to apply one or more voltages to a first gate terminal of the first transistor and a second gate terminal of the second transistor.

12. The circuit of claim 11, wherein the controller comprises: First current source; Second current source; A first conductive line, wherein the first conductive line couples the first current source to the reference potential; A resistor, wherein the resistor is disposed on the first conductive line; A set of transistors; A second conductive line is coupled to the second current source, wherein the source-drain terminals of a set of transistors are connected in series between the second conductive line and the reference potential; A third conductive line is coupled to the gate terminal of the group of transistors; An operational amplifier having a first input terminal coupled to a node on the first conductive line between the resistor and the first current source, a second input terminal coupled to the second conductive line, and an output terminal coupled to the third conductive line; and A control path that couples the third conductive line to the first gate terminal and the second gate terminal, wherein the operational amplifier is configured to output a voltage to the third conductive line, the voltage setting the first adjustable resistor and the second adjustable resistor to one or more values.

13. The circuit of claim 1, wherein the transmission line segment does not include any switches or adjustable resistors.

14. A radio frequency signal attenuator, the radio frequency signal attenuator being disposed on a signal line and comprising: A transmission line extends from a first terminal to a second terminal, the first terminal being coupled to the input of the radio frequency signal attenuator, and the second terminal being communicatively coupled to the output of the radio frequency signal attenuator. A first adjustable resistor, wherein the first adjustable resistor couples the first terminal to a grounding portion; and A second adjustable resistor couples the second terminal to the ground portion, wherein the transmission line has a length from the first terminal to the second terminal, the length being configured to match the input impedance of the RF signal attenuator with the impedance of the signal line.

15. The radio frequency signal attenuator of claim 14, wherein the radio frequency signal attenuator is configured to transmit a radio frequency signal at a wavelength, the length being equal to one-quarter of the wavelength.

16. The radio frequency signal attenuator according to claim 15, further comprising: An additional transmission line extends from a third terminal to a fourth terminal, wherein the third terminal is coupled to the second terminal, the fourth terminal is coupled to the output of the RF signal attenuator, and the additional transmission line has an additional length equal to one-quarter of the wavelength. and A third adjustable resistor couples the fourth terminal to the grounding portion.

17. The radio frequency signal attenuator of claim 14, wherein the radio frequency signal attenuator is configured to transmit a radio frequency signal at a wavelength, the length being equal to one-eighth of the wavelength, and the radio frequency signal attenuator further comprises: A first capacitor, wherein the first capacitor couples the first terminal to the ground portion; and A second capacitor, wherein the second terminal is coupled to the grounding portion.

18. An electronic device, the electronic device comprising: A signal path configured to transmit radio frequency signals; An attenuator is disposed on the signal path, wherein the attenuator is configured to attenuate the radio frequency signal and includes a first adjustable shunt resistor and a second adjustable shunt resistor. and A controller configured to adjust the magnitudes of the first adjustable shunt resistor and the second adjustable shunt resistor, wherein the controller includes... An operational amplifier having an output terminal communicatively coupled to the first adjustable shunt resistor and the second adjustable shunt resistor. A set of transistors, the set of transistors having gate terminals communicatively coupled to the output terminal of the operational amplifier, and A servo circuit that extends from the output of the operational amplifier through the set of transistors to the first input of the operational amplifier.

19. The electronic device of claim 18, wherein the controller further comprises: First current source; The first conductive line couples the first current source to the grounding part; A resistor is disposed on the first conductive line, wherein a node on the first conductive line located between the first current source and the resistor is coupled to the second input terminal of the operational amplifier. Second current source; and A second conductive line, which couples the second current source to the set of transistors, wherein the second conductive line is coupled to the first input terminal of the operational amplifier.

20. The electronic device of claim 18, wherein the attenuator comprises: A transmission line, which does not contain a switch and an adjustable resistor and is coupled in series along the signal path, wherein a first adjustable shunt resistor is coupled to a first end of the transmission line and a second adjustable shunt resistor is coupled to a second end of the transmission line opposite to the first end.

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