High-precision pulse error compensation method and system based on FPGA
By separating and delaying the rising and falling edge single pulse signals in the FPGA, the problem of pulse width error in high-precision pulse generation is solved, and high-precision compensation of pulse signals is achieved, with the error controlled within ±0.15ns.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-27
- Publication Date
- 2026-03-13
AI Technical Summary
In high-precision pulse generation technology, due to factors such as PCB trace length differences, temperature drift, signal integrity, and device characteristics, there is an error between the pulse width of the actual pulse signal and the pulse width of the ideal pulse signal, making it difficult to meet actual measurement requirements.
By dividing the pulse signal into rising edge single pulse signals and falling edge single pulse signals, and then combining them after delay processing, the FPGA is used to achieve precise control of the pulse width. This includes generating rising edge and falling edge single pulse signals, calculating pulse width error parameters and performing specified delay processing, and finally synthesizing a compensation pulse signal.
The pulse width accuracy of the pulse signal has been improved, with the error controlled within ±0.15ns, meeting the requirements for high-precision signal measurement and generation.
Smart Images
Figure CN121664154A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic technology and information, and more specifically, relates to a high-precision pulse error compensation method and system based on FPGA. Background Technology
[0002] High-precision pulse generation technology has a wide range of applications in signal measurement, signal generation, and excitation signal generation. In practical applications, due to various factors such as differences in printed circuit board (PCB) trace length, temperature drift, signal integrity, and device characteristics, there is an error between the pulse width of the generated actual pulse signal and the pulse width of the ideal pulse signal, making it difficult for the generated pulse signal to meet the requirements of actual measurement.
[0003] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention
[0004] The problem this invention aims to solve is how to improve the accuracy of the pulse width of a pulse signal in practical applications of high-precision pulse generation.
[0005] Firstly, a high-precision pulse error compensation method based on FPGA is provided, including: Generate rising edge single pulse signals and falling edge single pulse signals based on the pulse signal; The rising edge single pulse signal and the falling edge single pulse signal are combined to obtain the pre-compensation pulse signal, and the pulse width error parameter is obtained based on the pre-compensation pulse signal; The rising edge single pulse signal or the falling edge single pulse signal is subjected to a specified delay processing according to the pulse width error parameter; The delayed rising edge single pulse signal and the falling edge single pulse signal are combined to obtain the compensation pulse signal.
[0006] Preferably, the step of generating rising edge single-pulse signals and falling edge single-pulse signals based on the pulse signal specifically includes: A pulse signal is continuously input into the register, and a first new signal and a second new signal are generated simultaneously while the pulse signal is input into the register. When the pulse signal received by the register is at the rising edge, the first new signal will change from low level to high level in the next clock cycle and continue for one clock cycle before returning to low level. When the pulse signal received by the register is at a falling edge, the second new signal will change from low to high level in the next clock cycle and remain high for one clock cycle before returning to low level. The first new signal is used as the rising edge single pulse signal, and the second new signal is used as the falling edge single pulse signal.
[0007] Preferably, obtaining the pulse width error parameter based on the pre-compensation pulse signal specifically includes: The difference is obtained by subtracting the pulse width of the standard pulse signal from the pulse width of the pulse signal before compensation, and the difference is used as the pulse width error parameter.
[0008] Preferably, the step of performing a specified delay processing on the rising edge single-pulse signal or the falling edge single-pulse signal according to the pulse width error parameter specifically includes: When the pulse width error parameter is less than zero, the falling edge single pulse signal will be delayed by the same value of the pulse width error parameter or the preset error value. When the pulse width error parameter is greater than zero, the rising edge single pulse signal will be delayed by the same value as the pulse width error parameter or the preset error value. When the pulse width error parameter is equal to zero, the rising edge single pulse signal and the falling edge single pulse signal remain unchanged.
[0009] Secondly, a high-precision pulse error compensation system based on FPGA is provided for applying the aforementioned high-precision pulse error compensation method based on FPGA, comprising: a pulse generation unit, an edge separation unit, a first delay unit, a second delay unit, and a trigger unit, wherein: The pulse generating unit is used to generate the pulse signal and transmit the pulse signal to the edge separation unit; The edge separation unit is used to generate rising edge single pulse signals and falling edge single pulse signals according to the pulse signal, and transmits the rising edge single pulse signal to the first delay unit and the falling edge single pulse signal to the second delay unit. The first delay unit is used to delay the rising edge single pulse signal according to the pulse width error parameter, and the second delay unit is used to delay the falling edge single pulse signal according to the pulse width error parameter. The trigger unit is used to combine the delayed rising edge single pulse signal and the falling edge single pulse signal to obtain a compensation pulse signal.
[0010] Preferably, the edge separation unit is used to continuously input the pulse signal into the register, and simultaneously generate a first new signal and a second new signal while the pulse signal is input into the register; When the pulse signal received by the register is at the rising edge, the first new signal will change from low level to high level in the next clock cycle and continue for one clock cycle before returning to low level. When the pulse signal received by the register is at a falling edge, the second new signal will change from low to high level in the next clock cycle and remain high for one clock cycle before returning to low level. The first new signal is used as the rising edge single pulse signal, and the second new signal is used as the falling edge single pulse signal.
[0011] Preferably, the FPGA-based high-precision pulse error compensation system further includes a parameter configuration unit, wherein: The parameter configuration unit is used to obtain a delay coefficient based on the pulse width error parameter, and apply the delay coefficient and the pulse width error parameter to the first delay unit or the second delay unit; The first delay unit is used to delay the rising edge single pulse signal according to the pulse width error parameter and the delay coefficient, and the second delay unit is used to delay the falling edge single pulse signal according to the pulse width error parameter and the delay coefficient.
[0012] Preferably, the first delay unit is used to delay the rising edge single pulse signal according to the pulse width error parameter and the delay coefficient, and the second delay unit is used to delay the falling edge single pulse signal according to the pulse width error parameter and the delay coefficient, specifically including: The actual delay value is calculated based on the delay coefficient. When the pulse width error parameter is less than zero, the falling edge single pulse signal will be delayed by the actual delay value. When the pulse width error parameter is greater than zero, the rising edge single pulse signal will be delayed by the actual delay value. When the pulse width error parameter is equal to zero, the rising edge single pulse signal and the falling edge single pulse signal remain unchanged.
[0013] Preferably, the trigger unit includes a first NOR gate G1 and a second NOR gate G2, wherein: The first input terminal 21 of the second NOR gate G2 is connected to the first delay unit for receiving the signal from the first delay unit. The second input terminal 22 of the second NOR gate G2 is connected to the output terminal of the first NOR gate G1 for receiving the signal from the first NOR gate G1. The first output terminal of the second NOR gate G2 is connected to the fourth input terminal 12 of the first NOR gate G1 for transmitting the signal of the second NOR gate G2 to the first NOR gate G1. The third input terminal 11 of the first NOR gate G1 is connected to the second delay unit and is used to receive the signal from the second delay unit. The output terminal of the first NOR gate G1 serves as the output terminal of the trigger unit and is used to output the pre-compensation pulse signal or the compensation pulse signal.
[0014] Preferred options also include: When the first input terminal 21 of the second NOR gate G2 receives a low-level signal and the third input terminal 11 of the first NOR gate G1 receives a high-level signal, the output terminal of the first NOR gate G1 outputs a low level. When the first input terminal 21 of the second NOR gate G2 receives a high-level signal and the third input terminal 11 of the first NOR gate G1 receives a low-level signal, the output terminal of the first NOR gate G1 outputs a high level. When the first input terminal 21 of the second NOR gate G2 receives a low-level signal and the third input terminal 11 of the first NOR gate G1 receives a low-level signal, the output terminal of the first NOR gate G1 remains unchanged.
[0015] Unlike existing technologies, the present invention has at least the following beneficial effects: By dividing the pulse signal into rising edge single pulse signals and falling edge single pulse signals, and then combining the rising edge single pulse signals and falling edge single pulse signals separately after delay processing, the pulse width can be controlled, thereby improving the pulse width accuracy of the pulse signal. Attached Figure Description
[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.
[0017] Figure 1 This is a flowchart of a high-precision pulse error compensation method based on FPGA provided in an embodiment of the present invention; Figure 2 This is the timing diagram corresponding to a high-precision pulse error compensation method based on FPGA provided in an embodiment of the present invention; Figure 3 This is a flowchart of the delay processing method in a high-precision pulse error compensation method based on FPGA provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a high-precision pulse error compensation system based on FPGA provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of a trigger unit in a high-precision pulse error compensation system based on FPGA provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the modules corresponding to the first delay unit and the second delay unit in a high-precision pulse error compensation system based on FPGA provided in an embodiment of the present invention; The attached figures are numbered as follows: First input terminal 21; second input terminal 22; third input terminal 11; fourth input terminal 12. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0019] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.
[0020] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.
[0021] In the description of this invention, the expression “A and / or B” (where A and B are used to formally represent specific features) will be used. The corresponding expression includes the following three combinations: only A, only B, and a combination of A and B.
[0022] As used in this invention, “about,” “approximately,” or “preset error” includes the stated value and the average value within an acceptable deviation range of a particular value, wherein the acceptable deviation range is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).
[0023] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0024] Example 1: In existing high-precision pulse applications using Field-Programmable Gate Arrays (FPGAs), various factors such as PCB trace length differences, temperature drift, signal integrity, and device characteristics lead to errors between the pulse width of the generated actual pulse signal and the pulse width of the ideal pulse signal. This results in the generated pulse signal failing to meet the requirements of actual measurements. To address this issue, this embodiment provides a high-precision pulse error compensation method based on FPGA. Figure 1 As shown, the method flow includes the following.
[0025] In step 101, rising edge single pulse signals and falling edge single pulse signals are generated based on the pulse signals.
[0026] In this embodiment, the pulse signal transitions from a low level to a high level (rising edge) during the corresponding clock cycle, and remains at a high level for several clock cycles before transitioning from a high level to a low level (falling edge). The number of clock cycles from the rising edge to the falling edge is the pulse width. If the pulse signal is directly delayed, the rising and falling edges will be delayed synchronously, which will not adjust the pulse width. A rising edge single pulse signal is generated based on the rising edge position of the pulse signal to represent the rising edge-related part of the pulse signal, and a falling edge single pulse signal is generated based on the falling edge position of the pulse signal to represent the falling edge-related part of the pulse signal. In subsequent steps, the rising edge single pulse signal and the falling edge single pulse signal are individually controlled to achieve the purpose of pulse width adjustment.
[0027] In step 102, the rising edge single pulse signal and the falling edge single pulse signal are combined to obtain the pre-compensation pulse signal, and the pulse width error parameter is obtained based on the pre-compensation pulse signal.
[0028] In this embodiment, when the pulse signal is received for the first time, the generated rising edge single pulse signal or falling edge single pulse signal is not directly controlled separately. Instead, the rising edge single pulse signal and the falling edge single pulse signal are first combined to obtain the pre-compensation pulse signal. The pre-compensation pulse signal has not yet undergone pulse width control, and its pulse width is consistent with the original pulse signal. Therefore, by comparing the pulse width of the pre-compensation pulse signal with the required standard pulse width, the difference between the pulse signal and the standard pulse width can be obtained. Based on this difference, the pulse width error parameter can be obtained.
[0029] In step 103, the rising edge single pulse signal or the falling edge single pulse signal is subjected to a specified delay processing according to the pulse width error parameter.
[0030] In step 104, the delayed rising edge single pulse signal and the falling edge single pulse signal are combined to obtain the compensation pulse signal.
[0031] After obtaining the pulse width error parameters, the rising edge or falling edge single-pulse signal needs to be delayed according to these parameters. Since delay processing can only postpone the signal in the clock signal dimension, when the pulse width needs to be increased, the falling edge single-pulse signal needs to be delayed, while the rising edge single-pulse signal remains unchanged. Conversely, when the pulse width needs to be decreased, the rising edge single-pulse signal needs to be delayed, while the falling edge single-pulse signal remains unchanged. The adjusted rising edge and falling edge single-pulse signals are then combined to obtain a compensated pulse signal, which is the pulse that meets the pulse width requirements.
[0032] Furthermore, in this embodiment, since the rising edge single-pulse signal and the falling edge single-pulse signal are generated separately, they can be controlled separately. Therefore, how to generate the rising edge single-pulse signal and the falling edge single-pulse signal based on the pulse signal in this embodiment involves the following design. The specific steps for generating the rising edge single-pulse signal and the falling edge single-pulse signal based on the pulse signal are as follows: Figure 2 As shown, the method flow includes the following.
[0033] A pulse signal is continuously input into the register, and simultaneously a first new signal and a second new signal are generated. When the pulse signal received by the register is at a rising edge, the first new signal changes from low to high in the next clock cycle and remains high for one clock cycle before returning to low. When the pulse signal received by the register is at a falling edge, the second new signal changes from low to high in the next clock cycle and remains high for one clock cycle before returning to low. The first new signal is used as the rising edge single pulse signal, and the second new signal is used as the falling edge single pulse signal.
[0034] It is important to note that, such as Figure 2 The diagram shows the timing diagram for generating rising edge and falling edge single-pulse signals. In this embodiment, while the pulse signal is continuously input to the register, the level signal in the register changes with the input pulse signal. Therefore, the level change of the register can reflect the level change of the pulse signal, and the rising and falling edges of the level change in the register can reflect the rising and falling edges of the pulse signal. Thus, a rising edge single-pulse signal can be generated based on the rising edge of the register, and a falling edge single-pulse signal can be generated based on the falling edge of the register. However, the register signal is delayed by one clock cycle relative to the pulse signal, that is, when the pulse signal outputs from low level to high level... At the rising edge, the register signal transitions from low to high level after a one-clock-cycle delay. Since the rising edge pulse signal is generated based on the register signal and is consistent with the register signal, the level change position in the rising edge single pulse signal is delayed by one clock cycle compared to the rising edge of the pulse signal. Similarly, the level change position in the falling edge single pulse signal is delayed by one clock cycle compared to the falling edge of the pulse signal. However, since both the rising edge single pulse signal and the falling edge single pulse signal are synchronously delayed by one clock cycle, the pulse width obtained by subsequently combining the rising edge single pulse signal and the falling edge single pulse signal can be used as an equivalent pulse width of the pulse signal or a modulated pulse width.
[0035] Specifically, when the input pulse signal level is continuously 1, the register level is also continuously 1. When the input pulse signal level changes from 1 to 0 (i.e., falling edge), after one clock cycle, the register level is also changed from 1 to 0. At this time, the falling edge pulse signal is synchronously pulled high for one cycle and then pulled low. When the input pulse signal level is continuously 0, the register level is also continuously 0. When the input pulse signal level changes from 0 to 1 (i.e., rising edge), after one clock cycle, the register level is also changed from 0 to 1. At this time, the falling edge pulse signal is synchronously pulled high for one cycle and then pulled low.
[0036] Furthermore, in this embodiment, after obtaining the pulse width error parameter, it is necessary to obtain an adjustment scheme for the rising edge single pulse signal or the falling edge single pulse signal based on the pulse width error parameter, that is, whether the rising edge single pulse signal or the falling edge single pulse signal needs to be delayed, and the required delay value. In summary, this embodiment also involves the following design.
[0037] The pulse width error parameter is obtained based on the pre-compensation pulse signal, and the rising edge single pulse signal or falling edge single pulse signal is subjected to a specified delay processing based on the pulse width error parameter, such as... Figure 3 As shown, the method flow includes the following.
[0038] In step 201, the pulse width of the pre-compensation pulse signal is subtracted from the pulse width of the standard pulse signal to obtain the difference, which is used as the pulse width error parameter.
[0039] In step 202, when the pulse width error parameter is less than zero, the falling edge single pulse signal is delayed by the same value of the pulse width error parameter or by a preset error value.
[0040] In step 203, when the pulse width error parameter is greater than zero, the rising edge single pulse signal is delayed by the same value of the pulse width error parameter or by a preset error value.
[0041] In step 204, when the pulse width error parameter is equal to zero, the rising edge single pulse signal and the falling edge single pulse signal remain unchanged.
[0042] In this embodiment, the reason for using the preset error value for delay in some cases is that the delay processing accuracy for rising edge and falling edge single-pulse signals is limited, and the adjustment value may not be completely consistent with the pulse width error parameter. In this case, the preset error value of the pulse width error parameter can only be used to delay the rising edge and falling edge single-pulse signals within the allowable error range. The preset error value is allowed to have a numerical difference of up to 20% from the pulse width error parameter.
[0043] Example 2: Furthermore, this embodiment provides a high-precision pulse error compensation system based on FPGA, based on Embodiment 1, for applying the high-precision pulse error compensation method based on FPGA described in Embodiment 1, such as... Figure 4 As shown, it includes: a pulse generation unit, an edge separation unit, a first delay unit, a second delay unit, and a trigger unit, wherein: The pulse generation unit generates the pulse signal and transmits the pulse signal to the edge separation unit. The edge separation unit generates a rising edge single pulse signal and a falling edge single pulse signal based on the pulse signal, and transmits the rising edge single pulse signal to the first delay unit and the falling edge single pulse signal to the second delay unit. The first delay unit delays the rising edge single pulse signal according to the pulse width error parameter, and the second delay unit delays the falling edge single pulse signal according to the pulse width error parameter. The trigger unit merges the delayed rising edge single pulse signal and the falling edge single pulse signal to obtain a compensation pulse signal.
[0044] Furthermore, the edge separation unit is used to continuously input the pulse signal into the register, and simultaneously generate a first new signal and a second new signal while the pulse signal is input into the register; wherein, when the pulse signal received by the register is at a rising edge, the first new signal changes from a low level to a high level in the next clock cycle and remains at a low level for one clock cycle; wherein, when the pulse signal received by the register is at a falling edge, the second new signal changes from a low level to a high level in the next clock cycle and remains at a low level for one clock cycle; the first new signal is used as the rising edge single pulse signal, and the second new signal is used as the falling edge single pulse signal.
[0045] It is important to note that in this embodiment, while the pulse signal is continuously input to the register, the level signal in the register changes accordingly. Therefore, the level change of the pulse signal can be reflected by the level change of the register, and the rising and falling edges of the pulse signal can be reflected by the rising and falling edges of the level change in the register. Thus, a rising edge single pulse signal can be generated based on the rising edge of the register, and a falling edge single pulse signal can be generated based on the falling edge of the register. However, the register signal is delayed by one clock cycle relative to the pulse signal; that is, when the pulse signal has a rising edge from low to high level, the register signal will... The transition from low to high level is delayed by one clock cycle. Since the rising edge pulse signal is generated based on the register signal and is consistent with the register signal, the position of the level change in the rising edge single pulse signal is delayed by one clock cycle compared to the rising edge of the pulse signal. Similarly, the position of the level change in the falling edge single pulse signal is delayed by one clock cycle compared to the falling edge of the pulse signal. However, since both the rising edge single pulse signal and the falling edge single pulse signal are synchronously delayed by one clock cycle, the pulse width of the subsequent combination of the rising edge single pulse signal and the falling edge single pulse signal can be used as an equivalent pulse width of the pulse signal or a modulated pulse width.
[0046] Specifically, when the input pulse signal level is continuously 1, the register level is also continuously 1. When the input pulse signal level changes from 1 to 0 (i.e., falling edge), after one clock cycle, the register level is also changed from 1 to 0. At this time, the falling edge pulse signal is synchronously pulled high for one cycle and then pulled low. When the input pulse signal level is continuously 0, the register level is also continuously 0. When the input pulse signal level changes from 0 to 1 (i.e., rising edge), after one clock cycle, the register level is also changed from 0 to 1. At this time, the falling edge pulse signal is synchronously pulled high for one cycle and then pulled low.
[0047] like Figure 5 As shown, the trigger unit includes a first NOR gate G1 and a second NOR gate G2, wherein: the first input terminal 21 of the second NOR gate G2 is connected to a first delay unit for receiving a signal from the first delay unit; the second input terminal 22 of the second NOR gate G2 is connected to the output terminal of the first NOR gate G1 for receiving a signal from the first NOR gate G1; the first output terminal of the second NOR gate G2 is connected to the fourth input terminal 12 of the first NOR gate G1 for transmitting the signal of the second NOR gate G2 to the first NOR gate G1; the third input terminal 11 of the first NOR gate G1 is connected to the second delay unit for receiving a signal from the second delay unit; and the output terminal of the first NOR gate G1 serves as the output terminal of the trigger unit for outputting the pre-compensation pulse signal or the compensation pulse signal.
[0048] Furthermore, when the first input terminal 21 of the second NOR gate G2 receives a low-level signal and the third input terminal 11 of the first NOR gate G1 receives a high-level signal, the output terminal of the first NOR gate G1 outputs a low-level signal; when the first input terminal 21 of the second NOR gate G2 receives a high-level signal and the third input terminal 11 of the first NOR gate G1 receives a low-level signal, the output terminal of the first NOR gate G1 outputs a high-level signal; when the first input terminal 21 of the second NOR gate G2 receives a low-level signal and the third input terminal 11 of the first NOR gate G1 receives a low-level signal, the output terminal of the first NOR gate G1 maintains its original level.
[0049] In this embodiment, since the situation where the first input terminal 21 of the second NOR gate G2 receives a high-level signal and the third input terminal 11 of the first NOR gate G1 simultaneously receives a high-level signal is not allowed, it will not be discussed here.
[0050] Furthermore, such as Figure 4As shown, the FPGA-based high-precision pulse error compensation system further includes a parameter configuration unit, wherein: the parameter configuration unit is used to obtain a delay coefficient according to the pulse width error parameter, and apply the delay coefficient and the pulse width error parameter to a first delay unit or a second delay unit; the first delay unit is used to delay the rising edge single pulse signal according to the pulse width error parameter and the delay coefficient, and the second delay unit is used to delay the falling edge single pulse signal according to the pulse width error parameter and the delay coefficient.
[0051] Furthermore, in this embodiment, as Figure 6 As shown, the first and second delay units can utilize the ODELAYE2 module resources in the Xilinx FPGA. The ODELAYE2 module can delay signals for a specified time based on clock and configuration parameters. A schematic diagram and port information for the ODELAYE2 module are shown below. Figure 6 As shown. Furthermore, when calling this module, it is also necessary to configure its operating mode, clock frequency, etc. In this embodiment, the ODELAYE2 module can operate in VAR_LOAD mode, which allows for dynamic adjustment of the delay. The operating clock frequency can be set to the commonly used 200MHz. In this scheme, the rising edge pulse signal and falling edge pulse signal are transmitted to the corresponding data input signal interface of the ODELAYE2 module, and the required delay coefficient is input to the tap coefficient interface to make the delay effective. The tap coefficient output interface will display the currently effective delay coefficient. In this embodiment, the minimum adjustable delay unit is 0.078ns, and the maximum adjustable delay is 2.422ns. The signal output interface is directly connected to the FPGA port to output to the external FPGA chip.
[0052] In this embodiment, the delay coefficient is the pulse width error parameter divided by the minimum delay unit and then rounded down. For example, if the pulse width error parameter is 1ns and the minimum delay unit is 0.078ns, then 1ns / 0.078ns = 12.8, and the delay coefficient is 12.8 rounded down to 13.
[0053] Furthermore, in this embodiment, the control process of the pulse signal based on the delay coefficient is as follows: the first delay unit is used to delay the rising edge single pulse signal according to the pulse width error parameter and the delay coefficient, and the second delay unit is used to delay the falling edge single pulse signal according to the pulse width error parameter and the delay coefficient, specifically including: calculating the actual delay value according to the delay coefficient; when the pulse width error parameter is less than zero, delaying the falling edge single pulse signal by the actual delay value; when the pulse width error parameter is greater than zero, delaying the rising edge single pulse signal by the actual delay value; when the pulse width error parameter is equal to zero, the rising edge single pulse signal and the falling edge single pulse signal remain unchanged.
[0054] To illustrate the above method more intuitively, let's take the following actual process as an example: First, use an oscilloscope to measure the output pulse signal. The pulse width of the actual measured pulse signal is 1ns larger than that of the standard pulse signal. Therefore, the pulse width error parameter is 1ns, which is greater than 0. 1ns / 0.078ns = 12.8. 12.8 is rounded down to 13, so the delay coefficient is 13. Therefore, the actual delay value is 13 × 0.078 = 1.014ns.
[0055] Under the same environmental conditions, the pulse width error of the traditional method is ±1.5ns, while the error of the present invention is ≤±0.15ns, which is only one-tenth. In quantum computing and quantum measurement experiments, the pulse signal generated by the present invention has a pulse width error of ≤0.15ns, which can meet their high precision requirements.
[0056] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A high-precision pulse error compensation method based on FPGA, characterized in that, include: Generate rising edge single pulse signals and falling edge single pulse signals based on the pulse signal; The rising edge single pulse signal and the falling edge single pulse signal are combined to obtain the pre-compensation pulse signal, and the pulse width error parameter is obtained based on the pre-compensation pulse signal; The rising edge single pulse signal or the falling edge single pulse signal is subjected to a specified delay processing according to the pulse width error parameter; The delayed rising edge single pulse signal and the falling edge single pulse signal are combined to obtain the compensation pulse signal.
2. The high-precision pulse error compensation method based on FPGA according to claim 1, characterized in that, The process of generating rising edge single-pulse signals and falling edge single-pulse signals based on pulse signals specifically includes: A pulse signal is continuously input into the register, and a first new signal and a second new signal are generated simultaneously while the pulse signal is input into the register. When the pulse signal received by the register is at the rising edge, the first new signal will change from low level to high level in the next clock cycle and continue for one clock cycle before returning to low level. When the pulse signal received by the register is at a falling edge, the second new signal will change from low to high level in the next clock cycle and remain high for one clock cycle before returning to low level. The first new signal is used as the rising edge single pulse signal, and the second new signal is used as the falling edge single pulse signal.
3. The high-precision pulse error compensation method based on FPGA according to claim 1, characterized in that, The step of obtaining the pulse width error parameter based on the pre-compensation pulse signal specifically includes: The difference is obtained by subtracting the pulse width of the standard pulse signal from the pulse width of the pulse signal before compensation, and the difference is used as the pulse width error parameter.
4. The high-precision pulse error compensation method based on FPGA according to claim 3, characterized in that, The step of performing a specified delay processing on the rising edge single pulse signal or the falling edge single pulse signal according to the pulse width error parameter specifically includes: When the pulse width error parameter is less than zero, the falling edge single pulse signal will be delayed by the same value of the pulse width error parameter or the preset error value. When the pulse width error parameter is greater than zero, the rising edge single pulse signal will be delayed by the same value as the pulse width error parameter or the preset error value. When the pulse width error parameter is equal to zero, the rising edge single pulse signal and the falling edge single pulse signal remain unchanged.
5. A high-precision pulse error compensation system based on FPGA, used to apply the high-precision pulse error compensation method based on FPGA as described in any one of claims 1-4, characterized in that, include: The system comprises a pulse generation unit, an edge separation unit, a first delay unit, a second delay unit, and a trigger unit, wherein: The pulse generating unit is used to generate the pulse signal and transmit the pulse signal to the edge separation unit; The edge separation unit is used to generate rising edge single pulse signals and falling edge single pulse signals according to the pulse signal, and transmits the rising edge single pulse signal to the first delay unit and the falling edge single pulse signal to the second delay unit. The first delay unit is used to delay the rising edge single pulse signal according to the pulse width error parameter, and the second delay unit is used to delay the falling edge single pulse signal according to the pulse width error parameter. The trigger unit is used to combine the delayed rising edge single pulse signal and the falling edge single pulse signal to obtain a compensation pulse signal.
6. The FPGA-based high-precision pulse error compensation system according to claim 5, characterized in that, The edge separation unit is used to continuously input the pulse signal into the register, and simultaneously generate the first new signal and the second new signal while the pulse signal is input into the register; When the pulse signal received by the register is at the rising edge, the first new signal will change from low level to high level in the next clock cycle and continue for one clock cycle before returning to low level. When the pulse signal received by the register is at a falling edge, the second new signal will change from low to high level in the next clock cycle and remain high for one clock cycle before returning to low level. The first new signal is used as the rising edge single pulse signal, and the second new signal is used as the falling edge single pulse signal.
7. The FPGA-based high-precision pulse error compensation system according to claim 5, characterized in that, The FPGA-based high-precision pulse error compensation system also includes a parameter configuration unit, wherein: The parameter configuration unit is used to obtain a delay coefficient based on the pulse width error parameter, and apply the delay coefficient and the pulse width error parameter to the first delay unit or the second delay unit; The first delay unit is used to delay the rising edge single pulse signal according to the pulse width error parameter and the delay coefficient, and the second delay unit is used to delay the falling edge single pulse signal according to the pulse width error parameter and the delay coefficient.
8. The FPGA-based high-precision pulse error compensation system according to claim 7, characterized in that, The first delay unit is used to delay the rising edge single pulse signal according to the pulse width error parameter and the delay coefficient, and the second delay unit is used to delay the falling edge single pulse signal according to the pulse width error parameter and the delay coefficient, specifically including: The actual delay value is calculated based on the delay coefficient. When the pulse width error parameter is less than zero, the falling edge single pulse signal will be delayed by the actual delay value. When the pulse width error parameter is greater than zero, the rising edge single pulse signal will be delayed by the actual delay value. When the pulse width error parameter is equal to zero, the rising edge single pulse signal and the falling edge single pulse signal remain unchanged.
9. The FPGA-based high-precision pulse error compensation system according to claim 5, characterized in that, The trigger unit includes a first NOR gate G1 and a second NOR gate G2, wherein: The first input terminal (21) of the second NOR gate G2 is connected to the first delay unit for receiving the signal from the first delay unit. The second input terminal (22) of the second NOR gate G2 is connected to the output terminal of the first NOR gate G1 for receiving the signal from the first NOR gate G1. The first output terminal of the second NOR gate G2 is connected to the fourth input terminal (12) of the first NOR gate G1 for transmitting the signal of the second NOR gate G2 to the first NOR gate G1. The third input terminal (11) of the first NOR gate G1 is connected to the second delay unit and is used to receive the signal from the second delay unit. The output terminal of the first NOR gate G1 is used as the output terminal of the trigger unit and is used to output the pre-compensation pulse signal or the compensation pulse signal.
10. The FPGA-based high-precision pulse error compensation system according to claim 9, characterized in that, Also includes: When the first input terminal (21) of the second NOR gate G2 receives a low-level signal and the third input terminal (11) of the first NOR gate G1 receives a high-level signal, the output terminal of the first NOR gate G1 outputs a low level. When the first input terminal (21) of the second NOR gate G2 receives a high-level signal and the third input terminal (11) of the first NOR gate G1 receives a low-level signal, the output terminal of the first NOR gate G1 outputs a high level. When the first input terminal (21) of the second NOR gate G2 receives a low-level signal and the third input terminal (11) of the first NOR gate G1 receives a low-level signal, the output terminal of the first NOR gate G1 remains unchanged.