FPGA (Field Programmable Gate Array)-based accelerated compression data regular expression matching method and device

Abstract

The invention discloses an FPGA (Field Programmable Gate Array)-based compressed data regular expression matching acceleration method and an FPGA-based compressed data regular expression matching acceleration device, which are characterized in that an acceleration processing mechanism is provided for a pointer unit in compressed data, so that the matching throughput rate is remarkably improved and the time delay is greatly reduced on the premise that complete decompression is not carried out. The device adopts a co-processing architecture, and a scanning module of the co-processing architecture is responsible for identifying and separating literal quantities and pointers in data streams; the deterministic finite state automaton performs conventional state transition on the literal quantity; and the verification module, the pointer data queue and the storage control module carry out equivalent state jump calculation on the pointer in parallel, and finally the matching result is integrated by the output queue. According to the method, original one-by-one matching of long data sequences is converted into single-time efficient calculation of pointers, and the matching efficiency is optimized fundamentally.

Description

Technical Field

[0001] This invention belongs to the field of deep packet inspection technology, and involves related technologies such as regular expression matching, data encoding compression, and FPGA hardware programming. Specifically, it relates to an FPGA-based method and apparatus for accelerating compressed data regular expression matching. Background Technology

[0002] Regular expressions, due to their powerful pattern description capabilities and high flexibility, have been widely used in the field of deep packet inspection (DPI) and are a core component of key technologies such as network intrusion detection systems, next-generation firewalls, and intelligent network traffic management systems.

[0003] With the rapid development of mobile Internet technology and the continuous emergence of related applications, global network traffic has shown an explosive growth trend. In order to improve network bandwidth utilization and reduce data transmission latency, more and more network protocols and services (such as HTTP) use compression technology to encode transmitted data. However, the large-scale deployment of compression technology has brought severe performance challenges to systems that rely on deep packet inspection. Taking the widely used Gzip compression algorithm as an example, it can usually achieve a compression rate of about 20%, that is, reduce the original data volume to one-fifth of the original. In the existing technology, the mainstream method for processing compressed data is to first completely decompress the data packet and then perform regular expression matching. This "decompression-matching" serial mode has inherent defects: (1) The throughput drops sharply: the decompression operation restores the data to the original size (for example, 5 times the size after compression), which leads to a surge in the amount of data that the subsequent matching engine needs to process, and the overall throughput of the system drops to 20% or less of the original processing capacity. (2) The processing latency increases significantly: the decompression algorithm itself consumes a lot of computing resources and introduces additional processing latency.

[0004] From an implementation perspective, existing technical solutions can be divided into CPU-based software methods and FPGA-based hardware acceleration methods. CPU-based software methods typically run on general-purpose operating systems, and their data processing path involves multiple memory copies (from the network card to the kernel, and from the kernel to user space) and overhead such as operating system interrupts and system calls. This series of operations results in a latency of microseconds to milliseconds for the entire processing flow, constituting a serious performance bottleneck in high-speed network environments and failing to meet the requirements of low latency and high throughput.

[0005] FPGA-based hardware acceleration methods utilize its hardware programmability, high parallelism, and low latency to accelerate matching, aiming to overcome the performance bottleneck faced by the CPU. In the existing technology, FPGA-based acceleration schemes have made a series of advances. For example, some schemes are dedicated to compiling regular expressions into hardware logic circuits. In the implementation based on non-deterministic finite automata (NFA), such as the technology proposed in reference [1] Yi-Hua Yang and Viktor Prasanna. High-performance and compact architecture for regular expression matching on fpga. IEEE Transactions on Computers, 61(7):1013–1025,2011., the matching throughput is significantly improved by directly mapping the regular expression to NFA and implementing it on the FPGA. In order to further optimize the utilization of hardware resources, reference [2] Koša V, Žádník M, Ko Enek J. NFA reduction for regular expressions matching using FPGA[C]. 2013 International Conference on Field-Programmable Technology (FPT). IEEE, 2013: 338-341. and references [3] Hieu TT, Thinh TN, Tomiyama S. ENREM: An efficient NFA-based regular expression matching engine on reconfigurable hardware for NIDS[J]. Journal of Systems Architecture, 2013, 59(4-5): 202-212. focus on state simplification and structural optimization of NFA to reduce the logic resources required when deploying on FPGA. Another technical approach uses deterministic finite automaton (DFA) for hardware implementation. For example, the literature [4] Yang J, Jiang L, Tang Q, et al. PiDFA: A practical multi-stride regular expression matching engine based on FPGA[C]. 2016 IEEE International Conference on Communications (ICC). IEEE, 2016: 1-7. proposes a DFA engine based on path fusion and multi-stride matching, aiming to improve the matching efficiency on FPGA. In addition, to solve the problem of inconvenient rule set updates, the literature [5] Sun, Mingqian, et al. "PTME: A Regular Expression Matching Engine Based on Speculation and Enumerative Computation on FPGA." ACM Transactions on Reconfigurable Technology and Systems (2024). proposes a DFA matching device that supports dynamic updates of regular expression rule sets.Reference [4] Yang J, Jiang L, Tang Q, et al. PiDFA: Apractical multi-stride regular expression matching engine based on FPGA[C]. 2016 IEEE International Conference on Communications (ICC). IEEE, 2016: 1-7. A path fusion and multi-step matching method based on deterministic finite automaton (DFA) on FPGA is proposed. However, after in-depth analysis, it can be seen that all the above-mentioned hardware acceleration methods based on FPGA, whether based on NFA or DFA, have a common and fundamental technical defect: their design goal is uncompressed plaintext data streams. This means that when faced with compressed data that is common in the network, these hardware accelerators cannot process it directly and must rely on a front-end, complete decompression unit. This "complete decompression first, then hardware matching" processing mode fails to utilize the structural and redundant characteristics of the compressed encoded data itself, and instead reintroduces the performance bottleneck caused by the data volume expansion and decompression computation overhead, thereby greatly weakening the expected performance of hardware acceleration. Summary of the Invention

[0006] This invention provides a method and apparatus for accelerating regular expression matching of compressed data based on FPGA. This method utilizes the redundancy characteristics of compressed data to quickly skip pointer data matching, thereby improving regular expression matching throughput and reducing matching latency.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides an FPGA-based method for accelerating regular expression matching of compressed data, characterized by comprising the following steps: Step 1: Clear all data storage space except for the input queue; initialize the storage contents of the deterministic finite state automaton; set the matching state curState in the scanning module to its initial value and the scan index to 0; Step 2: The scanning module determines whether the input queue is not empty. If the input queue is empty, the matching process is paused; Otherwise, the scanning module reads a data unit from the input queue and distinguishes between literals and pointers based on whether the length field of the data unit is 0; if the data unit is a literal, it jumps to step 3; otherwise, it jumps to step 4. Step 3: The scanning module reads the literal data, concatenates the first state address based on the literal data, reads the matching state of the literal data from the deterministic finite state automaton based on the first state address and updates the matching state curState; then the matching state curState and the literal data are appended to the storage control module, and the scan index is incremented by 1; jump to step 2; Step 4: The scanning module reads the pointer data, reads the matching status of the last literal data referenced by the pointer data from the storage control module, and records the read content as the final predicted matching status of the pointer data; then it encapsulates the pointer data, the matching status curState, and the scan index to obtain an encapsulation unit, and writes the encapsulation unit into the pointer data queue; subsequently, curState is updated to the final predicted matching status, and the scan index is incremented by the length field value from the pointer data; finally, it jumps to steps 2 and 5 for parallel execution. Step 5: The verification module checks whether the pointer data queue is empty. If the pointer data queue is empty, the verification process is paused; Otherwise, the verification module reads a wrapper unit from the pointer data queue, assigns the matching state localState inside the verification module to the matching state in the wrapper unit, assigns the verification index inside the verification module to the index value of the wrapper unit, and encapsulates the pointer data and scan index into a verification address. Based on the verification address, it reads the literal data referenced by the pointer data and its matching state from the storage control module as decompressed data and predicted matching state. Subsequently, starting from the first character of the decompressed data, the predicted matching state is verified one by one. If the actual matching state and the predicted matching state are different, the predicted matching state of the character is corrected. For each character verified, the verification index is incremented by 1. Step 6: Write the decompressed data and the corrected prediction matching status back to the storage control module; once the decompressed data and the corrected prediction matching status are successfully written back, proceed to steps 5 and 7 for parallel execution. Step 7: The result collection module reads the status data from the storage control module, traverses the status data to obtain the accepted status, and writes it into the output queue.

[0008] Furthermore, in step 3, the scanning module combines the literal data and the matching state curState into a first state address by bit concatenation, and reads the matching state from the deterministic finite state automaton based on the first state address.

[0009] Furthermore, in step 4, the scanning module calculates the scanning address by scanning the distance field in the index and pointer data. Based on the scanning address, it reads the matching status of the last literal data referenced by the pointer data from the scanning acceleration area of ​​the storage control module. By using the matching status of the last literal data referenced as the final predicted matching status of the pointer data, the purpose of predicting the matching status is achieved, thereby realizing the function of quickly skipping the matching of pointer data.

[0010] Further, in step 5, the verification module uses the index in the encapsulation unit as the verification address. Based on the verification address, it reads the literal data referenced by the pointer data and its matching state from the copy area of ​​the storage control module as decompressed data and predicted matching state. Then, it starts verification from the first literal of the decompressed data, combines the literal with the matching state localState inside the verification module through bit concatenation to form a second state address, and reads the actual matching state trueState from the deterministic finite state automaton based on the second state address. It compares trueState with the predicted matching state of the first literal: if they are not equal, it corrects the predicted matching state of the character and continues to verify the matching state of the next character; if they are equal, the verification is completed, and the corrected predicted matching state and decompressed data are written back through the verification data write-back area of ​​the storage control module.

[0011] Furthermore, in step 5, reading the literal data referenced by the pointer data and its matching status from the storage control module as decompression data and predicted matching status includes: the verification module calculates the scan acceleration address through the index in the encapsulation unit and the distance field in the pointer data, and reads the decompression data and its predicted matching status from the storage control module based on the scan acceleration address.

[0012] In a second aspect, the present invention provides an FPGA-based accelerated compressed data regular expression matching device, characterized in that it includes an input queue, a scanning module, a deterministic finite state automaton, a verification module, a pointer data queue, a storage control module, a result collection module, and an output queue; The input queue is used to store input data written from outside the device, including literal data and pointer data; The scanning module is used to read input data from the input queue, match literal data, and predict the final matching status of pointer data. A deterministic finite state automaton is used to store the matching states of a deterministic finite state automaton compiled from a set of regular expression rules. The verification module is used to verify the predicted matching status of pointer data and correct erroneous predicted matching status. The pointer data queue is used to store the pointer data to be verified and related information written by the scanning module; The storage control module is used to store the scanning history literal data of the scanning module, predict the final matching state when the scanning module encounters pointer data, write back after the verification module has completed the verification, the actual state required by the result collection module, and control the reading and writing of BRAM. The result collection module is used to traverse the status data read from the storage control module and write the received status into the output queue; The output queue is used to temporarily store the status and position of a successful match.

[0013] Furthermore, the deterministic finite state automaton is constructed using a dual-port BROM IP core instance, connected to the scanning module via the address bus and data bus, and connected to the verification module via the address bus and data bus, outputting the matching status of literal data to the scanning module and the verification module.

[0014] Furthermore, the input queue, pointer data queue, and output queue are constructed using a FIFO IP core instance. The input queue is connected to the scanning module via the address bus and data bus, the pointer data queue is connected to the scanning module via the address bus and data bus, and is also connected to the verification module via the address bus and data bus. The output queue is connected to the result collection module via the address bus and data bus.

[0015] Furthermore, the storage control module includes a copy area, a verification data write-back area, a priority arbitration area, a scan acceleration area, and a ring storage area; The copy area is used to read the verification address of the verification module as the copy address, and to read the literal data referenced by the pointer data in the circular memory area and its matching status as the verification data. The verification data write-back area is used to read the literal data and corresponding status after the verification module has completed verification and write them back to the circular storage area. The priority arbitration area is used to control the read and write operations of the circular storage area by the copy area, the verification data write-back area, and the scan acceleration area in the storage control module. The scan acceleration area is used to read the address when the scan module encounters pointer data as the scan acceleration address. The matching status of the last literal data referenced by the pointer data is obtained from the circular memory area and returned to the scan module. The ring memory area is used to respond to read, write, and copy requests via the read / write control bus, address bus, and data bus connected to the priority arbitration area.

[0016] Furthermore, the ring-shaped storage area is constructed using a dual-port BRAM IP core instance.

[0017] Compared with the prior art, the present invention has at least the following beneficial technical effects: 1. High throughput and low latency The core technological advantage of this invention stems from its unique hardware architecture, which can natively process any compressed data unit (whether it is literal or pointer data) in a fixed two clock cycles. Specifically, for literal data, a two-clock-cycle scan can be achieved through the scanning module; for pointer data, a two-clock-cycle scan can be achieved by predicting its final matching state. This inherent characteristic ensures a deterministic low latency of only 10 nanoseconds (ns) at a 200MHz operating frequency. More importantly, its throughput is fundamentally improved compared to the traditional "decompress then match" baseline method because this invention directly acts on the compressed data, greatly reducing the total number of data units that need to be processed, thereby directly translating the data compression ratio into a performance speedup. Furthermore, this architecture has excellent scalability: by instantiating multiple processing cores in parallel on the FPGA, the total system throughput can achieve a linear increase in lossless latency. That is, while the total performance doubles, the processing latency of a single data unit remains constant at two clock cycles, demonstrating unique engineering value that balances high performance and flexible scalability.

[0018] 2. Excellent compatibility and wide applicability The hardware-accelerated compression device designed in this invention possesses high flexibility. Firstly, regarding rule set management, this device utilizes a block ROM (BROM) IP core to store the state transition table of the regular expression rule set. This design supports dynamic updates to the rule set without requiring modification and resynthesis of the FPGA project source code, greatly improving system maintainability. Secondly, in terms of algorithm compatibility, the input queue 101 of this device is designed to receive data streams conforming to the LZ77 algorithm encoding specification. Therefore, it can widely support and efficiently match various compression algorithms based on the LZ77 core idea, such as LZSS, Gzip, Brotli, and other mainstream compression formats.

[0019] 3. Excellent system scalability and integration capabilities In terms of integration, the input and output queues 108 of this invention adopt a standard PCIe (Peripheral Component Interconnect Express) interface design, allowing for seamless integration into existing servers as plug-and-play devices. They also interface with upper-layer applications via standard APIs to form a heterogeneous computing system. Regarding scalability, the system supports horizontal performance scaling through multiple instantiations. Simultaneously, leveraging the programmability of the FPGA, the state transition table can be updated online, enabling flexible functional expansion. This design allows computationally intensive CPU tasks to be efficiently offloaded to the FPGA. Through its parallel processing capabilities and low latency, it effectively overcomes the performance bottleneck of general-purpose CPUs in processing massive compressed data, providing high-performance, low-latency data inspection services for upper-layer applications and significantly improving the user experience. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the data format after the original data has been compressed using LZ77. Figure 2 It is the state transition diagram of the DFA constructed using the regular expression "(wx+y) | (xy+z)"; Figure 3 This is a framework diagram of the regular expression matching device for FPGA-accelerated compressed data proposed in this invention; Figure 4 This is a data flow diagram of a regular expression matching method for FPGA-accelerated compressed data proposed in this invention; Figure 5 This invention uses a cumulative distribution graph of dataset pointer lengths; Figure 6 This invention uses the input "xyyyzw<5,6>wwxyz" as an example to scan part of the signal simulation waveform of module 102; Figure 7 This invention uses the input "xyyyzw<5,6>wwxyz" as an example to verify the signal simulation waveform of module 104.

[0021] Among them, 101 is the input queue; 102 is the scanning module; 103 is the deterministic finite state automaton; 104 is the verification module; 105 is the pointer data queue; 106 is the storage control module; 107 is the result collection module; and 108 is the output queue. Detailed Implementation

[0022] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0023] It should be noted that when an element is referred to as being "set on" another element, it can be directly on the other element or may be interspersed with another element. When an element is considered to be "connected to" another element, it can be directly connected to the other element or may be interspersed with another element. The terms "upper," "lower," "front," "rear," "inner," and "outer," etc., used herein to indicate orientation or positional relationships are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the specification of this invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] The technical solution of the present invention will be clearly and completely described below with reference to simple specific embodiments. Based on these embodiments, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] In the description of this invention, unless otherwise stated, "a plurality of" means two or more. It should be noted that, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0027] This invention provides a regular expression matching method and apparatus for FPGA-accelerated compressed data, aiming to accelerate regular expression matching of compressed data with the help of FPGA.

[0028] Example 1 This embodiment proposes an FPGA-based device for accelerating regular expression matching of compressed data. The device is designed in modules, including an input queue 101, a scanning module 102, a deterministic finite state automaton 103, a verification module 104, a pointer data queue 105, a storage control module 106, a result collection module 107, and an output queue 108. This device accelerates regular expression matching by quickly skipping the matching of encoded data in compressed data, and finally achieves high throughput and low latency regular expression matching of compressed data on the FPGA board.

[0029] To further illustrate the specific content of the technical solution of this invention, the terms, technical terms, and related technologies involved in this invention will first be explained: (1) Gzip, Deflate Gzip is a content encoding standard defined in the HTTP / 1.1 protocol, and its Deflate compression algorithm is key to achieving data compression. Deflate compression is a hybrid algorithm that first uses the LZ77 algorithm to process repeating sequences in the data stream, and then uses Huffman coding to encode the processed data.

[0030] The LZ77 algorithm uses a 32KB sliding window as a dynamic dictionary during the compression of original data. During compression, it attempts to find the longest substring matching the current position from this dynamic dictionary. This repeated substring at the current position is encoded in the format <length, distance>, where "length" refers to the number of bytes in the matching string, and "distance" refers to the backtracking distance from the current position to the starting position of the matching string in the dictionary. For example, if the original data is "Anhui University is a greatuniversity", after compression using the LZ77 algorithm, the second "niversity" is encoded as a tuple <9, 22>, indicating that the data at the current position is a 9-byte repeated substring, and its original content is located 22 bytes backtracking from the current position. Figure 1 As shown.

[0031] Data compressed using the LZ77 algorithm contains literal and pointer data. The Huffman coding algorithm then further encodes this data to generate the final Gzip format. Because Huffman is a variable-length encoding algorithm, the length of the encoded original characters is uncertain, appearing as a continuous binary stream. Therefore, existing regular expression matching methods for network compressed data must perform matching only after Huffman decoding.

[0032] (2) Regular expression matching Pattern matching is a fundamental and crucial technology in computer science, generally categorized into string matching and regular expression matching. Classic string matching algorithms include, but are not limited to, the Knuth-Morris-Pratt (KMP) algorithm, the Aho-Corasick (AC) algorithm, and the Wu-Manber algorithm. From the perspective of formal language theory, an ordinary string is a special case of a regular expression, namely a pattern that does not contain any metacharacters. Therefore, regular expression matching is a more general and expressive matching paradigm that fully encompasses the functionality of string matching.

[0033] The theoretical foundation for regular expression matching stems from automata theory. A given regular expression can be systematically transformed into an equivalent non-deterministic finite automaton (NFA) using standard algorithms, such as Thompson's construction. Subsequently, this NFA can be further transformed into an equivalent deterministic finite automaton (DFA) using subset construction, the latter being widely used in high-performance matching engines due to its lack of state transition uncertainty.

[0034] The definition of a DFA is as follows: The definition is as follows: A non-empty, finite set of states; A non-empty, finite set of characters is called the input alphabet. : Transfer function, the input parameters are state and character, the output is state; Initial state, satisfying ; : A set of accepting states that satisfy ; Initially, the DFA is in its initial state. Each time a character is read, a state transition occurs according to the transition function. The new state is the matching state of that input character. If this matching state belongs to the accepting state set, it means the string has been successfully matched. For example... Figure 2 As shown, when the DFA constructed using “(wx+y)|(xy+z)” is used to match the string “wxxxy”, the resulting matching state path is “12223”, where “6” is the accept state, indicating that the string “wxxxy” was successfully matched by “wx+y”.

[0035] (3) Technical solution Building upon the aforementioned fundamental concepts and techniques, this paper further introduces the basic theory upon which the proposed method relies, as well as the technical solution of this invention. According to the LZ77 algorithm compression principle, the original data can be compressed because it contains repetitive and redundant parts. Encoding these repetitive and redundant parts into coded data that occupies less space achieves the purpose of compression. Currently, there are methods dedicated to utilizing these compression codes to quickly skip the matching of redundant data in compressed data, thereby accelerating the matching process.

[0036] Finite State Automata (FSA) are context-free models, meaning the next transition state depends only on the current active state and the next input character, and is independent of other historical states. This property guarantees a deterministic outcome: given the same starting state and input sequence, the FSA will inevitably reach the same final state. It is precisely by leveraging this that previous methods were able to accelerate processing of repetitive sequences in compressed data by "skipping" matching operations, since the matching results for repetitive sequences are predictable.

[0037] The regular expression matching method and apparatus for accelerating compressed data based on FPGA proposed in this invention utilize the context-independent characteristics of FSA. When processing redundant encoded data, the method and apparatus quickly skip matching the encoded data by reading the matching state of the last literal data it references as the final predicted matching state of the encoded data. To ensure that the predicted matching state is consistent with the actual matching state, this apparatus asynchronously verifies the predicted matching state of the pointer data through the storage control module 106 and the verification module 104, significantly improving the efficiency of regular expression matching for compressed data without sacrificing accuracy.

[0038] Reference Figure 3 An FPGA-based device for accelerating compressed data regular expression matching includes an input queue 101, a scanning module 102, a deterministic finite state automaton 103, a verification module 104, a pointer data queue 105, a storage control module 106, a result collection module 107, and an output queue 108.

[0039] The input queue 101 is used to store input data written externally to this device and output data units. The input data includes literal data and pointer data. It is constructed through a FIFO IP core instance and connected to the scan module 102 through the address bus and data bus.

[0040] The scanning module 102 is used to read input data and matching literal data from the input queue 101, and predict the final matching state of the pointer data to obtain the predicted matching state of the pointer data.

[0041] A deterministic finite state automaton 103 is used to store the state transition table of the deterministic finite state automaton compiled from the regular expression rule set. The deterministic finite state automaton 103 is constructed using a dual-port BROM IP core instance, therefore it has two independent ports, a and b. The deterministic finite state automaton 103 is connected to the scanning module 102 and the verification module 104 via the address bus and data bus, outputting the matching status of literal data to both the scanning module 102 and the verification module 104. Port a receives the first state address from the scanning module 102 via the address bus and outputs the matching status to 102 via the data bus. Port b receives the second state address from the verification module 104 via the address bus and outputs the matching status to 104 via the data bus.

[0042] The verification module 104 reads the literal data corresponding to the pointer data and its matching status, uses the matching status corresponding to the literal data as the predicted matching status of the pointer data, verifies the predicted matching status, and corrects erroneous predicted matching statuses.

[0043] The pointer data queue 105 is used to store the pointer data to be verified and related information written by the scanning module 102. It is constructed through a FIFO IP core instance, connected to the scanning module 102 through the address bus and the data bus, and connected to the verification module 104 through the data bus and the data bus.

[0044] The pointer data queue 105 is used to cache the pointer data to be verified and related information written by the scanning module 102, and provides it to the verification module 104 for reading. This queue is constructed using a FIFO IP core instance. Its input receives data from the scanning module 102, and its output provides data to the verification module 104, thereby achieving asynchronous data decoupling and sequential transmission between the two modules.

[0045] The storage control module 106 is used to store the scanning history literal data of the scanning module 102, the prediction of the final matching state when the scanning module 102 encounters pointer data, the write-back after the verification module 104 completes the verification, and the actual state of the scanning data required by the result collection module 107. It also controls the reading and writing of the ring storage area 1065 through the priority arbitration area 1063. The storage control module 106 includes a copy area 1061, a verification data write-back area 1062, a priority arbitration area 1063, a scanning acceleration area 1064, and a ring storage area 1065.

[0046] The copy area 1061 is used to read the verification address of the verification module 104 as the copy address, and to read the literal data referenced by the pointer data of the ring memory area 1065 and its matching status data as the verification data. The verification data write-back area 1062 is used to read the literal data and the corrected matching status data after verification by the verification module 104 and write them back to the circular storage area 1065 to achieve the purpose of decompressing data and verifying data. The priority arbitration area 1063 is used to make decisions based on a preset priority strategy to control the read / write enable signals of the circular storage area 1065 in the copy area 1061, the verification data write-back area 1062, and the scan acceleration area 1064 in the storage control module 106. The priority arbitration area 1063 is used to resolve concurrent access conflicts between the copy area 1061, the verification data write-back area 1062, and the scan acceleration area 1064 to the shared ring storage area 1065. When multiple access requests arrive simultaneously, the priority arbitration area will adjudicate according to a preset priority strategy. For example, the request from the scan acceleration area 1064 is given the highest priority to ensure timely response from the data processing pipeline; the next highest priority is given to the verification data write-back area 1062, and the last priority is given to the copy area 1061. The arbitration logic only grants access to the storage area to the requester with the highest current priority, while other requesters are made to wait temporarily, thereby ensuring orderly access to the shared storage resources.

[0047] The scanning acceleration area 1064 is used to read the address when the scanning module 102 encounters pointer data as the scanning acceleration address. The matching status of the last literal data referenced by the pointer data is obtained by reading the ring storage area 1065 through the scanning acceleration address and is passed to the scanning module 102 as the final predicted matching status of the pointer data. The ring memory area 1065 is constructed using a dual-port BRAM IP core instance. It responds to read, write and copy requests through the read / write control bus, address bus and data bus connected to the priority arbitration area 1063. The ring memory area 1065 is used to store the historical literal data and its matching status data after scanning by the scanning module 102, and the literal data and corrected matching status data after verification by the verification module 104.

[0048] The result collection module 107 is used to read and process the corrected matching status data output by the storage control module 106, traverse the corrected predicted matching status, and if there is an acceptance state, encapsulate the acceptance state and the corresponding index and write it into the output queue 108.

[0049] The output queue 108 is used to temporarily store the status and position of successfully matched results. It is constructed through a FIFO IP core instance and connected to the result collection module 107 through the address bus and data bus.

[0050] Specifically, the scanning module 102 reads one data unit from the input queue 101 each time. It distinguishes between literals and pointers based on whether the length field of the data unit is 0.

[0051] When reading a literal data unit (denoted as literal, 1-byte ASCII code value), the matching state maintained by the scanning module 102 (denoted as curState) is combined with the literal to form a first state address {literal, curState}. The deterministic finite state automaton 103 is read to obtain the matching state of the literal, which is denoted as newState. Then, newState is assigned to curState, the scan index is incremented by 1, and the literal and its matching state curState are appended and written to the circular storage area 1065 in the storage control module 106.

[0052] When the data read is a pointer data unit (denoted as pointer), its data structure is a tuple.<length,distance> The pointer is defined as follows: the length field indicates the byte length of the literal data referenced by the pointer, and the distance field indicates the distance between the pointer and the literal data it references. The scanning module 102 calculates the starting position of the literal data referenced by the pointer based on the maintained index and the distance field in the pointer, using this as the accelerated scanning address, i.e., index - distance. Using this starting position, the module reads the matching state of the last literal data referenced by the pointer from the accelerated scanning area 1064 of the storage control module 106 as the final predicted matching state of the pointer data. The matching of the pointer data is quickly skipped, and the scanning index plus the length is started. Since the literal data has not yet been copied, and the predicted matching state may not perfectly match the actual matching state of the pointer, the pointer, the current matching state curState, and the scanning index are encapsulated into the format {index, pointer, curState} and output to the pointer data queue 105. In the above processing flow, processing one literal data unit consumes 2 clock cycles, and processing one pointer data unit consumes 2 clock cycles.

[0053] The deterministic finite state automaton 103 stores a state transition table describing the state transitions that occur after the DFA, compiled from a set of regular expression rules, reads the input. Specifically, the deterministic finite state automaton 103 uses a dual-port BROM IP core instance to store matching states. The initial value is read from the coe file. To easily distinguish between accepting and non-accepting states, a highest-order bit is added; by default, the highest-order bit is 0 for non-accepting states and 1 for accepting states. When the input address signal is {literal, curState}, it indicates that the DFA is in the curState state and has read the literal state, which is the matching state it will jump to.

[0054] The verification module 104 reads a pointer data encapsulation unit {index, pointer, curState} to be verified from the pointer data queue 105 each time. Since the data at the corresponding position of the pointer has not yet been copied, the address of the literal data is obtained by using index-distance. The address of the literal data is used as the copy address to read the decompressed data of the pointer and its predicted matching state from the copy area 1061 of the storage control module 106. Then, the literal in the decompressed data is combined with the previous matching state in sequence to form a reading deterministic finite state automaton 103 to obtain the actual matching state trueState of the literal. The actual matching state trueState is then compared with the corresponding predicted matching state read from the storage control module 106: if they are different, the verification index is incremented by 1, and the predicted matching state of the literal is corrected to the actual matching state trueState. The next literal is verified, and the process is repeated until the states are the same; if the states are the same, the verification index is incremented by 1, and the verification and correction of the pointer's matching state is completed. Then, the corrected matching state is written back through the verification data write-back area 1062 of the storage control module 106.

[0055] The pointer data queue 105 uses a FIFO IP core instance to store the pointer data encapsulation unit to be verified output by the scanning module 102 in the format of {index, pointer, curState}, which is used to buffer the difference in processing speed between the scanning module 102 and the verification module 104.

[0056] The circular storage area 1065 stores the literal data that the pointer may reference and its matching status. The storage capacity supports dynamic adjustment. Taking the LZ77 encoding algorithm used by Gzip as an example, the maximum distance is 32K, so it is necessary to maintain literal data of dictionary size 32K and its matching status. The length range is 3-258. The cumulative distribution of dataset features and dataset pointer lengths used in this invention is shown in Table 2 and... Figure 5 As shown, the length of a BRAM row is set to 16. The BRAM instance storing literals is configured as follows: the storage row width is configured to 128 bits, each storage row can store 128 / 8 = 16 literals, and the depth is set to 1024. Therefore, two dual-port BRAM instances are instantiated as storage media, and the BRAM instance storing state is configured similarly. At the same time, to increase the read port, two BRAM instances storing state are copied simultaneously. In addition, the storage control module 106 also constructs a cache line through a register array to temporarily store data that is not full in a BRAM row, avoiding the time consumption caused by the cumbersome "read-modify-write back" steps when writing data to the BRAM. When the cache line is full, it is then written to the BRAM instance.

[0057] When the verification index is at least one row more than the result collection index, the result collection module 107 obtains the status data by reading the storage control module 106. Each time it reads, it obtains two rows of status data, and by traversing, it determines whether the status is an acceptance status and writes the successfully matched position to the output queue 108.

[0058] Output queue 108 is implemented using a FIFO IP core.

[0059] The device employs a collaborative processing architecture, in which the scanning module is responsible for identifying and separating literals and pointers in the data stream; the deterministic finite state automaton performs regular state transitions on the literals; and the verification module, pointer data queue, and storage control module perform equivalent state transition calculations on the pointers in parallel, with the final matching results being integrated by the output queue.

[0060] (4) Example To more intuitively illustrate the working process of this device, the present invention uses... Figure 2 The DFA shown here, along with the input data "xyyyzw<5,6>wwxyz", serves as an example to illustrate the working process of this device.

[0061] Initialization: Scan module 102 initializes the index to 0 and the matching state curState to 0; deterministic finite state automaton 103 is initialized, and the BROM IP core example is stored. Figure 2 The state transition table of the DFA is shown in Table 1. Rows represent the current matching state, and columns represent the scanned characters. The rows and columns uniquely determine the next matching state obtained by matching the scanned characters with the current matching state. For simplicity, this table does not contain the entire state transition table; states not explicitly mentioned are assumed to be 0. Figure 2As shown, there are 7 states in total. Among them, 3 and 6 are the accepting states. Since 3 bits can fully represent them, we add one more bit. The final state is represented by 4 bits, where 3 is 1011, i.e. b, and 6 is 1110, i.e. e. The remaining states are still the original states because the highest bit is 0.

[0062] Table 1 State Transition Table

[0063] like Figure 6 As shown, in the first clock cycle: at the rising edge of the system clock, the scanning module 102 reads the input character 'x', combines 'x' with the matching state curState to form the first state address {'x', 0}, and reads the matching state from the deterministic finite state automaton 103.

[0064] The third clock cycle: the rising edge of the system clock. As shown in Table 1, by looking up the table, the row is state 0, the column is the character 'x', and we can see that the corresponding matching state is '4'. The deterministic finite state automaton 103 returns the matching state '4'. The scanning module 102 writes the character 'x' and the matching state '4' to the storage control module 106. The scanning module 102 assigns the current matching state curState to '4' and increments the index by 1. The scanning module 102 reads the input character 'y', combines 'y' with the matching state curState to form the first state address {'y', 4}, and reads the matching state from the deterministic finite state automaton 103.

[0065] From the 5th to the 12th clock cycle: the scanning module 102 reads the characters 'y', 'y', 'z', and 'w' in sequence. By the 12th clock cycle, the current matching state curState of the scanning module 102 is '1', the index is 6, and the storage control module 106 has saved the string "xyyyzw" and its matching state "4555e1".

[0066] In the 13th clock cycle, the scanning module 102 receives the pointer data <5, 6>. The scanning module 102 calculates the index address of the last character referenced by the pointer data and reads the matching status corresponding to the last character 'z' of the literal data "xyyyz" pointed to by the pointer from the scanning acceleration area 1064 in the storage control module 106.

[0067] In the 15th clock cycle, the scanning module 102 receives the pointer data <5, 6> and finally predicts the matching state "e". This realizes the prediction of the pointer matching state, updates the current matching state to the final matching state 'e' of the literal data pointed to by the pointer, writes the pointer information {index=5, pointer=<5, 6>, curState=1} into the pointer data queue 105, and increments the index by 1. At the same time, the scanning module 102 reads the input character 'w', combines 'w' with the matching state curState to form the first state address {'w', e}, and reads the matching state from the deterministic finite state automaton 103.

[0068] From the 17th to the 24th clock cycle: Scanning module 102 reads the characters 'w', 'x', 'y', and 'z' sequentially. By the 24th clock cycle, the current matching state curState of scanning module 102 is 'e', ​​the index is 16, and storage control module 106 has saved the string "xyyyzw00000wwxyz" and its matching state "4555e10000011236".

[0069] like Figure 7 As shown, in the 32nd clock cycle, the literal data and predicted matching status referenced by the pointer given by the storage control module 106 are received, and the verification begins.

[0070] In the 33rd clock cycle, the verification module 104 reads the character 'x', combines 'x' with the matching state to form the second state address {'x', 1}, and reads the matching state from the deterministic finite state automaton 103.

[0071] In the 35th clock cycle, the deterministic finite state automaton 103 returns the matching state '2', which is compared with the predicted matching state '4'. Since they are not equal, the predicted matching state '4' is corrected to the actual matching state '2', and the verification continues.

[0072] In the 36th to 38th clock cycles, the verification module 104 verifies the character 'y', corrects the predicted matching state '5' to the actual matching state '3', and continues verification.

[0073] In the 39th to 41st clock cycles, the verification module 104 verifies the character 'y', compares the predicted matching state '5' with the actual matching state '5', and finds that they are equal. The verification is successful, and the data is written back to the verification data write-back area 1062 of the storage control module 106.

[0074] In the 63rd clock cycle, the result collection module 107 collects the state 'e' of the character 'z' with index 5 and writes it to the output queue 108.

[0075] During the 64th to 67th clock cycles, the result collection module 107 collects the states 'b', 'e', ​​'b', and 'e' at indices 8, 11, 15, and 16 respectively, and writes them into the output queue 108.

[0076] Specifically, after the scanning module 102 processes the pointer data <5, 6>, since the literal data "xyyyz" and its corresponding status "45556" corresponding to the pointer data <5, 6> are not copied, the storage control module 106 uses 0 to represent both the string and status of the pointer data <5, 6> as placeholders to prevent data misalignment. The copying and verification of the pointer data are implemented when the subsequent verification module 104 is working.

[0077] As can be seen from the above examples, the regular expression matching device based on FPGA-accelerated compressed data proposed in this invention can complete the matching of one literal data or one pointer data within two clock cycles.

[0078] (5) Performance evaluation To evaluate the throughput of this device when matching real network compressed data, we selected web pages crawled from the top 500 sites listed by Alex.com, Google search results pages, movie reviews from IMDb, and other datasets as scanning data. We also compiled the state transition tables into the regular expression rule sets Snort24, Snort31, and Snort34 from the well-known network intrusion detection system Snort. The features of the above datasets and rule sets are shown in Tables 2 and 3 below.

[0079] Table 2 Dataset Features

[0080] Table 3. Characteristics of Regular Expression Rule Sets

[0081] This invention provides an FPGA-based accelerated regular expression matching device for compressed data. To verify the technical superiority of this invention, its performance is compared with a baseline method in the prior art (hereinafter referred to as the "Baseline method"). The device is configured to directly process LZ77 encoded data streams after Huffman decoding, which consist of literal data units and pointer data units. We conducted experimental evaluations on a specific dataset, and statistically analyzed the number of clock cycles required for the device to process the LZ77 encoded data, the total number of data units processed, and the corresponding data size. The Baseline method follows a "complete decompression first, then matching" technical path, and its matching engine can only process the decompressed raw byte stream. To ensure the fairness of the evaluation, the overhead of the decompression process is not considered. Under these conditions, the Baseline method can achieve a throughput of one byte every two clock cycles at a clock frequency of 200MHz. In contrast, this invention adopts an innovative matching architecture that does not require complete decompression of the data. The matching engine of this invention can natively parse LZ77 data streams, treating literal and pointer data units as unified processing objects. At the same 200MHz clock frequency, this invention achieves high efficiency by processing one data unit (whether literal or pointer) every two clock cycles. Based on the principle of the LZ77 compression algorithm, the total number of data units in the compressed data stream is significantly less than the total number of original bytes after complete decompression. Therefore, this invention, by performing matching directly in the compressed domain, greatly reduces the total number of data units to be processed, thereby fundamentally reducing the total number of clock cycles required to process the same amount of original data, achieving a significant improvement in throughput. Furthermore, the hardware architecture of this invention has excellent scalability. By parallel instantiation on a single FPGA chip, the total system throughput can increase nearly linearly with the number of instances, while the processing latency of a single data unit remains constant at two clock cycles, ensuring low-latency response characteristics at high speeds.

[0082] Example 2 A regular expression matching method for accelerating compressed data based on FPGA, the workflow is as follows: Figure 4 As shown. Specifically, it includes the following steps: Step 1: Initialize the FPGA-accelerated compressed data regular expression matching device: clear all data storage space except for the input queue 101; initialize the storage content of the deterministic finite state automaton 103; set the matching state curState in the scanning module 102 to the initial value and the scanning index to 0; Step 2: Scanning module 102 determines whether input queue 101 is not empty. If input queue 101 is empty, the matching process is paused. Otherwise, the scanning module 102 reads a data unit from the input queue 101 and distinguishes between literals and pointers based on whether the length field of the data unit is 0. If the data unit is a literal, it jumps to step 3; otherwise, it jumps to step 4. Step 3: The scanning module 102 reads the literal data, concatenates the first state address, reads the matching state from the deterministic finite state automaton 103 based on the first state address and updates curState; then, curState and the literal data are appended to the storage control module 106, and the scan index is increased by 1; finally, jump to step 2. Step 4: The scanning module 102 reads the pointer data, reads the matching status of the last literal data referenced by the pointer data from the storage control module 106, and records the read content as the final predicted matching status of the pointer data; then it encapsulates the pointer data, the matching status curState, and the scan index and writes them into the pointer data queue 105; subsequently, curState is updated to the final predicted matching status, and the length field value in the pointer data is added to the scan index; finally, it jumps to steps 2 and 5 to be executed in parallel. Step 5: Verification module 104 checks whether pointer data queue 105 is empty. If pointer data queue 105 is empty, the verification process is paused; Otherwise, the verification module 104 reads a wrapping unit from the pointer data queue 105, assigns the matching state localState inside the verification module 104 to the matching state in the wrapping unit, assigns the verification index inside the verification module 104 to the index value of the wrapping unit, and simultaneously encapsulates the pointer data and scan index into a verification address. The verification address is used as the read address to read the literal data referenced by the pointer data and its matching state from the storage control module 106 as decompressed data and predicted matching state. Subsequently, starting from the first character of the decompressed data, the predicted matching state is verified one by one. If the actual matching state and the predicted matching state are different, the predicted matching state of the character is corrected. For each character verified, the verification index is incremented by 1. Step 6: After verification, write the decompressed data and the corrected prediction matching status back to the storage control module 106; once the decompressed data and the corrected prediction matching status are successfully written back, proceed to steps 5 and 7 for parallel execution. Step 7: The result collection module 107 reads the corrected prediction matching status data from the storage control module 106, traverses the corrected prediction matching status, and if there is an acceptance state, encapsulates the acceptance state and the corresponding index and writes it into the output queue 108.

[0083] Preferably, in step 3 above, the scanning module 102 combines the literal data and the matching state curState by bit concatenation to form a first state address, and reads the matching state from the deterministic finite state automaton 103 based on the first state address.

[0084] Preferably, in step 4 above, the scanning module 102 calculates the scanning acceleration address by scanning the distance field in the index and pointer data, and reads the matching status of the last literal data referenced by the pointer data from the scanning acceleration area 1064 of the storage control module 106 based on the accelerated scanning address. By using the matching status of the last literal data referenced as the final predicted matching status of the pointer data, the purpose of predicting the matching status is achieved, thereby realizing the function of quickly skipping the matching of pointer data.

[0085] Preferably, in step 5 above, the verification module 104 uses the index in the encapsulation unit as the address value, reads the literal data referenced by the pointer data and its matching state from the copy area 1061 of the storage control module 106 as decompression data and predicted matching state; then, starting from the first literal of the decompressed data, the verification module 104 combines the literal and the matching state localState inside the verification module 104 through bit concatenation to form the second state address, reads the actual matching state trueState from the deterministic finite state automaton 103, and compares trueState with the predicted matching state of the first literal: if they are not equal, the predicted matching state of the character is corrected, and the matching state of the next character is verified; if they are equal, the verification is completed, and the corrected predicted matching state and decompressed data are written back to the circular storage area 1065 through the verification data write-back area 1062 of the storage control module 106.

[0086] This invention provides an accelerated processing mechanism for pointer units in compressed data, thereby significantly improving matching throughput and greatly reducing latency without complete decompression. This method transforms the original step-by-step matching of long data sequences into a single, efficient calculation of pointers, fundamentally optimizing matching efficiency.

[0087] The above description is a further detailed explanation of the present invention in conjunction with specific preferred embodiments. It should not be considered that the specific embodiments of the present invention are limited to this. For those skilled in the art, several simple deductions or substitutions can be made without departing from the concept of the present invention, and all such deductions or substitutions should be considered to fall within the scope of patent protection determined by the submitted claims.

[0088] The term "constituting of" in describing a combination should include the identified elements, components, parts, or steps, as well as other elements, components, parts, or steps that do not substantially affect the essential novel features of the combination. The use of the terms "comprising" or "including" to describe combinations of elements, components, parts, or steps herein also contemplates embodiments that are essentially composed of such elements, components, parts, or steps. The use of the term "may" herein is intended to indicate that any described attribute included by "may" is optional.

[0089] Multiple elements, components, parts, or steps can be provided by a single integrated element, component, part, or step. Alternatively, a single integrated element, component, part, or step can be divided into multiple separate elements, components, parts, or steps. The use of "a" or "an" to describe an element, component, part, or step does not imply the exclusion of other elements, components, parts, or steps.

[0090] It should be understood that the above description is for illustrative purposes and not for limitation. Many embodiments and applications beyond the provided examples will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of this teaching should not be determined by reference to the above description, but rather by reference to the foregoing claims and the full scope of their equivalents. For purposes of completeness, all articles and references, including patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended as a waiver of that subject matter, nor should it be construed as an indication that the applicant has not considered that subject matter as part of the disclosed inventive subject matter.

Claims

1. A method for accelerating compressed data regular expression matching based on FPGA, characterized in that, Includes the following steps: Step 1: Clear all data storage space except for the input queue (101); initialize the storage content of the deterministic finite state automaton (103); set the matching state curState in the scanning module (102) to the initial value and the scanning index to 0; Step 2: The scanning module (102) determines whether the input queue (101) is not empty. If the input queue (101) is empty, the matching process is paused; Otherwise, the scanning module (102) reads a data unit from the input queue (101) and distinguishes between literals and pointers based on whether the length field of the data unit is 0; If the data unit is a literal, proceed to step 3; Otherwise, proceed to step 4; Step 3: The scanning module (102) reads the literal data, concatenates the first state address based on the literal data, reads the matching state of the literal data from the deterministic finite state automaton (103) based on the first state address and updates the matching state curState; then the matching state curState and the literal data are appended to the storage control module (106), the scanning index is increased by 1; jump to step 2; Step 4: The scanning module (102) reads the pointer data, reads the matching status of the last literal data referenced by the pointer data from the storage control module (106), records the read content as the final predicted matching status of the pointer data, and encapsulates the pointer data, matching status curState and scanning index to obtain an encapsulation unit, and writes the encapsulation unit into the pointer data queue (105); then curState is updated to the final predicted matching status, and the scanning index is incremented by the length field value in the pointer data; finally, it jumps to steps 2 and 5 to be executed in parallel. Step 5: The verification module (104) checks whether the pointer data queue (105) is empty. If the pointer data queue (105) is empty, the verification process is paused; Otherwise, the verification module (104) reads a packaged unit from the pointer data queue (105), assigns the matching state localState inside the verification module (104) to the matching state in the packaged unit, assigns the verification index inside the verification module (104) to the index value of the packaged unit, and packages the pointer data and scan index into a verification address. Based on the verification address, the literal data referenced by the pointer data and its matching state are read from the storage control module (106) as decompressed data and predicted matching state. Subsequently, the predicted matching state is verified one by one starting from the first character of the decompressed data. If the actual matching state and the predicted matching state are different, the predicted matching state of the character is corrected. The verification index is increased by 1 for each character verified. Step 6: Write the decompressed data and the corrected prediction matching status back to the storage control module (106); after the decompressed data and the corrected prediction matching status are successfully written back, jump to steps 5 and 7 to be executed in parallel; Step 7: The result collection module (107) reads the status data from the storage control module (106), traverses the status data to obtain the acceptance status and writes it into the output queue (108).

2. The FPGA-based accelerated compressed data regular expression matching method according to claim 1, characterized in that, In step 3, the scanning module (102) combines the literal data and the matching state curState into a first state address by bit concatenation, and reads the matching state from the deterministic finite state automaton (103) based on the first state address.

3. The FPGA-based accelerated compressed data regular expression matching method according to claim 1, characterized in that, In step 4, the scanning module (102) calculates the scanning address by scanning the distance field in the index and pointer data. Based on the scanning address, it reads the matching status of the last literal data referenced by the pointer data from the scanning acceleration area (1064) of the storage control module (106). By using the matching status of the last literal data referenced as the final predicted matching status of the pointer data, the purpose of predicting the matching status is achieved, thereby realizing the function of quickly skipping the matching of pointer data.

4. The FPGA-based accelerated compressed data regular expression matching method according to claim 1, characterized in that, In step 5, the verification module (104) uses the index in the encapsulation unit as the verification address. Based on the verification address, it reads the literal data referenced by the pointer data and its matching state from the copy area (1061) of the storage control module (106) as decompression data and predicted matching state. Then, it starts the verification from the first literal of the decompression data. The literal and the matching state localState inside the verification module (104) are combined by bit concatenation to form the second state address. Based on the second state address, the actual matching state trueState is read from the deterministic finite state automaton (103). The trueState is compared with the predicted matching state of the first literal. If they are not equal, the predicted matching state of the character is corrected and the matching state of the next character is verified. If they are equal, the verification is completed. The corrected predicted matching state and the decompression data are written back through the verification data write-back area (1062) of the storage control module (106).

5. The FPGA-based accelerated compressed data regular expression matching method according to claim 1, characterized in that, In step 5, reading the literal data referenced by the pointer data and its matching status from the storage control module (106) as decompression data and predicted matching status includes: the verification module (104) calculates the scan acceleration address through the index in the encapsulation unit and the distance field in the pointer data, and reads the decompression data and its predicted matching status from the storage control module (106) based on the scan acceleration address.

6. A regular expression matching device for accelerated compressed data based on FPGA, characterized in that, It includes an input queue (101), a scanning module (102), a deterministic finite state automaton (103), a verification module (104), a pointer data queue (105), a storage control module (106), a result collection module (107), and an output queue (108). The input queue (101) is used to store input data written from outside the device, including literal data and pointer data; The scanning module (102) is used to read the final matching status of input data, matching literal data and prediction pointer data from the input queue (101); A deterministic finite state automaton (103) is used to store the matching states of the deterministic finite state automaton compiled from the regular expression rule set; The verification module (104) is used to verify the predicted matching status of the pointer data and correct erroneous predicted matching status. The pointer data queue (105) is used to store the pointer data to be verified and related information written by the scanning module (102); The storage control module (106) is used to store the scanning history literal data of the scanning module (102), the prediction of the final matching state when the scanning module (102) encounters pointer data, the write-back after the verification module (104) has completed the verification, the actual state required by the result collection module (107), and to control the reading and writing of the BRAM. The result collection module (107) is used to traverse the status data read from the storage control module (106) and write the received status into the output queue (108); The output queue (108) is used to temporarily store the status and position of a successful match.

7. The FPGA-based accelerated compressed data regular expression matching device according to claim 6, characterized in that, The deterministic finite state automaton (103) is constructed using a dual-port BROM IP core instance, connected to the scanning module (102) via the address bus and data bus, and connected to the verification module (104) via the address bus and data bus, outputting the matching status of literal data to the scanning module (102) and the verification module (104).

8. The FPGA-based accelerated compressed data regular expression matching device according to claim 6, characterized in that, The input queue (101), pointer data queue (105), and output queue (108) are constructed using a FIFO IP core instance. The input queue (101) is connected to the scanning module (102) via the address bus and data bus. The pointer data queue (105) is connected to the scanning module (102) via the address bus and data bus, and to the verification module (104) via the address bus and data bus. The output queue (108) is connected to the result collection module (107) via the address bus and data bus.

9. The FPGA-based accelerated compressed data regular expression matching device according to claim 6, characterized in that, The storage control module (106) includes a copy area (1061), a verification data write-back area (1062), a priority arbitration area (1063), a scan acceleration area (1064), and a ring storage area (1065). The copy area (1061) is used to read the verification address of the verification module (104) as the copy address, and to read the literal data referenced by the pointer data of the ring storage area (1065) and its matching status as the verification data. The verification data write-back area (1062) is used to read the literal data and corresponding status after the verification module (104) has completed verification and write it back to the circular storage area (1065). The priority arbitration area (1063) is used to control the read and write operations of the copy area (1061), the verification data write-back area (1062), and the scan acceleration area (1064) in the storage control module (106) on the ring storage area (1065); The scanning acceleration area (1064) is used to read the address when the scanning module (102) encounters pointer data as the scanning acceleration address, and read the ring storage area (1065) to obtain the matching status of the last literal data referenced by the pointer data and return it to the scanning module (102). The ring-shaped storage area (1065) is used to respond to read, write and copy requests via the read / write control bus, address bus and data bus connected to the priority arbitration area (1063).

10. The FPGA-based accelerated compressed data regular expression matching device according to claim 9, characterized in that, The ring-shaped storage area (1065) is constructed using a dual-port BRAM IP core instance.

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