High-speed acquisition, transmission, storage and calculation method for radar processing array data

Abstract

The invention relates to the technical field of data access, discloses a high-speed acquisition, transmission, storage and calculation method for radar processing array data, and solves the problems of transmission bandwidth bottleneck, high data delay and poor system expansibility in a radar front-end data access link through a software architecture and a distributed processing mechanism. Specifically, the FPGA preprocessing capability, the high-speed network transmission technology and the dynamic resource management strategy are utilized, deep integration of data acquisition, transmission, storage and processing links is achieved, and the overhead caused by deep participation of a CPU in protocol stack analysis and multiple data copying in a traditional scheme is avoided. Meanwhile, the capacity of the system for adapting to a large-scale array is improved through elastic resource scheduling, and therefore the limitation of the prior art in the aspects of bandwidth capacity, delay control and hardware expansibility is broken through.

Description

Technical Field

[0001] This invention relates to the field of data access technology, specifically to a high-speed method for acquiring, transmitting, storing, and calculating radar processing array data. Background Technology

[0002] As the data channel connecting the array antenna elements and the signal processing platform, the radar front-end data access link directly affects the overall performance of the radar system, including its transmission bandwidth, data latency, and system scalability. With the continuous expansion of radar array size and the constant improvement of data acquisition accuracy, the front-end access link has become a key factor restricting the system's processing capacity.

[0003] Currently widely used radar data access solutions have revealed several limitations in practical engineering. At the data transmission level, existing systems mostly use traditional Ethernet as the primary transmission medium, whose bandwidth capacity is insufficient to meet the high-speed data flow demands of large-scale arrays, easily creating transmission bottlenecks when multiple channels operate simultaneously. In the data processing stage, traditional architectures require the central processing unit (CPU) to be deeply involved in parsing the network protocol stack and processing data packets, while also requiring multiple data copy operations between different areas of system memory. This not only consumes significant processor computing resources but also leads to a substantial increase in data transmission latency. Regarding hardware platforms, existing solutions mostly rely on customized dedicated processing equipment. While these devices are optimized for specific application scenarios, they suffer from high hardware costs, long upgrade cycles, and poor compatibility with general-purpose computing platforms. When the system needs to increase processing capacity or adjust functional configurations, it often requires replacing or adding dedicated hardware modules, significantly limiting flexibility.

[0004] Therefore, we propose a high-speed acquisition, transmission, storage, and computation method for radar array data to address the aforementioned problems. Summary of the Invention

[0005] The purpose of this invention is to provide a high-speed acquisition, transmission, storage, and calculation method for radar processing array data, in order to solve the problem mentioned in the background art that, at the data transmission level, existing systems mostly use traditional Ethernet as the main transmission medium, whose bandwidth capacity is difficult to meet the high-speed data flow requirements generated by large-scale arrays, and which easily forms a transmission bottleneck when multiple channels are working simultaneously.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for high-speed acquisition, transmission, storage, and calculation of radar processing array data, characterized by the following specific steps:

[0007] S1. Data Acquisition: The FPGA module is used to acquire raw data from the radar array, perform timing alignment, data format conversion and signal denoising operations, cache the processed data according to a predetermined format, and add a timestamp and metadata identifier to each data packet;

[0008] S2, Data Channel Mapping: Maps the data from each radar channel to the logic processing unit, performs time alignment and phase compensation operations on the multi-channel data, and eliminates deviations caused by hardware delays;

[0009] S3. Data Blocking: Divide the continuous data stream into data blocks of fixed length, add an identifier and metadata to each data block, and transmit the data blocks to the subsequent processing unit through a preset distribution strategy;

[0010] S4. High-speed data transmission configuration: Configure InfiniBand network to connect the FPGA and the server array, and use RDMA technology to directly transmit data from the FPGA storage area to the server memory, bypassing the traditional transmission path involving the CPU;

[0011] S5. Distributed data storage: The received data is distributed and stored in a server array, using a ring buffer management method, and the buffer size is dynamically adjusted according to the system load;

[0012] S6. Data Synchronization: Perform time synchronization operation on data from multiple processing nodes, and dynamically allocate computing tasks to the corresponding nodes based on load monitoring results;

[0013] S7. Radar signal processing algorithm execution: The radar signal processing algorithm runs on a distributed server array, and the number of server nodes participating in the calculation is dynamically adjusted according to data traffic requirements.

[0014] S8. Calculation Result Aggregation: Collect the processing results output by each computing node, perform data merging and target recognition operations, and output the final results to the system display or decision module;

[0015] S9. System Performance Monitoring: Real-time collection of system operating parameters, including data transmission rate, node load, and processing latency, and adjustment of system configuration parameters based on monitoring data.

[0016] Preferably, in step S1, the data acquisition method is as follows:

[0017] S1.1 The raw echo data output from each channel of the radar array is received through the field programmable gate array module. The time alignment of the multi-channel data is performed through the delay compensation circuit to eliminate the time deviation between channels. The analog signal is converted into a digital signal by the analog-to-digital converter and the data format is unified. The out-of-band interference and random noise are filtered out by the digital filter.

[0018] S1.2 Write the processed data into a high-speed buffer according to a predetermined structure, generate a timestamp for each data packet and write it into the data packet header, and write metadata information, including channel number, data length, sampling rate and data block sequence number.

[0019] Preferably, in step S2, the data channel mapping is specifically performed as follows:

[0020] S2.1 Establish a mapping table between physical channels and logical processing units. The mapping table records the correspondence between physical channel numbers and logical processing unit addresses. Based on the mapping table, route the data of each radar channel to the designated logical processing unit, obtain the hardware transmission delay parameters and phase characteristic parameters of each channel, and store them in the parameter register.

[0021] S2.2 Read the hardware transmission delay parameters from the parameter register, apply the time delay to the data of each channel through the delay adjustment circuit, read the phase characteristic parameters from the parameter register, and apply the phase compensation to the data of each channel through the phase correction unit.

[0022] Preferably, in step S3, the data blockization is specifically implemented as follows:

[0023] S3.1. Divide the continuous data stream into multiple data blocks according to the preset fixed length threshold, assign an incrementing sequence number as an identifier to each data block, and write identification information and metadata information in the header of the data block. The identification information includes the data block sequence number and byte length, and the metadata information includes the start timestamp, channel source number, data type identifier and check code.

[0024] S3.2 Determine the target processing unit address for each data block according to the preset distribution strategy. The distribution strategy is based on the round-robin scheduling algorithm or the weighted load balancing algorithm, combined with the load parameters of the processing unit and the available space parameters of the buffer. Transmit the data block to the target processing unit through the high-speed data bus and update the transmission queue status table.

[0025] Preferably, in step S4, the high-speed data transmission configuration is specifically as follows:

[0026] S4.1 Configure the unlimited bandwidth network adapter to establish the physical connection between the field-programmable gate array module and the server array. Set the working parameters through the driver, including data transmission rate, queue depth, buffer size and transmission priority. Establish a network topology mapping table. The mapping table records the network identifier, communication port number and connection status flag of the server node.

[0027] S4.2 Load the Remote Direct Memory Access Protocol stack in the Field Programmable Gate Array (FPGA) module and the server array. Register the physical address and access permissions of the data storage area on the FPGA side and register the physical address and write permissions of the target memory area on the server side. Establish a memory address mapping table, configure the transmission channel parameters, and have the network adapter's built-in engine read the data and write it to the server memory.

[0028] Preferably, in step S5, the distributed data storage is implemented in the following specific manner:

[0029] S5.1 Obtain the storage capacity parameters and network topology parameters of each node in the server array, determine the data distribution strategy based on the parameters, and use the consistent hashing algorithm or weighted round-robin algorithm to allocate data blocks to the corresponding node storage space. Allocate a continuous physical address space in the memory area of ​​each node to establish a circular buffer, including the data storage area, read / write pointer register and status flag register, and set the pointer initial value and wraparound condition.

[0030] S5.2. Periodically collect load parameters of each node through the system monitoring interface, including processor utilization, memory usage, buffer fill rate and data processing rate. Calculate the buffer adjustment coefficient based on the load parameters using the adjustment strategy function. Compare the fill rate with a preset threshold. If it exceeds the upper limit, request additional physical address space and migrate data. If it is below the lower limit, release the excess space and update the address parameters and wraparound boundary values.

[0031] Preferably, in step S6, the data synchronization is performed in the following specific manner:

[0032] S6.1 Select one node in the server array as the time reference node, and set the remaining nodes as slave nodes. The time reference node periodically generates time synchronization messages and broadcasts them to each slave node. The message contains a reference timestamp field, a sequence number field, and a checksum field. After receiving the message, each slave node calculates the time deviation, corrects the local clock count value through the clock adjustment interface, corrects the timestamp of the data block, and sorts them in chronological order.

[0033] S6.2. Periodically collect load status parameters of each node through system call interface, including task queue length, processor idle rate, available memory capacity and task completion rate. Calculate load weight value based on parameters and preset weight coefficient, establish priority queue to arrange nodes in order of weight value from low to high, retrieve tasks from task pool and allocate them to target nodes in priority queue order, send task information through network interface and update task queue status table.

[0034] Preferably, in step S7, the radar signal processing algorithm is executed in the following specific manner:

[0035] S7.1 Load the radar signal processing algorithm program on each computing node of the distributed server array, including pulse compression module, moving target detection module, constant false alarm rate processing module and target tracking module. Each node retrieves data blocks from the task queue, reads the header metadata to determine the processing flow, calls the modules in sequence for processing, stores intermediate results in the local cache, and writes the final results and metadata to the output buffer.

[0036] S7.2. Collect data traffic parameters periodically through the system monitoring interface, including the amount of data received, the length of the queue to be processed, the average latency and the node saturation. Calculate the system load index based on the parameters using the load evaluation function. Compare the load index with a preset threshold. If the load index exceeds the expansion threshold, select a node from the standby pool to add to the calculation set and distribute the algorithm program. If the load index is below the contraction threshold, remove the node with the lowest load and reclaim its resources. Update the node configuration table.

[0037] Preferably, in step S8, the specific method for aggregating the calculation results is as follows:

[0038] S8.1 Set up a result aggregation node in the distributed server array, and read the processing result data packets from the output buffer of each computing node through the network communication interface. The data packets contain radar signal data and metadata information. The metadata includes result type identifier, timestamp, channel number and sequence number. Store the data packets in a temporary area and sort them by sequence number. Create an index table to record the storage address and metadata. Group and merge the data according to the type identifier. The merging operation includes data splicing, deduplication and format unification. Write the aggregated result data into the result buffer.

[0039] S8.2 Read aggregated data from the result aggregation buffer, load the target recognition algorithm module for recognition processing. The module includes a feature extraction unit, a pattern matching unit, and a target classification unit. The feature extraction unit extracts the target position, velocity, scattering cross-section, and azimuth and elevation angles. The pattern matching unit reads templates from the target feature library and calculates similarity using Euclidean distance or cosine similarity algorithms. The target classification unit determines the target type and confidence level, and generates a result report containing the number, type, position, and velocity parameters of the targets. The report is then transmitted to the display module or decision module through the data output interface.

[0040] Preferably, in step S9, the system performance monitoring is performed in the following specific way:

[0041] S9.1 Deploy performance monitoring agents on each node of the distributed server array. Read running status parameters at preset intervals through system call interfaces, including data transmission rate, network bandwidth utilization, processor load, memory utilization, buffer utilization, and task latency. Encapsulate the collected parameters into monitoring data packets in a predefined format, including node identifier, parameter type, value, timestamp, and sequence number. Transmit the data packets to the central monitoring node through the network interface and store them in the performance database.

[0042] S9.2 Read historical and real-time running parameter data from the performance database, calculate the average, peak, standard deviation and trend of each parameter, compare the current value with the normal range threshold in the configuration library, and calculate the configuration adjustment amount according to the parameter type, deviation and historical characteristics through the adjustment strategy function when the threshold is exceeded. Generate an adjustment instruction containing the target node identifier, parameter type and adjustment value, send it to the target node through the configuration interface and modify the configuration parameters, and record the adjustment operation to the system log.

[0043] Compared with the prior art, the beneficial effects of the present invention are:

[0044] 1. By employing a software-based architecture and distributed processing mechanism, the bottlenecks in transmission bandwidth, high data latency, and poor system scalability in the radar front-end data access link are resolved. Specifically, by utilizing FPGA preprocessing capabilities, high-speed network transmission technology, and dynamic resource management strategies, deep integration of data acquisition, transmission, storage, and processing is achieved, avoiding the overhead caused by deep CPU involvement in protocol stack parsing and multiple data copies in traditional solutions. Simultaneously, elastic resource scheduling enhances the system's adaptability to large-scale arrays, thereby overcoming the limitations of existing technologies in terms of bandwidth capacity, latency control, and hardware scalability.

[0045] 2. By directly receiving raw echo data through a field-programmable gate array (FPGA) module, deep involvement of the central processing unit (CPU) is avoided, effectively reducing data transmission latency and system resource consumption. During data processing, a delay compensation circuit first performs precise timing alignment on the multi-channel data, ensuring strict synchronization of data across all channels in the time dimension. Subsequently, an analog-to-digital converter (ADC) converts the analog signal into a unified digital format, resolving parsing issues caused by format inconsistencies. Digital filters are used to selectively remove out-of-band interference and random noise, significantly improving the signal-to-noise ratio. The processed data is stored in a high-speed cache according to a predetermined structure, and a timestamp and metadata information are added to each data packet, including channel number, data length, sampling rate, and data block sequence number. This provides complete contextual information for subsequent data management and distribution. These steps not only solve key problems in multi-channel radar data acquisition but also achieve precise control and efficient management of the data acquisition process through the organic integration of various processing stages, thereby improving the overall accuracy, reliability, and real-time performance of radar data processing. Attached Figure Description

[0046] Figure 1 This is a diagram illustrating the method steps of the present invention. Detailed Implementation

[0047] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0048] Example 1: Please refer to Figure 1 A high-speed acquisition, transmission, storage, and calculation method for radar array data, characterized by the following specific steps:

[0049] S1. Data Acquisition: The FPGA module is used to acquire raw data from the radar array, perform timing alignment, data format conversion and signal denoising operations, cache the processed data according to a predetermined format, and add a timestamp and metadata identifier to each data packet;

[0050] S2, Data Channel Mapping: Maps the data from each radar channel to the logic processing unit, performs time alignment and phase compensation operations on the multi-channel data, and eliminates deviations caused by hardware delays;

[0051] S3. Data Blocking: Divide the continuous data stream into data blocks of fixed length, add an identifier and metadata to each data block, and transmit the data blocks to the subsequent processing unit through a preset distribution strategy;

[0052] S4. High-speed data transmission configuration: Configure InfiniBand network to connect the FPGA and the server array, and use RDMA technology to directly transmit data from the FPGA storage area to the server memory, bypassing the traditional transmission path involving the CPU;

[0053] S5. Distributed data storage: The received data is distributed and stored in a server array, using a ring buffer management method, and the buffer size is dynamically adjusted according to the system load;

[0054] S6. Data Synchronization: Perform time synchronization operation on data from multiple processing nodes, and dynamically allocate computing tasks to the corresponding nodes based on load monitoring results;

[0055] S7. Radar signal processing algorithm execution: The radar signal processing algorithm runs on a distributed server array, and the number of server nodes participating in the calculation is dynamically adjusted according to data traffic requirements.

[0056] S8. Calculation Result Aggregation: Collect the processing results output by each computing node, perform data merging and target recognition operations, and output the final results to the system display or decision module;

[0057] S9. System Performance Monitoring: Real-time collection of system operating parameters, including data transmission rate, node load, and processing latency, and adjustment of system configuration parameters based on monitoring data.

[0058] In this embodiment, a software-based architecture and distributed processing mechanism address the bottlenecks in transmission bandwidth, high data latency, and poor system scalability in the radar front-end data access link. Specifically, by utilizing FPGA preprocessing capabilities, high-speed network transmission technology, and dynamic resource management strategies, deep integration of data acquisition, transmission, storage, and processing is achieved, avoiding the overhead caused by deep CPU involvement in protocol stack parsing and multiple data copies in traditional solutions. Simultaneously, elastic resource scheduling enhances the system's adaptability to large-scale arrays, thereby overcoming the limitations of existing technologies in terms of bandwidth capacity, latency control, and hardware scalability.

[0059] By employing a software-based architecture and distributed processing mechanism, an end-to-end optimization solution was constructed to address the bottlenecks in transmission bandwidth, high data latency, and poor system scalability in the radar front-end data access link. Specifically, by leveraging FPGA preprocessing capabilities, high-speed network transmission technology, and dynamic resource management strategies, the data acquisition, transmission, storage, and processing stages are deeply integrated. This avoids the overhead caused by deep CPU involvement in protocol stack parsing and multiple data copies in traditional solutions. Furthermore, elastic resource scheduling enhances the system's ability to adapt to large-scale arrays.

[0060] During the data acquisition phase, preprocessed radar data is transmitted at high speed via the InfiniBand (IB) network. InfiniBand, a high-performance computer networking technology, is designed for applications with extremely high bandwidth and latency requirements. In this method, the InfiniBand network acts as a data highway, seamlessly transmitting the FPGA-preprocessed data to the backend server array. The FPGA module directly acquires raw data from the radar array and performs timing alignment, data format conversion, and signal denoising operations. This real-time preprocessing based on the raw echo characteristics output by the radar array avoids the latency accumulation of directly processing raw data by the CPU, thus ensuring data quality at the source and freeing up CPU resources. Furthermore, the processed data is cached according to a predetermined format and timestamped and marked with metadata identifiers. This marking is based on the physical channel status and time information at the time of data packet generation, providing a precise synchronization basis for subsequent multi-node collaborative processing.

[0061] During the data channel mapping stage, data from each radar channel is mapped to the logic processing unit, and time alignment and phase compensation operations are performed. This dynamically corrects deviations based on hardware transmission delay parameters and phase characteristic parameters, ensuring the consistency of multi-channel data at the logical level and solving the signal distortion problem caused by inherent hardware delays. Specifically, a mapping table between physical channels and logic processing units is established, and precise correction is achieved by combining delay adjustment circuits and phase correction units.

[0062] During the data blockization stage, the continuous data stream is divided into data blocks of fixed length and an identifier and metadata are added. This is based on a preset fixed length threshold to structurally segment the data stream, which facilitates subsequent parallel processing and error detection. The data blocks are transmitted to the subsequent processing units through a preset distribution strategy. This combines the load parameters of the processing unit and the available space in the buffer to dynamically select the target address, which optimizes the data distribution efficiency and avoids overload of a single node.

[0063] During the high-speed data transmission configuration phase, the InfiniBand network is configured to connect the FPGA and the server array, and RDMA technology is used to directly transmit data from the FPGA storage area to the server memory. This establishes a direct connection channel based on the physical address and access permissions registered on the FPGA side, bypassing the traditional transmission path involving the CPU, significantly reducing protocol stack parsing overhead and memory copying times, thereby breaking through the bandwidth limitations of traditional Ethernet.

[0064] In the distributed data storage phase, the received data is distributed and stored in the server array and managed using a ring buffer. This dynamically adjusts the buffer size according to the system load and calculates the adjustment coefficient in real time based on the processor utilization and buffer fill rate, so that the storage resources can adapt flexibly to traffic fluctuations and avoid resource waste or overflow caused by fixed buffers.

[0065] During the data synchronization phase, time synchronization operations are performed on the data of multiple processing nodes, and computing tasks are dynamically allocated based on load monitoring results. This is done by correcting the local clock based on the synchronization message generated by the time reference node, ensuring the time sequence consistency of data across nodes. At the same time, the load weight value is calculated based on the task queue length and processor idle rate to achieve intelligent task allocation and improve the utilization of computing resources.

[0066] During the radar signal processing algorithm execution phase, the radar signal processing algorithm runs on a distributed server array and dynamically adjusts the number of server nodes participating in the calculation according to the data traffic demand. This is based on the received data volume and node saturation to evaluate the system load index and trigger the elastic expansion or contraction of nodes, so that the processing capacity is accurately matched with the real-time traffic demand, solving the problem of insufficient scalability of dedicated hardware.

[0067] During the result aggregation phase, the processing results output by each computing node are collected and data merging and target identification operations are performed. This grouping and merging of data packets according to the result type identifier and sequence number ensures the complete integration of multi-node outputs. The final result is then output to the system display or decision module, completing the closed-loop transformation from raw data to usable information.

[0068] During the system performance monitoring phase, system operating parameters are collected in real time, and system configuration parameters are adjusted based on the monitoring data. This involves calculating the configuration adjustment amount based on the changing trends of historical and real-time parameters, achieving adaptive optimization of the system configuration and maintaining stable and efficient overall performance. Thus, the entire technical solution, through close cooperation among all components, effectively solves key issues in the radar front-end data access link.

[0069] Example 2: Please refer to Figure 1 In step S1, the data acquisition method is as follows:

[0070] S1.1 The raw echo data output from each channel of the radar array is received through the field programmable gate array module. The time alignment of the multi-channel data is performed through the delay compensation circuit to eliminate the time deviation between channels. The analog signal is converted into a digital signal by the analog-to-digital converter and the data format is unified. The out-of-band interference and random noise are filtered out by the digital filter.

[0071] S1.2 Write the processed data into a high-speed buffer according to a predetermined structure, generate a timestamp for each data packet and write it into the data packet header, and write metadata information, including channel number, data length, sampling rate and data block sequence number.

[0072] In this embodiment, the raw echo data is directly received via a field-programmable gate array (FPGA) module, avoiding deep involvement of the central processing unit (CPU) and effectively reducing data transmission latency and system resource consumption. During data processing, a delay compensation circuit first performs precise timing alignment on the multi-channel data, ensuring strict synchronization of data across all channels in the time dimension. Subsequently, an analog-to-digital converter (ADC) converts the analog signal into a unified digital format, resolving parsing issues caused by format inconsistencies. Digital filters are used to selectively remove out-of-band interference and random noise, significantly improving the signal-to-noise ratio. The processed data is stored in a high-speed cache according to a predetermined structure, and a timestamp and metadata information are added to each data packet, including channel number, data length, sampling rate, and data block sequence number. This provides complete contextual information for subsequent data management and distribution. These steps not only solve key problems in multi-channel radar data acquisition but also achieve precise control and efficient management of the data acquisition process through the organic combination of various processing stages, thereby improving the overall accuracy, reliability, and real-time performance of radar data processing.

[0073] Example 3: Please refer to Figure 1 In step S2, the data channel mapping is specifically performed as follows:

[0074] S2.1 Establish a mapping table between physical channels and logical processing units. The mapping table records the correspondence between physical channel numbers and logical processing unit addresses. Based on the mapping table, route the data of each radar channel to the designated logical processing unit, obtain the hardware transmission delay parameters and phase characteristic parameters of each channel, and store them in the parameter register.

[0075] S2.2 Read the hardware transmission delay parameters from the parameter register, apply the time delay to the data of each channel through the delay adjustment circuit, read the phase characteristic parameters from the parameter register, and apply the phase compensation to the data of each channel through the phase correction unit.

[0076] In this embodiment, by establishing a mapping table between physical channels and logical processing units, directional transmission of data streams is achieved. This process not only reduces routing decision time but also avoids additional delays and resource conflicts caused by random allocation. Subsequently, the system acquires the hardware transmission delay parameters and phase characteristic parameters of each channel through real-time measurement and stores them in a parameter register. This dynamic acquisition mechanism accurately reflects changes in hardware status, providing a reliable basis for subsequent compensation. Based on this, the delay adjustment circuit applies a precise time delay to the data of each channel according to the hardware transmission delay parameters in the parameter register, thereby effectively eliminating timing deviations caused by differences in hardware transmission paths. Simultaneously, the phase correction unit applies phase compensation to the data of each channel based on the actually measured phase characteristic parameters, ensuring the phase consistency of multi-channel signals and avoiding signal distortion caused by phase mismatch. Overall, this scheme significantly improves the accuracy of time alignment and phase compensation through a collaborative mechanism of dynamic parameter acquisition, centralized storage, and hardware-level compensation, laying the foundation for the real-time performance and accuracy of radar signal processing.

[0077] Example 4: Please refer to Figure 1 In step S3, the specific method of data blockization is as follows:

[0078] S3.1. Divide the continuous data stream into multiple data blocks according to the preset fixed length threshold, assign an incrementing sequence number as an identifier to each data block, and write identification information and metadata information in the header of the data block. The identification information includes the data block sequence number and byte length, and the metadata information includes the start timestamp, channel source number, data type identifier and check code.

[0079] S3.2 Determine the target processing unit address for each data block according to the preset distribution strategy. The distribution strategy is based on the round-robin scheduling algorithm or the weighted load balancing algorithm, combined with the load parameters of the processing unit and the available space parameters of the buffer. Transmit the data block to the target processing unit through the high-speed data bus and update the transmission queue status table.

[0080] In this embodiment, a refined data block segmentation and distribution mechanism effectively addresses the load balancing challenges in data transmission. In the data stream segmentation stage, a fixed length threshold ensures standardized data block sizes, incremental sequence numbers maintain data temporal continuity, and identification and metadata information provide crucial contextual support for subsequent processing. In the data distribution stage, the distribution strategy dynamically responds to system load changes, a high-speed data bus improves data flow efficiency, and a transmission queue status table ensures stable system operation under dynamic loads. These technical features work together to solve the problem of uneven data distribution and prevent node overload or resource idleness.

[0081] This system forms an organic whole with the aforementioned data acquisition and data channel mapping steps. For example, the data blocks, after being divided into chunks, are transmitted to the target processing unit through a distribution strategy. This process relies on the mapping table and hardware parameter configuration established in the previous steps, thereby further optimizing the overall performance of the system. Simultaneously, the data block design provides standardized data input for subsequent distributed data storage and data synchronization, enhancing the system's scalability and adaptability. Through the above technical solutions, high efficiency and stability in data transmission are achieved, significantly improving the overall performance of the radar processing array.

[0082] Example 5: Please refer to Figure 1 In step S4, the high-speed data transmission configuration is specifically as follows:

[0083] S4.1 Configure the unlimited bandwidth network adapter to establish the physical connection between the field-programmable gate array module and the server array. Set the working parameters through the driver, including data transmission rate, queue depth, buffer size and transmission priority. Establish a network topology mapping table. The mapping table records the network identifier, communication port number and connection status flag of the server node.

[0084] S4.2 Load the Remote Direct Memory Access Protocol stack in the Field Programmable Gate Array (FPGA) module and the server array. Register the physical address and access permissions of the data storage area on the FPGA side and register the physical address and write permissions of the target memory area on the server side. Establish a memory address mapping table, configure the transmission channel parameters, and have the network adapter's built-in engine read the data and write it to the server memory.

[0085] In this embodiment, the problems of limited bandwidth, high latency, and high CPU resource consumption under traditional transmission methods are effectively solved by constructing a high-speed data transmission channel. First, a physical connection is established by configuring an unlimited bandwidth network adapter, and operating parameters such as data transmission rate and queue depth are set. This not only ensures high bandwidth and low latency characteristics during transmission but also avoids the bottleneck problem of traditional Ethernet under multi-channel data flow. Simultaneously, a network topology mapping table is established to record the network identifier, communication port number, and connection status flag of the server nodes. Based on this mapping table, the node connection status is dynamically managed, thereby achieving precise scheduling of data transmission paths and rapid fault recovery, significantly improving the overall system transmission efficiency. Second, a remote direct memory access protocol stack is loaded into the field-programmable gate array module and the server array. By registering the physical address and access permissions of the data storage area, a memory address mapping table is established, and transmission channel parameters are configured. The network adapter's built-in engine automatically completes data reading and writing operations. This not only bypasses the central processing unit's parsing of the network protocol stack and data copying operations, avoiding excessive CPU resource consumption, but also significantly reduces transmission latency, ensuring the real-time processing capability of high-speed data streams.

[0086] By combining dedicated network configuration and direct memory access mechanisms, data transmission is decoupled from CPU intervention, providing a low-latency, high-bandwidth data access foundation for subsequent distributed processing. Furthermore, by integrating the aforementioned data blockization scheme with high-speed data transmission configuration, data distribution and transmission efficiency are further optimized, thus laying a solid technical foundation for the high-performance operation of the entire system.

[0087] Example 6: Please refer to Figure 1 In step S5, the specific method of distributed data storage is as follows:

[0088] S5.1 Obtain the storage capacity parameters and network topology parameters of each node in the server array, determine the data distribution strategy based on the parameters, and use the consistent hashing algorithm or weighted round-robin algorithm to allocate data blocks to the corresponding node storage space. Allocate a continuous physical address space in the memory area of ​​each node to establish a circular buffer, including the data storage area, read / write pointer register and status flag register, and set the pointer initial value and wraparound condition.

[0089] S5.2. Periodically collect load parameters of each node through the system monitoring interface, including processor utilization, memory usage, buffer fill rate and data processing rate. Calculate the buffer adjustment coefficient based on the load parameters using the adjustment strategy function. Compare the fill rate with a preset threshold. If it exceeds the upper limit, request additional physical address space and migrate data. If it is below the lower limit, release the excess space and update the address parameters and wraparound boundary values.

[0090] In this embodiment, by acquiring the storage capacity parameters and network topology parameters of each node in the server array, and combining them with a consistent hashing algorithm or a weighted round-robin algorithm to determine the data distribution strategy, this intelligent allocation method based on actual node parameters effectively solves the problem of uneven data distribution. Simultaneously, a circular buffer is established by allocating contiguous physical address space in the memory region of each node, and managed through read / write pointer registers and status flag registers. This design not only reduces memory fragmentation but also avoids the latency caused by multiple data copying in traditional buffer management. Furthermore, the load parameters of each node are periodically collected through the system monitoring interface, and the buffer adjustment coefficient is calculated using an adjustment strategy function. The buffer size is dynamically adjusted based on the comparison between the fill rate and a preset threshold. This mechanism can automatically adapt to changes in system load, avoiding the risk of overflow or resource idleness caused by a fixed size. In addition, the entire process reduces the involvement of the central processing unit through direct memory operations, significantly reducing system latency and maintaining the real-time performance and stability of data processing. Through its organic combination with the aforementioned data access method, stable and efficient operation under high load scenarios is achieved, improving resource utilization.

[0091] Example 7: Please refer to Figure 1 In step S6, the data synchronization is performed in the following specific manner:

[0092] S6.1 Select one node in the server array as the time reference node, and set the remaining nodes as slave nodes. The time reference node periodically generates time synchronization messages and broadcasts them to each slave node. The message contains a reference timestamp field, a sequence number field, and a checksum field. After receiving the message, each slave node calculates the time deviation, corrects the local clock count value through the clock adjustment interface, corrects the timestamp of the data block, and sorts them in chronological order.

[0093] S6.2. Periodically collect load status parameters of each node through system call interface, including task queue length, processor idle rate, available memory capacity and task completion rate. Calculate load weight value based on parameters and preset weight coefficient, establish priority queue to arrange nodes in order of weight value from low to high, retrieve tasks from task pool and allocate them to target nodes in priority queue order, send task information through network interface and update task queue status table.

[0094] In this embodiment, by deploying modular radar signal processing algorithms in a distributed server array, the signal processing flow is standardized and decomposed, facilitating parallel execution on multiple nodes. Each node dynamically selects its processing flow based on metadata, eliminating the limitations of traditional fixed flows when dealing with complex radar data. By periodically collecting data flow parameters and calculating the system load index, the system can accurately capture the dynamic changes in the data flow. The node scaling mechanism based on the load index not only quickly replenishes computing power under high load, preventing latency accumulation due to task backlog, but also promptly releases idle resources under low load, avoiding continuous idle hardware resources. Overall, this solution, through a data-driven elastic scaling strategy, achieves dynamic matching of computing resources and data flow, fundamentally solving the problem of large fluctuations in resource utilization in radar data processing with fixed-node architectures.

[0095] Example 8: Please refer to Figure 1 In step S7, the radar signal processing algorithm is executed in the following specific manner:

[0096] S7.1 Load the radar signal processing algorithm program on each computing node of the distributed server array, including pulse compression module, moving target detection module, constant false alarm rate processing module and target tracking module. Each node retrieves data blocks from the task queue, reads the header metadata to determine the processing flow, calls the modules in sequence for processing, stores intermediate results in the local cache, and writes the final results and metadata to the output buffer.

[0097] S7.2. Collect data traffic parameters periodically through the system monitoring interface, including the amount of data received, the length of the queue to be processed, the average latency and the node saturation. Calculate the system load index based on the parameters using the load evaluation function. Compare the load index with a preset threshold. If the load index exceeds the expansion threshold, select a node from the standby pool to add to the calculation set and distribute the algorithm program. If the load index is below the contraction threshold, remove the node with the lowest load and reclaim its resources. Update the node configuration table.

[0098] In this embodiment, by loading complete radar signal processing algorithm programs onto each computing node, functional integrity under a distributed processing architecture is achieved. Each node determines its processing flow based on metadata, demonstrating the flexibility and adaptability of the processing mechanism. Intermediate results are stored in a local cache, effectively reducing data transmission requirements between nodes. Multi-dimensional data flow parameters are collected through a system monitoring interface, and quantitative analysis is performed using a load assessment function, resulting in precise control over the system's state. When the load index exceeds the expansion threshold, additional nodes are promptly called from the backup pool, ensuring the system's processing capacity under high load; when it falls below the contraction threshold, idle resources are rationally reclaimed, avoiding resource waste. This dynamic adjustment mechanism significantly improves the overall efficiency and response speed of the system, solving the load imbalance problem caused by a fixed number of computing nodes.

[0099] Example 9: Please refer to Figure 1 In step S8, the specific method for aggregating the calculation results is as follows:

[0100] S8.1 Set up a result aggregation node in the distributed server array, and read the processing result data packets from the output buffer of each computing node through the network communication interface. The data packets contain radar signal data and metadata information. The metadata includes result type identifier, timestamp, channel number and sequence number. Store the data packets in a temporary area and sort them by sequence number. Create an index table to record the storage address and metadata. Group and merge the data according to the type identifier. The merging operation includes data splicing, deduplication and format unification. Write the aggregated result data into the result buffer.

[0101] S8.2 Read aggregated data from the result aggregation buffer, load the target recognition algorithm module for recognition processing. The module includes a feature extraction unit, a pattern matching unit, and a target classification unit. The feature extraction unit extracts the target position, velocity, scattering cross-section, and azimuth and elevation angles. The pattern matching unit reads templates from the target feature library and calculates similarity using Euclidean distance or cosine similarity algorithms. The target classification unit determines the target type and confidence level, and generates a result report containing the number, type, position, and velocity parameters of the targets. The report is then transmitted to the display module or decision module through the data output interface.

[0102] In this embodiment: By directly reading the processing result data packets from the output buffers of each computing node at the network communication interface level, the data copying overhead in intermediate steps is effectively reduced. Data packets are sorted based on sequence numbers in the metadata, strictly ensuring data temporal consistency and resolving data out-of-order issues caused by network latency or differences in node processing speeds. An index table is established to record storage addresses and metadata, significantly improving data access efficiency and avoiding performance losses from repeated scanning. Grouping and merging are performed using type identifiers, implementing differentiated processing strategies for different data types to prevent data confusion and incorrect associations. Data splicing, deduplication, and format unification during the merging operation, guided by metadata, accurately eliminate redundant data and format differences, ensuring the integrity and standardization of the aggregation results.

[0103] After reading data from the result aggregation buffer, the target recognition algorithm module is loaded for processing. The feature extraction unit extracts key parameters such as target position, velocity, scattering cross-section, and azimuth / elevation angles, laying a comprehensive feature foundation for the recognition process. The pattern matching unit reads templates from the target feature library and calculates similarity using Euclidean distance or cosine similarity algorithms, achieving high-precision pattern matching based on the mathematical properties of the feature parameters. The target classification unit combines the similarity results to determine the target type and confidence level, enhancing the reliability of the recognition conclusions. The final result report integrates target quantity, type, position, and velocity parameters, seamlessly transmitting them to the display or decision-making module through the data output interface, ensuring the system's practicality and decision support capabilities.

[0104] Example 10: Please refer to Figure 1 In step S9, the specific method for system performance monitoring is as follows:

[0105] S9.1 Deploy performance monitoring agents on each node of the distributed server array. Read running status parameters at preset intervals through system call interfaces, including data transmission rate, network bandwidth utilization, processor load, memory utilization, buffer utilization, and task latency. Encapsulate the collected parameters into monitoring data packets in a predefined format, including node identifier, parameter type, value, timestamp, and sequence number. Transmit the data packets to the central monitoring node through the network interface and store them in the performance database.

[0106] S9.2 Read historical and real-time running parameter data from the performance database, calculate the average, peak, standard deviation and trend of each parameter, compare the current value with the normal range threshold in the configuration library, and calculate the configuration adjustment amount according to the parameter type, deviation and historical characteristics through the adjustment strategy function when the threshold is exceeded. Generate an adjustment instruction containing the target node identifier, parameter type and adjustment value, send it to the target node through the configuration interface and modify the configuration parameters, and record the adjustment operation to the system log.

[0107] In this embodiment: By deploying performance monitoring agents on each node of the distributed server array, and using system call interfaces to read operational status parameters at preset intervals, this periodic collection method avoids excessive consumption of computing resources by real-time monitoring, while ensuring the regularity and predictability of parameter acquisition. Key parameters such as data transmission rate and network bandwidth utilization are included in the monitoring scope, providing comprehensive data for subsequent analysis. By encapsulating the collected parameters into monitoring data packets containing node identifiers, timestamps, and sequence numbers according to a predefined format, the central monitoring node can accurately trace the data source and temporal relationship, laying the foundation for cross-node performance comparison. The monitoring data packets are transmitted to the central monitoring node via the network interface and stored in the performance database, achieving centralized data management and facilitating historical trend analysis and real-time status comparison.

[0108] After retrieving historical and real-time operational parameter data from the performance database, the average, peak, standard deviation, and trend of each parameter are calculated. This multi-dimensional statistical analysis method reveals potential patterns and abnormal fluctuations in system operation. The current values ​​are compared with normal range thresholds in the configuration library. Combining parameter type, deviation, and historical characteristics, the configuration adjustment amount is calculated using an adjustment strategy function. This differentiated processing mechanism avoids the risk of misjudgment triggered by simple thresholds. Adjustment instructions containing target node identifiers and parameter types are generated. Node configuration parameters are directly modified through the configuration interface, achieving precise and targeted execution of the adjustment instructions. The adjustment operations are recorded in the system log, forming a complete operation audit chain, providing traceable decision-making basis for subsequent strategy optimization.

[0109] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

[0110] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-speed acquisition, transmission, storage, and calculation method for radar array data, characterized in that: The specific steps are as follows: S1. Data Acquisition: The FPGA module is used to acquire raw data from the radar array, perform timing alignment, data format conversion and signal denoising operations, cache the processed data according to a predetermined format, and add a timestamp and metadata identifier to each data packet; S2, Data Channel Mapping: Maps the data from each radar channel to the logic processing unit, performs time alignment and phase compensation operations on the multi-channel data, and eliminates deviations caused by hardware delays; S3. Data Blocking: Divide the continuous data stream into data blocks of fixed length, add an identifier and metadata to each data block, and transmit the data blocks to the subsequent processing unit through a preset distribution strategy; S4. High-speed data transmission configuration: Configure InfiniBand network to connect the FPGA and the server array, and use RDMA technology to directly transmit data from the FPGA storage area to the server memory, bypassing the traditional transmission path involving the CPU; S5. Distributed data storage: The received data is distributed and stored in a server array, using a ring buffer management method, and the buffer size is dynamically adjusted according to the system load; S6. Data Synchronization: Perform time synchronization operation on data from multiple processing nodes, and dynamically allocate computing tasks to the corresponding nodes based on load monitoring results; S7. Radar signal processing algorithm execution: The radar signal processing algorithm runs on a distributed server array, and the number of server nodes participating in the calculation is dynamically adjusted according to data traffic requirements. S8. Calculation Result Aggregation: Collect the processing results output by each computing node, perform data merging and target recognition operations, and output the final results to the system display or decision module; S9. System Performance Monitoring: Real-time collection of system operating parameters, including data transmission rate, node load, and processing latency, and adjustment of system configuration parameters based on monitoring data.

2. The high-speed acquisition, transmission, storage, and calculation method for radar processing array data according to claim 1, characterized in that: In step S1, the data acquisition method is as follows: S1.1 The raw echo data output from each channel of the radar array is received through the field programmable gate array module. The time alignment of the multi-channel data is performed through the delay compensation circuit to eliminate the time deviation between channels. The analog signal is converted into a digital signal by the analog-to-digital converter and the data format is unified. The out-of-band interference and random noise are filtered out by the digital filter. S1.2 Write the processed data into a high-speed buffer according to a predetermined structure, generate a timestamp for each data packet and write it into the data packet header, and write metadata information, including channel number, data length, sampling rate and data block sequence number.

3. The high-speed acquisition, transmission, storage, and calculation method for radar processing array data according to claim 2, characterized in that: In step S2, the data channel mapping is specifically implemented as follows: S2.1 Establish a mapping table between physical channels and logical processing units. The mapping table records the correspondence between physical channel numbers and logical processing unit addresses. Based on the mapping table, route the data of each radar channel to the designated logical processing unit, obtain the hardware transmission delay parameters and phase characteristic parameters of each channel, and store them in the parameter register. S2.2 Read the hardware transmission delay parameters from the parameter register, apply the time delay to the data of each channel through the delay adjustment circuit, read the phase characteristic parameters from the parameter register, and apply the phase compensation to the data of each channel through the phase correction unit.

4. The high-speed acquisition, transmission, storage, and calculation method for radar processing array data according to claim 3, characterized in that: In step S3, the data blockization is specifically implemented as follows: S3.

1. Divide the continuous data stream into multiple data blocks according to the preset fixed length threshold, assign an incrementing sequence number as an identifier to each data block, and write identification information and metadata information in the header of the data block. The identification information includes the data block sequence number and byte length, and the metadata information includes the start timestamp, channel source number, data type identifier and check code. S3.2 Determine the target processing unit address for each data block according to the preset distribution strategy. The distribution strategy is based on the round-robin scheduling algorithm or the weighted load balancing algorithm, combined with the load parameters of the processing unit and the available space parameters of the buffer. Transmit the data block to the target processing unit through the high-speed data bus and update the transmission queue status table.

5. The high-speed acquisition, transmission, storage, and calculation method for radar processing array data according to claim 4, characterized in that: In step S4, the high-speed data transmission configuration is specifically as follows: S4.1 Configure the unlimited bandwidth network adapter to establish the physical connection between the field-programmable gate array module and the server array. Set the working parameters through the driver, including data transmission rate, queue depth, buffer size and transmission priority. Establish a network topology mapping table. The mapping table records the network identifier, communication port number and connection status flag of the server node. S4.2 Load the Remote Direct Memory Access Protocol stack in the Field Programmable Gate Array (FPGA) module and the server array. Register the physical address and access permissions of the data storage area on the FPGA side and register the physical address and write permissions of the target memory area on the server side. Establish a memory address mapping table, configure the transmission channel parameters, and have the network adapter's built-in engine read the data and write it to the server memory.

6. The high-speed acquisition, transmission, storage, and calculation method for radar processing array data according to claim 5, characterized in that: In step S5, the specific method of distributed data storage is as follows: S5.1 Obtain the storage capacity parameters and network topology parameters of each node in the server array, determine the data distribution strategy based on the parameters, and use the consistent hashing algorithm or weighted round-robin algorithm to allocate data blocks to the corresponding node storage space. Allocate a continuous physical address space in the memory area of ​​each node to establish a circular buffer, including the data storage area, read / write pointer register and status flag register, and set the pointer initial value and wraparound condition. S5.

2. Periodically collect load parameters of each node through the system monitoring interface, including processor utilization, memory usage, buffer fill rate and data processing rate. Calculate the buffer adjustment coefficient based on the load parameters using the adjustment strategy function. Compare the fill rate with a preset threshold. If it exceeds the upper limit, request additional physical address space and migrate data. If it is below the lower limit, release the excess space and update the address parameters and wraparound boundary values.

7. The high-speed acquisition, transmission, storage, and calculation method for radar processing array data according to claim 6, characterized in that: In step S6, the data synchronization is performed in the following specific manner: S6.1 Select one node in the server array as the time reference node, and set the remaining nodes as slave nodes. The time reference node periodically generates time synchronization messages and broadcasts them to each slave node. The message contains a reference timestamp field, a sequence number field, and a checksum field. After receiving the message, each slave node calculates the time deviation, corrects the local clock count value through the clock adjustment interface, corrects the timestamp of the data block, and sorts them in chronological order. S6.

2. Periodically collect load status parameters of each node through system call interface, including task queue length, processor idle rate, available memory capacity and task completion rate. Calculate load weight value based on parameters and preset weight coefficient, establish priority queue to arrange nodes in order of weight value from low to high, retrieve tasks from task pool and allocate them to target nodes in priority queue order, send task information through network interface and update task queue status table.

8. The high-speed acquisition, transmission, storage, and calculation method for radar processing array data according to claim 7, characterized in that: In step S7, the radar signal processing algorithm is executed in the following specific manner: S7.1 Load the radar signal processing algorithm program on each computing node of the distributed server array, including pulse compression module, moving target detection module, constant false alarm rate processing module and target tracking module. Each node retrieves data blocks from the task queue, reads the header metadata to determine the processing flow, calls the modules in sequence for processing, stores intermediate results in the local cache, and writes the final results and metadata to the output buffer. S7.

2. Collect data traffic parameters periodically through the system monitoring interface, including the amount of data received, the length of the queue to be processed, the average latency and the node saturation. Calculate the system load index based on the parameters using the load evaluation function. Compare the load index with a preset threshold. If the load index exceeds the expansion threshold, select a node from the standby pool to add to the calculation set and distribute the algorithm program. If the load index is below the contraction threshold, remove the node with the lowest load and reclaim its resources. Update the node configuration table.

9. The high-speed acquisition, transmission, storage, and calculation method for radar processing array data according to claim 8, characterized in that: In step S8, the specific method for aggregating the calculation results is as follows: S8.1 Set up a result aggregation node in the distributed server array, and read the processing result data packets from the output buffer of each computing node through the network communication interface. The data packets contain radar signal data and metadata information. The metadata includes result type identifier, timestamp, channel number and sequence number. Store the data packets in a temporary area and sort them by sequence number. Create an index table to record the storage address and metadata. Group and merge the data according to the type identifier. The merging operation includes data splicing, deduplication and format unification. Write the aggregated result data into the result buffer. S8.2 Read aggregated data from the result aggregation buffer, load the target recognition algorithm module for recognition processing. The module includes a feature extraction unit, a pattern matching unit, and a target classification unit. The feature extraction unit extracts the target position, velocity, scattering cross-section, and azimuth and elevation angles. The pattern matching unit reads templates from the target feature library and calculates similarity using Euclidean distance or cosine similarity algorithms. The target classification unit determines the target type and confidence level, and generates a result report containing the number, type, position, and velocity parameters of the targets. The report is then transmitted to the display module or decision module through the data output interface.

10. The high-speed acquisition, transmission, storage, and calculation method for radar processing array data according to claim 9, characterized in that: In step S9, the specific method for system performance monitoring is as follows: S9.1 Deploy performance monitoring agents on each node of the distributed server array. Read running status parameters at preset intervals through system call interfaces, including data transmission rate, network bandwidth utilization, processor load, memory utilization, buffer utilization, and task latency. Encapsulate the collected parameters into monitoring data packets in a predefined format, including node identifier, parameter type, value, timestamp, and sequence number. Transmit the data packets to the central monitoring node through the network interface and store them in the performance database. S9.2 Read historical and real-time running parameter data from the performance database, calculate the average, peak, standard deviation and trend of each parameter, compare the current value with the normal range threshold in the configuration library, and calculate the configuration adjustment amount according to the parameter type, deviation and historical characteristics through the adjustment strategy function when the threshold is exceeded. Generate an adjustment instruction containing the target node identifier, parameter type and adjustment value, send it to the target node through the configuration interface and modify the configuration parameters, and record the adjustment operation to the system log.

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