Semiconductor device

Abstract

The semiconductor device includes a bit line extending in a first direction, a mold structure extending in a second direction and having a first side surface and a second side surface opposite to each other in the first direction, and a first vertical semiconductor pattern and a second vertical semiconductor pattern on the bit line and on the first side surface and the second side surface of the mold structure, respectively. Each of a first side surface and a second side surface of the mold structure has a non-linear portion, the first vertical semiconductor pattern extends along the non-linear portion of the first side surface, and the second vertical semiconductor pattern extends along the non-linear portion of the second side surface.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and methods of manufacturing the same, and more particularly, to semiconductor memory devices including vertical channel transistors and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices can include integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to shrink, the scaling down of MOSFETs is also accelerating. However, as MOSFETs shrink, the operating characteristics of semiconductor devices may deteriorate or be suppressed. Therefore, research is underway on various methods to overcome the limitations caused by the high integration of semiconductor devices and to form semiconductor devices with improved performance. Summary of the Invention

[0003] This disclosure provides a semiconductor device including a vertical channel transistor with an increased channel width and a method for manufacturing the same.

[0004] This disclosure also provides a semiconductor device including a vertical channel transistor with improved electrical characteristics and a method for manufacturing the same.

[0005] Embodiments of this disclosure provide a semiconductor device including bit lines extending on a substrate in a first direction and spaced apart from each other in a second direction, the first and second directions being parallel to and intersecting each other on an upper surface of the substrate. An insulating pattern extends between the bit lines in the first direction. The semiconductor device may include a mold structure extending on the bit lines and the insulating pattern in the second direction, and including a first portion that at least partially overlaps with each bit line in a third direction perpendicular to the upper surface of the substrate, and a second portion that at least partially overlaps with the insulating pattern in a third direction. The semiconductor device may include a first vertical semiconductor pattern and a second vertical semiconductor pattern spaced apart from each other on the bit lines in the first direction, the first portion of the mold structure being between the first and second vertical semiconductor patterns. The semiconductor device may include a first gate electrode and a second gate electrode spaced apart from each other in the first direction, with the mold structure therebetween, the first and second gate electrodes extending in the second direction and on the bit lines and the insulating pattern. The first vertical semiconductor pattern is between the first gate electrode and the mold structure, the second vertical semiconductor pattern is between the second gate electrode and the mold structure, and a first width of the first portion of the mold structure in the first direction is different from a second width of the second portion of the mold structure in the first direction.

[0006] In embodiments of this disclosure, a semiconductor device includes a bit line extending on a substrate in a first direction and a mold structure extending on the bit line in a second direction, the first and second directions being parallel to the upper surface of the substrate and intersecting each other. The semiconductor device may include a first vertical semiconductor pattern and a second vertical semiconductor pattern spaced apart from each other on the bit line and in the first direction, with the mold structure between the first and second vertical semiconductor patterns. The mold structure includes a first portion having a first width in the first direction and a second portion having a second width in the first direction, the second width being different from the first width, and the first portion of the mold structure at least partially overlaps with the bit line in a third direction perpendicular to the upper surface of the substrate and between the first and second vertical semiconductor patterns.

[0007] In embodiments of this disclosure, a semiconductor device includes a bit line extending on a substrate in a first direction and a mold structure extending on the bit line in a second direction and including first and second side surfaces opposite to each other in the first direction. The first and second directions are parallel to the upper surface of the substrate and intersect each other. The semiconductor device may include a first vertical semiconductor pattern and a second vertical semiconductor pattern on the bit line and respectively on the first and second side surfaces of the mold structure. Each of the first and second side surfaces of the mold structure includes a non-linear portion, the first vertical semiconductor pattern extending along the non-linear portion of the first side surface, and the second vertical semiconductor pattern extending along the non-linear portion of the second side surface. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure. In the drawings:

[0009] Figure 1 This is a block diagram illustrating a semiconductor device according to some embodiments of the present disclosure;

[0010] Figure 2 and Figure 3 These are perspective views schematically illustrating some embodiments of a semiconductor device according to this disclosure;

[0011] Figure 4 This is a plan view of a semiconductor device according to some embodiments of the present disclosure;

[0012] Figure 5 It is along Figure 4 The cross-sectional view taken from A-A', and Figure 6 It is along Figure 4 A cross-sectional view taken at B-B';

[0013] Figure 7 , Figure 10 , Figure 13 and Figure 16 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0014] Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 14 , Figure 15 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0015] Figure 23 This is a plan view of a semiconductor device according to some embodiments of the present disclosure;

[0016] Figure 24 It is along Figure 23 The cross-sectional view taken from A-A', and Figure 25 It is along Figure 23 A cross-sectional view taken at B-B';

[0017] Figure 26 and Figure 29 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0018] Figure 27 , Figure 28 , Figure 30 and Figure 31 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0019] Figure 32 This is a plan view of a semiconductor device according to some embodiments of the present disclosure;

[0020] Figure 33 and Figure 34 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0021] Figure 35 This is a plan view of a semiconductor device according to some embodiments of the present disclosure;

[0022] Figure 36 and Figure 37 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0023] Figure 38 This is a plan view of a semiconductor device according to some embodiments of the present disclosure;

[0024] Figure 39 and Figure 40 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0025] Figure 41 This is a plan view of a semiconductor device according to some embodiments of the present disclosure;

[0026] Figure 42 and Figure 43 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0027] Figure 44 These are plan views of semiconductor devices according to some embodiments of the present disclosure; and

[0028] Figure 45 and Figure 46 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Detailed Implementation

[0029] To clarify this disclosure, the same elements or equivalents are designated by the same reference numerals throughout the specification. Furthermore, since the dimensions and thicknesses of the constituent components shown in the drawings are arbitrarily given for better understanding and ease of description, this disclosure is not limited to the dimensions and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc., are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are shown excessively for better understanding and ease of description.

[0030] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it can be directly on the other element, or there may be intermediate elements present. Conversely, when an element is referred to as being “directly on” another element, there are no intermediate elements present. Furthermore, for ease of description, this document may use spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature and another element or feature as shown in the figures. It should be understood that, in addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. For example, if the device in the figure is flipped, an element described as being “below” or “under” another element or feature will be oriented “above” the other element or feature. Thus, the term “below” can encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0031] Furthermore, unless explicitly stated otherwise, the word “comprising” and variations such as “including” or “comprising…” will be understood to imply inclusion of the stated elements but not exclusion of any other elements. As used herein, the singular forms “a,” “an,” and “the” are intended to also include the plural forms unless the context clearly indicates otherwise. The term “and / or” includes any and all combinations of one or more of the associated listed items. The term “connection” may be used herein to refer to a physical and / or electrical connection, and may refer to a direct or indirect physical and / or electrical connection. The term “exposed” may be used to define the relationship between a particular layer or surface, but it does not require that the layer or surface be free of other elements or layers in the finished device. When viewed along a line extending in a particular direction or in a plane perpendicular to a particular direction, components or layers described with reference to “overlapping” in a particular direction may at least partially obscure each other. The terms “first,” “second,” etc., may be used herein to distinguish only one component, element, etc. from another component, element, etc.

[0032] In the following description, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0033] Figure 1 This is a block diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0034] refer to Figure 1 The semiconductor device may include a memory cell array 1, a row decoder 2, a sense amplifier 3, a column decoder 4, and control logic 5.

[0035] The memory cell array 1 may include multiple memory cells MC arranged in a two-dimensional or three-dimensional manner. Each memory cell MC may be connected to word lines WL and bit lines BL that intersect each other. Each memory cell MC may include a select element TR and a data storage element DS. The select element TR and the data storage element DS may be electrically connected to each other. The select element TR may be connected to the word lines WL and BL and may be provided at the points where the word lines WL and BL intersect each other.

[0036] The selector element TR may include a field-effect transistor. The data storage element DS may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. When the selector element TR includes a field-effect transistor, the gate terminal of the transistor may be connected to the word line WL, and the source / drain terminals of the transistor may be connected to the bit line BL and the data storage element DS, respectively.

[0037] The row decoder 2 can select any word line WL of the memory cell array 1 by decoding an address input from an external source. The address decoded by the row decoder 2 can be provided to the row driver (not shown), and the row driver can provide a predetermined voltage to the selected word line WL and the unselected word line WL in response to control by the control circuit.

[0038] The sensing amplifier 3 can sense and amplify the voltage difference between the bit line BL and the reference bit line selected according to the address decoded by the column decoder 4, and can output the voltage difference.

[0039] The column decoder 4 provides a data transmission path between the sense amplifier 3 and an external device (e.g., a memory controller). The column decoder 4 can select any bit line BL of the memory cell array 1 by decoding an address input from its external source. The control logic 5 generates control signals to control operations that write data to or read data from the memory cell array 1.

[0040] Figure 2 and Figure 3 These are perspective views schematically illustrating some embodiments of a semiconductor device according to this disclosure.

[0041] refer to Figure 2 and Figure 3 The semiconductor device may include a peripheral circuit structure PS on a first substrate SUB1 and a cell array structure CS on the peripheral circuit structure PS. In the following, a first direction D1 and a second direction D2 are directions parallel to the upper surface of the first substrate SUB1 and intersecting each other, and a third direction D3 is a direction perpendicular to the upper surface of the first substrate SUB1. The peripheral circuit structure PS and the cell array structure CS may be stacked on the first substrate SUB1 on the third direction D3.

[0042] The peripheral circuit structure PS may include core and peripheral circuitry formed on the first substrate SUB1. The core and peripheral circuitry may include reference circuitry. Figure 1 The described row decoder 2 and column decoder 4, sensing amplifier 3 and control logic 5.

[0043] The cell array structure CS may include memory cell array 1 (see...) Figure 1 ), memory cell array 1 includes memory cells MC arranged in two or three dimensions (see Figure 1 For example, memory cell MC (see...) Figure 1 The selection element TR for each of the elements in ) (see Figure 1 The device may include a vertical channel transistor (VCT). A vertical channel transistor may include a channel pattern extending along a third direction to D3.

[0044] refer to Figure 2 According to some implementations, the peripheral circuit structure PS can be disposed between the first substrate SUB1 and the unit array structure CS, and can be electrically connected to the unit array structure CS through conductive contacts.

[0045] refer to Figure 3 According to some embodiments, the semiconductor device may have a chip-to-chip bonding structure. Specifically, a peripheral circuit structure PS may be provided on a first substrate SUB1, and a first metal pad LMP may be disposed on the peripheral circuit structure PS. The first metal pad LMP may be electrically connected to the core and the peripheral circuit. A cell array structure CS may be provided on a second substrate SUB2. A second metal pad UMP may be provided below the cell array structure CS. The second metal pad UMP may be electrically connected to the memory cell array 1 (see...). Figure 1 The first metal pad (LMP) and the second metal pad (UMP) can be directly bonded to each other. The peripheral circuit structure (PS) and the cell array structure (CS) can be electrically connected to each other through the first metal pad (LMP) and the second metal pad (UMP).

[0046] Figure 4 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. Figure 5 It is along Figure 4 The cross-sectional view taken from A-A', and Figure 6 It is along Figure 4 The cross-sectional view taken from B-B'.

[0047] refer to Figures 4 to 6 ,refer to Figure 2 and Figure 3 The described cell array structure CS can be disposed on the substrate 100. According to some embodiments, the substrate 100 may include... Figure 2 The substrate 100 comprises a first substrate SUB1 and a peripheral circuit structure PS, and may further include an insulating layer covering or overlapping the peripheral circuit structure PS. A cell array structure CS may be disposed on the insulating layer. According to other embodiments, the substrate 100 may include... Figure 3 The second substrate SUB2 may further include an insulating layer on the second substrate SUB2. The cell array structure CS may be disposed on the insulating layer.

[0048] The components of the cell array structure CS will be described below.

[0049] Bit lines BL can be disposed on substrate 100. Bit lines BL can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. The first direction D1 and the second direction D2 can be parallel to the upper surface 100U of substrate 100 and can intersect each other (e.g., perpendicular to each other). Insulating patterns 110 can be interposed between bit lines BL and can extend between bit lines BL in the first direction D1. Bit lines BL can include conductive materials. For example, bit lines BL can include at least one of doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), metals (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), metal silicides (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), or conductive metal nitrides (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). According to some embodiments, bit lines BL can include carbon-based two-dimensional materials (e.g., graphene), carbon-based three-dimensional materials (e.g., carbon nanotubes), or combinations thereof. The insulating pattern 110 may include an insulating material, and may include, for example, silicon oxide, silicon nitride and / or silicon nitride.

[0050] A mold structure MS can be disposed on and intersect with the bit line BL and the insulating pattern 110. The mold structures MS can extend in a second direction D2 and can be spaced apart from each other in a first direction D1. Each of the mold structures MS can include a lower mold pattern 120 and an upper mold pattern 130 stacked on a third direction D3 perpendicular to the upper surface 100U of the substrate 100. The lower mold pattern 120 can extend in the second direction D2 to intersect with the bit line BL and the insulating pattern 110. The upper mold pattern 130 can be disposed on the upper surface of the lower mold pattern 120 and can extend along the upper surface of the lower mold pattern 120 in the second direction D2. The lower mold pattern 120 can include an insulating material, and for example, can include silicon oxide, silicon nitride, and / or silicon nitride. The upper mold pattern 130 can include an insulating material different from the lower mold pattern 120, and for example, can include silicon nitride.

[0051] Each of the mold structure MS may include a first portion P1 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the bit lines BL and a second portion P2 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the insulating patterns 110 between the bit lines BL. Each of the mold structure MS may have a width along the first direction D1, and a first width W1 of the first portion P1 may be different from a second width W2 of the second portion P2. According to some embodiments, the first width W1 of the first portion P1 may be smaller than or less than the second width W2 of the second portion P2.

[0052] Each of the mold structures MS may have a first side surface S1 and a second side surface S2 opposite to each other in a first direction D1. Each of the first side surface S1 and the second side surface S2 may have a non-flat structure; for example, the first side surface S1 and the second side surface S2 may have a non-linear shape in the second direction D2 due to one or more recesses and / or protrusions, as described in further detail below. The recesses and / or protrusions of the first side surface S1 and / or the second side surface S2 may be collectively (or individually) referred to below as "non-linear portions". According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 extending from a first portion P1 toward an internal recess in each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. Each of the mold structures MS has a second side surface S2 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. The first recessed side surface RS1 and the second recessed side surface RS2 may face each other in a first direction D1 and may be mirror images (or symmetrical) to each other.

[0053] A first vertical semiconductor pattern VSP1 and a second vertical semiconductor pattern VSP2 may be disposed on each of the bit lines BL and may be spaced apart from each other in a first direction D1, with each of the mold structures MS located therebetween. The first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 may be spaced apart from each other in the first direction D1, with a first portion P1 of each of the mold structures MS located therebetween. The first vertical semiconductor pattern VSP1 may be disposed on a first side surface S1 of each of the mold structures MS and may extend along a non-flat structure of the first side surface S1. The second vertical semiconductor pattern VSP2 may be disposed on a second side surface S2 of each of the mold structures MS and may extend along a non-flat structure of the second side surface S2. According to some embodiments, the first vertical semiconductor pattern VSP1 may be disposed on a first recessed side surface RS1 of the first portion P1 and may extend conformally along the first recessed side surface RS1. The first vertical semiconductor pattern VSP1 may partially fill the first recessed region. The second vertical semiconductor pattern VSP2 may be disposed on a second recessed side surface RS2 of the first portion P1 and may extend conformally along the second recessed side surface RS2. The second recessed area can be partially filled with the second vertical semiconductor pattern VSP2.

[0054] A horizontal semiconductor pattern HSP can be disposed on each bit line BL and between module structures MS. A horizontal semiconductor pattern HSP can be disposed between a pair of module structures MS that are adjacent to each other. A horizontal semiconductor pattern HSP can connect the lower portion of a first vertical semiconductor pattern VSP1 disposed on the first recessed side surface RS1 of the first portion P1 of one pair of module structures MS and the lower portion of a second vertical semiconductor pattern VSP2 disposed on the second recessed side surface RS2 of the first portion P1 of the other pair of module structures MS. The lower surface of the horizontal semiconductor pattern HSP can contact the upper surface of each bit line BL. The horizontal semiconductor pattern HSP can contact the lower portion of the first vertical semiconductor pattern VSP1 and the lower portion of the second vertical semiconductor pattern VSP2 without a boundary surface. The first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP can be connected to each other for integral configuration and can be referred to as semiconductor patterns. Semiconductor patterns VSP1, VSP2, and HSP can have a U-shape in cross-sectional view.

[0055] According to some embodiments, the first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP may include oxide semiconductors. For example, the oxide semiconductor may include InxGayZnzO, InxGaySizO, InxSnyZnzO, InxZnyO, ZnxO, ZnxSnyO, ZnxOyN, ZrxZnySnzO, SnxO, HfxInyZnzO, GaxZnySnzO, AlxZnySnzO, YbxGayZnzO, InxGayO, or combinations thereof. The first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP may include, for example, indium gallium zinc oxide (IGZO). The first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP may include a single layer or multiple layers of oxide semiconductors, and may include amorphous, crystalline, or polycrystalline oxide semiconductors. The first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP may have a larger bandgap energy than silicon. For example, the first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP can have a bandgap energy of about 1.5 eV to about 5.6 eV, and in some embodiments, they can have a bandgap energy of about 2.0 eV to about 4.0 eV.

[0056] According to some embodiments, the first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP may comprise semiconductor materials, and may comprise, for example, at least one of silicon (e.g., single-crystal silicon), germanium, and / or silicon-germanium. According to some embodiments, the first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP may comprise two-dimensional semiconductor materials, and may comprise, for example, graphene, carbon nanotubes, or combinations thereof.

[0057] Gate electrodes GE can be disposed on bit lines BL and insulating patterns 110, and can intersect bit lines BL and insulating patterns 110. Gate electrodes GE can extend in a second direction D2 and can be spaced apart from each other in a first direction D1. Gate electrodes GE can include a first gate electrode GE1 on a first side surface S1 of each of the mold structures MS and a second gate electrode GE2 on a second side surface S2 of each of the mold structures MS. The first gate electrode GE1 can extend along the first side surface S1 of each of the mold structures MS in the second direction D2, and the second gate electrode GE2 can extend along the second side surface S2 of each of the mold structures MS in the second direction D2. The first gate electrode GE1 and the second gate electrode GE2 can be spaced apart from each other in the first direction D1, with each of the mold structures MS located therebetween.

[0058] A first vertical semiconductor pattern VSP1 can be interposed between a first gate electrode GE1 and a first side surface S1 of each of the mold structures MS. The first vertical semiconductor pattern VSP1 can also be interposed between the first gate electrode GE1 and a first recessed side surface RS1 of a first portion P1 of each of the mold structures MS. According to some embodiments, the first gate electrode GE1 can conformally extend along the first recessed side surface RS1 of the first portion P1 of each of the mold structures MS and can partially fill the first recessed region. A second vertical semiconductor pattern VSP2 can be interposed between a second gate electrode GE2 and a second side surface S2 of each of the mold structures MS. The second vertical semiconductor pattern VSP2 can also be interposed between the second gate electrode GE2 and a second recessed side surface RS2 of the first portion P1 of each of the mold structures MS. According to some embodiments, the second gate electrode GE2 can conformally extend along the second recessed side surface RS2 of the first portion P1 of each of the mold structures MS and can partially fill the second recessed region.

[0059] A pair of gate electrodes GE can be disposed between a pair of adjacent or closely spaced module structures MS. A pair of gate electrodes GE may include a first gate electrode GE1 disposed on a first side surface S1 of one module structure MS and a second gate electrode GE2 disposed on a second side surface S2 of the other module structure MS. The pair of gate electrodes GE can be disposed on a horizontal semiconductor pattern HSP and may intersect with the horizontal semiconductor pattern HSP.

[0060] The gate electrode GE may include a conductive material, and may include, for example, at least one of a metal (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal silicide (e.g., silicides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), and / or a conductive metal nitride (e.g., nitrides of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0061] A gate insulating pattern GI can be interposed between each of the module structure MS and each of the gate electrodes GE. The gate insulating pattern GI can be interposed between the first gate electrode GE1 and the first side surface S1 of each of the module structure MS, and can extend between the first vertical semiconductor pattern VSP1 and the first gate electrode GE1. The gate insulating pattern GI can be interposed between the second gate electrode GE2 and the second side surface S2 of each of the module structure MS, and can extend between the second vertical semiconductor pattern VSP2 and the second gate electrode GE2. The gate insulating pattern GI can extend between the horizontal semiconductor pattern HSP and each of the gate electrodes GE.

[0062] A gate insulating pattern GI can be interposed between a first gate electrode GE1 and a first vertical semiconductor pattern VSP1 disposed on a first side surface S1 (e.g., a first recessed side surface RS1) of one of a pair of mode structures MS, and can extend between a horizontal semiconductor pattern HSP and the first gate electrode GE1. Furthermore, the gate insulating pattern GI can be interposed between a second gate electrode GE2 and a second vertical semiconductor pattern VSP2 disposed on a second side surface S2 (e.g., a second recessed side surface RS2) of the other of the pair of mode structures MS, and can extend between a horizontal semiconductor pattern HSP and a second gate electrode GE2. The gate insulating pattern GI can extend between each of the insulating patterns 110 and each of the gate electrodes GE.

[0063] The gate insulating pattern GI may include a first gate insulating pattern GI1 and a second gate insulating pattern GI2. The first gate insulating pattern GI1 may be interposed between a first gate electrode GE1 and a first vertical semiconductor pattern VSP1, and may extend between a horizontal semiconductor pattern HSP and the first gate electrode GE1. Furthermore, the first gate insulating pattern GI1 may be interposed between a second gate electrode GE2 and a second vertical semiconductor pattern VSP2, and may extend between the horizontal semiconductor pattern HSP and the second gate electrode GE2. The second gate insulating pattern GI2 may be interposed between the first gate insulating pattern GI1 and the first gate electrode GE1, and between the first gate insulating pattern GI1 and the second gate electrode GE2, and may extend between the first gate electrode GE1 and a first side surface S1 of each of the module structures MS, and between the second gate electrode GE2 and a second side surface S2 of each of the module structures MS. The second gate insulating pattern GI2 may extend between each of the insulating patterns 110 and each of the gate electrodes GE, and may further extend to the upper surface of each of the module structures MS.

[0064] For example, the gate insulating pattern GI may include at least one of silicon oxide or a high dielectric constant material. In this disclosure, a high dielectric constant material may be defined as a material having a higher dielectric constant than silicon oxide.

[0065] The buried insulating layer 160 can be interposed between the mold structures MS and can cover or at least partially overlap the upper and side surfaces of the gate electrode GE. The buried insulating layer 160 can be disposed between a first gate electrode GE1 on a first side surface S1 of one of the mold structures MS and a second gate electrode GE2 on a second side surface S2 of the other of the mold structures MS, and can extend to the upper surfaces of the first gate electrode GE1 and the second gate electrode GE2. The gate insulating pattern GI can be interposed between the first gate electrode GE1 and the first vertical semiconductor pattern VSP1 on a first side surface S1 (e.g., a first recessed side surface RS1) of one of the mold structures MS, and can extend along a third direction D3 between the buried insulating layer 160 and the first side surface S1 (e.g., the first recessed side surface RS1) of one of the mold structures MS. The gate insulating pattern GI can be interposed between the second gate electrode GE2 and the second vertical semiconductor pattern VSP2 on the second side surface S2 (e.g., the second recessed side surface RS2) of the other of the pair of mode structures MS, and can extend along the third direction D3 between the buried insulating layer 160 and the second side surface S2 (e.g., the second recessed side surface RS2) of the other of the pair of mode structures MS. The gate insulating pattern GI can extend between the horizontal semiconductor pattern HSP and the buried insulating layer 160.

[0066] The gate insulating pattern GI can extend between each of the insulating patterns 110 and the buried insulating layer 160. The gate insulating pattern GI can extend between the first gate electrode GE1 and a first side surface S1 of one of the pair of mode structures MS and between the buried insulating layer 160 and a first side surface S1 of one of the pair of mode structures MS, and can extend between the second gate electrode GE2 and a second side surface S2 of the other of the pair of mode structures MS and between the buried insulating layer 160 and a second side surface S2 of the other of the pair of mode structures MS.

[0067] A cap insulating layer 150 may be interposed between each of the gate electrodes GE and a buried insulating layer 160. The cap insulating layer 150 may be interposed between the buried insulating layer 160 and the upper surface of each of the gate electrodes GE, and may extend between the buried insulating layer 160 and the side surface of each of the gate electrodes GE. The cap insulating layer 150 may extend onto a horizontal semiconductor pattern HSP between a first gate electrode GE1 on a first side surface S1 of one of the pair of mold structures MS and a second gate electrode GE2 on a second side surface S2 of the other of the pair of mold structures MS, and may be interposed between the buried insulating layer 160 on the horizontal semiconductor pattern HSP and a gate insulating pattern GI. The cap insulating layer 150 may extend onto each of the insulating patterns 110 between the first gate electrode GE1 on a first side surface S1 of one of the pair of mold structures MS and the second gate electrode GE2 on a second side surface S2 of the other of the pair of mold structures MS, and may be interposed between the buried insulating layer 160 on each of the insulating patterns 110 and the gate insulating pattern GI. The cap insulating layer 150 may extend between the buried insulating layer 160 and the gate insulating pattern GI on the first side surface S1 of each of the mold structures MS, and between the buried insulating layer 160 and the gate insulating pattern GI on the second side surface S2 of each of the mold structures MS. The cap insulating layer 150 may extend to the upper surface of each of the mold structures MS, and the gate insulating pattern GI may be interposed between the cap insulating layer 150 and the upper surface of each of the mold structures MS.

[0068] For example, the buried insulating layer 160 may include a silicon oxide layer, a silicon nitride layer, a silicon nitride layer, and / or a low dielectric constant layer. The cover insulating layer 150 may include an insulating material different from that of the buried insulating layer 160, and may include, for example, a silicon nitride layer.

[0069] A first upper insulating layer 170 may be disposed on the mold structure MS and the buried insulating layer 160. The first upper insulating layer 170 may cover or at least partially overlap the cover insulating layer 150 on the upper surface of the mold structure MS, and may also cover or at least partially overlap the upper surface of the buried insulating layer 160. A second upper insulating layer 180 may be disposed on the first upper insulating layer 170, and may cover or at least partially overlap the upper surface of the first upper insulating layer 170. For example, the first upper insulating layer 170 and the second upper insulating layer 180 may include a silicon oxide layer, a silicon nitride layer, a silicon oxide nitride layer, and / or a low dielectric constant layer.

[0070] Node contacts 175 may be respectively disposed on the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2. Each of the node contacts 175 may penetrate or extend into the first upper insulating layer 170, the cap insulating layer 150, and the gate insulating pattern GI, and may be electrically connected to a corresponding one of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2. Each of the node contacts 175 may contact the upper surface of a corresponding one of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2.

[0071] The landing pads LP can be individually disposed on the node contacts 175. Each of the landing pads LP can penetrate the second upper insulating layer 180 and can be electrically connected to each of the node contacts 175. Each of the landing pads LP can contact the upper surface of each of the node contacts 175, and in a plan view, can have various shapes, such as circular, elliptical, rectangular, square, rhomboid, or hexagonal.

[0072] The node contact 175 and the landing pad LP may comprise the same conductive material as each other. For example, the node contact 175 and the landing pad LP may be composed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof, but embodiments of this disclosure are not limited thereto.

[0073] Data storage patterns DS can be disposed on landing pads LP. Data storage patterns DS can be electrically connected to a first vertical semiconductor pattern VSP1 and a second vertical semiconductor pattern VSP2 via landing pads LP and node contacts 175, respectively. Data storage patterns DS can be spaced apart from each other along a first direction D1 and a second direction D2. According to some embodiments, data storage patterns DS can be capacitors. In this case, data storage patterns DS can include lower electrodes disposed on landing pads LP, upper electrodes covering or at least partially overlapping the lower electrodes, and a dielectric film between each of the lower electrodes and the upper electrode. According to other embodiments, data storage patterns DS can be variable resistance patterns capable of switching between two resistance states by electrical pulses. For example, data storage patterns DS can include phase change materials, perovskite compounds, transition metal oxides, magnetic materials, ferromagnetic materials, or antiferromagnetic materials whose crystallization state changes according to the amount of current.

[0074] According to this disclosure, a first vertical semiconductor pattern VSP1 can be used as a vertical channel of a transistor including a first gate electrode GE1 and the first vertical semiconductor pattern VSP1, and a second vertical semiconductor pattern VSP2 can be used as a vertical channel of a transistor including a second gate electrode GE2 and the second vertical semiconductor pattern VSP2. The first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 can be respectively disposed on a first recessed side surface RS1 and a second recessed side surface RS2 of a first portion P1 in each of the module structure MS, and can extend conformally along the first recessed side surface RS1 and the second recessed side surface RS2. Therefore, in a plan view, the area of ​​each of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 can be increased. As a result, the channel width of the vertical channel transistor using the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 as the channel can be increased, thus improving the operating characteristics of the vertical channel transistor.

[0075] Furthermore, since the area of ​​each of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 is increased, the contact area between each of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 and each of the node contacts 175 can be increased. Therefore, the resistance between each of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 and each of the node contacts 175 can be reduced, thereby improving the electrical characteristics of the vertical channel transistor.

[0076] Figure 7 , Figure 10 , Figure 13 and Figure 16This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 8 , Figure 9 , Figure 11 , Figure 12 , Figure 14 , Figure 15 , Figure 17 , Figure 18 , Figure 19 , Figure 20 , Figure 21 and Figure 22 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 8 and Figure 9 They are respectively along Figure 7 The cross-sectional views taken from A-A' and B-B'. Figure 11 and Figure 12 They are respectively along Figure 10 The cross-sectional views taken from A-A' and B-B'. Figure 14 and Figure 15 They are respectively along Figure 13 The cross-sectional views taken from A-A' and B-B', and Figure 17 and Figure 18 They are respectively along Figure 16 The cross-sectional views taken from A-A' and B-B'. Figure 19 and Figure 21 It is along Figure 4 The cross-sectional view taken from A-A', and Figure 20 and Figure 22 It is along Figure 4 The cross-sectional view taken at B-B'. References will be omitted for simplicity. Figures 4 to 6 The description of the semiconductor device is repeated.

[0077] refer to Figures 7 to 9 Bit lines BL can be formed on substrate 100. For example, forming bit lines BL can include forming and patterning a conductive film on the substrate. Bit lines BL can extend in a first direction D1 and can be spaced apart from each other in a second direction D2. Insulating patterns 110 can be formed between bit lines BL and can extend between bit lines BL in the first direction D1. For example, forming insulating patterns 110 can include forming an insulating layer that covers or at least partially overlaps with and at least partially fills the space between bit lines BL, and planarizing the insulating layer until the upper surface of the bit lines BL is exposed.

[0078] A mold structure MS can be formed on the bit line BL and the insulating pattern 110, and can intersect with the bit line BL and the insulating pattern 110. The mold structures MS can extend in a second direction D2 and can be spaced apart from each other in a first direction D1. Each of the mold structures MS can include a lower mold pattern 120 and an upper mold pattern 130 stacked on a third direction D3. For example, forming the mold structure MS can include sequentially stacking a lower mold film and an upper mold film on the bit line BL and the insulating pattern 110, and sequentially patterning the upper mold film and the lower mold film. Each of the mold structures MS can have a first side surface S1 and a second side surface S2 opposite to each other in the first direction D1.

[0079] A mask film 200 may be formed on the bit line BL and the insulating pattern 110, and may cover or at least partially overlap with the mold structure MS. The mask film 200 may have a plurality of openings 200P spaced apart from each other in a first direction D1 and a second direction D2. According to some embodiments, each of the plurality of openings 200P may have the shape of a strip extending in the first direction D1 and may expose portions of a pair of mold structures MS that are adjacent to each other and the upper surface of the bit line BL between the pair of mold structures MS. That is, each of the plurality of openings 200P may expose a first side surface S1 of one of the pair of mold structures MS and a second side surface S2 of the other of the pair of mold structures MS, as well as the upper surface of the bit line BL between the pair of mold structures MS. For example, the mask film 200 may be a photoresist film or a hard mask film.

[0080] refer to Figures 10 to 12 An etching process using a mask film 200 as an etching mask can be performed, and the portion of the mold structure MS exposed by the plurality of openings 200P can be etched by the etching process. Each of the mold structures MS can include a first portion P1 having a first width W1 and a second portion P2 having a second width W2 greater than the first width W1. The first portion P1 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the bit lines BL, and the second portion P2 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the insulating patterns 110 between the bit lines BL.

[0081] Each of the first side surface S1 and the second side surface S2 of each of the mold structures MS can have a non-flat structure by an etching process. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed from a first portion P1 toward the interior of each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed from a first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. The first recessed side surface RS1 and the second recessed side surface RS2 may face each other in a first direction D1 and may be mirror images (or symmetrical) to each other.

[0082] The mask 200 can be removed after the etching process. For example, the mask 200 can be removed by ashing and / or stripping processes.

[0083] refer to Figures 13 to 15 A first vertical semiconductor pattern VSP1 may be formed on a first recessed side surface RS1 of a first portion P1 in each of the mold structures MS, and a second vertical semiconductor pattern VSP2 may be formed on a second recessed side surface RS2 of a first portion P1 in each of the mold structures MS. The first vertical semiconductor pattern VSP1 may conformally extend along the first recessed side surface RS1 and may partially fill the first recessed region. The second vertical semiconductor pattern VSP2 may conformally extend along the second recessed side surface RS2 and may partially fill the second recessed region.

[0084] Horizontal semiconductor patterns HSPs can be formed on each bit line BL and between module structures MS. Horizontal semiconductor patterns HSPs can be formed between a pair of module structures MS that are adjacent to each other. Horizontal semiconductor patterns HSPs can connect the lower portion of a first vertical semiconductor pattern VSP1 disposed on the first recessed side surface RS1 of the first portion P1 of one pair of module structures MS and the lower portion of a second vertical semiconductor pattern VSP2 disposed on the second recessed side surface RS2 of the first portion P1 of the other pair of module structures MS. The first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSPs can be connected to each other for integral configuration and can be referred to as semiconductor patterns. Semiconductor patterns VSP1, VSP2, and HSPs can have a U-shape in cross-sectional views.

[0085] The first gate insulating pattern GI1 can be formed to cover or at least partially overlap with the first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP. The first gate insulating pattern GI1 can be formed on the first recessed side surface RS1 of the first portion P1 of each of the module structures MS, and can cover or at least partially overlap with the first vertical semiconductor pattern VSP1. The first gate insulating pattern GI1 can be formed on the second recessed side surface RS2 of the first portion P1 of each of the module structures MS, and can cover or at least partially overlap with the second vertical semiconductor pattern VSP2. The first gate insulating pattern GI1 can be formed on each bit line BL and between module structures MS, and can cover or at least partially overlap with the horizontal semiconductor pattern HSP. The first gate insulating pattern GI1 can have a U-shape in a cross-sectional view.

[0086] For example, forming a first vertical semiconductor pattern VSP1, a second vertical semiconductor pattern VSP2, a horizontal semiconductor pattern HSP, and a first gate insulating pattern GI1 may include forming a semiconductor film that covers a mold structure MS or at least partially overlaps with the mold structure MS and covers bit lines BL between the mold structures MS and an insulating pattern 110 or at least partially overlaps with bit lines BL between the mold structures MS and an insulating pattern 110, forming a first gate insulating layer on the semiconductor film, removing the semiconductor film and the first gate insulating layer on the insulating pattern 110, and planarizing the semiconductor film and the first gate insulating layer on the bit lines BL until the upper surface of the mold structure MS is exposed.

[0087] Each of the semiconductor film and the first gate insulating layer may conformally cover or overlap the first side surface S1, the first recessed side surface RS1, the second side surface S2, the second recessed side surface RS2, and the top surface of each of the mold structures MS, and may conformally cover or overlap the upper surface of the insulating pattern 110 and the bit line BL between the mold structures MS. For example, removing the semiconductor film and the first gate insulating layer on the insulating pattern 110 may include removing the semiconductor film and the first gate insulating layer from the first side surface S1, the second side surface S2, and the top surface of each of the mold structures MS on the insulating pattern 110, and removing the semiconductor film and the first gate insulating layer from the top surface of the insulating pattern 110 between the mold structures MS. Planarizing the semiconductor film and the first gate insulating layer on the bit line BL may include removing the semiconductor film and the first gate insulating layer from the top surface of each of the mold structures MS on the bit line BL. Therefore, a first vertical semiconductor pattern VSP1 can be formed on a first side surface S1 of each bit line BL in the module structure MS, and a second vertical semiconductor pattern VSP2 can be formed on a second side surface S2 of each bit line BL in the module structure MS. Furthermore, a horizontal semiconductor pattern HSP can be formed on the upper surface of each bit line BL between the module structures MS, and a first gate insulating pattern GI1 can be formed to conformally cover or overlap the first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSP.

[0088] refer to Figures 16 to 18The second gate insulating pattern GI2 can be formed to cover the mold structure MS or at least partially overlap with the mold structure MS, and cover the bit line BL and insulating pattern 110 between the mold structures MS or at least partially overlap with the bit line BL and insulating pattern 110 between the MS. The second gate insulating pattern GI2 can conformally cover or overlap the first side surface S1, the first recessed side surface RS1, the second side surface S2, the second recessed side surface RS2 and the upper surface of each of the mold structures MS, and can conformally cover or overlap the upper surface of the insulating pattern 110 and the bit line BL between the mold structures MS. The second gate insulating pattern GI2 can cover the first side surface S1 of each of the mold structures MS or at least partially overlap with the first side surface S1 of each of the mold structures MS, and can cover the first gate insulating pattern GI1 and the first vertical semiconductor pattern VSP1 on the first recessed side surface RS1 or at least partially overlap with the first gate insulating pattern GI1 and the first vertical semiconductor pattern VSP1 on the first recessed side surface RS1. The second gate insulating pattern GI2 may cover the second side surface S2 of each of the module structures MS or at least partially overlap with the second side surface S2 of each of the module structures MS, and may cover the first gate insulating pattern GI1 and the second vertical semiconductor pattern VSP2 on the second recessed side surface RS2 or at least partially overlap with the first gate insulating pattern GI1 and the second vertical semiconductor pattern VSP2 on the second recessed side surface RS2. The second gate insulating pattern GI2 may cover the first gate insulating pattern GI1 and the horizontal semiconductor pattern HSP on the bit line BL between the module structures MS or at least partially overlap with the first gate insulating pattern GI1 and the horizontal semiconductor pattern HSP on the bit line BL between the module structures MS, and may extend to the upper surface of the module structure MS. The first gate insulating pattern GI1 and the second gate insulating pattern GI2 may be referred to as gate insulating pattern GI.

[0089] Gate electrodes GE can be formed on bit lines BL and insulating patterns 110, and can intersect bit lines BL and insulating patterns 110. Gate electrodes GE can extend in a second direction D2 and can be spaced apart from each other in a first direction D1. Gate electrodes GE can include a first gate electrode GE1 on a first side surface S1 of each of the mold structures MS and a second gate electrode GE2 on a second side surface S2 of each of the mold structures MS. The first gate electrode GE1 and the second gate electrode GE2 can be spaced apart from each other in the first direction D1, with each of the mold structures MS located therebetween. For example, forming gate electrodes GE can include forming a gate electrode film covering the mold structure MS on bit lines BL and insulating patterns 110 or at least partially overlapping the mold structure MS on bit lines BL and insulating patterns 110, and anisotropically etching the gate electrode film. An anisotropic etching process can be performed such that the gate electrodes GE are partially left on the side surface of the mold structure MS.

[0090] refer to Figure 4 , Figure 19 and Figure 20 The upper portion of the gate electrode GE may be recessed. Subsequently, a cap insulating layer 150 may be formed to cover the mode structure MS and the gate electrode GE, or at least partially overlap with the mode structure MS and the gate electrode GE. The cap insulating layer 150 may cover the gate insulating pattern GI on the upper surface of the mode structure MS, or at least partially overlap with the gate insulating pattern GI on the upper surface of the mode structure MS, and may extend to cover the gate insulating pattern GI on the upper side surface of the mode structure MS, or at least partially overlap with the gate insulating pattern GI on the upper side surface of the mode structure MS. The cap insulating layer 150 may extend to cover the upper and side surfaces of the gate electrode GE, or at least partially overlap with the upper and side surfaces of the gate electrode GE, and may extend to cover the gate insulating patterns GI between mode structures MS and between gate electrodes GE, or at least partially overlap with the gate insulating patterns GI between mode structures MS and between gate electrodes GE.

[0091] A buried insulating layer 160 may be formed on the cover insulating layer 150 and may at least partially fill the space between the mold structures MS. The buried insulating layer 160 may extend between the gate electrodes GE. For example, forming the buried insulating layer 160 may include forming an insulating layer that covers or at least partially overlaps with the mold structure MS and the gate electrodes GE, and planarizing the insulating layer until the cover insulating layer 150 is exposed on the upper surface of the mold structure MS.

[0092] The first upper insulating layer 170 may be formed on the mold structure MS and the buried insulating layer 160. The first upper insulating layer 170 may cover the cover insulating layer 150 on the upper surface of the mold structure MS or at least partially overlap with the cover insulating layer 150 on the upper surface of the mold structure MS, and may cover the upper surface of the buried insulating layer 160 or at least partially overlap with the upper surface of the buried insulating layer 160.

[0093] refer to Figure 4 , Figure 21 and Figure 22Node contact holes 175H can be formed in the first upper insulating layer 170. Each of the node contact holes 175H can penetrate or extend into the first upper insulating layer 170, the cap insulating layer 150, and the gate insulating pattern GI, and can expose a corresponding one of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2. The upper portions of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 exposed by the node contact holes 175H can be recessed, so that each of the node contact holes 175H can extend between the gate insulating pattern GI and a side surface (e.g., a first side surface S1 or a second side surface S2) of each module structure MS.

[0094] Return to reference Figures 4 to 6 Node contacts 175 can be formed in node contact holes 175H, and landing pads LP can be formed on node contacts 175. For example, forming node contacts 175 and landing pads LP may include forming an upper conductive film on a first upper insulating layer 170, the upper conductive film at least partially filling the node contact holes 175H and extending onto the first upper insulating layer 170, and patterning the upper conductive film. The landing pads LP can be formed by patterning the upper conductive film, and the portion of the upper conductive film filling the node contact holes 175H can be referred to as node contacts 175.

[0095] The second upper insulating layer 180 may be formed to at least partially fill the space between the landing pads LP. For example, forming the second upper insulating layer 180 may include forming a second upper insulating layer 180 on the first upper insulating layer 170 that covers or at least partially overlaps with the landing pads LP, and planarizing the second upper insulating layer 180 until the upper surface of the landing pads LP is exposed. Data storage patterns DS may be formed on the exposed upper surfaces of the landing pads LP.

[0096] Figure 23 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. Figure 24 It is along Figure 23 The cross-sectional view taken from A-A', and Figure 25 It is along Figure 23 The cross-sectional view taken at B-B'. For simplicity, the main description will be compared with the reference. Figures 4 to 6 The differences described in the semiconductor devices.

[0097] refer to Figures 23 to 25 The mold structure MS can be disposed on the bit line BL and the insulating pattern 110, and can intersect with the bit line BL and the insulating pattern 110. The mold structure MS can extend in the second direction D2 and can be spaced apart from each other in the first direction D1.

[0098] Each of the module structures MS may include a first portion P1 that overlaps vertically (e.g., in the third direction D3) with each bit line BL and a second portion P2 that overlaps vertically (e.g., in the third direction D3) with each of the insulating patterns 110 between the bit lines BL. The first width W1 of the first portion P1 may differ from the second width W2 of the second portion P2. According to some embodiments, the first width W1 of the first portion P1 may be greater than the second width W2 of the second portion P2.

[0099] Each of the mold structures MS may have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1. Each of the first side surface S1 and the second side surface S2 may have an uneven structure. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first protruding side surface PS1 that protrudes or extends from each of the mold structures MS in the first portion P1 (e.g., the first protruding side surface PS1 extends away from the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first protrusion defined by the first protruding side surface PS1. The second side surface S2 of each of the mold structures MS may have a second protruding side surface PS2 that protrudes or extends from each of the mold structures MS in the first portion P1 (e.g., the second protruding side surface PS2 extends away from the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second protrusion defined by the second protruding side surface PS2. The first protruding side surface PS1 and the second protruding side surface PS2 may face each other in the first direction D1 and may be mirror images (or symmetrical) to each other.

[0100] A first vertical semiconductor pattern VSP1 and a second vertical semiconductor pattern VSP2 may be disposed on each of the bit lines BL, and may be spaced apart from each other in the first direction D1, with each of the mold structures MS located therebetween. The first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 may be spaced apart from each other in the first direction D1, with a first portion P1 of each of the mold structures MS located therebetween. According to some embodiments, the first vertical semiconductor pattern VSP1 may be disposed on a first protruding side surface PS1 of the first portion P1, and may extend conformally along the first protruding side surface PS1. The second vertical semiconductor pattern VSP2 may be disposed on a second protruding side surface PS2 of the first portion P1, and may extend conformally along the second protruding side surface PS2.

[0101] Horizontal semiconductor patterns HSPs can be disposed on each bit line BL and between module structures MS. Horizontal semiconductor patterns HSPs can be disposed between a pair of module structures MS that are adjacent to each other. Horizontal semiconductor patterns HSPs can connect the lower portion of a first vertical semiconductor pattern VSP1 disposed on the first protruding side surface PS1 of the first portion P1 of one pair of module structures MS and the lower portion of a second vertical semiconductor pattern VSP2 disposed on the second protruding side surface PS2 of the first portion P1 of the other pair of module structures MS. The first vertical semiconductor pattern VSP1, the second vertical semiconductor pattern VSP2, and the horizontal semiconductor pattern HSPs can be connected to each other for integral configuration and can be referred to as semiconductor patterns. Semiconductor patterns VSP1, VSP2, and HSPs can have a U-shape in cross-sectional view.

[0102] Gate electrodes GE can be disposed on bit lines BL and insulating patterns 110, and can intersect bit lines BL and insulating patterns 110. Gate electrodes GE can extend in a second direction D2 and can be spaced apart from each other in a first direction D1. Gate electrodes GE can include a first gate electrode GE1 on a first side surface S1 of each of the mold structures MS and a second gate electrode GE2 on a second side surface S2 of each of the mold structures MS.

[0103] A first vertical semiconductor pattern VSP1 can be interposed between the first gate electrode GE1 and the first side surface S1 of each of the mold structures MS. The first vertical semiconductor pattern VSP1 can also be interposed between the first gate electrode GE1 and the first protruding side surface PS1 of the first portion P1 of each of the mold structures MS. According to some embodiments, the first gate electrode GE1 can conformally extend along the first protruding side surface PS1 of the first portion P1 of each of the mold structures MS. A second vertical semiconductor pattern VSP2 can be interposed between the second gate electrode GE2 and the second side surface S2 of each of the mold structures MS. The second vertical semiconductor pattern VSP2 can also be interposed between the second gate electrode GE2 and the second protruding side surface PS2 of the first portion P1 of each of the mold structures MS. According to some embodiments, the second gate electrode GE2 can conformally extend along the second protruding side surface PS2 of the first portion P1 of each of the mold structures MS.

[0104] A gate insulating pattern GI can be interposed between each of the module structure MS and each of the gate electrodes GE. The gate insulating pattern GI can be interposed between the first gate electrode GE1 and the first side surface S1 of each of the module structure MS, and can extend between the first vertical semiconductor pattern VSP1 and the first gate electrode GE1. The gate insulating pattern GI can be interposed between the second gate electrode GE2 and the second side surface S2 of each of the module structure MS, and can extend between the second vertical semiconductor pattern VSP2 and the second gate electrode GE2. The gate insulating pattern GI can extend between the horizontal semiconductor pattern HSP and each of the gate electrodes GE, and can extend between each of the insulating patterns 110 and each of the gate electrodes GE.

[0105] According to some embodiments, the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 can be respectively disposed on the first protrusion side surface PS1 and the second protrusion side surface PS2 of the first portion P1 of each of the module structure MS, and can extend conformally along the first protrusion side surface PS1 and the second protrusion side surface PS2. Therefore, in a planar view, the area of ​​each of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 can be increased. As a result, the channel width of the vertical channel transistor using the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 as the channel can be increased, thereby improving the operating characteristics of the vertical channel transistor. Furthermore, since the area of ​​each of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 is increased, the contact area between each of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 and each of the node contacts 175 can be increased. Therefore, the resistance between each of the first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 and each of the node contacts 175 can be reduced, thereby improving the electrical characteristics of the vertical channel transistor.

[0106] Figure 26 and Figure 29 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 27 , Figure 28 , Figure 30 and Figure 31 This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 27 and Figure 28 They are respectively along Figure 26 The cross-sectional views taken from A-A' and B-B', and Figure 30 and Figure 31 They are respectively along Figure 29 The cross-sectional views are taken along lines A-A' and B-B'. For simplicity, the main description will be compared with the references. Figures 7 to 22 The differences described in the methods used to manufacture semiconductor devices.

[0107] refer to Figures 26 to 28 Bit lines BL can be formed on substrate 100, and insulating patterns 110 can be formed between bit lines BL. Mold structures MS can be formed on bit lines BL and insulating patterns 110, and can intersect bit lines BL and insulating patterns 110. Each of the mold structures MS can have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1.

[0108] A mask film 200 may be formed on bit lines BL and insulating patterns 110, and may cover or at least partially overlap with mold structures MS. The mask film 200 may have a plurality of openings 200P spaced apart from each other in a first direction D1 and a second direction D2. According to some embodiments, each of the plurality of openings 200P may expose portions of a pair of mold structures MS that are adjacent to or next to each other, and the upper surface of the insulating pattern 110 between the pair of mold structures MS. That is, each of the plurality of openings 200P may expose a first side surface S1 of one of the pair of mold structures MS and a second side surface S2 of the other of the pair of mold structures MS, as well as the upper surface of the insulating pattern 110 between the pair of mold structures MS.

[0109] refer to Figures 29 to 31 An etching process using a mask film 200 as an etching mask can be performed, and the portion of the mold structure MS exposed by the plurality of openings 200P can be etched by the etching process. Each of the mold structures MS can include a first portion P1 having a first width W1 and a second portion P2 having a second width W2 less than or equal to the first width W1. The first portion P1 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the bit lines BL, and the second portion P2 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the insulating patterns 110 between the bit lines BL.

[0110] Each of the first side surface S1 and the second side surface S2 of each of the mold structures MS can have a non-flat structure by an etching process. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first protruding side surface PS1 protruding or extending from each of the mold structures MS in the first portion P1 (e.g., the first protruding side surface PS1 extends away from the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first protrusion defined by the first protruding side surface PS1. The second side surface S2 of each of the mold structures MS may have a second protruding side surface PS2 protruding or extending from each of the mold structures MS in the first portion P1 (e.g., the second protruding side surface PS2 extends away from the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second protrusion defined by the second protruding side surface PS2. The first protruding side surface PS1 and the second protruding side surface PS2 may face each other in a first direction D1 and may be mirror images (or symmetrical) to each other.

[0111] The mask 200 can be removed after the etching process. Afterwards, it can be essentially aligned with the reference. Figures 4 to 6 and Figures 13 to 22 The process described for manufacturing semiconductor devices is performed in the same manner.

[0112] Figure 32 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. Along Figure 32 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 5 and Figure 6 They are essentially the same. For the sake of simplicity, details have been omitted. Figure 4 and Figure 23 The diagram shows the placement pad LP. For simplicity, the main description will be based on the references. Figures 4 to 6 The differences described in the semiconductor devices.

[0113] refer to Figure 5 , Figure 6 and Figure 32 The mold structure MS can be disposed on the bit line BL and the insulating pattern 110, and can intersect with the bit line BL and the insulating pattern 110. The mold structure MS can extend in the second direction D2 and can be spaced apart from each other in the first direction D1.

[0114] Each of the module structures MS may include a first portion P1 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the bit lines BL and a second portion P2 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the insulating patterns 110 between the bit lines BL. The first width W1 of the first portion P1 may differ from the second width W2 of the second portion P2. According to some embodiments, the first width W1 of the first portion P1 may be smaller than or less than the second width W2 of the second portion P2.

[0115] Each of the mold structures MS may have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1. Each of the first side surface S1 and the second side surface S2 may have a non-flat structure. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed from a first portion P1 toward the interior of each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. According to some embodiments, the width of the first recessed region along the second direction D2 may decrease in a direction that gets closer to or closer to each of the mold structures MS, and the first recessed region may have a tapered shape toward each of the mold structures MS. Additionally, the width of the second recessed region along the second direction D2 may decrease in a direction that gets closer to or closer to each of the mold structures MS, and the second recessed region may have a tapered shape toward each of the mold structures MS. The first recessed side surface RS1 and the second recessed side surface RS2 may face each other in the first direction D1 and may be asymmetrical.

[0116] In addition to the differences mentioned above, according to Figure 32 Semiconductor devices and references of embodiments illustrated in the figure Figures 4 to 6 The semiconductor devices described are basically the same.

[0117] Figure 33 and Figure 34 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Except for the shape of the opening 200P, along... Figure 33 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 8 and Figure 9Basically the same, and along Figure 34 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 11 and Figure 12 They are essentially the same. To simplify the description, the main description and references will be presented separately. Figures 7 to 22 The differences described in the methods used to manufacture semiconductor devices.

[0118] refer to Figure 8 , Figure 9 and Figure 33 Bit lines BL can be formed on substrate 100, and insulating patterns 110 can be formed between bit lines BL. Mold structures MS can be formed on bit lines BL and insulating patterns 110, and can intersect bit lines BL and insulating patterns 110. Each of the mold structures MS can have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1.

[0119] A mask film 200 may be formed on bit lines BL and insulating patterns 110, and may cover or at least partially overlap with mold structures MS. The mask film 200 may have a plurality of openings 200P spaced apart from each other in a first direction D1 and a second direction D2. According to some embodiments, each of the plurality of openings 200P may have the shape of a strip extending parallel to the upper surface 100U of the substrate 100 and in a fourth direction D4, which is parallel to the upper surface 100U of the substrate 100 and intersects the first direction D1 and the second direction D2. Each of the plurality of openings 200P may expose portions of a pair of mold structures MS that are adjacent to each other and the upper surface of the insulating pattern 110 between the pair of mold structures MS. That is, each of the plurality of openings 200P may expose a first side surface S1 of one of the pair of mold structures MS and a second side surface S2 of the other of the pair of mold structures MS, as well as the upper surface of the insulating pattern 110 between the pair of mold structures MS.

[0120] refer to Figure 11 , Figure 12 and Figure 34 An etching process using a mask film 200 as an etching mask can be performed, and the portion of the mold structure MS exposed by the plurality of openings 200P can be etched by the etching process. Each of the mold structures MS can include a first portion P1 having a first width W1 and a second portion P2 having a second width W2 greater than the first width W1. The first portion P1 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the bit lines BL, and the second portion P2 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the insulating patterns 110 between the bit lines BL.

[0121] Each of the first side surface S1 and the second side surface S2 of each of the mold structures MS can have a non-flat structure by an etching process. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. According to some embodiments, the width of the first recessed region along the second direction D2 may decrease in a direction that gets closer to or near each of the mold structures MS, and the first recessed region may have a tapered shape toward each of the mold structures MS. Furthermore, the width of the second recessed region along the second direction D2 can decrease in a direction that gets closer to or closer to each of the mold structures MS, and the second recessed region can have a tapered shape toward each of the mold structures MS. The first recessed side surface RS1 and the second recessed side surface RS2 can face each other in the first direction D1 and can be asymmetrical.

[0122] The mask 200 can be removed after the etching process. Afterwards, it can be essentially aligned with the reference. Figures 4 to 6 and Figures 13 to 22 The process described for manufacturing semiconductor devices is performed in the same manner.

[0123] Figure 35 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. Along Figure 35 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 5 and Figure 6 They are essentially the same. For the sake of simplicity, details have been omitted. Figure 4 and Figure 23 The diagram shows the placement pad LP. For simplicity, the main description will be based on the references. Figures 4 to 6 The differences described in the semiconductor devices.

[0124] refer to Figure 5 , Figure 6 and Figure 35The mold structure MS can be disposed on the bit line BL and the insulating pattern 110, and can intersect with the bit line BL and the insulating pattern 110. The mold structure MS can extend in the second direction D2 and can be spaced apart from each other in the first direction D1.

[0125] Each of the module structures MS may include a first portion P1 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the bit lines BL and a second portion P2 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the insulating patterns 110 between the bit lines BL. The first width W1 of the first portion P1 may differ from the second width W2 of the second portion P2. According to some embodiments, the first width W1 of the first portion P1 may be smaller than or less than the second width W2 of the second portion P2.

[0126] Each of the mold structures MS may have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1. Each of the first side surface S1 and the second side surface S2 may have a non-flat structure. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed from a first portion P1 toward the interior of each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. According to some embodiments, the width of the first recessed region along the second direction D2 may decrease in a direction that gets closer to or closer to each of the mold structures MS, and the first recessed region may have a tapered shape toward each of the mold structures MS. Additionally, the width of the second recessed region along the second direction D2 may decrease in a direction that gets closer to or closer to each of the mold structures MS, and the second recessed region may have a tapered shape toward each of the mold structures MS. The first recessed side surface RS1 and the second recessed side surface RS2 may face each other in the first direction D1 and may be mirror images (or symmetrical) to each other.

[0127] In addition to the differences mentioned above, according to Figure 35 Semiconductor devices and references of embodiments illustrated in the figure Figures 4 to 6 The semiconductor devices described are basically the same.

[0128] Figure 36 and Figure 37This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Along Figure 36 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 8 and Figure 9 Basically the same, and along Figure 37 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 11 and Figure 12 They are essentially the same. To simplify the description, the main description will be compared with the reference. Figures 7 to 22 The differences described in the methods used to manufacture semiconductor devices.

[0129] refer to Figure 8 , Figure 9 and Figure 36 Bit lines BL can be formed on substrate 100, and insulating patterns 110 can be formed between bit lines BL. Mold structures MS can be formed on bit lines BL and insulating patterns 110, and can intersect bit lines BL and insulating patterns 110. Each of the mold structures MS can have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1.

[0130] A mask film 200 may be formed on bit lines BL and insulating patterns 110, and may cover or at least partially overlap with the mold structure MS. The mask film 200 may have a plurality of openings 200P spaced apart from each other in a first direction D1 and a second direction D2. According to some embodiments, each of the plurality of openings 200P may have a rhomboid shape and may partially expose the corresponding mold structure MS within the mold structure MS. Each of the plurality of openings 200P may expose a first side surface S1 or a second side surface S2 of the corresponding mold structure MS. A pair of openings 200P that are adjacent or close to each other in the first direction D1 may respectively expose the first side surface S1 and the second side surface S2 of each of the mold structures MS. Openings 200P in a first column of the plurality of openings 200P may be spaced apart from each other in the second direction D2 along the first side surface S1 of each of the mold structures MS, and may expose the first side surface S1 of each of the mold structures MS. The openings 200P in the second column of the plurality of openings 200P can be spaced apart from each other along the second side surface S2 of each of the mold structure MS in the second direction D2, and can expose the second side surface S2 of each of the mold structure MS.

[0131] refer to Figure 11 , Figure 12 and Figure 37An etching process using a mask film 200 as an etching mask can be performed, and the portion of the mold structure MS exposed by the plurality of openings 200P can be etched by the etching process. Each of the mold structures MS can include a first portion P1 having a first width W1 and a second portion P2 having a second width W2 greater than the first width W1. The first portion P1 of each of the mold structures MS can overlap perpendicularly (e.g., in the third direction D3) with at least a portion of each of the bit lines BL, and the second portion P2 of each of the mold structures MS can overlap perpendicularly (e.g., in the third direction D3) with at least a portion of each of the insulating patterns 110 between the bit lines BL.

[0132] Each of the first side surface S1 and the second side surface S2 of each of the mold structures MS can have a non-flat structure by an etching process. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. According to some embodiments, the width of the first recessed region along the second direction D2 may decrease in a direction that gets closer to or near each of the mold structures MS, and the first recessed region may have a tapered shape toward each of the mold structures MS. Furthermore, the width of the second recessed region along the second direction D2 may decrease in a direction that gets closer to or closer to each of the mold structures MS, and the second recessed region may have a tapered shape toward each of the mold structures MS. The first recessed side surface RS1 and the second recessed side surface RS2 may face each other in the first direction D1 and may be mirror images (or symmetrical) to each other.

[0133] The mask 200 can be removed after the etching process. Afterwards, it can be essentially aligned with the reference. Figures 4 to 6 and Figures 13 to 22 The process described for manufacturing semiconductor devices is performed in the same manner.

[0134] Figure 38 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. Along Figure 38 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 5and Figure 6 They are essentially the same. For the sake of simplicity, details have been omitted. Figure 4 and Figure 23 The diagram shows the placement pad LP. For simplicity, the main description will be based on the references. Figures 4 to 6 The differences described in the semiconductor devices.

[0135] refer to Figure 5 , Figure 6 and Figure 38 The mold structure MS can be disposed on the bit line BL and the insulating pattern 110, and can intersect with the bit line BL and the insulating pattern 110. The mold structure MS can extend in the second direction D2 and can be spaced apart from each other in the first direction D1.

[0136] Each of the module structures MS may include a first portion P1 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the bit lines BL and a second portion P2 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the insulating patterns 110 between the bit lines BL. The first width W1 of the first portion P1 may differ from the second width W2 of the second portion P2. According to some embodiments, the first width W1 of the first portion P1 may be smaller than or less than the second width W2 of the second portion P2.

[0137] Each of the mold structures MS may have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1. Each of the first side surface S1 and the second side surface S2 may have a non-flat structure. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed from a first portion P1 toward the interior of each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. According to some embodiments, each of the first recessed side surface RS1 and the second recessed side surface RS2 may be a rounded side surface extending toward the interior of each of the mold structures MS. The first recessed side surface RS1 and the second recessed side surface RS2 can face each other in the first direction D1 and can be mirror images (or symmetrical) of each other.

[0138] In addition to the differences mentioned above, according to Figure 38Semiconductor devices and references of embodiments illustrated in the figure Figures 4 to 6 The semiconductor devices described are basically the same.

[0139] Figure 39 and Figure 40 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Along Figure 39 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 8 and Figure 9 Basically the same, and along Figure 40 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 11 and Figure 12 They are essentially the same. To simplify the description, the main description will be compared with the reference. Figures 7 to 22 The differences described in the methods used to manufacture semiconductor devices.

[0140] refer to Figure 8 , Figure 9 and Figure 39 Bit lines BL can be formed on substrate 100, and insulating patterns 110 can be formed between bit lines BL. Mold structures MS can be formed on bit lines BL and insulating patterns 110, and can intersect bit lines BL and insulating patterns 110. Each of the mold structures MS can have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1.

[0141] A mask film 200 may be formed on bit lines BL and insulating patterns 110, and may cover or at least partially overlap with the mold structure MS. The mask film 200 may have a plurality of openings 200P spaced apart from each other in a first direction D1 and a second direction D2. According to some embodiments, each of the plurality of openings 200P may have a circular shape and may partially expose the corresponding mold structure MS within the mold structure MS. Each of the plurality of openings 200P may expose a first side surface S1 or a second side surface S2 of the corresponding mold structure MS. A pair of openings 200P that are adjacent or close to each other in the first direction D1 may respectively expose the first side surface S1 and the second side surface S2 of each of the mold structures MS. Openings 200P in a first column of the plurality of openings 200P may be spaced apart from each other along the first side surface S1 of each of the mold structures MS in the second direction D2, and may expose the first side surface S1 of each of the mold structures MS. The openings 200P in the second column of the plurality of openings 200P can be spaced apart from each other along the second side surface S2 of each of the mold structure MS in the second direction D2, and can expose the second side surface S2 of each of the mold structure MS.

[0142] refer to Figure 11 , Figure 12 and Figure 40 An etching process using a mask film 200 as an etching mask can be performed, and the portion of the mold structure MS exposed by the plurality of openings 200P can be etched by the etching process. Each of the mold structures MS can include a first portion P1 having a first width W1 and a second portion P2 having a second width W2 greater than the first width W1. The first portion P1 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the bit lines BL, and the second portion P2 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the insulating patterns 110 between the bit lines BL.

[0143] Each of the first side surface S1 and the second side surface S2 of each of the mold structures MS can have a non-flat structure by an etching process. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed from a first portion P1 toward the interior of each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. According to some embodiments, each of the first recessed side surface RS1 and the second recessed side surface RS2 may be a rounded side surface extending toward the interior of each of the mold structures MS. The first recessed side surface RS1 and the second recessed side surface RS2 can face each other in the first direction D1 and can be mirror images (or symmetrical) of each other.

[0144] The mask 200 can be removed after the etching process. Afterwards, it can be essentially aligned with the reference. Figures 4 to 6 and Figures 13 to 22 The process described for manufacturing semiconductor devices is performed in the same manner.

[0145] Figure 41 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. Along Figure 41 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 5 and Figure 6 They are essentially the same. For the sake of simplicity, details have been omitted. Figure 4 and Figure 23 The diagram shows the placement pad LP. For simplicity, the main description will be based on the references. Figures 4 to 6 The differences described in the semiconductor devices.

[0146] refer to Figure 5 , Figure 6 and Figure 41 The mold structure MS can be disposed on the bit line BL and the insulating pattern 110, and can intersect with the bit line BL and the insulating pattern 110. The mold structure MS can extend in the second direction D2 and can be spaced apart from each other in the first direction D1.

[0147] Each of the module structures MS may include a first portion P1 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the bit lines BL and a second portion P2 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the insulating patterns 110 between the bit lines BL. The first width W1 of the first portion P1 may differ from the second width W2 of the second portion P2. According to some embodiments, the first width W1 of the first portion P1 may be smaller than or less than the second width W2 of the second portion P2.

[0148] Each of the mold structures MS may have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1. Each of the first side surface S1 and the second side surface S2 may have a non-flat structure. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed into each of the mold structures MS from a first portion P1 that perpendicularly overlaps with at least a portion of the odd bit lines BL in the bit lines BL. Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed into each of the mold structures MS from a first portion P1 that perpendicularly overlaps with at least a portion of the even bit lines BL in the bit lines BL. Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. According to some embodiments, each of the mold structures MS may have a shape in which the first recessed side surface RS1 and the second recessed side surface RS2 are arranged alternately in a second direction D2.

[0149] The first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 can be disposed on each of the bit lines BL and can be spaced apart from each other in the first direction D1, with each of the module structures MS located therebetween. The first vertical semiconductor pattern VSP1 and the second vertical semiconductor pattern VSP2 can be spaced apart from each other in the first direction D1, with the first portion P1 of each of the module structures MS located therebetween.

[0150] A first vertical semiconductor pattern VSP1 on an odd-numbered bit line BL can be disposed on a first recessed side surface RS1 of a first portion P1 and can conformally extend along the first recessed side surface RS1. The first vertical semiconductor pattern VSP1 on the odd-numbered bit line BL can partially fill the first recessed region. A second vertical semiconductor pattern VSP2 on an odd-numbered bit line BL can be disposed on a second side surface S2 of the first portion P1. A first vertical semiconductor pattern VSP1 on an even-numbered bit line BL can be disposed on a first side surface S1 of the first portion P1. A second vertical semiconductor pattern VSP2 on an even-numbered bit line BL can be disposed on a second recessed side surface RS2 of the first portion P1 and can conformally extend along the second recessed side surface RS2. The second vertical semiconductor pattern VSP2 on the even-numbered bit line BL can partially fill the second recessed region.

[0151] Horizontal semiconductor patterns HSPs can be disposed on each bit line BL and between module structures MS. Horizontal semiconductor patterns HSPs can be disposed between adjacent or contiguous pairs of module structures MS. Horizontal semiconductor patterns HSPs on odd-numbered bit lines BL can connect the lower portion of a first vertical semiconductor pattern VSP1 disposed on the first recessed side surface RS1 of the first portion P1 of one pair of module structures MS and the lower portion of a second vertical semiconductor pattern VSP2 disposed on the second side surface S2 of the first portion P1 of the other pair of module structures MS. Horizontal semiconductor patterns HSPs on even-numbered bit lines BL can connect the lower portion of the first vertical semiconductor pattern VSP1 disposed on the first side surface S1 of the first portion P1 of one pair of module structures MS and the lower portion of the second vertical semiconductor pattern VSP2 disposed on the second recessed side surface RS2 of the first portion P1 of the other pair of module structures MS.

[0152] In addition to the differences mentioned above, according to Figure 41 Semiconductor devices and references of embodiments illustrated in the figure Figures 4 to 6 The semiconductor devices described are basically the same.

[0153] Figure 42 and Figure 43 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Except for the shape of the opening 200P, along... Figure 42 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 8 and Figure 9 Basically the same, and along Figure 43 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 11 and Figure 12 They are essentially the same. To simplify the description, the main description and references will be presented separately. Figures 7 to 22 The differences described in the methods used to manufacture semiconductor devices.

[0154] refer to Figure 8 , Figure 9 and Figure 42 Bit lines BL can be formed on substrate 100, and insulating patterns 110 can be formed between bit lines BL. Mold structures MS can be formed on bit lines BL and insulating patterns 110, and can intersect bit lines BL and insulating patterns 110. Each of the mold structures MS can have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1.

[0155] A mask film 200 may be formed on bit lines BL and insulating patterns 110, and may cover or at least partially overlap with the mold structure MS. The mask film 200 may have a plurality of openings 200P spaced apart from each other in a first direction D1 and extending in a second direction D2. According to some embodiments, each of the plurality of openings 200P may have a non-linear shape, such as a waveform, extending in the second direction D2. Each of the plurality of openings 200P may be arranged in a planar view between a pair of mold structures MS that are adjacent to each other, and may alternately expose a first side surface S1 of one of the pair of mold structures MS and a second side surface S2 of the other of the pair of mold structures MS along the second direction D2.

[0156] refer to Figure 11 , Figure 12 and Figure 43 An etching process using a mask film 200 as an etching mask can be performed, and the portion of the mold structure MS exposed by the plurality of openings 200P can be etched by the etching process. Each of the mold structures MS can include a first portion P1 having a first width W1 and a second portion P2 having a second width W2 greater than the first width W1. The first portion P1 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the bit lines BL, and the second portion P2 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the insulating patterns 110 between the bit lines BL.

[0157] Each of the first side surface S1 and the second side surface S2 of each of the mold structures MS can have a non-flat structure by an etching process. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed into the interior of each of the mold structures MS from a first portion P1 that perpendicularly overlaps with at least a portion of the odd-numbered bit lines BL in the bit lines BL. Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed into the interior of each of the mold structures MS from a first portion P1 that perpendicularly overlaps with at least a portion of the even-numbered bit lines BL in the bit lines BL. Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2. According to some embodiments, each of the mold structures MS may have a shape in which the first recessed side surface RS1 and the second recessed side surface RS2 are arranged alternately in a second direction D2.

[0158] The mask 200 can be removed after the etching process. Afterwards, it can be essentially aligned with the reference. Figures 4 to 6 and Figures 13 to 22 The process described for manufacturing semiconductor devices is performed in the same manner.

[0159] Figure 44 This is a plan view of a semiconductor device according to some embodiments of the present disclosure. Along Figure 44 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 5 and Figure 6 They are essentially the same. For the sake of simplicity, details have been omitted. Figure 4 and Figure 23 The diagram shows the placement pad LP. For simplicity, the main description will be based on the references. Figures 4 to 6 The differences described in the semiconductor devices.

[0160] refer to Figure 5 , Figure 6 and Figure 44 The mold structure MS can be disposed on the bit line BL and the insulating pattern 110, and can intersect with the bit line BL and the insulating pattern 110. The mold structure MS can extend in the second direction D2 and can be spaced apart from each other in the first direction D1.

[0161] Each of the module structures MS may include a first portion P1 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the bit lines BL and a second portion P2 that vertically (e.g., in the third direction D3) overlaps at least a portion of each of the insulating patterns 110 between the bit lines BL. The first width W1 of the first portion P1 may differ from the second width W2 of the second portion P2. According to some embodiments, the first width W1 of the first portion P1 may be smaller than or less than the second width W2 of the second portion P2.

[0162] Each of the mold structures MS may have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1. Each of the first side surface S1 and the second side surface S2 may have a non-flat structure. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed from a first portion P1 toward the interior of each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2.

[0163] According to some embodiments, the first recessed side surface RS1 may be a rounded side surface extending toward the interior of each of the mold structures MS, and the width of the first recessed region along the second direction D2 may decrease in a direction that gets closer to or closer to each of the mold structures MS. The second recessed side surface RS2 may be a rounded side surface extending toward the interior of each of the mold structures MS, and the width of the second recessed region along the second direction D2 may decrease in a direction that gets closer to or closer to each of the mold structures MS. The first recessed side surface RS1 and the second recessed side surface RS2 may face each other in the first direction D1 and may be asymmetrical.

[0164] In addition to the differences mentioned above, according to Figure 44 Semiconductor devices and references of embodiments illustrated in the figure Figures 4 to 6 The semiconductor devices described are basically the same.

[0165] Figure 45 and Figure 46 This is a plan view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present disclosure. Except for the shape of the opening 200P, along... Figure 45The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 8 and Figure 9 Basically the same, and along Figure 46 The cross-sectional views taken from A-A' and B-B' are respectively compared with Figure 11 and Figure 12 They are essentially the same. To simplify the description, the main description and references will be presented separately. Figures 7 to 22 The differences described in the methods used to manufacture semiconductor devices.

[0166] refer to Figure 8 , Figure 9 and Figure 45 Bit lines BL can be formed on substrate 100, and insulating patterns 110 can be formed between bit lines BL. Mold structures MS can be formed on bit lines BL and insulating patterns 110, and can intersect bit lines BL and insulating patterns 110. Each of the mold structures MS can have a first side surface S1 and a second side surface S2 that are opposite to each other in a first direction D1.

[0167] A mask film 200 may be formed on bit lines BL and insulating patterns 110, and may cover or at least partially overlap with mold structures MS. The mask film 200 may have a plurality of openings 200P spaced apart from each other in a first direction D1 and a second direction D2. According to some embodiments, each of the plurality of openings 200P may have an elliptical shape having a major axis parallel to a fourth direction D4. Each of the plurality of openings 200P may expose portions of a pair of adjacent mold structures MS and the upper surface of the insulating pattern 110 between the pair of mold structures MS. That is, each of the plurality of openings 200P may expose a first side surface S1 of one of the pair of mold structures MS and a second side surface S2 of the other of the pair of mold structures MS, as well as the upper surface of the insulating pattern 110 between the pair of mold structures MS.

[0168] refer to Figure 11 , Figure 12 and Figure 46 An etching process using a mask film 200 as an etching mask can be performed, and the portion of the mold structure MS exposed by the plurality of openings 200P can be etched by the etching process. Each of the mold structures MS can include a first portion P1 having a first width W1 and a second portion P2 having a second width W2 greater than the first width W1. The first portion P1 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the bit lines BL, and the second portion P2 of each of the mold structures MS can vertically (e.g., in the third direction D3) overlap at least a portion of each of the insulating patterns 110 between the bit lines BL.

[0169] Each of the first side surface S1 and the second side surface S2 of each of the mold structures MS can have a non-flat structure by an etching process. According to some embodiments, the first side surface S1 of each of the mold structures MS may have a first recessed side surface RS1 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the first recessed side surface RS1 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a first recessed region defined by the first recessed side surface RS1. The second side surface S2 of each of the mold structures MS may have a second recessed side surface RS2 that is recessed from the first portion P1 toward the interior of each of the mold structures MS (e.g., the second recessed side surface RS2 extends toward the center of the mold structure MS). Therefore, the first portion P1 of each of the mold structures MS may include a second recessed region defined by the second recessed side surface RS2.

[0170] According to some embodiments, the first recessed side surface RS1 may be a rounded side surface extending toward the interior of each of the mold structures MS, and the width of the first recessed region along the second direction D2 may decrease in a direction that gets closer to or closer to each of the mold structures MS. The second recessed side surface RS2 may be a rounded side surface extending toward the interior of each of the mold structures MS, and the width of the second recessed region along the second direction D2 may decrease in a direction that gets closer to or closer to each of the mold structures MS. The first recessed side surface RS1 and the second recessed side surface RS2 may face each other in the first direction D1 and may be asymmetrical.

[0171] The mask 200 can be removed after the etching process. Afterwards, it can be essentially aligned with the reference. Figures 4 to 6 and Figures 13 to 22 The process described for manufacturing semiconductor devices is performed in the same manner.

[0172] According to this disclosure, a vertical semiconductor pattern can be disposed on one side surface of the mold structure and can conformally extend along the uneven structure of the side surface of the mold structure. Therefore, in a planar view, the area of ​​the vertical semiconductor pattern can be increased. As a result, the channel width of a vertical channel transistor using the vertical semiconductor pattern as the channel can be increased, thus improving the operating characteristics of the vertical channel transistor.

[0173] Furthermore, the increased area of ​​the vertical semiconductor pattern allows for a larger contact area between the vertical semiconductor pattern and the node contact. This reduces the resistance between the vertical semiconductor pattern and the node contact, thereby improving the electrical characteristics of the vertical channel transistor.

[0174] Therefore, it is possible to provide semiconductor devices including vertical channel transistors and methods for manufacturing the same, wherein the vertical channel transistors have increased channel width and improved operating and electrical characteristics.

[0175] Although embodiments of this disclosure have been described, it should be understood that this disclosure is not limited to these embodiments, but rather that various changes and modifications can be made by those skilled in the art within the scope of this disclosure as defined in the claims.

[0176] This application claims priority to Korean Patent Application No. 10-2024-0125773, filed on September 13, 2024, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: Bit lines extend on the substrate in a first direction and are spaced apart from each other in a second direction, the first direction and the second direction being parallel to the upper surface of the substrate and intersecting each other; An insulating pattern, between the bit lines and extending in the first direction; The mold structure extends in the second direction on the bit lines and the insulating pattern, and includes a first portion that at least partially overlaps with each bit line in the bit lines in a third direction perpendicular to the upper surface of the substrate, and a second portion that at least partially overlaps with the insulating pattern in the third direction. A first vertical semiconductor pattern and a second vertical semiconductor pattern are spaced apart from each other on the bit line and in the first direction, and the first portion of the mold structure is between the first vertical semiconductor pattern and the second vertical semiconductor pattern. as well as A first gate electrode and a second gate electrode are spaced apart from each other in the first direction, and the mold structure is located between the first gate electrode and the second gate electrode, which extend in the second direction and are located on the bit line and the insulating pattern. The first vertical semiconductor pattern is located between the first gate electrode and the mold structure. The second vertical semiconductor pattern is located between the second gate electrode and the mold structure, and The first width of the first portion of the mold structure in the first direction is different from the second width of the second portion of the mold structure in the first direction.

2. The semiconductor device according to claim 1, wherein the first width is smaller than the second width.

3. The semiconductor device according to claim 2, wherein: The first portion of the mold structure includes a first side surface and a second side surface that are opposite to each other in the first direction. The first side surface includes a first recessed side surface extending toward the center of the mold structure, and The second side surface includes a second recessed side surface extending toward the center of the mold structure.

4. The semiconductor device according to claim 3, wherein: The first vertical semiconductor pattern extends along the first recessed side surface of the first side surface of the mold structure, and The second vertical semiconductor pattern extends along the second recessed side surface of the second side surface of the mold structure.

5. The semiconductor device of claim 4, further comprising a gate insulating pattern between the first gate electrode and the first vertical semiconductor pattern and between the second gate electrode and the second vertical semiconductor pattern.

6. The semiconductor device of claim 1, wherein the first width is greater than the second width.

7. The semiconductor device according to claim 6, wherein: The first portion of the mold structure includes a first side surface and a second side surface that are opposite to each other in the first direction. The first side surface includes a first protruding side surface extending away from the center of the mold structure, and The second side surface includes a second protruding side surface extending away from the center of the mold structure.

8. The semiconductor device according to claim 7, wherein: The first vertical semiconductor pattern extends along the first protruding side surface of the first side surface of the mold structure, and The second vertical semiconductor pattern extends along the second protruding side surface of the second side surface of the mold structure.

9. The semiconductor device of claim 8, further comprising a gate insulating pattern between the first gate electrode and the first vertical semiconductor pattern and between the second gate electrode and the second vertical semiconductor pattern.

10. The semiconductor device according to claim 1, wherein: The mold structure includes a first side surface and a second side surface that are opposite to each other in the first direction. The first vertical semiconductor pattern is located between the first gate electrode and the first side surface of the mold structure. The second vertical semiconductor pattern is located between the second gate electrode and the second side surface of the mold structure, and Each of the first side surface and the second side surface has a non-linear shape in the second direction.

11. A semiconductor device, comprising: Bit lines extend on the substrate in a first direction; The mold structure extends on the bit line in a second direction, the first direction and the second direction being parallel to the upper surface of the substrate and intersecting each other; as well as A first vertical semiconductor pattern and a second vertical semiconductor pattern are spaced apart from each other on the bit line and in the first direction, and the mold structure is located between the first vertical semiconductor pattern and the second vertical semiconductor pattern. The mold structure includes a first portion having a first width in the first direction and a second portion having a second width in the first direction, the second width being different from the first width. The first portion of the mold structure at least partially overlaps the bit line in a third direction perpendicular to the upper surface of the substrate and lies between the first vertical semiconductor pattern and the second vertical semiconductor pattern.

12. The semiconductor device according to claim 11, wherein: The mold structure includes a first side surface and a second side surface that are opposite to each other in the first direction, and Each of the first and second side surfaces of the mold structure has a non-linear shape in the second direction.

13. The semiconductor device of claim 11, wherein the first width is smaller than the second width.

14. The semiconductor device according to claim 13, wherein: The first portion of the mold structure has a first side surface and a second side surface that are opposite to each other in the first direction. The first portion of the mold structure includes a first recessed region extending toward the center of the mold structure, and The first vertical semiconductor pattern is in the first recessed region.

15. The semiconductor device according to claim 14, wherein: The first portion of the mold structure includes a second recessed region extending toward the center of the mold structure, and The second vertical semiconductor pattern is in the second recessed region.

16. The semiconductor device of claim 11, wherein the first width is greater than the second width.

17. The semiconductor device according to claim 16, wherein: The first portion of the mold structure includes a first side surface and a second side surface that are opposite to each other in the first direction. The first portion of the mold structure includes a first protrusion extending from the first side surface, and The first vertical semiconductor pattern is on the first protrusion.

18. The semiconductor device according to claim 17, wherein: The first portion of the mold structure includes a second protrusion extending from the second side surface, and The second vertical semiconductor pattern is on the second protrusion.

19. A semiconductor device, comprising: Bit lines extend on the substrate in a first direction; A mold structure extends along the bit line in a second direction and includes a first side surface and a second side surface opposite to each other in the first direction, the first direction and the second direction being parallel to the upper surface of the substrate and intersecting each other; as well as A first vertical semiconductor pattern and a second vertical semiconductor pattern are located on the bit line and respectively on the first side surface and the second side surface of the mold structure. Each of the first and second side surfaces of the mold structure includes a non-linear portion. Wherein the first vertical semiconductor pattern extends along the nonlinear portion of the first side surface, and The second vertical semiconductor pattern extends along the nonlinear portion of the second side surface.

20. The semiconductor device of claim 19, further comprising: A first gate electrode extends on the first side surface of the mold structure and in the second direction; as well as The second gate electrode extends on the second side surface of the mold structure and in the second direction. The first vertical semiconductor pattern is located between the first gate electrode and the first side surface of the mold structure, and The second vertical semiconductor pattern is located between the second gate electrode and the second side surface of the mold structure.

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