Semiconductor memory device

Abstract

A semiconductor memory device includes a substrate, a plurality of word lines stacked in a first direction on the substrate, a channel region extending between adjacent word lines in the first direction and in a second direction, a first source / drain region at a first side of the channel region, a second source / drain region at a second side of the channel region, bit lines extending in a first direction on the substrate and connected to respective ones of the first source / drain regions, respectively, data storage elements connected to respective ones of the second source / drain regions, respectively, and capping films between respective ones of the data storage elements and the second source / drain regions, respectively, the cover films respectively include insertion holes, wherein at least portions of the second source / drain regions are respectively inserted into corresponding ones of the insertion holes of the cover films.

Description

Technical Field

[0001] This disclosure relates to semiconductor memory devices. Background Technology

[0002] In the case of conventional two-dimensional (2D) or planar semiconductor devices, integration density is primarily determined by the area occupied by a single memory cell and is therefore significantly influenced by the level of fine patterning technology. However, due to the need for extremely expensive equipment for fine patterning, the integration density of 2D semiconductor devices, despite its increasing capabilities, remains limited. Therefore, three-dimensional (3D) semiconductor memory devices incorporating memory cells arranged in three dimensions have been proposed. Summary of the Invention

[0003] Some exemplary embodiments of this disclosure provide semiconductor memory devices with improved performance and reliability.

[0004] However, the exemplary embodiments of this disclosure are not limited to those set forth herein. The above and other aspects of this disclosure will become more apparent to those skilled in the art upon which this disclosure pertains by referring to the detailed description of some exemplary embodiments given below.

[0005] According to an exemplary embodiment of this disclosure, a semiconductor memory device includes a substrate, a plurality of word lines stacked on the substrate in a first direction, a channel region (the channel region extending in a second direction) between corresponding pairs of adjacent word lines in the plurality of word lines in the first direction, a first source / drain region on a first side of the channel region, a second source / drain region on a second side of the channel region, a bit line extending on the substrate in the first direction (each bit line being connected to a group of the first source / drain regions), a data storage element on the substrate and connected to a corresponding second source / drain region in the second source / drain region, and a cover film between the second source / drain region and the corresponding data storage element in the data storage element, the cover film each including an insertion hole, wherein a first portion of the second source / drain region is inserted into a corresponding insertion hole in the insertion hole of the cover film.

[0006] According to an exemplary embodiment of this disclosure, a semiconductor memory device includes a substrate, a plurality of word lines stacked on the substrate in a first direction, a semiconductor pattern (the semiconductor pattern extends in a second direction and includes first terminals and second terminals, each of the first terminals and a corresponding second terminal of the second terminals being spaced apart in the second direction) between corresponding pairs of adjacent word lines in the plurality of word lines in the first direction, bit lines extending on the substrate in the first direction (each bit line being connected to a group of first terminals of the semiconductor pattern), a cover film respectively connected to a corresponding second terminal of the second terminal of the semiconductor pattern, and data storage elements respectively connected to a corresponding cover film in the cover film, wherein the cover film includes a vertical portion, a protruding portion and an insertion hole, each of the insertion holes being defined by a corresponding vertical portion of the vertical portion and a corresponding protruding portion of the protruding portion, the vertical portion respectively contacting a corresponding data storage element in the data storage element, the protruding portion respectively extending from the corresponding vertical portion of the vertical portion in the second direction, and a first portion of the semiconductor pattern being inserted into a corresponding insertion hole in the insertion hole at a corresponding second terminal of the second terminal.

[0007] According to an exemplary embodiment of this disclosure, a semiconductor memory device includes a substrate, a plurality of word lines stacked on the substrate in a first direction, a channel region (extending in a second direction) between corresponding pairs of adjacent word lines in the plurality of word lines in the first direction, first source / drain regions on a first side of the channel region, second source / drain regions on a second side of the channel region, bit lines extending on the substrate in the first direction (each bit line being connected to a group of first source / drain regions), data storage elements on the substrate and respectively connected to corresponding second source / drain regions in the second source / drain regions, internal insulating films on the corresponding second source / drain regions in the second source / drain regions, and cover films between the second source / drain regions and corresponding data storage elements in the data storage elements, the cover films including vertical portions that contact the corresponding data storage elements in the data storage elements and protrusions extending from the corresponding vertical portions in the second direction. The protruding portions respectively contact the corresponding internal insulating film in the inner insulating film, wherein the second source / drain region includes a first portion covered by a cover film and a second portion covered by an inner insulating film. The first portion includes a first surface, an upper surface, a lower surface, a first side surface, and a second side surface. The first surface respectively contacts the corresponding vertical portion in the vertical portion. Each of the upper surface and the corresponding lower surface in the lower surface contact the corresponding protruding portion in the protruding portion. Each of the upper surface and the corresponding lower surface in the lower surface are opposite to each other in a first direction. Each of the first side surface and the corresponding second side surface in the second side surface contact the corresponding protruding portion in the protruding portion. Each of the first side surface and the corresponding second side surface in the second side surface are opposite to each other in a third direction. The cover film contacts the first surface, upper surface, lower surface, first side surface, and second side surface of the first portion, and each of the upper surfaces of the inner insulating film and the corresponding upper surface of the upper surface of the cover film are on the same plane.

[0008] It should be noted that the effects of this disclosure are not limited to those described above, and other effects of this disclosure will be apparent from the following description. Attached Figure Description

[0009] The above and other aspects and features of this disclosure will become more apparent from the detailed description of some exemplary embodiments thereof with reference to the accompanying drawings, in which:

[0010] Figure 1 This is an example circuit diagram illustrating a cell array of a semiconductor memory device according to some exemplary embodiments of the present disclosure.

[0011] Figure 2 This is an example perspective view illustrating a semiconductor memory device according to some example embodiments of the present disclosure.

[0012] Figure 3 This is an example plan view illustrating a semiconductor memory device according to some exemplary embodiments of the present disclosure.

[0013] Figure 4 It is along Figure 3 Example cross-sectional view taken from line A-A'.

[0014] Figure 5 It is along Figure 3 Example cross-sectional view taken from line B-B'.

[0015] Figure 6 It is along Figure 3 Example cross-sectional view taken from line C-C'.

[0016] Figure 7 yes Figure 4 A magnified view of part P in the image.

[0017] Figure 8 yes Figure 7 A magnified view of part Q in the image.

[0018] Figure 9 It is shown Figure 8 A perspective view of the cover film, the second source / drain region, and the internal insulating film.

[0019] Figure 10 It is used for explanation Figure 8 A perspective view of the cover film.

[0020] Figure 11 and Figure 12 This is a cross-sectional view used to illustrate some exemplary embodiments of the cover membrane according to this disclosure.

[0021] Figures 13 to 30 This is a diagram illustrating a method of manufacturing a semiconductor memory device according to some exemplary embodiments of the present disclosure. Detailed Implementation

[0022] Although terms such as first, second, upper, and lower are used in this specification to describe various devices or components, these devices and / or components are not limited by these terms. These terms are used only to distinguish one device or component from another. Therefore, a first device or component mentioned below may be a second device or component within the scope of this disclosure. Similarly, a lower device or component mentioned below may be an upper device or component within the scope of this disclosure.

[0023] As used herein, expressions such as “one of…”, “any one of…”, and “at least one of…” modify the entire list of elements when they follow the list of elements and do not modify any individual element in the list. Thus, for example, “at least one of A, B, or C” and “at least one of A, B, and C” both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0024] Although the terms “identical,” “equal,” or “same” are used in the description of the example implementations, it should be understood that some inaccuracies may exist. Therefore, when an element is referred to as being identical to another element, it should be understood that the element or value is identical to the other element within a desired range of manufacturing or operational tolerances (e.g., ±10%).

[0025] When the terms “about,” “substantially,” or “approximately” are used in conjunction with numerical values ​​in this specification, the numerical values ​​intended to be associated include manufacturing or operational tolerances (e.g., ±10%) around said numerical value. Furthermore, when the terms “about,” “substantially,” or “approximately” are used in conjunction with geometry, it is intended that the precision of the geometry is not required, but rather the tolerance of the shape is within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified with “about” or “substantially,” it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) around said numerical value or shape.

[0026] Some exemplary embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals will be used for the same parts in the drawings, and redundant descriptions of such parts will be omitted.

[0027] Figure 1 This is an example circuit diagram illustrating a cell array of a semiconductor memory device according to some exemplary embodiments of the present disclosure.

[0028] refer to Figure 1 The semiconductor memory device may include a plurality of memory cells MC arranged along a second direction D2 and a third direction D3. Each of the memory cells MC may include a memory cell transistor and a data storage element CAP arranged along the second direction D2 and connected to each other.

[0029] Bit lines BL can be conductive patterns (e.g., metallic conductive lines) extending in a direction perpendicular to the substrate (e.g., a third direction D3). Bit lines BL can be arranged along a second direction D2. Adjacent bit lines BL can be spaced apart from each other along the second direction D2.

[0030] In some example implementations, some of the bit lines BL can be connected by a bit line bundle line (BLS). For example, the bit line bundle line (BLS) can connect bit lines BL arranged along the second direction D2.

[0031] The word line WL can be a conductive pattern (e.g., a metallic conductive line) stacked on a substrate in a third direction D3. The word line WL can extend in a first direction D1. Adjacent word lines WL can be spaced apart from each other in the third direction D3.

[0032] The data storage element CAP can be connected together to a plate electrode PLAT extending in a first direction D1 and a third direction D3. In some example embodiments, the plate electrode PLAT arranged along the first direction D1 can form a monolithic structure.

[0033] The data storage element CAP and memory cell transistor arranged along the second direction D2 can be arranged symmetrically with respect to the plane extending along the first direction D1 and the third direction D3, where the plate electrode PLATE is located.

[0034] The gate of the memory cell transistor can be connected to the word line WL, and the first source / drain of the memory cell transistor can be connected to the bit line BL. The second source / drain of the memory cell transistor can be connected to the data storage element CAP. For example, the data storage element CAP can be a capacitor. The second source / drain of the memory cell transistor can be connected to the storage electrode of the capacitor.

[0035] Figure 2 This is an example perspective view illustrating a semiconductor memory device according to some example embodiments of the present disclosure. Figure 3 This is an example plan view illustrating a semiconductor memory device according to some exemplary embodiments of the present disclosure. Figure 4 It is along Figure 3 Example cross-sectional view taken from line A-A'. Figure 5 It is along Figure 3 Example cross-sectional view taken from line B-B'. Figure 6 It is along Figure 3 Example cross-sectional view taken from line C-C'. Figure 7 yes Figure 4 A magnified view of part P in the image. Figure 8 yes Figure 7 A magnified view of part Q in the image. Figure 9 It is shown Figure 8 A perspective view of the cover film, the second source / drain region, and the internal insulating film. Figure 10 It is used for explanation Figure 8 A perspective view of the cover film. Figure 11 and Figure 12This is a cross-sectional view used to illustrate some exemplary embodiments of the cover membrane according to this disclosure.

[0036] refer to Figures 2 to 12 The semiconductor memory device may include a substrate 100, a stacked structure SS, a semiconductor pattern SP, a bit line BL, a data storage element CAP, a cover film 170, and an internal insulating film 141.

[0037] The upper surface of the substrate 100 may be disposed on a plane extending along a first direction D1 and a second direction D2. The upper surface of the substrate 100 may be perpendicular to a third direction D3. In this specification, the first direction D1, the second direction D2, and the third direction D3 may intersect each other. The first direction D1, the second direction D2, and the third direction D3 may be substantially perpendicular to each other.

[0038] The substrate 100 may be a bulk silicon (Si) or silicon-on-insulator (SOI) substrate. In some example embodiments, the substrate 100 may be a Si substrate, or may include other materials such as silicon germanium (SiGe), SiGe on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but this disclosure is not limited to these.

[0039] A stacked structure SS can be disposed on a substrate 100. The stacked structure SS may include multiple interlayer insulating films 110 and multiple word lines WL. The interlayer insulating films 110 and word lines WL may be stacked alternately and repeatedly on a third direction D3. For example, two word lines WL may be disposed on a third direction D3 between adjacent interlayer insulating films 110.

[0040] Each word line WL may include a line portion extending parallel to the upper surface of the substrate 100 in a first direction D1 and a gate electrode portion protruding in a second direction D2. Here, the line portion of the word line WL may be located between a first insulating pattern STI1 and a second insulating pattern STI2, which is spaced apart from a corresponding first insulating pattern in the first insulating pattern STI1. That is, the line portion may overlap with the first insulating pattern STI1 and the second insulating pattern STI2 in the second direction D2. The gate electrode portion of the word line WL may not overlap with either the first insulating pattern STI1 or the second insulating pattern STI2 in the second direction D2. From a plan view, a pair of word lines WL may be symmetrical with respect to the vertical insulating pattern 130, which will be described later.

[0041] The word line WL may include a conductive material. For example, the word line WL may include at least one of a doped semiconductor material (e.g., doped Si, doped SiGe, or doped germanium (Ge)), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a metal (e.g., tungsten, titanium, or tantalum), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide), but this disclosure is not limited thereto.

[0042] Interlayer insulating film 110 may be provided on third-party direction D3 between adjacent word lines WL. Interlayer insulating film 110 may electrically isolate word lines WL. Some of the interlayer insulating films 110 may also electrically isolate data storage element CAP. Interlayer insulating film 110 may overlap with data storage element CAP on third-party direction D3. Interlayer insulating film 110 may contact the storage electrode SE of data storage element CAP. Interlayer insulating film 110 may contact the capacitor dielectric film CIL of data storage element CAP. Still others of the interlayer insulating film 110 may contact the gate insulating film Gox and bit line BL.

[0043] The interlayer insulating film 110 may include an insulating material. For example, the interlayer insulating film 110 may include at least one of a silicon oxide film, a silicon nitride film, a silicon nitride film, a carbon (Ca)-containing silicon oxide film, a Ca-containing silicon nitride film, and a Ca-containing silicon nitride film. For example, the interlayer insulating film 110 may include a silicon oxide film.

[0044] Semiconductor patterns SP can be disposed on a third direction D3 between corresponding pairs of adjacent word lines WL. Semiconductor patterns SP can extend in a second direction D2. Each semiconductor pattern SP can have a first terminal (e.g., a first source / drain region SD1, described later) and a second terminal (e.g., a second source / drain region SD2, described later) spaced apart in the second direction D2. The first terminal of the semiconductor pattern SP can be connected to a bit line BL. The second terminal of the semiconductor pattern SP can be connected to a data storage element CAP, described later.

[0045] Each semiconductor pattern SP may include a channel region CH, a first source / drain region SD1, and a second source / drain region SD2.

[0046] The channel region CH of the semiconductor pattern SP can be stacked on the third direction D3. The channel region CH of the semiconductor pattern SP can be provided on the third direction D3 between corresponding pairs of adjacent word lines WL. For example, if three word lines WL including a first, second, and third word line are provided, the channel region CH can be provided between the first and second word lines, and the interlayer insulating film 110 can be provided between the second and third word lines. However, this disclosure is not limited to this example.

[0047] The channel region CH can be spaced apart in a first direction D1 and a third direction D3. The channel region CH can extend in a second direction D2. That is, the channel region CH can be arranged three-dimensionally on the substrate 100. The channel region CH can include at least one of Si and Ge. For example, the channel region CH can include single-crystal Si.

[0048] The channel region CH can have a strip shape having a long axis extending in the second direction D2. The channel region CH can penetrate the word line WL in the second direction D2. The word line WL can have a structure that completely surrounds the channel region CH (e.g., a gate full-around structure). The gate insulating film Gox can be interposed between the channel region CH and the word line WL. The gate insulating film Gox can contact the cover insulating film 150, which will be described later, and the spacer insulating film 140, which will also be described later. The gate insulating film Gox can contact the interlayer insulating film 110.

[0049] The gate insulating film Gox may include at least one of a high-k dielectric film, a silicon oxide film, a silicon nitride film, and a silicon nitride film. For example, the high-k dielectric film may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalate, and lead zinc niobate.

[0050] The first source / drain region SD1 can be disposed on the first side of the channel region CH. The second source / drain region SD2 can be disposed on the second side of the channel region CH. The first source / drain region SD1 and the second source / drain region SD2 can be configured to have a channel region CH between them. The first source / drain region SD1 and the second source / drain region SD2 can each include Si doped with impurities. For example, the first source / drain region SD1 and the second source / drain region SD2 can each include SiP or SiAs, but this disclosure is not limited thereto.

[0051] In some example implementations, the impurity concentration in the first source / drain region SD1 may be higher than the impurity concentration in the second source / drain region SD2. This may be because the first source / drain region SD1 is formed using a selective epitaxial growth (SEG) process, while the second source / drain region SD2 is formed using an ion doping process.

[0052] The first source / drain region SD1 can be connected to the bit line BL. The second source / drain region SD2 can be connected to the data storage element CAP. For example, the second source / drain region SD2 can be electrically connected to the storage electrode SE of the data storage element CAP.

[0053] The second source / drain region SD2 may include a first part SD2_1 and a second part SD2_2. The first part SD2_1 may be closer to the channel region CH than the second part SD2_2. The second part SD2_2 may be closer to the data storage element CAP than the first part SD2_1.

[0054] An internal insulating film 141 may be disposed on the second source / drain region SD2. The internal insulating film 141 may surround a portion of the second source / drain region SD2. The internal insulating film 141 may cover a first portion SD2_1 of the second source / drain region SD2.

[0055] The inner insulating film 141 may include an insulating material. For example, the inner insulating film 141 may include at least one of a silicon oxide film, a silicon nitride film, a silicon nitride film, a Ca-containing silicon oxide film, a Ca-containing silicon nitride film, and a Ca-containing silicon nitride film.

[0056] A capping film 170 can be disposed on the second source / drain region SD2. The capping film 170 can surround a portion of the second source / drain region SD2. The capping film 170 can cover a second portion SD2_2 of the second source / drain region SD2.

[0057] The cover film 170 may extend in a third direction D3 and may each include a vertical portion 170V that contacts the data storage element CAP and a protrusion 170P that protrudes from the vertical portion 170V in a second direction D2. The cover film 170 may include an insertion hole OP. The insertion hole OP may be defined by the vertical portion 170V and the protrusion 170P of the cover film 170.

[0058] The insertion hole OP can be open in the second direction D2. The insertion hole OP can be surrounded by the protruding part 170P and can be not open in the second direction D2 or the third direction D3.

[0059] At least a portion of the second source / drain region SD2 can be inserted into the insertion hole OP. For example, a second portion SD2_2 of the second source / drain region SD2 can be inserted into the insertion hole OP. The portion of the second source / drain region SD2 inserted into the insertion hole OP may not be exposed. The second portion SD2_2 of the second source / drain region SD2 inserted into the insertion hole OP may not be exposed in the second direction D2 or the third direction D3. The portion of the second source / drain region SD2 inserted into the insertion hole OP can contact the cover film 170.

[0060] The second portion SD2_2 of the second source / drain region SD2 may include a first surface SD2_2S in contact with the capping film 170, an upper surface SD2_2US and a lower surface SD2_2BS opposite to each other in the third direction D3, and a first side surface SW1 and a second side surface SW2 opposite to each other in the first direction D1. The capping film 170 may contact the first surface SD2_2S, the upper surface SD2_2US, the lower surface SD2_2BS, the first side surface SW1, and the second side surface SW2 of the second portion SD2_2. That is, the capping film 170 may cover all surfaces of the second portion SD2_2 of the second source / drain region SD2. The capping film 170 may completely surround the second portion SD2_2 of the second source / drain region SD2.

[0061] The vertical portion 170V of the cover film 170 can be disposed on the first surface SD2_2S of the second portion SD2_2. The protruding portion 170P of the cover film 170 can be disposed on the upper surface SD2_2US, the lower surface SD2_2BS, the first side surface SW1, and the second side surface SW2 of the second portion SD2_2. The vertical portion 170V of the cover film 170 can contact the first surface SD2_2S of the second portion SD2_2. The protruding portion 170P of the cover film 170 can contact the upper surface SD2_2US, the lower surface SD2_2BS, the first side surface SW1, and the second side surface SW2 of the second portion SD2_2.

[0062] In some example implementations, the second source / drain region SD2 may include Si.

[0063] In this case, the cover film 170 may include at least one of molybdenum (Mo) silicide, titanium (Ti) silicide, cobalt (Co) silicide, nickel (Ni) silicide, nickel-platinum (NiPt) silicide, ruthenium (Ru) silicide, and zirconium (Zr) silicide.

[0064] In some example implementations, the second source / drain region SD2 may include an oxide semiconductor. The oxide semiconductor may include, for example, one of indium gallium zinc oxide (IGZO), doped indium zinc oxide (IZO), indium oxide (InO), zinc oxide (ZnO), gallium oxide (GaO), tin oxide (SnO), aluminum zinc oxide (AZO), and indium tin oxide (ITO). The impurities in the doped IZO may include at least one of magnesium (Mg), strontium (Sr), barium (Ba), scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), tin (Sn), and tantalum (Ta).

[0065] In this case, the cover film 170 may include indium oxide (InO) xITO, Ruthenium oxide (RuO) x ), molybdenum oxide (MoO) x At least one of titanium nitride (TiN), Mo, and Ru.

[0066] In some example implementations, the second source / drain region SD2 may include a two-dimensional (2D) material, such as MoS2 or WSe2, but this disclosure is not limited thereto.

[0067] In this case, the cover film 170 may include at least one of antimony (Sb), antimony telluride (Sb2Te3), palladium / nickel (Pd / Ni), nickel / gold (Ni / Au), Ti, chromium (Cr), palladium (Pd), gold (Au), platinum (Pt), silver (Ag), copper (Cu), Ni, and cobalt (Co).

[0068] The cover film 170 can be disposed between the inner insulating film 141 and the data storage element CAP. The inner insulating film 141 can be disposed on the cover film 170. The inner insulating film 141 can contact the protrusion 170P of the cover film 170.

[0069] The capping film 170 and the inner insulating film 141 may surround the second source / drain region SD2. For example, the first portion SD2_1 of the second source / drain region SD2 may be covered by the inner insulating film 141. The second portion SD2_2 of the second source / drain region SD2 may be covered by the capping film 170. The second source / drain region SD2 surrounded by the inner insulating film 141 and the capping film 170 may not be exposed.

[0070] The upper surface 141US of the inner insulating film 141 and the upper surface 170US of the cover film 170 can be on the same plane. The lower surface 141BS of the inner insulating film 141 and the lower surface 170BS of the cover film 170 can also be on the same plane. For example, based on the upper surface of the second source / drain region SD2, the height of the upper surface 141US of the inner insulating film 141 and the height of the upper surface 170US of the cover film 170 can be the same. Based on the lower surface of the second source / drain region SD2, the height of the lower surface 141BS of the inner insulating film 141 and the height of the lower surface 170BS of the cover film 170 can also be the same.

[0071] The cover film 170 can be disposed between the second source / drain region SD2 and the data storage element CAP. The cover film 170 can connect the second source / drain region SD2 and the data storage element CAP.

[0072] The cover film 170 may include an outer wall 170OWS and an inner wall 170IWS. The outer wall 170OWS of the cover film 170 may contact the data storage element CAP. The inner wall 170IWS of the cover film 170 may contact the second source / drain region SD2. The width of the inner wall 170IWS of the cover film 170 in the third direction D3 may be smaller than the width of the outer wall 170OWS of the cover film 170 in the third direction D3. The width of the outer wall 170OWS of the cover film 170 in the third direction D3 may be smaller than the width of the data storage element CAP in the third direction D3.

[0073] The surfaces of the outer wall 170OWS, upper surface 170US, and lower surface 170BS of the connecting cover film 170 can protrude relative to the data storage element CAP. The surfaces of the inner wall 170IWS, the upper surface, and the lower surface of the protruding portion 170P of the connecting cover film 170 can be recessed relative to the data storage element CAP.

[0074] refer to Figure 11 In some example embodiments, the outer wall 170OWS of the cover 170 may protrude toward the data storage element CAP. In some example embodiments, reference... Figure 12 In some example embodiments, the outer wall 170OWS of the cover 170 may be recessed toward the data storage element CAP. However, the shape of the cover 170 is not limited to these examples.

[0075] A cover insulating film 150 may be provided between the bit line BL and the word line WL. The cover insulating film 150 may be provided between the first source / drain region SD1 and the interlayer insulating film 110. The cover insulating film 150 may electrically isolate the bit line BL from the word line WL. The cover insulating film 150 may surround the first source / drain region SD1. The cover insulating film 150 may be in direct contact with the word line WL. While the cover insulating film 150 may be in direct contact with the first source / drain region SD1, this disclosure is not limited thereto.

[0076] The cover insulating film 150 may include at least one of a silicon oxide film, a silicon nitride film, a silicon nitride film, a Ca-containing silicon oxide film, a Ca-containing silicon nitride film, and a Ca-containing silicon nitride film. For example, the cover insulating film 150 may be formed of or include a silicon nitride.

[0077] A spacer insulating film 140 may be provided between the word line WL and the data storage element CAP. The spacer insulating film 140 may be disposed between the second source / drain region SD2 and the interlayer insulating film 110. The spacer insulating film 140 may be spaced apart from the word line WL, with a gate insulating film Gox therebetween. In some example embodiments, the spacer insulating film 140 may be formed as a multilayer film. For example, if the spacer insulating film 140 is formed as a multilayer film, it may include a pad film and a fill film. The pad film may surround the second source / drain region SD2 and the interlayer insulating film 110. The fill film may fill the trench defined by the pad film, the gate insulating film Gox, and the storage electrode SE.

[0078] The spacer insulating film 140 may include at least one of, for example, a silicon oxide film, a silicon nitride film, a silicon nitride film, a Ca-containing silicon oxide film, a Ca-containing silicon nitride film, and a Ca-containing silicon nitride film.

[0079] The semiconductor memory device may further include a first isolation insulating pattern STI1, a second isolation insulating pattern STI2, a lower protective pattern 120, a vertical insulating pattern 130, and an upper insulating film 160.

[0080] A lower protective pattern 120 may be provided on the substrate 100. The lower protective pattern 120 may be provided between the substrate 100 and the bit line BL. The lower protective pattern 120 may overlap with the word line WL closest to the substrate 100 in the second direction D2. The lower protective pattern 120 may be formed of or comprise the same material as the cover insulating film 150, but this disclosure is not limited thereto.

[0081] A vertical insulating pattern 130 may be disposed on the lower protective pattern 120. The vertical insulating pattern 130 may be disposed on the bit line BL. Although not shown, the vertical insulating pattern 130 may be provided between the bit lines BL. The vertical insulating pattern 130 may extend from the lower protective pattern 120 in the third direction D3. The vertical insulating pattern 130 may cover the sidewalls of the bit line BL and the sidewalls of the first isolation insulating pattern STI1.

[0082] The upper insulating film 160 can be formed on the stacked structure SS. The upper insulating film 160 can be provided between the plate electrode PE and the vertical insulating pattern 130. The upper insulating film 160 can be disposed on the uppermost word line WL. The upper insulating film 160 can be formed of or include a silicon oxide film, but this disclosure is not limited thereto.

[0083] A first insulating pattern STI1 can be provided between the word line WL and the vertical insulating pattern 130. A first insulating pattern STI1 can also be provided between the bit lines BL. A second insulating pattern STI2 can be provided between the word line WL and the data storage element CAP. A second insulating pattern STI2 can also be provided between the storage electrodes SE. The first insulating pattern STI1 and the second insulating pattern STI2 can each be formed of or comprise an insulating material. For example, the first insulating pattern STI1 and the second insulating pattern STI2 can each be formed of or comprise a silicon oxide film.

[0084] The data storage element CAP can be connected to the cover membrane 170. In some example embodiments, the data storage element CAP can be a capacitor.

[0085] The data storage element CAP may include storage electrodes SE, plate electrodes PE, and capacitor dielectric film CIL. The data storage element CAP may share the capacitor dielectric film CIL and the plate electrodes PE. That is, multiple storage electrodes SE can be provided, each connected to a corresponding second source / drain region SD2 in the second source / drain region SD2, and a single capacitor dielectric film CIL may cover the surfaces of the multiple storage electrodes SE. A single plate electrode PE may cover a single capacitor dielectric film CIL. Here, the plate electrode PE may be connected to... Figure 1 The plate electrode PLAT is the same as that in the memory. That is, the data storage element CAP can be defined by the storage electrode SE.

[0086] The storage electrode SE may have a closed first portion facing the second source / drain region SD2 and an open second portion opposite to the first portion, and may thus have a hollow cylindrical shape. In other words, the storage electrode SE may have a U-shape rotated 90 degrees. The storage electrode SE may be electrically connected to the second source / drain region SD2. The storage electrode SE may, for example, be in direct contact with the cover film 170.

[0087] The storage electrode SE and the plate electrode PE may each comprise, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, niobium, tungsten, cobalt, molybdenum, or tantalum), and a conductive metal oxide (e.g., iridium oxide or niobium oxide), but this disclosure is not limited thereto. For example, the storage electrode SE may comprise a conductive metal nitride, a metal, and a conductive metal oxide. The conductive metal nitride, the metal, and the conductive metal oxide may be contained in a metal conductive film (e.g., collectively referred to as a metal conductive film).

[0088] The capacitor dielectric film (CIL) may include, for example, high-k materials (e.g., hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, lithium oxide, aluminum oxide, lead scandium tantalate, lead zinc niobate, or combinations thereof). In some example embodiments, the capacitor dielectric film (CIL) may include a laminated film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. In some example embodiments, the capacitor dielectric film (CIL) may include Hf.

[0089] Three-dimensional (3D) semiconductor memory devices have a very small contact area between the semiconductor and the metal, resulting in relatively high contact resistance. When the contact resistance is high, the characteristics of the semiconductor memory device may deteriorate.

[0090] However, in some exemplary embodiments of the semiconductor memory device according to this disclosure, a cover film 170 may be disposed between the second source / drain region SD2 and the data storage element CAP. The cover film 170 may include an insertion hole OP. A portion of the second source / drain region SD2 may be inserted into the insertion hole OP of the cover film 170. Because contact resistance is inversely proportional to contact area, the contact resistance may decrease as the contact area increases. The cover film 170 may contact the first surface SD2_2S, the upper surface SD2_2US, the lower surface SD2_2BS, the first side surface SW1, and the second side surface SW2 of the second source / drain region SD2. The cover film 170 may form a fully surrounding contact structure around all surfaces of the second portion SD2_2 of the second source / drain region SD2. Therefore, the contact resistance between the cover film 170 and the second source / drain region SD2 can be improved, thereby improving the contact resistance between the semiconductor pattern SP and the data storage element CAP.

[0091] The following text will refer to 13 to Figure 30 Methods for manufacturing a semiconductor memory device according to some exemplary embodiments of the present disclosure are described.

[0092] Figures 13 to 30 This is a diagram illustrating a method of manufacturing a semiconductor memory device according to some exemplary embodiments of the present disclosure. For ease of explanation, brief descriptions or omissions will be made with reference to the reference. Figures 1 to 12 The content described is repetitive.

[0093] refer to Figure 13 A substrate 100 can be provided. A first mode structure MS1 can be formed on the substrate 100.

[0094] The first mode structure MS1 may include a first sacrificial film 10 and a semiconductor film 20. The first mode structure MS1 may be formed by alternately stacking the first sacrificial film 10 and the semiconductor film 20. For example, the first sacrificial film 10 may be formed on a third-direction D3 between adjacent semiconductor films 20, and the semiconductor film 20 may be formed on a third-direction D3 between adjacent first sacrificial films 10. The thickness of the first sacrificial film 10 may be less than the thickness of the semiconductor film 20.

[0095] The first sacrificial film 10 may be formed of or comprise a material that is etch-selective relative to the semiconductor film 20. For example, the first sacrificial film 10 may be formed of or comprise at least one of SiGe, Ca-doped SiGeC, silicon oxide, silicon nitride, and silicon nitride.

[0096] The semiconductor film 20 can be formed of, for example, Si, Ge, SiGe, 2D semiconductor materials, or IGZO. In some example embodiments, the semiconductor film 20 can be formed of or comprise the same material as the substrate 100. For example, the semiconductor film 20 can be a single-crystal Si film or a polycrystalline Si film.

[0097] In some example embodiments, the first sacrificial film 10 and the semiconductor film 20 can be formed using an epitaxial growth process. For example, the semiconductor film 20 can be a single-crystal Si film, and the first sacrificial film 10 can be a SiGe film with a superlattice structure.

[0098] An upper insulating film 160 may be formed on the first mold structure MS1. The upper insulating film 160 may cover the semiconductor film 20 located at the highest vertical level. The upper insulating film 160 may be formed of or comprise an insulating material having etch selectivity relative to the first sacrificial film 10 and the semiconductor film 20. For example, the upper insulating film 160 may be formed of or comprise silicon oxide.

[0099] refer to Figure 14 A first trench TR1 and a second trench TR2 can be formed through the first mold structure MS1. The first trench TR1 and the second trench TR2 can respectively expose the sidewalls of the first sacrificial film 10 and the sidewalls of the semiconductor film 20.

[0100] Forming the first trench TR1 and the second trench TR2 may involve forming a mask pattern on the first mold structure MS1 with openings corresponding to the first trench TR1 and the second trench TR2, and using the mask pattern as an etching mask to etch the first mold structure MS1.

[0101] The first trench TR1 and the second trench TR2 can expose the upper surface of the substrate 100, and during etching, the upper surface of the substrate 100 below the first trench TR1 and the second trench TR2 can be recessed due to over-etching, thereby forming a recessed area.

[0102] refer to Figure 15 The exposed first sacrificial membrane 10 can be removed through the first trench TR1 and the second trench TR2.

[0103] The first horizontal region HR1 can be formed in a vertical direction (e.g., third direction D3) between adjacent semiconductor films 20. Forming the first horizontal region HR1 may involve performing an etching process with etch selectivity relative to the substrate 100 and the semiconductor films 20 to isotropically etch the first sacrificial film 10. When the first sacrificial film 10 is removed, the semiconductor films 20 can remain spaced apart from each other in the third direction D3 without collapsing.

[0104] refer to Figure 16 An expansion process can be performed to increase the thickness of the first horizontal region HR1 in the third direction D3. For example, the expansion process may include etching the upper and lower surfaces of the semiconductor film 20 exposed by the first horizontal region HR1. The expansion process may involve performing an isotropic etching process with etch selectivity relative to the upper insulating film 160. The thickness of the semiconductor film 20 can be reduced by the expansion process. Therefore, a first semiconductor pattern SP1 can be formed, and second horizontal regions HR2 can be formed in the third direction D3 between corresponding pairs of adjacent first semiconductor patterns SP1.

[0105] In some example embodiments, the first semiconductor pattern SP1 can be oxidized to form a sacrificial oxide film on its surface. The sacrificial oxide film can then be removed, thereby re-exposing the surface of the first semiconductor pattern SP1. After removing the sacrificial oxide film, the distance between adjacent first semiconductor patterns SP1 in the third direction D3 can be increased. That is, the second horizontal region HR2 can be further expanded in the vertical direction.

[0106] refer to Figure 17 A second sacrificial film 30 and a preliminary interlayer insulating film 40 can be formed on the surface of the first semiconductor pattern SP1. The second sacrificial film 30 and the preliminary interlayer insulating film 40 can be deposited sequentially.

[0107] The second sacrificial film 30 may include a material that is etch-selective relative to the substrate 100 and the first semiconductor pattern SP1. For example, the second sacrificial film 30 may be formed of or include at least one of silicon oxide, silicon nitride, and silicon nitride. The second sacrificial film 30 may be formed by atomic layer deposition (ALD) or chemical vapor deposition (CVD).

[0108] A second sacrificial film 30 can be deposited to surround the corresponding first semiconductor pattern SP1. Therefore, after depositing the second sacrificial film 30, a gap region can be defined between adjacent first semiconductor patterns SP1 on the third direction D3.

[0109] Subsequently, a preliminary interlayer insulating film 40 can be formed on the second sacrificial film 30 to fill the second horizontal region HR2 where the second sacrificial film 30 has been formed. The preliminary interlayer insulating film 40 can be formed of or comprise an insulating material having etch selectivity relative to the second sacrificial film 30 and the substrate 100. For example, the preliminary interlayer insulating film 40 can be formed of or comprise silicon oxide.

[0110] refer to Figure 18 A second mode structure MS2 can be formed by etching the initial interlayer insulating film 40 and the second sacrificial film 30. The second mode structure MS2 may include multiple interlayer insulating films 110, multiple first semiconductor patterns SP1, and multiple second sacrificial patterns 35.

[0111] For example, the interlayer insulating film 110 can be formed by etching a portion of the preliminary interlayer insulating film 40. The interlayer insulating film 110 can be formed by isotropically etching the preliminary interlayer insulating film 40 until the second sacrificial film 30 is exposed in the first trench TR1 and the second trench TR2. The interlayer insulating films 110 can be separated from each other in a third direction D3.

[0112] After forming the interlayer insulating film 110, a portion of the second sacrificial film 30 can be etched to form a second sacrificial pattern 35. The second sacrificial pattern 35 can be formed by isotropically etching the second sacrificial film 30 until the first semiconductor pattern SP1 is exposed. The second sacrificial patterns 35 can be separated from each other in a third direction D3. The first semiconductor pattern SP1 can be disposed between the second sacrificial patterns 35.

[0113] After forming the second mold structure MS2, a first buried insulating pattern 210 and a second buried insulating pattern 220 can be formed to fill the first trench TR1 and the second trench TR2. Forming the first buried insulating pattern 210 and the second buried insulating pattern 220 may involve forming a buried insulating film to fill the first trench TR1 and the second trench TR2 and planarizing the buried insulating film to expose the upper surface of the upper insulating film 160. The first buried insulating pattern 210 and the second buried insulating pattern 220 may each be formed of or include at least one of silicon oxide, silicon nitride, and silicon nitride. The first buried insulating pattern 210 and the second buried insulating pattern 220 may each be formed as a single layer or a multilayer film.

[0114] refer to Figure 19 and Figure 20 The third trench TR3 can be formed by etching a portion of the first buried insulating pattern 210 and the second mode structure MS2. The width of the third trench TR3 can be greater than the width of the first buried insulating pattern 210.

[0115] Subsequently, the portion of the second sacrificial pattern 35 exposed by the third trench TR3 can be removed. The second sacrificial pattern 35 can be removed by an isotropic etching process. The second sacrificial pattern 35 can be selectively removed without removing the interlayer insulating film 110 and the first semiconductor pattern SP1.

[0116] For example, if the second sacrificial pattern 35 is a silicon nitride film and the interlayer insulating film 110 is a silicon oxide film, the second sacrificial pattern 35 can be etched using an etching solution containing phosphoric acid. A portion of the second sacrificial pattern 35 can be removed to form the third sacrificial pattern 37.

[0117] The spacer insulating film 140 and the inner insulating film 141 can be formed in the space from which the second sacrificial pattern 35 has been removed. The spacer insulating film 140 and the inner insulating film 141 can fill the portion of the space from which the second sacrificial pattern 35 has been removed. Thereafter, the gate insulating film Gox, the word line WL, and the cover insulating film 150 can be formed in the space that remains unfilled by the spacer insulating film 140 and the inner insulating film 141.

[0118] The gate insulating film Gox can be formed along the contour of the space filled by the spacer insulating film 140 and the inner insulating film 141. The word line WL and the cover insulating film 150 can be formed sequentially on the gate insulating film Gox.

[0119] refer to Figure 21The first recess RC1 can be formed by etching a portion of the first semiconductor pattern SP1. The first semiconductor pattern SP1 can be etched isotropically using an etch solution that has etch selectivity relative to the gate insulating film Gox and the cap insulating film 150. Therefore, the first semiconductor pattern SP1 can be selectively removed only. The depth of the first recess RC1 can be substantially equal to the thickness of the cap insulating film 150 in the second direction D2, but this disclosure is not limited thereto.

[0120] If the etching solution contains fluorine (F), chlorine (Cl), or bromine (Br), F, Cl, or Br can be detected on the exposed surface of the first semiconductor pattern SP1. Additionally, oxygen (O) can also be detected on the exposed surface of the first semiconductor pattern SP1.

[0121] refer to Figure 22 The second recess RC2 can be formed by removing a portion of the gate insulating film Gox. The second recess RC2 exposes the surface of the cover insulating film 150. The second recess RC2 does not expose the word line WL.

[0122] refer to Figure 23 and Figure 24 The first source / drain region SD1 can be formed. The first source / drain region SD1 can be formed using a selective epitaxial growth (SEG) process. The first source / drain region SD1 can fill the interior of the second recess RC2.

[0123] In some example implementations, the surface of the first semiconductor pattern SP1 can be exposed by first forming a first recess RC1 and a second recess RC2. Therefore, oxygen (O) may be present at the interface between the exposed surface of the first semiconductor pattern SP1 and the first source / drain region SD1. Additionally, if an etching solution containing F, Cl, or Br is used during the formation of the first recess RC1, F, Cl, or Br may be present at the interface between the surface of the semiconductor pattern SP and the first source / drain region SD1.

[0124] refer to Figure 25 and Figure 26 This can form bit lines BL covering the first source / drain region SD1, the capping insulating film 150, and the interlayer insulating film 110.

[0125] Forming the bit line BL may involve forming a conductive film to fill the third trench TR3 and removing a portion of the conductive film. The bit line BL may cover the first source / drain region SD1.

[0126] refer to Figure 27 The second source / drain region SD2 can be formed by doping a portion of the first semiconductor pattern SP1, and the third sacrificial pattern 37 can be removed.

[0127] The third sacrificial pattern 37 can be removed, and a portion of the second source / drain region SD2 can also be removed. The internal insulating film 141 can protrude beyond the second source / drain region SD2 in the second direction D2.

[0128] refer to Figure 28 A portion of the internal insulating film 141 formed on the second source / drain region SD2 can be removed using a recess process.

[0129] By removing a portion of the inner insulating film 141, an empty space can be formed between the second source / drain region SD2 and the spacer insulating film 140. The second source / drain region SD2 can protrude beyond the inner insulating film 141 in the second direction D2.

[0130] refer to Figure 29 and Figure 30 A cover film 170 can be formed on the inner insulating film 141 and the second source / drain region SD2. Subsequently, a data storage element CAP can be formed on the cover film 170. The cover film 170 can connect the second source / drain region SD2 and the data storage element CAP.

[0131] Although some exemplary embodiments of this disclosure have been described with reference to the accompanying drawings, this disclosure is not limited to the exemplary embodiments described above, but can be implemented in various different forms. Those skilled in the art will understand that this disclosure can be practiced in other specific forms without changing the technical spirit or essential characteristics of this disclosure. Therefore, it should be understood that the exemplary embodiments described above are illustrative in all respects and are not limiting.

[0132] This application claims priority to Korean Patent Application No. 10-2024-0126147, filed on September 13, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: Substrate; Multiple word lines are stacked on the substrate in a first direction; The channel area extends in the second direction between corresponding pairs of adjacent word lines in the first direction. The first source / drain regions are respectively located on the first side of the channel region; The second source / drain regions are located on the second side of the channel region, respectively; Bit lines extending in the first direction on the substrate, each of the bit lines being connected to the group of the first source / drain regions; Data storage elements are located on the substrate and are respectively connected to the corresponding second source / drain regions in the second source / drain regions; as well as Cover films are respectively located between the second source / drain regions and the corresponding data storage elements in the data storage elements, and each cover film includes an insertion hole. The first portion of the second source / drain region is inserted into the corresponding insertion hole in the insertion hole of the cover film.

2. The semiconductor memory device according to claim 1, wherein, The first portion of the second source / drain region is not exposed by the corresponding capping membrane in the capping membrane.

3. The semiconductor memory device according to claim 1, further comprising: An internal insulating film is placed on a corresponding cover film in the cover film in the second direction, and the internal insulating film surrounds a second portion of a corresponding second source / drain region in the second source / drain region.

4. The semiconductor memory device according to claim 3, wherein, The upper surface of each of the cover films and the upper surface of the corresponding inner insulating film in the inner insulating film are on the same plane.

5. The semiconductor memory device according to claim 3, wherein, The lower surface of each of the cover films and the lower surface of the corresponding inner insulating film in the inner insulating film are on the same plane.

6. The semiconductor memory device according to claim 3, wherein, The first portion of the second source / drain region includes a first surface, an upper surface, a lower surface, a first side surface, and a second side surface. The first surface contacts a corresponding cover film in the cover film in the second direction. Each of the upper surfaces and a corresponding lower surface in the lower surface are opposite to each other in the first direction. Each of the first side surfaces and a corresponding second side surface in the second side surface are opposite to each other in the third direction. The cover film is in contact with the first surface, the upper surface, the lower surface, the first side surface, and the second side surface of the first portion.

7. The semiconductor memory device according to claim 3, wherein, The cover film includes a vertical portion that contacts the data storage element and a protruding portion that extends from the vertical portion in the second direction. The first portion of the second source / drain region includes an upper surface, a lower surface, a first side surface, and a second side surface. Each of the upper surfaces is opposite to a corresponding lower surface in the lower surface in a first direction, and each of the first side surfaces is opposite to a corresponding second side surface in the second side surface in a third direction. The protruding portion of the cover membrane is on the upper surface, the lower surface, the first side surface, and the second side surface of the first portion of the second source / drain region.

8. The semiconductor memory device according to claim 1, wherein, The cover film includes an outer surface that contacts the data storage element and an inner surface that contacts the second source / drain region. The outer surface of the cover membrane protrudes toward the data storage element.

9. The semiconductor memory device according to claim 1, wherein, The cover film includes an outer surface that contacts the data storage element and an inner surface that contacts the second source / drain region. The outer surface of the cover film is recessed toward the data storage element.

10. The semiconductor memory device according to claim 1, wherein, The second source / drain region includes silicon, and The cover membrane comprises a metal silicide.

11. The semiconductor memory device according to claim 1, wherein, The second source / drain region includes an oxide semiconductor material, and The cover film includes at least one of indium oxide, indium tin oxide, ruthenium oxide, molybdenum oxide, titanium nitride, molybdenum, and ruthenium.

12. The semiconductor memory device according to claim 1, wherein, The second source / drain region comprises a two-dimensional material, and The cover membrane includes at least one of antimony, antimony telluride, palladium nickel, nickel / gold, titanium, chromium, palladium, gold, platinum, silver, copper, nickel, and cobalt.

13. The semiconductor memory device according to claim 1, wherein, The first width of the cover film in the first direction is smaller than the second width of the data storage element in the first direction.

14. A semiconductor memory device, comprising: Substrate; Multiple word lines are stacked on the substrate in a first direction; A semiconductor pattern extending in a second direction between corresponding pairs of adjacent word lines among the plurality of word lines in a first direction, the semiconductor pattern including first terminals and second terminals, each of the first terminals and a corresponding second terminal of the second terminals being spaced apart in the second direction; Bit lines extending in the first direction on the substrate, each of the bit lines being connected to a group of first terminals of the semiconductor pattern; A cover film is respectively connected to the corresponding second terminal in the second terminal of the semiconductor pattern; as well as Data storage elements are respectively connected to corresponding covers in the cover film. in The cover membrane includes vertical portions, protruding portions, and insertion holes, each of the insertion holes being defined by a corresponding vertical portion of the vertical portions and a corresponding protruding portion of the protruding portions. The vertical portions respectively contact corresponding data storage elements in the data storage elements, and the protruding portions extend from the corresponding vertical portions of the vertical portions in the second direction. The first portion of the semiconductor pattern is inserted into the corresponding insertion hole in the insertion hole at the corresponding second terminal in the second terminal.

15. The semiconductor memory device of claim 14, further comprising: An inner insulating film, respectively, is disposed on a corresponding cover film in the cover film in the second direction, and the inner insulating film respectively surrounds a second portion of a corresponding semiconductor pattern in the semiconductor pattern. The upper surface of each of the inner insulating films and the upper surface of the corresponding cover film are on the same plane.

16. The semiconductor memory device according to claim 15, wherein, The first portion of the semiconductor pattern includes a first surface, an upper surface, a lower surface, a first side surface, and a second side surface. The first surface is in contact with a corresponding cover film in the cover film in the second direction. Each of the upper surfaces and a corresponding lower surface of the lower surface are opposite to each other in the first direction. Each of the first side surfaces and a corresponding second side surface of the second side surface are opposite to each other in the third direction. The cover film is in contact with the first surface, the upper surface, the lower surface, the first side surface, and the second side surface of the first portion.

17. The semiconductor memory device of claim 14, wherein, The width of each of the vertical portions in the first direction is smaller than the width of the corresponding data storage element in the first direction.

18. The semiconductor memory device of claim 14, wherein, The cover membrane comprises a metal silicide.

19. A semiconductor memory device, comprising: Substrate; Multiple word lines are stacked on the substrate in a first direction; The channel area extends in the second direction between corresponding pairs of adjacent word lines in the first direction. The first source / drain regions are respectively located on the first side of the channel region; The second source / drain regions are located on the second side of the channel region, respectively; Bit lines extending in the first direction on the substrate, each of the bit lines being connected to the group of the first source / drain regions; Data storage elements are located on the substrate and are respectively connected to the corresponding second source / drain regions in the second source / drain regions; Internal insulating films are respectively located on the corresponding second source / drain regions in the second source / drain regions; as well as A cover film is respectively located between the second source / drain region and a corresponding data storage element in the data storage element. The cover film includes vertical portions that contact the corresponding data storage elements and protruding portions extending from the corresponding vertical portions in the second direction. The protruding portions contact corresponding internal insulating films in the internal insulating film. in The second source / drain region includes a first portion covered by the capping film and a second portion covered by the inner insulating film. The first portion includes a first surface, an upper surface, a lower surface, a first side surface, and a second side surface. The first surface contacts a corresponding vertical portion of the vertical portion. Each of the upper surface and a corresponding lower surface of the lower surface contacts a corresponding protruding portion of the protruding portion. Each of the upper surface and a corresponding lower surface of the lower surface are opposite to each other in the first direction. Each of the first side surface and a corresponding second side surface of the second side surface contacts a corresponding protruding portion of the protruding portion. Each of the first side surface and a corresponding second side surface of the second side surface are opposite to each other in the third direction. The cover film contacts the first surface, the upper surface, the lower surface, the first side surface, and the second side surface of the first portion, and Each of the upper surfaces of the inner insulating film and the corresponding upper surface of the cover film are on the same plane.

20. The semiconductor memory device of claim 19, wherein, The cover film includes an outer surface that contacts the data storage element and an inner surface that contacts the second source / drain region. The outer surface of the cover membrane protrudes toward the corresponding data storage element in the data storage element.

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