Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device capable of easily forming a pattern with a high aspect ratio and a method for manufacturing the semiconductor device. A semiconductor device (1) according to an embodiment includes: a first structure; a first columnar body extending in a first direction in the first structural body; a second structure; a second columnar body extending in the first direction in the second structural body; and a bonding surface interposed between the first structure body and the second structure body. In the bonding surface, the first columnar body and the second columnar body are connected in the first direction.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0002] As the aspect ratio increases, there is a tendency for patterns to be difficult to form. As a result, the yield of semiconductor devices may decrease. Summary of the Invention

[0003] One embodiment aims to provide a semiconductor device and a method for manufacturing a semiconductor device that can easily form patterns with a high aspect ratio.

[0004] The semiconductor device of the embodiment includes: a first structure; a first column extending in a first direction within the first structure; a second structure; a second column extending in the first direction within the second structure; and a bonding surface disposed between the first structure and the second structure; wherein the first column and the second column are connected in the first direction in the bonding surface. Attached Figure Description

[0005] Figures 1A-1B This is a diagram illustrating a schematic configuration example of a semiconductor device according to an embodiment.

[0006] Figures 2A-2B This is a cross-sectional view showing a detailed configuration example of the storage area in the implementation method.

[0007] Figures 3A-3B This is a diagram showing a detailed example of the configuration of the stepped area in the implementation method.

[0008] Figures 4A-4B This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0009] Figures 5A-5B This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0010] Figures 6A-6B This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0011] Figures 7A-7B This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0012] Figure 8 This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0013] Figure 9 This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0014] Figures 10A to 10D This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0015] Figures 11A-11B This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0016] Figures 12A-12B This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0017] Figures 13A-13B This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0018] Figures 14A-14B This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0019] Figure 15 This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device according to an exemplary embodiment.

[0020] Figure 16 This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device, as illustrated in Variation 1.

[0021] Figures 17A-17B This is a diagram showing a part of the sequence of a method for manufacturing a semiconductor device, as illustrated in Variation 1.

[0022] Figure 18 This is a diagram showing the detailed structure of the stepped region in variation example 2. Detailed Implementation

[0023] Hereinafter, with reference to the accompanying drawings, the semiconductor device and its manufacturing method according to the embodiments will be described in detail. However, the present invention is not limited to these embodiments.

[0024] (Example of a semiconductor device configuration)

[0025] Figures 1A-1B This is a diagram illustrating a schematic configuration example of the semiconductor device 1 according to an embodiment. Figure 1A A cross-section of semiconductor device 1 along the X direction is shown. Wherein, in Figure 1A In the accompanying diagram, the shading lines have been omitted for easier observation.

[0026] Furthermore, in this specification, the directions along the orientation of the surfaces of the multiple word lines WL are designated as the X direction and the Y direction, which are orthogonal to each other. Additionally, the electrical lead-out direction of the word lines WL is sometimes referred to as the second direction, which is the direction along the X direction. Furthermore, the direction intersecting the X and Y directions, i.e., the direction intersecting the orientation of the surfaces of the multiple word lines WL, is designated as the Z direction. The Z direction is an example of the first direction. Furthermore, in the extension direction of the contact CC, the side of the contact CC that connects to the word line WL is designated as the lower side of the semiconductor device 1, and the opposite side is designated as the upper side.

[0027] like Figure 1A As shown, semiconductor device 1 sequentially comprises an electrode film EL, a source line SL, and a multilayer LM formed by stacking multiple word lines WL, starting from the bottom of the paper. Furthermore, semiconductor device 1 has a peripheral circuit CBA disposed above the multilayer LM, on a semiconductor substrate SB.

[0028] On the electrode film EL, a source line SL is disposed with an insulating layer 60 in between. The source line SL is, for example, a polysilicon layer.

[0029] Multiple plugs PG are disposed in the insulating layer 60, and the source line SL and the electrode film EL are electrically connected through the plugs PG. Thus, a source potential can be applied to the source line SL from outside the semiconductor device 1 through the electrode film EL and the plugs PG.

[0030] like Figure 1A , Figure 1B As shown, a stacked layer LM, composed of multiple word lines WL, is arranged on the source line SL. A memory region MR is arranged in the center of the stacked layer LM, and stepped regions ER are arranged at both ends of the stacked layer LM. These memory regions MR and stepped regions ER are divided into multiple regions by multiple plate-shaped contacts LI, which extend through the stacked layer LM in the X direction.

[0031] Multiple pillars PL are arranged in the storage region MR, and the multiple pillars PL extend through the word line WL in the stacking direction. The lower end of the pillar PL reaches the source line SL. Multiple memory cells are formed at the intersection of the pillar PL and the word line WL. Thus, the semiconductor device 1 is configured, for example, as a three-dimensional non-volatile memory in which memory cells are arranged in three dimensions in the storage region MR.

[0032] The stepped area ER is equipped with multiple contacts CC that are connected to multiple word lines WL respectively.

[0033] Write and read voltages are applied to the memory cells contained in the memory region MR in the central part of the stacked matrix LM via contact CC, through word lines WL at the same height as the memory cells. In this way, word lines WL, which are multi-layered, are brought out separately through these contacts CC.

[0034] Multiple word lines WL, posts PL, and contacts CC are covered by an insulating layer 50. The insulating layer 50 also extends around the multiple word lines WL.

[0035] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. Peripheral circuitry CBA, including transistors TR and wiring, is disposed on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from the contacts CC are controlled by the peripheral circuitry CBA, which is electrically connected to these contacts CC. In this way, the peripheral circuitry CBA controls the electrical operation of the memory cell.

[0036] The peripheral circuit CBA is covered by an insulating layer 40. The semiconductor device 1 is formed by bonding the insulating layer 40 to the insulating layer 50 covering the stacked body LM. The semiconductor device 1 includes multiple word lines WL, pillars PL and contacts CC, as well as the peripheral circuit CBA.

[0037] Next, use Figures 2A to 3B A detailed configuration example of semiconductor device 1 will be described. Figure 2A , Figure 2B This is a cross-sectional view showing a detailed configuration example of the storage region MR in the implementation method.

[0038] Figure 2A This is a cross-sectional view along the Y direction of the storage region MR of semiconductor device 1. Figure 2A The structure above the insulating layer 52 and below the insulating layer 60 is omitted in the text. Figure 2B This is an enlarged sectional view of column PL at the height of the mating surface SP1.

[0039] like Figure 2A As shown, the laminate LM has a structure in which laminates LM1, LM2, and LM3 are sequentially bonded together from bottom to top. Therefore, the laminate LM has a bonding surface SP1 between laminates LM1 and LM2, and a bonding surface SP2 between laminates LM2 and LM3. The laminate LM3 is sequentially covered by insulating layers 51 and 52. Insulating layers 51 and 52 constitute a part of the insulating layer 50 in FIG. 1.

[0040] The stacked body LM1 has a structure in which multiple word lines WL1 and multiple insulating layers OL1 are stacked alternately layer by layer. The topmost layer of the stacked body LM1 is, for example, the insulating layer OL1. Furthermore, the stacked body LM1 is an example of a first structure and a first stacked body. In addition, the word lines WL1 are an example of a first conductive layer, and the insulating layer OL1 is an example of a first insulating layer.

[0041] Multiple columns PL1 and plate-like portions LI1 are formed in the laminate LM1.

[0042] Multiple pillars PL1 have a generally cylindrical shape extending along the Z direction within the stacked body LM1. These pillars PL1 are, for example, tapered in shape with a diameter decreasing from the upper end to the lower end. The lower end of the multiple pillars PL1 reaches the source line SL, and the upper end reaches the bonding surface SP1. The multiple pillars PL1 sequentially have a core layer CR1, a channel layer CN1 serving as the first semiconductor layer, and a memory film ME1 from the center outwards. The pillars PL1 are an example of a first pillar-shaped body and a first pillar.

[0043] The plate-shaped portion LI1 is formed as a plate extending along the XZ direction within the laminate LM1. The lower end of the plate-shaped portion LI1 reaches the source line SL, and the upper end reaches the bonding surface SP1. In the plate-shaped portion LI1, the conductive portion EC1 and the pad layer LL1 are arranged sequentially from the inside. The plate-shaped portion LI1 is an example of the first plate-shaped portion.

[0044] The laminate LM2 is bonded to the laminate LM1 via the bonding surface SP1. The laminate LM2 has a structure in which multiple word lines WL2 and multiple insulating layers OL2 are stacked alternately layer by layer. The bottom layer of the laminate LM2 is the insulating layer OL2. Therefore, the bottom insulating layer OL2 of the laminate LM2 and the top insulating layer OL1 of the laminate LM1 are directly bonded via the bonding surface SP1. In addition, the top layer of the laminate LM2 is the insulating layer OL2. Furthermore, the laminate LM2 is an example of a second structure and a second laminate. In addition, the word lines WL2 are an example of a second conductive layer, and the insulating layer OL2 is an example of a second insulating layer.

[0045] Multiple columns PL2 and plate-like parts LI2 are formed in the laminate LM2.

[0046] Multiple pillars PL2 extend along the Z direction within the laminate LM2. The lower ends of the multiple pillars PL2 are connected in the Z direction to the upper ends of their respective pillars PL1 in the bonding surface SP1, and the upper ends of the multiple pillars PL2 reach the bonding surface SP2.

[0047] In more detail, such as Figure 2B As shown, each column PL2 has: an extension PE1 extending in the Z direction from the mating surface SP2 to a predetermined depth of the laminate LM2; and a joint PJ1 extending from the predetermined depth to the mating surface SP1. The joint PJ1 is connected to the lower end of the extension PE1 with a surface SE1 as a first surface, and is connected to the upper end of the column PL1 with a surface SE2 as a second surface.

[0048] The joint PJ1 is formed into a generally cylindrical shape with a diameter D2. The extension PE1 is formed into a generally cylindrical, tapered shape with its diameter decreasing from the upper end to the lower end. That is, the diameter D1 of the lower end of the extension PE1 is smaller than the diameter D3 of the upper end of the extension PE1. Furthermore, the diameter D2 of the joint PJ1 is greater than or equal to the diameter D1 of the lower end of the extension PE2, and less than or equal to the diameter D3 of the upper end of the extension PE2. The upper end of the extension PE2 is an example of the other end.

[0049] Each pillar PL2 has a core layer CR2, a channel layer CN2 serving as a second semiconductor layer, and a memory film ME2, starting from its center. The core layer CR2, the channel layer CN2, and the memory film ME2 are respectively connected to the core layer CR1, the channel layer CN1, and the memory film ME1 of pillar PL1 in the bonding surface SP1. Pillar PL2 is an example of a second pillar body and a second pillar.

[0050] The plate-shaped portion LI2 is formed as a plate extending along the XZ direction within the laminate LM2. The lower end of the plate-shaped portion LI2 is connected to the plate-shaped portion LI1 in the Z direction at the bonding surface SP1, and the upper end reaches the bonding surface SP2. In the plate-shaped portion LI2, a conductive portion EC2 and a padding layer LL2 are disposed from the inside. The lower end of the conductive portion EC2 is connected to the conductive portion EC1 of the plate-shaped portion LI1 in the bonding surface SP1. The plate-shaped portion LI2 is an example of a second plate-shaped portion.

[0051] On the upper surface of the laminate LM2, the laminate LM3 is bonded to it via the bonding surface SP2. The laminate LM3 has a structure in which multiple word lines WL3 and multiple insulating layers OL3 are stacked alternately layer by layer. The bottom layer of the laminate LM3 is the insulating layer OL3. Therefore, the top insulating layer OL2 of the laminate LM2 and the bottom insulating layer OL3 of the laminate LM3 are directly bonded to each other via the bonding surface SP2.

[0052] Furthermore, the word lines WL1 to WL3 are, for example, tungsten or molybdenum layers, and the insulating layers OL1 to OL3 are, for example, silicon oxide layers.

[0053] Multiple columns PL3 and plate-like portions LI3 are formed in the laminate LM3.

[0054] Multiple pillars PL3 extend along the Z direction within the laminate LM3. The lower ends of each of the multiple pillars PL3 are connected to the multiple pillars PL2 in the Z direction in the bonding surface SP2, and the upper ends of each of the multiple pillars PL3 penetrate through the uppermost insulating layer OL3 of the laminate LM3, reaching the insulating layer 51.

[0055] In addition, each of the multiple pillars PL3 also has: an extension PE2 extending from the insulating layer 52 to a predetermined depth in the Z direction from the insulating layer 52 to the laminate LM3; and a bonding portion PJ2 extending from the predetermined depth of the laminate LM3 to the mating surface SP2. Since the bonding portion PJ2 and the extension PE2 have the same configuration as the bonding portion PJ1 and the extension PE2, their description is omitted here.

[0056] Each of the multiple pillars PL3 has a core layer CR3, a channel layer CN3, a memory film ME3, and a capping layer CP above the core layer CR3, starting from the center. The core layer CR3, the channel layer CN3, and the memory film ME3 are respectively connected to the core layer CR2, the channel layer CN2, and the memory film ME2 of the pillar PL2 in the bonding surface SP2.

[0057] The capping layer CP is connected to the bit line BL disposed in insulating layer 52 via a plug CH disposed in insulating layers 51 and 52. The bit line BL is connected to the transistor TR (not shown) via an upper wiring and via. Figure 1A )connect.

[0058] Furthermore, the core layers CR1 to CR3 are, for example, silicon oxide, and the channel layers CN1 to CN3 and the capping layer CP are, for example, semiconductor layers such as polycrystalline silicon or amorphous silicon. Additionally, the memory films ME1 to ME3 have, in a direction from the center of each pillar PL1 to PL3 outwards, a tunnel insulating layer (not shown), a charge storage layer, and a barrier insulating layer, arranged sequentially (not shown). The tunnel insulating layer and the barrier insulating layer are, for example, silicon oxide layers, and the charge storage layer is, for example, a silicon nitride layer.

[0059] The plate-shaped portion LI3 is formed as a plate extending along the XZ direction within the laminate LM3. The lower end of the plate-shaped portion LI3 is connected to the plate-shaped portion LI2 in the Z direction at the bonding surface SP2, and the upper end reaches the insulating layer 52. Furthermore, a conductive portion EC3 and a padding layer LL3 are also disposed on the plate-shaped portion LI3 from the inside. The lower end of the conductive portion EC3 is connected to the conductive portion EC2 of the plate-shaped portion LI2 at the bonding surface SP2.

[0060] Furthermore, the padding layers LL1 to LL3 are, for example, silicon oxide layers. Additionally, the conductive parts EC1 to EC3, which are conductive materials, are, for example, tungsten layers, tungsten nitride layers, titanium layers, titanium nitride layers, molybdenum layers, or molybdenum nitride layers.

[0061] The column PL is formed by connecting the columns PL1 to PL3 described above to each other, and the plate-shaped contact LI is formed by connecting the plate-shaped parts LI1 to LI3 to each other.

[0062] Figures 3A-3B This is a diagram showing a detailed configuration example of the stepped region ER in the implementation method.

[0063] Figure 3A This is a cross-sectional view along the X direction of the stepped region ER of semiconductor device 1. Figure 3A The structure above the insulating layer 52 and below the insulating layer 60 is omitted in the text. Figure 3B This is an enlarged cross-sectional view of the contact point CC at the height position of the mating surface SP1.

[0064] like Figure 3A As shown, a stepped portion SR1 and a contact CC1 are formed at the end of the laminate LM1 in the X direction.

[0065] A stepped portion SR1 is formed by processing multiple word lines WL1 of the laminate LM1 into a stepped shape extending in the X direction. The stepped portion SR1 is covered by an insulating layer 53 up to the height of the uppermost insulating layer OL1, i.e., the height of the bonding surface SP1. The insulating layer 53 is, for example, a silicon oxide layer, and together with insulating layers 51 and 52, forms part of the insulating layer 50 in FIG. 1. Insulating layer 53 is an example of a third insulating layer. The stepped portion SR1 is an example of a first stepped portion.

[0066] Contact CC1 extends in the Z direction within insulating layer 53. The lower end of contact CC1 connects to the letter lines WL1 of each step constituting stepped portion SR1, and the upper end reaches the mating surface SP1. Contact CC1 has a conductive layer EL1 and an insulating layer LE1 from the inside to the outside. Contact CC1 is an example of a first column and a first contact.

[0067] In more detail, such as Figure 3B As shown, contact CC1 has: a bonding portion CJ1 extending in the Z direction from the mating surface SP1 to a predetermined depth in the insulating layer 53; and an extension portion CE1 extending from the predetermined depth to each letter line WL1. The bonding portion CJ1 is connected to the upper end of the extension portion CE1 via a surface SJ1, which is a third surface, and is connected to the lower end of contact CC2 via a surface SJ2, which is a fourth surface. The diameter D4 of the conductive layer EL1 formed in the bonding portion CJ1 is greater than or equal to the diameter D5 of the lower end of the conductive layer EL2 of contact CC2.

[0068] A stepped portion SR2 and a contact point CC2 are formed at the X-direction end of the laminate LM2.

[0069] Stepped section SR2 is formed by machining multiple letter lines WL2 of the laminate LM2 into a stepped shape extending in the X direction. The lowermost step surface TRb of each step in stepped section SR2 is located further towards the rising step than the uppermost step surface TRa of stepped section SR1. In other words, stepped sections SR1 and SR2 form a continuous stepped shape in the X direction. Stepped section SR2 is an example of a second stepped section.

[0070] The stepped portion SR2 and the bonding surface SP1 are covered by an insulating layer 54 up to the height of the uppermost insulating layer OL2, which is also the height of the bonding surface SP2. The insulating layer 54 is, for example, a silicon oxide layer, and together with the insulating layer 53, forms part of the insulating layer 50 in FIG1. ​​The insulating layer 54 is an example of a fourth insulating layer.

[0071] Contact CC2 extends in the Z direction within insulating layer 54. A portion of the lower end of contact CC2 connects to the letter lines WL2 of each step constituting stepped portion SR2, and the upper end reaches the mating surface SP2. Additionally, the lower end of the remaining portion of contact CC2 connects to contact CC1 in the Z direction within mating surface SP1, and the upper end reaches the mating surface SP2. Contact CC2 is an example of a second columnar body and a second contact.

[0072] Contact CC2 has a conductive layer EL2 and an insulating layer LE2 starting from the inside. The conductive layer EL2 is connected to the conductive layer EL1 in the bonding surface SP1.

[0073] In addition, contact CC2 also has: a joining portion CJ2 extending in the Z direction from the mating surface SP2 to a predetermined depth in the insulating layer 54; and an extension portion CE2 extending from the predetermined depth in the insulating layer 54 to the mating surface SP1. Since the joining portion CJ2 and the extension portion CE2 have configurations corresponding to the joining portion CJ1 and the extension portion CE1, their description is omitted here.

[0074] A stepped portion SR3 and a contact point CC3 are formed at the X-direction end of the laminate LM3.

[0075] The stepped section SR3 is formed by machining multiple letter lines WL3 of the laminate LM3 into a stepped shape extending in the X direction. The lowermost stepped surface TRd of the stepped section SR3 is located on the rising step side than the uppermost stepped surface TRc of the stepped section SR2. In other words, the stepped sections SR2 and SR3 form a continuous stepped shape in the X direction.

[0076] The stepped portion SR3 and the bonding surface SP2 are covered by an insulating layer 55 up to the height of the uppermost insulating layer OL3. The insulating layer 55 is, for example, a silicon oxide layer, and together with the insulating layers 53 and 54, forms part of the insulating layer 50 in FIG1. ​​Thus, insulating layers 53-55 are made of the same material, for example, and are therefore essentially integral.

[0077] Contact CC3 extends along the Z direction within insulating layer 55. The lower end of a portion of contact CC3 is connected to the letter lines WL3 of each step constituting the stepped portion SR3, and the upper end penetrates insulating layer 51 to reach insulating layer 52. In addition, the lower end of the remaining portion of contact CC3 is connected to contact CC2 in the mating surface SP2, and the upper end penetrates insulating layer 51 to reach insulating layer 52.

[0078] Contact CC3 has a conductive layer EL3 and an insulating layer LE3 starting from the inside. The conductive layer EL3 is connected to the conductive layer EL2 of contact CC2 in the mating surface SP2.

[0079] The conductive layer EL3 is connected to the upper layer wiring MX via the plug CH disposed in the insulating layer 52. Thus, the word lines WL1 to WL3 of each layer are electrically led out via contacts CC1 to CC3.

[0080] Contact CC is formed by connecting the contacts CC1 to CC3 described above together.

[0081] Furthermore, Figures 2 and 3 illustrate suitable number of layers for illustration as laminates LM1 to LM3, but the number of layers in laminates LM1 to LM3 is not limited to the examples shown. In each laminate LM1 to LM3, multiple word lines and multiple insulating layers can be laminated, for example, more than 100 layers.

[0082] Furthermore, when the aspect ratio is obtained by dividing the height of the column PL and the contact CC in the Z direction by the diameter of the portion with the largest diameter, such as the upper end of each, the aspect ratio of the column PL and the contact CC in this embodiment is, for example, 25 or more and 100 or less, more preferably 50 or more and 100 or less.

[0083] (Semiconductor device manufacturing method)

[0084] Figures 4A to 15 This is a diagram showing a part of the manufacturing process of a semiconductor device 1 according to an exemplary embodiment.

[0085] The manufacturing steps of the semiconductor device 1 include at least: a first step of forming a multilayer LM1 on a substrate SB1; a second step of forming a multilayer LM2 on a substrate SB2; a third step of forming a multilayer LM3 on a substrate SB3; and a bonding step of bonding the substrates SB1 to SB3 respectively.

[0086] Furthermore, step 1 includes at least the formation steps of the pillar PL1, contact CC1, and plate-shaped portion LI1; step 2 includes at least the formation steps of the pillar PL2, contact CC2, and plate-shaped portion LI2; and step 3 includes at least the formation steps of the pillar PL3, contact CC3, and plate-shaped portion LI3. Moreover, steps 1 to 3 each include an inspection step to check the shape of the formed pattern.

[0087] use Figures 4A to 9 The process of step 1 will be explained.

[0088] First of all, Figure 4A , Figure 4B The diagram shows the formation of portions on substrate SB1 that will subsequently become the stepped portion SR1 and the pillar PL1. Figure 4A The image shows a cross-section along the X direction of the portion of substrate SB1 that will subsequently become the stepped region ER. Figure 4B A cross-section along the Y direction is shown in the portion of substrate SB1 that will subsequently become the memory region MR.

[0089] like Figure 4A As shown, an insulating layer 60 and a source line SL are formed on a substrate SB1, such as a silicon substrate. A multilayer stack LMs1, consisting of multiple insulating layers OL1 and multiple sacrificial layers NL1, is formed on the source line SL by alternating layers. The substrate SB1 is an example of a first substrate.

[0090] The sacrificial layer NL1 is, for example, a silicon nitride layer. The sacrificial layer NL1 functions as a sacrificial layer that will subsequently be replaced by the word line WL1. The sacrificial layer NL1 is an example of a second insulating layer.

[0091] Subsequently, a stepped portion SR1 is fabricated on a portion of the laminate LMs1 through a series of steps: forming a mask using a photoresist, etching using the mask, refining the mask, and etching using the refined mask. At this point, the stepped portion SR1 is formed such that each step of the stepped portion SR1 is positioned between positions P1 and P2. Position P1 is located in the X direction at a distance L1 from a predetermined reference point P0 of the laminate LMs1, and position P2 is located in the X direction at a distance L2 from the predetermined reference point P0 of the laminate LMs1. Position P2 is closer to the reference point P0 than position P1. Therefore, each step of the stepped portion SR1 continuously increases from position P1 to position P2.

[0092] Subsequently, an insulating layer 53 is formed that covers the stepped section SR1 and reaches the height position of the uppermost insulating layer OL1.

[0093] like Figure 4BAs shown, an insulating layer 60, a source line SL, and a stacked matrix LMs1 are also formed on the substrate SB1 in the region that will subsequently become the memory region MR. Multiple memory vias MHA1 are formed, penetrating the stacked matrix LMs1 in the Z direction to reach the source line SL. The memory vias MHA1 are configured to form pillars PL1.

[0094] Here, the multiple exposure areas (shots) SH of the substrate SB1 are explained. Figure 5A This is a top view showing the state of the exposure area formed on substrate SB1. Figure 5B This is an example diagram showing the inspection results of the memory holes MHA1 formed in each exposure area.

[0095] like Figure 5A As shown, the area of ​​substrate SB1 excluding the outermost periphery is the element region DA where the semiconductor device 1 will be disposed. The element region DA is divided into multiple exposure regions SH1 to SHn (n is an integer greater than or equal to 1) by multiple intersecting dividing lines DL. Each of these exposure regions SH is an element of a processing unit in the manufacturing process of the semiconductor device 1.

[0096] In the Figure 4A , Figure 4B In this process, at least one stacked layer LMs1 is formed in each of the exposure regions SH1 to SHn. That is, at least n stacked layers LMs1 are formed on the substrate SB1, and multiple memory vias MHA1 are formed in each of the n stacked layers LMs1. In the final stage of the semiconductor device 1 manufacturing process, these n stacked layers LMs1 are monolithized along multiple dividing lines DL and cut into chip shapes, each carrying a semiconductor device 1. Therefore, the example in Figure 5 shows a case where the exposure region SH and the chip to be monolithized have approximately the same area. However, a single semiconductor device 1 chip may contain multiple stacked layers LM1, etc.

[0097] In the inspection step of memory hole MHA1, the substrate SB1 is first moved into the inspection apparatus. As an inspection apparatus, for example, a length measuring SEM (CD-SEM: Critical Dimension Scanning Electron Microscope) is used.

[0098] Length measurement SEM acquires image data of multiple memory holes (MHA1) formed on substrate SB1, analyzes the acquired image data, and measures the size of each memory hole (MHA1). For example, based on the size deviation of multiple memory holes (MHA1), length measurement SEM determines whether the memory hole (MHA1) is formed normally for each exposed area.

[0099] For example, if the dimensional deviation of multiple memory vias MHA1 exceeds a specified threshold, it is determined that the memory vias MHA1 have not formed properly (unqualified) in their exposure area, such as not penetrating the stacked body LMs1. If the memory vias MHA1 are not formed properly, then the pillars PL1 may not be formed properly in subsequent steps. As a result, the memory cell may sometimes not operate normally. On the other hand, if the dimensional deviation of multiple memory vias MHA1 is below the specified threshold, it is determined that the memory vias MHA1 have formed properly (qualified) in their exposure area.

[0100] like Figure 5B As shown, the length measurement SEM output establishes a correspondence between the judgment result and the exposure area number. The substrate SB1 is then removed from the inspection device, and the inspection process ends.

[0101] Furthermore, the determination process based on the measurement results of the memory hole MHA1 can also be performed in an information processing device different from the length measurement SEM. Additionally, these devices can also be operated by an operator or similar personnel.

[0102] Subsequently, in Figure 6A , Figure 6B The diagram shows the formation of multiple pillars PL1 and plate-like portions LI1 on a substrate SB1 that has undergone inspection. Figures 6A-6B A cross-section along the Y direction is shown in the portion of substrate SB1 that will subsequently become the memory region MR.

[0103] like Figure 6A As shown, a memory film ME1 and a channel layer CN1 are sequentially formed inside the memory aperture MHA1. Furthermore, before forming the channel layer CN1, the memory film ME1 on the bottom surface of the memory aperture MHA1 is removed. Thus, the channel layer CN1 is connected to the source line SL on its bottom surface. Additionally, a core layer CR1 is filled into the voids remaining inside the channel layer CN1. Through these operations, multiple pillars PL1 are formed.

[0104] Subsequently, a slit STA1 is formed that penetrates the stacked body LMs1 and reaches the source line SL. Slit STA1 also extends in the stacked body LMs1 along the X-direction. Slit STA1 is the part that will become the plate-like portion LI1.

[0105] Subsequently, in Figure 6B In the process, word lines WL1 are formed in the portion where the sacrificial layer NL1 of the laminate LMs1 is located, thus forming the laminate LMs1.

[0106] Specifically, firstly, the sacrificial layer NL1 is removed via wet etching through slit STA1. As a result, the sacrificial layer NL1 exposed on the side of slit STA1 is removed in both the X and Y directions, creating a space (not shown) between insulating layers OL1. This space extends in the XY plane and is arranged in a layered manner in the Z direction. Next, a raw material gas of a conductive material such as tungsten or molybdenum is injected into the space between the insulating layers OL1 through slit STA1. Thus, the sacrificial layer NL1 is replaced by word lines WL1, forming a stacked body LM1. The subsequent process of forming word lines at the locations where the sacrificial layer was previously located is sometimes referred to as a replacement process.

[0107] Subsequently, a padding layer LL1 is formed on the sidewall of the slit STA1, and a conductive part EC1 is filled in the padding layer LL1 to form a plate-shaped part LI1.

[0108] Next, in Figures 7A-8 The diagram shows the formation of contact CC. Figures 7A-7B and Figure 8 A cross-section along the X direction is shown in the portion of substrate SB1 that will subsequently become the stepped region ER.

[0109] like Figure 7A As shown, through Figure 6B The replacement process described herein also forms multiple word lines WL1 in the stepped section SR1.

[0110] Multiple contact holes HLc are formed that penetrate the insulating layer 53 and reach each word line WL1. The contact holes HLc will subsequently become the contact CC1.

[0111] Next, a photoresist film RF is coated on the multilayer LM1 and the insulating layer 53. Through exposure and development, the photoresist film RF is opened so that it is exposed above the contact hole HLc. Furthermore, the opening OP is made such that its diameter is larger than the diameter of the contact hole HLc. Additionally, using the photoresist film RF as a mask, dry etching is performed to a depth that does not penetrate the insulating layer 53. This forms the opening OP at the upper end of the contact CC1. The opening OP will subsequently become the junction CJ1.

[0112] Therefore, in the subsequent bonding step, when the joint SJ1 of contact CC1 is connected to the lower end of contact CC2, it can be ensured that the allowable range of positional offset of contact CC2 relative to the upper end of contact CC1 is large. As a result, contact CC1 and contact CC2 can be connected more reliably.

[0113] After removing the photoresist film RF, Figure 8In this process, conductive layers EL1 are filled into the insulating layer LE1 covering the sidewalls of multiple contact holes HLC, and into the gaps of the contact holes HLC retained inside the insulating layer LE1. Through the above operations, contact CC1 is formed.

[0114] Subsequently, in Figure 9 The diagram illustrates the process of monolithizing the substrate SB1 into multiple chips for each stacked layer LM1 and selecting qualified chips from these chips.

[0115] like Figure 9 As shown, substrate SB1 is cut along the dividing line DL in the Z direction. This forms chips CPL1 to CPLn. As described above, in this embodiment, chips CPL1 to CPLn each correspond to exposure areas SH1 to SHn.

[0116] Based on use Figure 5A , Figure 5B The inspection results of memory hole MHA1, as explained in the inspection steps, are used to filter chips from chips CPL1 to CPLn that contain "qualified" exposure areas. For example, in Figure 9 In this example, all chips except CPL3 are considered qualified. The selected qualified chips are then bonded to the other chips in the bonding step described later. With these steps completed, step 1 is finished.

[0117] Next, use Figures 10A to 12B The process of step 2 will be explained.

[0118] First, Figures 10 and 11 show the formation of the portion on the substrate SB2 that will subsequently become pillar PL2. Figures 10A to 10D , Figure 11A , Figure 11B A cross-section along the X direction is shown in the portion of substrate SB2 that will subsequently become the stepped region ER.

[0119] like Figure 10A As shown, a stacked body LMs21 is formed by alternately depositing a predetermined number of insulating layers OL2 and sacrificial layers NL2 on a substrate SB2, such as a silicon substrate. The sacrificial layer NL2 is, for example, a silicon nitride layer. The sacrificial layer NL2 functions as a sacrificial layer that will subsequently be replaced by word lines WL2. The sacrificial layer NL2 is an example of a third insulating layer. The substrate SB2 is an example of a second substrate.

[0120] like Figure 10B As shown, multiple holes MHA21 are formed, which penetrate the laminate LMs21 in the Z direction and reach the substrate SB2. Holes MHA21 will subsequently form part of the junction PJ1. The multiple holes MHA21 have a diameter D2.

[0121] like Figure 10C As shown, for example, a CVD carbon layer is embedded in a hole MHA21, and an insulating layer OL2 and a sacrificial layer NL2 are further deposited on top of the laminate LMs21 and the CVD carbon layer. Thus, the laminate LMs2 is formed.

[0122] Then, as Figure 10D As shown, a hole MHA22 is formed above hole MHA21. Hole MHA22 penetrates the insulating layer OL2 and the sacrificial layer NL2 in the Z direction, reaching the CVD carbon layer embedded in hole MHA21. Hole MHA22 will subsequently become part of the extension PE2. The upper end of hole MHA22 has a diameter D3, and the lower end has a diameter D1 smaller than D3. That is, hole MHA22 is a tapered shape with a diameter decreasing from the upper end to the lower end.

[0123] Here, the diameter D2 of hole MHA21 is larger than the diameter D1 of the lower end of hole MHA22. Therefore, in the subsequent bonding step, when the joint PJ1 of post PL2 is connected to the upper end of post PL1, a larger allowable range of positional offset of post PL2 relative to the upper end of post PL1 can be ensured. As a result, post PL1 and post PL2 can be connected more reliably.

[0124] Furthermore, the diameter D2 of hole MHA21 is less than or equal to the diameter D3 of the upper end of hole MHA22. In other words, when viewed from the Z direction, the cross-sectional area of ​​joint PJ1 does not exceed the cross-sectional area of ​​the upper end of column PL2. Therefore, it is possible to avoid a decrease in the arrangement density of columns PL2 due to the formation of joint PJ1. Additionally, it is possible to suppress interference between adjacent columns PL2 in joint PJ1.

[0125] like Figure 11A As shown, the CVD carbon layer in the embedded hole MHA21 is removed by ashing or other methods. This forms the memory hole MHA2.

[0126] Next, the substrate SB2 is moved into the inspection device to inspect the shape of the multiple memory holes MHA2 formed on the substrate SB2.

[0127] Although the diagram is omitted, the unshown component area of ​​substrate SB2 is also divided into n exposure areas corresponding to exposure areas SH1 to SHn. Figures 10A to 11A The process involves forming stacked layers LMs2 and multiple memory holes MHA2 in multiple exposure areas.

[0128] pass Figure 5A , Figure 5BThe method described herein determines whether the memory hole MHA2 is formed correctly for each exposed area. The output establishes a correspondence between the determination result and the exposed area number. The inspection process ends after the substrate SB2 is removed from the inspection apparatus.

[0129] Then, as Figure 11B As shown, a memory film ME2, a channel layer CN2, and a core layer CR2 are sequentially formed inside the memory hole MHA2 of the substrate SB2 after the inspection step. Before forming the channel layer CN2, the memory film ME2 on the bottom surface of the memory hole MHA2 is removed, so that the channel layer CN2 is in contact with the substrate SB2. Therefore, when subsequently connecting to the pillar PL1 of the laminate LM1, the channel layer CN2 can be connected to the channel layer CN1 of the pillar PL1. Through the above operations, multiple pillars PL2, each containing a junction portion PJ1 and an extension portion PE1, are formed.

[0130] Next, a slit (not shown) is formed that extends through the stacked body LMs2 and reaches the substrate SB2. Through a replacement process, a word line WL2 is formed at the location of the sacrificial layer NL2 of the stacked body LMs2, thus forming the stacked body LM2. A pad layer LL2 and a conductive portion EC2 are formed within the slit. Through these operations, a plate-like portion LI2 is formed.

[0131] Next, Figure 12 shows the formation of contact CC2. Figure 12A , Figure 12B A cross-section along the X direction is shown in the portion of substrate SB2 that will subsequently become the stepped region ER.

[0132] The region that will subsequently become the stepped region ER on substrate SB2, through Figures 10A to 10C The stacked body LMs2 is formed by the process shown, and although detailed description is omitted, the stepped portion SR2 is formed by a process corresponding to the stepped portion SR1. Then, an insulating layer 54 reaching the height of the uppermost insulating layer OL2 is formed on the substrate SB2 and the stepped portion SR2. Then, through... Figure 11B The replacement process in the middle forms, such as Figure 12A The multiple word lines WL2 are shown.

[0133] When forming the stepped portion SR2, the stepped surface formed as the stepped portion SR2 is arranged between position P2 and position P3. Position P2 is a position in the X direction at a distance L2 from a predetermined reference point P0 of the laminate LMs2, and position P3 is a position in the X direction at a distance L3 from the predetermined reference point P0 of the laminate LMs2. Reference point P0 is defined such that the positions on each substrate SB1, SB2 are aligned with the positions on the laminate LMs2. Figure 4AIn the processing, the reference point P0 set for the laminate LMs1 is the same. The distance L2 from the reference point P0 at position P2 is the same as the position P2 set for the laminate LMs1. Position P3 is closer to the reference point P0 than position P2. Therefore, each step of the stepped section SR2 rises continuously from position P2 to position P3. Thus, when the laminates LM1 and LM2 are subsequently bonded together with their respective reference points P0 overlapping vertically, the stepped sections SR1 and SR2 become a continuous stepped shape in the X direction.

[0134] Subsequently, after discussions with Figure 7A , Figure 7B and Figure 8 The processing shown corresponds to the processing, forming Figure 12B The contact shown is CC2.

[0135] Next, after grinding the substrate SB2 until the bottom insulating layer OL2 is exposed from below, it is cut along the dividing line in the Z direction. Thus, n chips are formed.

[0136] Subsequently, based on Figure 11A The inspection results of the memory hole MHA2 output in the inspection step are used to select chips containing "qualified" exposure areas from n chips. The selected qualified chips are then bonded to the other chips in the bonding step, which will be described later. With these operations completed, step 2 ends.

[0137] Next, use Figures 13A to 14B The process of step 3 will be explained.

[0138] First of all, Figure 13A This illustrates the formation of a portion on substrate SB3 that will subsequently become pillar PL3. Figure 13A A cross-section along the X direction is shown in the portion of substrate SB3 that will subsequently become the memory region MR.

[0139] Specifically, on a substrate SB3 such as a silicon substrate, an insulating layer OL3 and a sacrificial layer NL3 are alternately deposited layer by layer to form a stacked body LMs3. The sacrificial layer NL3 is, for example, a silicon nitride layer. The sacrificial layer NL3 functions as a sacrificial layer to be subsequently replaced by word lines WL3.

[0140] Through with Figures 10A to 11A The corresponding processing forms multiple memory holes MHA3, which penetrate the stacked layer LMs3 in the Z direction and reach the substrate SB3.

[0141] Furthermore, the plurality of memory holes MHA3 include hole MHA31, which will subsequently become the junction PJ2, and hole MHA32, which will subsequently become the extension PE2. Regarding the method of forming holes MHA31 and MHA32, [the following is a description of the method used]. Figures 10A to 10D The explanation has already been provided, therefore, it is omitted here.

[0142] Next, the substrate SB3 is moved into the inspection device to inspect the shape of the multiple memory holes MHA3 formed on the substrate SB3.

[0143] Although the diagram is omitted, the unshown component area of ​​substrate SB3 is also divided into n exposure areas corresponding to the exposure areas SH1 to SHn of substrate SB1. Multilayer stacks LMs3 and multiple memory vias MHA3 are formed in these multiple exposure areas.

[0144] pass Figure 5A , Figure 5B The method described herein determines whether the memory hole MHA3 is formed correctly for each exposed area. The output establishes a correspondence between the determination result and the exposed area number. The inspection process ends after the substrate SB3 is removed from the inspection apparatus.

[0145] Then, as Figure 13B As shown, a memory film ME3, a channel layer CN3, and a core layer CR3 are sequentially formed inside the memory hole MHA3 of the substrate SB3 after the inspection step. A capping layer CP is formed above the core layer CR3. Through the above operations, multiple pillars PL3 are formed.

[0146] Next, an insulating layer 51 is formed on the laminate LMs3, and a slit (not shown) is formed that penetrates the laminate LMs3 and the insulating layer 51 in the Z direction and reaches the substrate SB3. The laminate LM3 is then formed by a replacement process. A pad layer LL3 and a conductive portion EC3 are formed in the slit. Through the above operations, a plate-shaped portion LI3 is formed.

[0147] An insulating layer 52 is formed on the insulating layer 51, and a plug CH is formed in the insulating layer 52 extending in the Z direction and connecting to the capping layer CP and the conductive portion EC3. A bit line BL connected to the post PL3 ​​via the plug CH and an upper layer wiring MX connected to the conductive portion EC3 via the plug CH are formed.

[0148] Next, Figure 14 shows the formation of contact CC3. Figure 14A , Figure 14B A cross-section along the X direction is shown in the portion of substrate SB3 that will subsequently become the stepped region ER.

[0149] A multilayer LMs3 is formed in the region of substrate SB3 that will subsequently become the step region ER, and a step portion SR3 is formed through a process corresponding to the step portions SR1 and SR2. Then, an insulating layer 55 is formed on substrate SB3 and the step portion SR3, reaching a height position of the uppermost insulating layer OL3, and through a replacement process, an insulating layer 55 is formed as shown. Figure 14AThe multiple word lines WL3 are shown.

[0150] also, Figure 14A It shows the use of the Figure 13B The process is to form the state before the insulating layer 52, plug CH, bit line BL and upper wiring MX are formed.

[0151] When forming the stepped portion SR3, the stepped surface of the stepped portion SR3 is positioned between position P3 and reference point P0. Position P3 is a position in the X direction at a distance L3 from the predetermined reference point P0 of the laminate LMs3. Reference point P0 is set at the same position as the reference point P0 set for the laminates LMs1 and LMs2, and position P3 is set at the same position P3 set for the laminate LMs2. Furthermore, each step of the stepped portion SR3 continuously rises from position P3 towards the reference point P0. Thus, when the laminates LM2 and LM3 are subsequently bonded together with their respective reference points P0 overlapping vertically, the stepped portions SR2 and SR3 become a continuous stepped shape in the X direction.

[0152] Subsequently, multiple contact holes are formed, penetrating the insulating layer 55 and reaching each word line WL1 and the substrate SB3. An insulating layer LE3 and a conductive layer EL3 are formed within these contact holes. Through the above operations, as... Figure 14B As shown, contact CC3 is formed.

[0153] In addition, with the above Figure 13B In parallel processing, in the stepped section SR3, an insulating layer 52 is also formed on the insulating layer 51, and a plug CH is formed in the insulating layer 52 extending in the Z direction and connected to the contact CC3 of the conductive layer EL3. An upper layer wiring MX is formed that is connected to the contact CC3 via the plug CH.

[0154] Next, the substrate SB3 is polished until the bottom insulating layer OL3 is exposed from below, and then cut along the dividing line in the Z direction. In this way, n chips are formed.

[0155] Subsequently, based on Figure 13A The inspection results of memory hole MHA3 output in the inspection step are used to select chips containing "qualified" exposure areas from n chips. After the above operations, step 3 ends.

[0156] Next, in Figure 15 The image shows the process of bonding the chips selected in steps 1 through 3 together. Figure 15 A cross-section along the X direction is shown, which will subsequently become part of the storage region MR. Figure 15 The bonding step shown is performed as part of the manufacturing process of semiconductor device 1.

[0157] Although the illustration is omitted here, the upper surface F15 of the monolithized multilayer LM3 is respectively attached to the semiconductor substrate SB, which contains multiple peripheral circuits CBA, corresponding to the multiple exposure areas set on the semiconductor substrate SB.

[0158] For example, the upper surface F15 of the multilayer LM3 and the insulating layer 40 covering the peripheral circuit CBA can be pretreated using plasma or similar methods (see reference). Figure 1A The LM3 stack and the peripheral circuit CBA are then activated and bonded together. This electrically connects the LM3 stack and the CBA.

[0159] Then, as Figure 15 As shown, the lower surface F14 of the laminate LM3 is bonded to the upper surface F13 of the laminate LM2 cut from the substrate SB2 and screened out.

[0160] These laminates LM2 and LM3 can be joined, for example, by activating the upper surface F14 and lower surface F13 beforehand using plasma treatment. Furthermore, when joining laminates LM2 and LM3, they are aligned such that the pillar PL2, plate-like portion LI2, and contact CC2 (not shown) formed on laminate LM2 coincide with the pillar PL3, plate-like portion LI3, and contact CC3 (not shown) formed on laminate LM3 in the Z direction.

[0161] After the laminates LM2 and LM3 are joined together, an annealing process is performed. This electrically connects the pillars PL2-PL3, the plate portions LI2-LI3, and the contacts CC2-CC3.

[0162] Then, the lower surface F12 of the laminate LM2 is bonded to the lower surface F11 of the laminate LM1, respectively.

[0163] Next, using CMP (Chemical Mechanical Polishing) or similar methods, the substrate SB1 and the insulating layer 60 are polished from below the substrate SB1 to the specified position of the insulating layer 60, thereby forming a plug PG that penetrates the insulating layer 60 and reaches the source line SL. At this time, the insulating layer 60 can also be thickened as needed. Then, the electrode film EL is formed below the plug PG.

[0164] Through the above operations, the manufacturing of semiconductor device 1 is completed.

[0165] (Summary)

[0166] Previously, with the miniaturization of semiconductor devices, it was desirable to increase the number of word lines and arrange more pillar patterns in order to form more memory cells within a defined area of ​​the semiconductor device. Due to the high stacking density of word lines and pillar patterns, sometimes reducing the diameter of each pillar pattern also results in the pillar patterns being too close together. If the diameter of the pillar patterns decreases while increasing the stacking density of word lines, problems such as poor pattern bottom detachment can sometimes occur during etching. The more word lines stacked, that is, the higher the aspect ratio of the pillar patterns, the more significant these problems become. Furthermore, if the pillar patterns are arranged too close together, short circuits can sometimes occur between the pillar patterns.

[0167] The semiconductor device 1 of the embodiment includes a stacked body LM1, a pillar PL1 extending in the Z direction within the stacked body LM1, a stacked body LM2, a pillar PL2 extending in the Z direction within the stacked body LM2, and a bonding surface SP1 disposed between the pillar PL1 and the pillar PL2. The pillar PL1 and the pillar PL2 are connected in the Z direction in the bonding surface SP1.

[0168] In this way, by connecting columns PL1 and PL2, which are formed in different stacked bodies, in the Z direction, it is easy to form columns PL with a high aspect ratio.

[0169] Furthermore, in the semiconductor device 1 of the embodiment, the pillar PL2 has: an extension PE2 extending in the Z direction within the laminate LM2; and a bonding portion PJ1 connected to the lower end of the extension PE2 with surface SE1 and to the upper end of the pillar PL1 with surface SE2. The diameter of the bonding portion PJ1 is greater than or equal to the diameter of the lower end of the extension PE2 and less than or equal to the diameter of the upper end of the extension PE2.

[0170] By setting the diameter D2 of the joint PJ1 to be greater than or equal to the diameter D1 of the lower end of the extension PE2, a larger allowable range of positional offset can be ensured when the upper ends of the post PL2 and post PL1 are connected. Furthermore, by setting the diameter D2 of the joint PJ1 to be less than or equal to the diameter D3 of the upper end of the extension PE2, the posts PL2 can be formed more closely together, and contact between adjacent posts PL2 within the joint PJ1 can be suppressed.

[0171] Furthermore, in the manufacturing method of the semiconductor device 1 according to the embodiment, when the substrate SB1 is monolithically formed, multiple stacked layers LM1 are inspected, and stacked layers LM1 that pass the inspection are selected. When the substrate SB2 is monolithically formed, multiple stacked layers LM2 are inspected, and stacked layers LM2 that pass the inspection are selected. The selected stacked layers LM1 and the selected stacked layers LM2 are then bonded together.

[0172] By bonding the inspected and qualified laminates LM1 and LM2 together, the formation defects of pillar PL can be reduced. This is because, for example, if pillar PL is formed together without bonding LM1 and LM2, a formation defect in either the portion corresponding to pillar PL1 or the portion corresponding to pillar PL2 would be judged as an overall pillar PL defect. By bonding the selected laminates together, the yield of semiconductor device 1 can be improved.

[0173] (Variation Example 1)

[0174] Figure 16 Figure 17 is a diagram illustrating a portion of the manufacturing process of the semiconductor device according to Variation 1. In the manufacturing process of the semiconductor device in Variation 1, the timing of bonding the laminates together differs from that in the embodiment described below. Furthermore, in the following Variation 1, for the sake of simplicity, the description will focus on the manufacturing process of the portion that will subsequently become the memory region MR. Additionally, hereafter, components identical to those in the embodiment will sometimes be labeled with the same symbols, and their descriptions will be omitted.

[0175] Figure 16 and Figure 17A , Figure 17B A cross-section along the X direction is shown, which will subsequently become part of the storage region MR.

[0176] First, an insulating layer 60, a source line SL, and a stacked body LMs1 are formed on the substrate SB1 to form a memory hole MHA1. Next, a slit STA1 is formed. After the memory hole MHA1 is inspected, a CVD carbon layer or the like is embedded in the memory hole MHA1 and the slit STA1.

[0177] Next, stacked layers LMs2 and memory vias MHA2 are formed on substrate SB2. Following an inspection of the memory vias MHA2, slits STA2 are formed, and CVD carbon layers are embedded within the memory vias MHA2 and slits STA2. Each stacked layer LMs2 is then monolithically assembled.

[0178] Next, stacked layers LMs3 and memory vias MHA3 are formed on substrate SB3. Following an inspection of the memory vias MHA3, slits STA3 are formed, and CVD carbon layers are embedded within the memory vias MHA3 and slits STA3. Additionally, an insulating layer 52 is formed on insulating layer 51, forming plugs CH, bit lines BL, and upper layer wiring MX. Each stacked layer LMs3 is monolithically fabricated.

[0179] Then, as Figure 16As shown, the upper surface F31 of stacked layer LMs1 is bonded to the lower surface F32 of stacked layer LMs2, and the upper surface F33 of stacked layer LMs2 is bonded to the lower surface F34 of stacked layer LMs3. That is, in Variation 1, the monolithized substrates SB2 to SB3 are bonded to the unmonolithified substrate SB1. Furthermore, whenever these stacked layers LM2 and LM3 are bonded to stacked layers LM1 and LM2 respectively, the substrates SB2 and SB3 of these stacked layers LM2 and LM3 are removed separately by CMP or the like. Additionally, when bonding stacked layers LM2 and LM3 to stacked layer LM1, in addition to using only stacked layers LM2 and LM3 with qualified chips, these stacked layers LM2 and LM3 are bonded only to the inspected and qualified stacked layer LM1.

[0180] Then, as Figure 17A As shown, after removing the CVD carbon layer, a memory film ME, a channel layer CN, a core layer CR, and a capping layer CP are formed in the memory holes MHA1 to MHA3, forming pillars PL. Subsequently, through a replacement process, laminates LM1 to LM3 are formed. A padding layer LL and a conductive portion EC are filled into the sidewalls of slits STA1 to 3 to form plate-shaped contacts LI.

[0181] Subsequently, although the illustration is omitted, the semiconductor substrate SB containing the peripheral circuit CBA is attached to the upper surface F35 of the multilayer LM3. After removing the substrate SB1 of the multilayer LM1 by CMP or similar means, as shown... Figure 17B As shown, a plug PG with a through insulating layer 60 and an electrode film EL are formed below the source line SL. Then, the substrate SB is monolithized for each stack LM1 to LM3 and the peripheral circuit CBA.

[0182] Through the above operations, the semiconductor device of Variation 1 is manufactured.

[0183] The semiconductor device and its manufacturing method according to Variation 1 achieve the same effects as the described embodiment.

[0184] [Variation Example 2]

[0185] Next, use Figure 18 Variation 2 will now be described. The configuration of the stepped region ER of the semiconductor device in Variation 2 differs from that in Embodiment 1.

[0186] Figure 18 This is a diagram showing the detailed structure of the stepped region ER in variation example 2. More specifically, Figure 18 It is a cross-sectional view of the stepped region ER along the X direction, and is related to... Figure 3A The corresponding diagram. Furthermore, in Figure 18In this text, the structures above the insulating layer 52 and below the insulating layer 60 are omitted. Furthermore, in the following, the same symbols may be used to refer to components identical to those in Embodiment 1 and Variation 1, and their descriptions will be omitted.

[0187] like Figure 18 As shown, multiple contacts CC1 are formed at the X-direction end of the laminate LM1. These multiple contacts CC1 extend along the Z-direction within the laminate LM1. That is, in the laminate LM1 where the stepped portion SR1 is not formed... Figure 3A The lower ends of contact CC1 reach the respective letter lines WL1 that constitute the laminate LM1, and the upper ends reach the mating surface SP1. The depth reached by the lower ends of contact CC1 gradually becomes shallower when viewed from the end side of the laminate LM1 in the X direction.

[0188] Multiple contacts CC2 are formed at the X-direction end of the laminate LM2. The contacts CC2 extend along the Z-direction within the laminate LM2. That is, before the stepped portion SR2 is formed in the laminate LM2... Figure 3A The lower end of a portion of contact CC2 reaches the letter lines WL2 constituting the laminate LM2, and the upper end reaches the mating surface SP2. The depth reached by the lower end of contact CC2 gradually decreases when viewed from the end side of the laminate LM2 in the X direction. In addition, the lower end of the remaining portion of contact CC2 is connected to contact CC1 in the Z direction in the mating surface SP1, and the upper end reaches the mating surface SP2.

[0189] Multiple contacts CC3 are formed at the X-direction end of the laminate LM3. The contacts CC3 extend along the Z-direction within the laminate LM3. That is, no stepped portion SR3 is formed in the laminate LM3. Figure 3A The lower end of a portion of contact CC3 reaches the word line WL3 constituting the laminate LM3, and the upper end penetrates the insulating layer 51 and reaches the insulating layer 52. The depth reached by the lower end of contact CC3 gradually decreases when viewed from the end side of the laminate LM3 in the X direction. In addition, the lower end of the remaining portion of contact CC3 is connected to contact CC2 in the mating surface SP2, and the upper end penetrates the insulating layer 51 and reaches the insulating layer 52.

[0190] By connecting the contacts CC1 to CC3 as described above, a contact CC with a depth that gradually decreases from the end side in the X direction is formed. Furthermore, although the illustration is omitted, the semiconductor device of Variation 2 may also have a configuration corresponding to the junction CJ1 and extension CE1 of Embodiment 1.

[0191] Furthermore, although the illustrations are omitted, the semiconductor device of Variation Example 2 is manufactured in the same manner as Embodiment 1 through steps 1 to 3 and the bonding step.

[0192] In step 1, forming contact CC1, after forming the multilayer LMs1, a mask pattern with multiple openings is formed on the upper surface of the multilayer LMs1. The mask pattern is, for example, a silicon oxide layer. Next, a resist pattern covering a portion of the mask pattern is formed, and the multilayer LMs1 is etched through the mask pattern exposed from the resist pattern. Then, the resist pattern is refined so that the openings of the mask pattern gradually expose from the end side in the X direction, while etching is repeated. This forms a contact hole whose depth gradually decreases from the end side in the X direction. A replacement process is then performed, and then the insulating layer LE1 and the conductive layer EL1 are filled into the contact hole, respectively. Through these operations, contact CC1 is formed. Then, after screening for qualified chips, step 1 ends.

[0193] In each of steps 2 and 3, contacts CC2 and CC3 are formed through steps corresponding to those in step 1. Then, after bonding steps, the manufacturing of the semiconductor device of Variation 2 is completed.

[0194] The semiconductor device and its manufacturing method according to Variation 2 achieve the same effects as Embodiment 1 and Variation 1.

[0195] (Other variations)

[0196] In the described embodiments and variations, the shape of the memory holes MHA1 to MHA3 was inspected during the inspection step. However, the inspection target is not limited to the memory holes MHA1 to MHA3. For example, contact holes HLc, slits STA1 to STA3, or pillars PL1 to PL3 on which the memory film ME, channel layer CN, and core layer CR are formed may also be inspected.

[0197] In the described embodiments and variations, joints PJ1 and PJ2 are formed at the lower ends of pillars PL2 and PL3, while joints CJ1 and CJ2 are formed at the upper ends of contacts CC1 and CC2. However, the formation positions of the joints are not limited to these descriptions. For example, joints PJ1 and PJ2 may be formed at the upper ends of pillars PL1 and PL2, and joints CJ1 and CJ2 may be formed at the lower ends of contacts CC2 and CC3. Furthermore, when sufficient alignment accuracy is achieved when joining the various laminates LM1 to LM3, joints PJ1 and PJ2 of pillars PL2 and PL3, and joints CJ1 and CJ2 of contacts CC2 and CC3, may not be formed.

[0198] In the described embodiments and variations, multilayers LM1 to LM3 are formed on substrates SB1 to SB3 respectively, but the multilayers LM1 to LM3 may not be distinguished. For example, multilayers with the same structure may be formed on multiple substrates. Alternatively, multilayers with the same structure may be formed on a single substrate. Then, they are monolithically processed, qualified chips are selected from them, and they are sequentially bonded to substrate SB on which the peripheral circuit CBA is formed, in any of the embodiments or variations 1 and 2. In this case, bit lines BL, upper layer wiring MX, plugs CH, etc., can be pre-formed on the peripheral circuit CBA side. In addition, by forming source lines SL, insulating layer 60, plugs PG, and electrode films EL on the side of the multilayer LM opposite to the peripheral circuit CBA after bonding with the peripheral circuit CBA, the same semiconductor device 1 as described in the embodiments can be obtained.

[0199] In the described embodiments and variations, the semiconductor device 1 includes three stacked layers LM1 to LM3. However, the semiconductor device 1 may also include two or more stacked layers.

[0200] Furthermore, in the described embodiments and variations, pillars or the like are formed in a state where at least one of the substrates SB1 to SB3 is not monolithized. However, for example, it is also possible to monolithize all of the substrates SB1 to SB3 before forming pillars or the like, and to form pillars or the like on substrates SB1 to SB3 while they are fixed to a non-monolithically monolithized substrate different from substrates SB1 to SB3.

[0201] In the described embodiments and variations, the case of forming a three-dimensional non-volatile memory as a semiconductor device 1 has been explained, but the application of the present invention is not limited to three-dimensional non-volatile memories. The present invention can also be applied to other semiconductor devices with structures having a high aspect ratio. For example, the present invention can also be applied to volatile memories such as DRAM (Dynamic Random Access Memory).

[0202] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention and are included in the scope of the invention as set forth in the claims and their equivalents.

[0203] [Explanation of Symbols]

[0204] 1: Semiconductor devices

[0205] CC, CC1, CC2, CC3: Contacts

[0206] CE1, CE2, PE1, PE2: Extensions

[0207] CJ1, CJ2, PJ1, PJ2: Joint

[0208] CN, CN1, CN2, CN3: Channel Layer

[0209] CR, CR1, CR2, CR3: Core layer

[0210] D1,D2,D3,D4,D5: diameter

[0211] EL1, EL2, EL3: Conductive parts

[0212] ER: Stepped area

[0213] LI1, LI2, LI3: plate-shaped part

[0214] LM1, LM2, LM3, LMs1, LMs2, LMs3, LMs21: laminated body

[0215] NL1, NL2, NL3: Sacrificial Layers

[0216] ME, ME1, ME2, ME3: Memory membranes

[0217] OL1, OL2, OL3: Insulation layer

[0218] 100, SB1, SB2, SB3: Substrates

[0219] SP1, SP2: Adhesive Surface

[0220] SR1, SR2, SR3: Stepped section

[0221] WL1, WL2, WL3: Word lines

[0222] PL, PL1, PL2, PL3: Columns.

Claims

1. A semiconductor device comprising: First structure; The first column extends along the first direction within the first structure; Second structure; A second columnar body extends within the second structure along the first direction; and The bonding surface is disposed between the first structure and the second structure; and In the bonding surface, the first columnar body and the second columnar body are connected in the first direction.

2. The semiconductor device according to claim 1, wherein The first structure is configured as a first layered structure. The first laminate is formed by alternating layers of a first conductive layer and a first insulating layer. The first columnar body constitutes the first column. The first pillar has a first semiconductor layer extending along the first direction within the first stacked body. The second structure is configured as a second laminate. The second laminate is formed by alternating layers of multiple second conductive layers and multiple second insulating layers. The second column is configured as a second column. The second pillar has a second semiconductor layer extending along the first direction within the second stacked body.

3. The semiconductor device according to claim 2, wherein The second column has: The extension extends along the first direction within the second laminate; and The joint is connected to the end of the extension on the mating surface side with a first surface, and to the end of the first post on the mating surface side with a second surface; and The diameter of the joint is greater than or equal to the diameter of the end of the extension on the mating surface side and less than or equal to the diameter of the other end of the extension.

4. The semiconductor device according to claim 1, wherein The first structure is configured as a first layered structure. The first laminate is formed by alternating layers of a plurality of first conductive layers and a plurality of first insulating layers, and includes a first stepped portion. The first stepped portion is formed by processing the plurality of first conductive layers into a stepped shape extending in a second direction intersecting the first direction. The first step is covered by the third insulating layer. The first columnar body constitutes the first contact point. The first contact extends along the first direction in the third insulating layer and is connected to any one of the plurality of first conductive layers that are processed into a stepped shape. The second structure is configured as a second laminate. The second laminate is formed by alternating layers of a plurality of second conductive layers and a plurality of second insulating layers, and includes a second stepped portion. The second stepped portion is formed by processing the plurality of second conductive layers into a stepped shape that is continuous with the first stepped portion in the second direction. The second step is covered by a fourth insulating layer. The second columnar body constitutes the second contact point. The second contact extends along the first direction in the fourth insulating layer and is connected to any one of the plurality of second conductive layers that are processed into a stepped shape.

5. The semiconductor device according to claim 4, wherein The first and second contacts have conductive portions containing a conductive material. The diameter of the conductive portion in the bonding surface of the first contact is greater than the diameter of the conductive portion in the bonding surface of the second contact.

6. The semiconductor device according to claim 2, further comprising: The first plate-like portion extends within the first structure along the first direction and in a second direction intersecting the first direction; and The second plate-like portion extends within the second structure along both the first and second directions; and The first plate-shaped portion and the second plate-shaped portion are connected in the first direction on the mating surface.

7. A method for manufacturing a semiconductor device, wherein... A first structure and a first columnar body extending along a first direction are formed on a first substrate. A second structure is formed on a second substrate, and a second columnar body extends within the second structure along the first direction. Using the first surface of the first structure intersecting the first direction and the second surface of the second structure intersecting the first direction as bonding surfaces, the first structure and the second structure are bonded together so that the first columnar body and the second columnar body are connected in the first direction.

8. The method of manufacturing a semiconductor device according to claim 7, wherein When forming the first structure and the first columnar body Form a plurality of first structures that include the first structure. Each of the plurality of first structures forms a plurality of first columnar bodies containing the first columnar bodies. When forming the second structure and the second columnar body, Form a plurality of second structures that include the second structure. Each of the plurality of second structures forms a plurality of second columnar bodies containing the second columnar bodies. Before attaching the first structure to the second structure, For each individual first structure of the plurality of first structures, the first substrate is monolithically prepared. The second substrate is monolithically formed for each individual second structure of the plurality of second structures.

9. The method of manufacturing a semiconductor device according to claim 8, wherein When the first structure and the second structure are attached together, The multiple first structures are inspected, and the first structures that pass the inspection are selected. Perform the checks on the multiple second structures, and select the second structures that pass the checks. The first and second substrates containing the selected first and second structures are bonded together.

10. The method of manufacturing a semiconductor device according to claim 7, wherein The first structure is configured as a first layered structure. The first laminate is formed by alternating layers of a first conductive layer and a first insulating layer. The first columnar body constitutes the first column. The first pillar has a first semiconductor layer extending along the first direction within the first stacked body. The second structure is configured as a second laminate. The second laminate is formed by alternating layers of multiple second conductive layers and multiple second insulating layers. The second column is configured as a second column. The second pillar has a second semiconductor layer extending along the first direction within the second stacked body.

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