Semiconductor device and method for manufacturing semiconductor device

Abstract

Embodiments provide a semiconductor device capable of stacking a plurality of transistors while suppressing an increase in parasitic capacitance, and a method of manufacturing the semiconductor device. According to one embodiment, a semiconductor device includes: a semiconductor substrate; a first transistor provided on the semiconductor substrate; a semiconductor layer provided above the semiconductor substrate and having a smaller area than the semiconductor substrate; a second transistor provided on a side of the semiconductor layer facing the semiconductor substrate; an insulating layer provided on the semiconductor layer and having a larger area than the semiconductor layer; and a contact extending upward from the first transistor through the insulating layer at a position not overlapping the semiconductor layer in the vertical direction.

Description

Related applications

[0001] This application claims priority to Japanese Patent Application No. 2024-159434 (filed on September 13, 2024). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0002] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing a semiconductor device. Background Technology

[0003] A semiconductor device is known to have multiple transistors disposed on a semiconductor substrate. To achieve miniaturization of the semiconductor device, attempts are made, for example, to stack multiple semiconductor substrates on which transistors are disposed. However, in order to bring out the transistors on the lower layer to the upper layer, it is necessary to penetrate the semiconductor substrate on which the transistors on the upper layer are disposed and to provide contacts, etc., which leads to an increase in parasitic capacitance. Summary of the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device and a method for manufacturing a semiconductor device that can stack multiple transistors while suppressing the increase of parasitic capacitance.

[0005] The semiconductor device of the embodiment includes: a semiconductor substrate; a first transistor disposed on the semiconductor substrate; a semiconductor layer disposed above the semiconductor substrate and having an area smaller than that of the semiconductor substrate; a second transistor disposed on the side of the semiconductor layer opposite to the semiconductor substrate; an insulating layer disposed on the semiconductor layer and having an area larger than that of the semiconductor layer; and a contact extending upward from the first transistor through the insulating layer at a position that does not overlap with the semiconductor layer in the vertical direction. Attached Figure Description

[0006] Figure 1 This is a block diagram of the semiconductor device involved in the implementation. Figure 2 This is an equivalent circuit diagram illustrating an example of the configuration of a memory cell array in a semiconductor device according to an embodiment. Figure 3 This is a circuit diagram illustrating an example of the configuration of the sense amplifier circuit and latch circuit included in the semiconductor device according to the embodiment. Figure 4 This is a circuit diagram illustrating an example of the configuration of a line decoder included in a semiconductor device according to an embodiment. Figure 5 This is a cross-sectional view showing an example of the configuration of a semiconductor device according to an embodiment. Figure 6This is a cross-sectional view illustrating a portion of the steps in the manufacturing method of the semiconductor device according to the embodiments. Figure 7 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor device according to an embodiment. Figure 8 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor device according to an embodiment. Figure 9 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor device according to an embodiment. Figure 10 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor device according to an embodiment. Figure 11 This is a cross-sectional view illustrating a portion of the steps in the manufacturing method of the semiconductor device according to the embodiments. Figure 12 This is a cross-sectional view illustrating a portion of the steps in the manufacturing method of the semiconductor device according to the embodiments. Figure 13 This is a cross-sectional view illustrating a portion of the steps in a method for manufacturing a semiconductor device according to an embodiment. Figure 14 This is a cross-sectional view showing a configuration example of a semiconductor device according to a variation of the embodiment. Detailed Implementation

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below. Furthermore, the constituent elements in the following embodiments include elements readily conceived by those skilled in the art or substantially the same elements.

[0008] [Circuit Structure of Semiconductor Devices] First, use Figures 1-4 An example of the circuit configuration of the semiconductor device 1 in the embodiment will be described.

[0009] (Overall structure of a semiconductor device) Figure 1 This is a block diagram of the semiconductor device 1 according to the embodiment. For example... Figure 1 As shown, the semiconductor device 1 includes: an input / output circuit 310, a logic control circuit 320, a status register 330, an address register 340, a command register 350, a sequencer 360, a ready / busy circuit 370, a voltage generation circuit 380, a memory cell array 510, a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550.

[0010] The input / output circuit 310 controls the input and output of signal DQ between the semiconductor device 1 and external devices such as a memory controller (not shown). The input / output circuit 310 includes input circuitry and output circuitry (not shown).

[0011] The input circuit sends the write data WDT and other data DAT received from the external device to the data register 540, the address ADD to the address register 340, and the command CMD to the command register 350.

[0012] The output circuit sends the status information STS received from the status register 330, the read data RDT and other data DAT received from the data register 540, and the address ADD received from the address register 340 to the external device.

[0013] The logic control circuit 320 receives signals from external devices, such as a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, and a read enable signal REn. Furthermore, the logic control circuit 320 controls the input / output circuit 310 and the sequencer 360 based on the received signals.

[0014] Status register 330 temporarily holds status information STS for actions such as writing, reading, and erasing data, and notifies external devices whether the action has been completed normally.

[0015] Address register 340 temporarily holds the address ADD received from the external device via input / output circuit 310. Additionally, address register 340 transmits the row address RA to row decoder 520 and the column address CA to column decoder 550.

[0016] Command register 350 temporarily stores the command CMD received from the external device via input / output circuit 310 and transmits it to sequencer 360.

[0017] The sequencer 360 controls the operation of the entire semiconductor device 1. More specifically, the sequencer 360 performs write operations, read operations, and erase operations according to the commands CMD held in the command register 350, such as the control status register 330, the ready / busy circuit 370, the voltage generation circuit 380, the row decoder 520, the sense amplifier module 530, the data register 540, and the column decoder 550.

[0018] The ready / busy circuit 370 sends a ready / busy signal R / Bn to an external device based on the operating status of the sequencer 360.

[0019] The voltage generation circuit 380, under the control of the sequencer 360, generates the voltages required for write, read, and erase operations, and supplies the generated voltages to components such as the memory cell array 510, the line decoder 520, and the sense amplifier module 530. The line decoder 520 and the sense amplifier module 530 apply the voltages supplied by the voltage generation circuit 380 to the memory cells within the memory cell array 510.

[0020] The memory cell array 510 contains multiple blocks BLK (BLK0 to BLKn). n is an integer greater than or equal to 2. A block BLK is a collection of multiple memory cells associated with bit lines and word lines, serving as an erasure unit for data, for example. The memory cells are configured, for example, as transistors, to hold non-volatile data.

[0021] By having such a storage unit, the semiconductor device 1 is configured, for example, as a NAND-type non-volatile memory.

[0022] The row decoder 520 decodes the row address RA. Additionally, based on the decoding result, the row decoder 520 selects a specific block BLK. Furthermore, the row decoder 520 applies the required voltage to the block BLK.

[0023] During a read operation, the sense amplifier module 530 senses the data read from the memory cell array 510. Additionally, the sense amplifier module 530 sends the read data RDT to the data register 540. During a write operation, the sense amplifier module 530 sends the write data WDT to the memory cell array 510.

[0024] Data register 540 includes multiple latching circuits. These latching circuits hold write data (WDT) and read data (RDT). For example, during a write operation, data register 540 temporarily holds the write data (WDT) received from input / output circuit 310 and sends it to sense amplifier module 530. Similarly, for example, during a read operation, data register 540 temporarily holds the read data (RDT) received from sense amplifier module 530 and sends it to input / output circuit 310.

[0025] The column decoder 550 decodes the column address CA during operations such as write, read, and erase, and selects the latch circuit in the data register 540 based on the decoding result.

[0026] Additionally, the circuitry surrounding the memory cell array 510 is referred to as peripheral circuitry. Peripheral circuitry includes at least a row decoder 520, a sense amplifier module 530, a data register 540, and a column decoder 550. Peripheral circuitry may include a status register 330, an address register 340, a command register 350, and a sequencer 360, and may also include input / output circuitry 310, logic control circuitry 320, a ready / busy circuitry 370, and voltage generation circuitry 380.

[0027] Thus, the semiconductor device 1 includes a memory cell array 510 containing multiple memory cells and peripheral circuitry for operating the multiple memory cells.

[0028] (Circuit configuration of a memory cell array) Figure 2 This is an equivalent circuit diagram showing an example of the configuration of the memory cell array 510 included in the semiconductor device 1 according to the embodiment.

[0029] The memory cell array 510, as described above, has multiple blocks BLK. Each block BLK has multiple string cells SU. Each string cell SU has multiple memory strings MS. One end of each memory string MS is connected to peripheral circuits such as the sense amplifier module 530 via bit lines BL. The other end of each memory string MS is connected to peripheral circuit PC via a common source line SL.

[0030] The memory string (MS) has a drain selection transistor (STD) connected in series between the bit line (BL) and the source line (SL), multiple memory cells (MC), and a source selection transistor (STS). Hereinafter, the drain selection transistor (STD) and the source selection transistor (STS) are sometimes simply referred to as selection transistors (STD, STS).

[0031] A memory cell MC is, for example, a field-effect transistor (FET) that contains a charge storage layer within its gate insulating layer. The threshold voltage of the memory cell MC varies depending on the amount of charge in the charge storage layer. By setting one or more threshold voltages, the memory cell MC can store one or more bits of data. Furthermore, word lines WL are connected to the gate electrodes of multiple memory cells MC corresponding to a memory string MS. These word lines WL are commonly connected to all memory strings MS within a block BLK.

[0032] The selection transistors (STD, STS) are, for example, field-effect transistors. Selection gate lines (SGD, SGS) are connected to the gate electrodes of the selection transistors (STD, STS). The drain selection line SGD, connected to the drain selection transistor STD, is configured corresponding to the string cell SU and is commonly connected to all memory strings MS in one string cell SU. The source selection line SGS, connected to the source selection transistor STS, is commonly connected to all memory strings MS in one block BLK.

[0033] One end of the word line WL and the select gate lines (SGD, SGS) are connected to the peripheral circuits such as the line decoder 520.

[0034] (Circuit configuration of the sensing amplifier module) Figure 3 This is a circuit diagram illustrating an example of the configuration of the sense amplifier circuit SA and latch circuits DL and XDL included in the semiconductor device 1 according to the embodiment.

[0035] The aforementioned sensing amplifier module 530 consists of multiple sensing amplifier circuits SA configured for each bit line BL. For example, during a read operation, each sensing amplifier circuit SA senses the data read from the corresponding bit line BL and determines whether the read data is "0" or "1".

[0036] Furthermore, the aforementioned data register 540 includes multiple latch circuits DL and XDL corresponding to multiple sense amplifier circuits SA. Each latch circuit XDL is also configured for each bit line BL. On the other hand, multiple latch circuits DL are configured for their corresponding sense amplifier circuits SA. In this case, the number of latch circuits DL is designed, for example, based on the number of bits of data that one memory cell MC can hold. The latch circuits DL and XDL temporarily hold the data associated with their corresponding bit lines BL.

[0037] Figure 3 The diagram shows a sense amplifier circuit SA within the sense amplifier module 530 and latch circuits DL and XDL within the data register 540. Additionally, multiple control signals supplied to the sense amplifier circuit SA, etc., are controlled by a sequencer 360.

[0038] like Figure 3 As shown, the sensing amplifier circuit SA includes transistor TR. 31 ~TR 38 And capacitor CAP. In the diagram, transistor TR... 31 It is a low-voltage P-channel MOS (Metal-Oxide-Semiconductor) transistor. Additionally, the transistor TR... 32 ~TR 38It is a low-voltage N-channel MOS transistor.

[0039] Low-voltage CMOS transistors, which include low-voltage P-channel MOS transistors and low-voltage N-channel MOS transistors, are transistors to which relatively low voltages are applied, and are also known as low-voltage (LV: Low Voltage, VLV: Very Low Voltage) MOS transistors.

[0040] transistor TR 31 One end of the transistor TR is connected to the power supply line supplied with the power supply voltage Vdd. 31 The gate electrode of transistor TR is connected to node INV. 32 One end is connected to transistor TR 31 The other end is connected to the transistor TR 32 The other end is connected to node COM, transistor TR 32 The gate electrode of the transistor is fed with the control signal BLX. 33 One end is connected to node COM, transistor TR 33 The other end is connected to the corresponding bit line BL, transistor TR 33 The gate electrode is input with the control signal BLC.

[0041] transistor TR 34 One end is connected to node COM, transistor TR 34 The other end is connected to node SRC, transistor TR 34 The gate electrode is connected to node INV.

[0042] transistor TR 35 One end is connected to transistor TR 31 The other end is connected to the transistor TR 35 The other end is connected to node SEN, transistor TR 35 The gate electrode of the transistor is fed with the control signal HLL. 36 One end is connected to node SEN, transistor TR 36 The other end is connected to node COM, transistor TR 36 The gate electrode is input with the control signal XXL.

[0043] transistor TR 37 One end is fed with the clock input CLK, transistor TR 37 The gate electrode of transistor TR is connected to node SEN. 38 One end is connected to transistor TR 37 The other end is connected to the transistor TR 38 The other end is connected to the LBUS bus, transistor TR 38The gate electrode is fed with the control signal STB. One end of capacitor CAP is connected to node SEN, and the other end of capacitor CAP is fed with the clock signal CLK.

[0044] The latch circuit DL includes inverters IVa and IVb, and transistor TR. 41 and TR 42 In the diagram, transistor TR 41 TR 42 It is a low-voltage N-channel MOS transistor. Hereinafter, the transistor TR included in data register 540 will sometimes be referred to as... 41 TR 42 It is abbreviated as transistor TR.

[0045] In addition, Figure 3 One latch circuit DL is shown, but other latch circuits DL have the same configuration.

[0046] The input terminal of inverter IVa is connected to node LAT, and the output terminal is connected to node INV. The input terminal of inverter IVb is connected to node INV, and the output terminal is connected to node LAT.

[0047] transistor TR 41 One end of the transistor is connected to node INV, and the other end is connected to the bus LBUS. The gate electrode is fed by the control signal STI. Transistor TR 42 One end is connected to node LAT, and the other end is connected to bus LBUS. The gate electrode is fed with control signal STL.

[0048] The latch circuit XDL has, for example, a configuration substantially the same as that of the latch circuit DL, and is connected to the LBUS bus in a manner capable of transmitting and receiving data with the sense amplifier circuit SA and the latch circuit DL. Furthermore, the latch circuit XDL is connected to the aforementioned input / output circuit 310 for inputting and outputting data between the sense amplifier circuit SA and the input / output circuit 310.

[0049] In addition, the latch circuit XDL can also be used for buffering operations of the semiconductor device 1. That is, even if all the latch circuits DL corresponding to the sense amplifier circuit SA are in use, the semiconductor device 1 can still receive data from the outside as long as the latch circuit XDL is idle.

[0050] Thus, the sensing amplifier circuit SA and the latch circuits DL and XDL, which belong to the peripheral circuits, have multiple transistors TR.

[0051] Next, the operation of the sensing amplifier circuit SA constructed above will be briefly explained.

[0052] As an example of writing data to the memory cell MC, when the threshold of the memory cell MC is raised due to the injection of charge, the "H" level ("1" data) is stored in node INV of the latch circuit DL. Thus, the transistor TR... 34 When the circuit is turned on, the bit line BL becomes 0V.

[0053] As another example of writing data to the memory cell MC, without injecting charge into the memory cell MC to avoid changing the threshold, the "L" level ("0" data) is stored in node INV of the latch circuit DL. Thus, the transistor TR... 31 When the circuit is turned on, a specified positive voltage is applied to the bit line BL.

[0054] During reading, node INV becomes "L" level, and transistor TR... 31 Turn-on. Additionally, via transistor TR... 41 TR 42 Bit line BL is controlled by transistor TR 31 Pre-charge. Additionally, transistor TR 35 It also conducts, and node SEN is charged to the specified potential.

[0055] Then, transistor TR 35 Cut off, signal XXL is set to "H" level, thus transistor TR 36 Turning on. Therefore, if the corresponding memory cell MC is turned on, the potential of node SEN decreases, and transistor TR... 37 Cut-off. On the other hand, if the corresponding memory cell MC is cut off, the potential of node SEN remains at the "H" level, and transistor TR... 37 Conduction.

[0056] Additionally, transistor TR 38 It is turned on according to the signal STB, and is related to the transistor TR. 37 The corresponding potential for the on / off state is read into the bus LBUS and held in the latch circuit DL.

[0057] in addition, Figure 3 The circuit configurations of the sense amplifier circuit SA and latch circuits DL and XDL shown are only one example. Various other configurations can be used for the sense amplifier circuit SA and latch circuits DL and XDL. Therefore, the number and type of transistors TR included in each of the sense amplifier circuit SA and latch circuits DL and XDL can also differ. For example, the sense amplifier circuit SA and latch circuits DL and XDL can also be configured to include high-voltage P-channel MOS transistors or high-voltage N-channel MOS transistors, etc.

[0058] (Circuit configuration of the line decoder) Figure 4This is a circuit diagram showing an example of the configuration of the line decoder 520 included in the semiconductor device 1 according to the embodiment.

[0059] like Figure 4 As shown, the row decoder 520 includes an address decoder 21, a block selection circuit 22, and a voltage selection circuit 23.

[0060] Address decoder 21 has multiple block select lines (BLKSEL) and multiple voltage select lines (VOLSEL).

[0061] The address decoder 21, for example, refers to the address data of the address register 340 included in the aforementioned peripheral circuitry, based on the control signal from the sequencer 360.

[0062] In addition, the address decoder 21 decodes the referenced address data, causing the transistor TR corresponding to the address data to... 22 and transistor TR 23 Turn on, and enable all other transistors TR 22 and transistor TR 23 Cut-off. Additionally, transistor TR 22 and transistor TR 23 These are transistors contained in the block selection circuit 22 and the voltage selection circuit 23, which will be described later.

[0063] Additionally, the address decoder 21 sets the voltages of the block select line BLKSEL and the voltage select line VOLSEL corresponding to the address data to, for example, an "H" state, and sets all other voltages to an "L" state. Furthermore, depending on whether an N-channel or P-channel transistor is used, the voltages applied to the wiring of the block select circuit 22 and the voltage select circuit 23 are opposite. The above voltages are an example when the transistor is an N-channel type.

[0064] exist Figure 4 In the example, in address decoder 21, one block select line BLKSEL is provided for each block BLK within the memory cell array 510. However, this configuration can be modified appropriately. For example, one block select line BLKSEL can be provided for every two or more blocks BLK.

[0065] The block selection circuit 22 includes multiple block selection units 220, each corresponding to a block BLK of the memory cell array 510. Each of these multiple block selection units 220 includes multiple transistors TR corresponding to a word line WL and a select gate line (SGD, SGS). 22 .

[0066] transistor TR 22 It is a high-voltage N-channel MOS transistor, functioning as a block drive transistor. Transistor TR22 The drain electrodes of each transistor are electrically connected to their corresponding word line WL or select gate line (SGD, SGS). Transistor TR 22 The source electrodes are each electrically connected to the voltage output terminal OTM via wiring WR and voltage selection circuit 23. Transistor TR 22 The gate electrodes are commonly connected to the corresponding block selection line BLKSEL.

[0067] Additionally, the block selection circuit 22 includes multiple transistors (not shown). These transistors are high-voltage CMOS transistors connected between the select gate lines (SGD, SGS) and the ground voltage supply terminal. These transistors enable the select gate lines (SGD, SGS) within the unselected block BLK in the memory cell array 510 to conduct to the ground voltage supply terminal. Furthermore, the multiple word lines WL within the unselected block BLK are in a floating state.

[0068] The voltage selection circuit 23 includes multiple voltage selection sections 230 corresponding to the word line WL and the select gate lines (SGD, SGS). Each of these multiple voltage selection sections 230 includes multiple transistors TR. 23 .

[0069] transistor TR 23 It is a high-voltage N-channel MOS transistor, functioning as a voltage-selective transistor. Transistor TR 23 The drain terminals are each electrically connected to their corresponding word line WL or select gate line (SGD, SGS) via wiring WR and block select circuit 22. The source terminals are each electrically connected to their corresponding voltage output terminal OTM. The gate terminals are each connected to their corresponding voltage select line VOLSEL.

[0070] The high-voltage CMOS transistors mentioned above, which include high-voltage P-channel MOS transistors and high-voltage N-channel MOS transistors, are transistors to which relatively high voltages are applied, and are also known as high-voltage (HV) MOS transistors.

[0071] Thus, the line decoder 520, which belongs to the peripheral circuitry, has multiple transistors TR. 22 TR 23 Wait. But... Figure 4 The circuit configuration of the line decoder 520 shown is just one example. The line decoder 520 contains transistors TR. 22 TR 23 The number and types of these can also vary.

[0072] [Physical Structure of Semiconductor Devices] Next, use Figure 5An example of the physical configuration of the semiconductor device 1 in the embodiment will be described.

[0073] Figure 5 This is a cross-sectional view showing an example of the configuration of the semiconductor device 1 according to the embodiment. However, in Figure 5 In the attached diagram, some of the shadow lines have been omitted for ease of viewing.

[0074] also, Figure 5 The X-direction and the X-direction shown are orthogonal to each other. Additionally, in Figure 5 In this context, the X direction is orthogonal to the extension directions of the gate electrodes GEv and GEh, which will be described later; that is, it is along the gate length of the gate electrodes GEv and GEh. The Y direction is along the gate width of the gate electrodes GEv and GEh.

[0075] like Figure 5 As shown, the semiconductor device 1 includes, in sequence above the semiconductor substrate SB, a peripheral circuit CBA, a laminate LM containing multiple word lines WL with pillars PL formed thereon, a source line SL, and an electrode layer EL. Furthermore, in the following description, the side where the semiconductor substrate SB is disposed will be referred to as the lower side of the semiconductor device 1.

[0076] The semiconductor substrate SB is, for example, a monolithic silicon substrate. Multiple semiconductor layers DB, each having an area smaller than the upper surface of the semiconductor substrate SB, are disposed on top of the semiconductor substrate SB. These semiconductor layers DB are, for example, polycrystalline silicon layers.

[0077] Between the semiconductor substrate SB and multiple semiconductor layers DB, a peripheral circuit CBA consisting of multiple stacked transistors TRv and TRh is disposed. Among these transistors TRv and TRh, transistor TRv is disposed on the semiconductor substrate SB, and transistor TRh is disposed on the surface of the semiconductor layer DB opposite to the semiconductor substrate SB.

[0078] That is, these transistors TRh are arranged above the transistors TRv on the semiconductor substrate SB, in an inverted position relative to the transistors TRv. However, these transistors TRh and TRv can be arranged as follows: Figure 5 It can be configured as shown in a position where it overlaps in the vertical direction, or it can be configured in a position where it does not overlap in the vertical direction, either partially or entirely.

[0079] An insulating layer 31 is disposed on a semiconductor substrate SB, covering a transistor TRv on the semiconductor substrate SB. An insulating layer 32 is disposed on a semiconductor layer DB, covering a transistor TRh on the semiconductor layer DB. By bonding the semiconductor substrate SB and the semiconductor layer DB through these insulating layers 31 and 32, multiple transistors TRv and TRh are stacked in multiple stages.

[0080] The transistor TRv on the semiconductor substrate SB has a source / drain region SDv, a gate insulating layer GXv, a gate electrode GEv, and a liner LLv.

[0081] The source / drain regions SDv are disposed separately on the semiconductor substrate SB and are regions diffused with impurities of a specified conductivity type. The gate electrode GEv is disposed on the semiconductor substrate SB, spanning the separated source / drain regions SDv, separated by a gate insulating layer GXv. The gate electrode GEv and the gate insulating layer GXv are entirely covered by a substrate LLv. The substrate LLv is a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or has a multilayer structure combining some of these layers.

[0082] These transistors TRv are configured, for example, as low-voltage (LV, VLV) MOS transistors to which a relatively low voltage is applied, and are included in, for example, a sense amplifier module 530 (see reference) in the peripheral circuit CBA. Figure 3 ), and input / output circuit 310, logic control circuit 320, and ready / busy circuit 370 (see reference). Figure 1 In circuits that serve as interfaces with external devices, such as those used for communication.

[0083] The transistors TRv used in these circuits, which serve as interfaces, require high-speed operation and are preferably configured with a relatively short gate length. Therefore, the gate electrode GEv of the transistor TRv is, for example, made of tungsten or a nickel-platinum silicide layer. These tungsten or nickel-platinum silicide layers, etc., require high-speed operation and are suitable gate electrode materials for low-voltage MOS transistors with relatively short gate lengths.

[0084] In addition, as mentioned above, in Figure 5 In the X direction, the distance between the gate electrodes GEv and GEh of each transistor TRv and TRh is equivalent to the gate length of the gate electrodes GEv and GEh in these transistors TRv and TRh, and the distance between the gate electrodes GEv and GEh in the Y direction is equivalent to the gate width of the gate electrodes GEv and GEh in these transistors TRv and TRh.

[0085] On the source / drain regions SDv and gate electrode GEv of these transistors TRv, contacts CSv and CGv extending in the insulating layer 31 covering the transistors TRv are respectively connected. On each contact CSv and CGv, starting from the transistor TRv side, wiring layer D0v, path C1v, wiring layer D1v... disposed in the insulating layer 31 are sequentially connected. Thus, some of the multiple transistors TRv are connected to transistors TRh disposed opposite to these transistors TRv, and some transistors TRv are connected to the electrode layer EL via contacts C3 extending vertically in the same layer as the stack LM.

[0086] The transistor TRh on the semiconductor layer DB has a source / drain region SDh, a gate insulating layer GXh, a gate electrode GEh, and a liner LLh.

[0087] The source / drain regions SDh are separated from each other in the semiconductor layer DB and are regions diffused with impurities of a specified conductivity type. The gate electrode GEh is disposed on the semiconductor layer DB across the separated source / drain regions SDh, separated by a gate insulating layer GXh. The gate electrode GEh and the gate insulating layer GXh are completely covered by a substrate LLh. The substrate LLh is a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or has a multilayer structure combining some of these layers.

[0088] These transistors TRh are configured, for example, as high-voltage (HV) MOS transistors to which a relatively high voltage is applied. However, some of these transistors TRh can also be configured as low-voltage (VLV) MOS transistors. These transistors TRh on the semiconductor layer DB are included in, for example, a line decoder 520 (see reference 520) in the peripheral circuit CBA. Figure 4 (etc.)

[0089] Furthermore, high-voltage transistors (TRh) do not require the high-speed operation of low-voltage MOS transistors. Therefore, for the gate electrode (GEh) of transistor TRh, compared to the tungsten layer or nickel-platinum silicide layer used in the gate electrode materials of low-voltage MOS transistors, easier-to-process gate electrode materials such as tungsten silicide or tungsten nitride can be used.

[0090] Furthermore, the transistor TRh to which a high voltage is applied is configured, for example, to have a higher withstand voltage than the transistor TRv used for low voltage as described above.

[0091] Specifically, the gate insulating layer GXh of these transistors TRh is, for example, thicker than the gate insulating layer GXv of the aforementioned transistor TRv. Furthermore, the gate electrode GEh of these transistors TRh has, for example, a longer gate length than the gate electrode GEv of the aforementioned transistor TRv.

[0092] Furthermore, in the semiconductor layer DB of a single-crystal semiconductor substrate SB and a polycrystalline silicon layer, a higher carrier mobility is obtained at the semiconductor substrate SB. Therefore, by placing the low-voltage transistor TRv, which is required to operate at high speed in some applications, on the semiconductor substrate SB, the operating performance of the transistor TRv can be improved.

[0093] On the source / drain region SDh and gate electrode GEh of transistor TRh, contacts CSh and CGh extending in the insulating layer 32 covering transistor TRh are connected. On each contact CSh and CGh, starting from the transistor TRh side, wiring layer D0h, path C1h, wiring layer D1h, etc., disposed in the insulating layer 32 are sequentially connected. Thus, some of the multiple transistors TRh are connected to transistors TRv disposed opposite to these transistors TRh, and some transistors TRh are connected to contacts CC (described later) that supply power to word line WL via contacts C4 extending towards the stack LM side.

[0094] In addition, the aforementioned peripheral circuit CBA may also include, in addition to transistors TRv and TRh, contacts CSv and CGv, wiring layer D0v, path C1v and wiring layer D1v... and contacts CSh, CGh, wiring layer D0h, path C1h, wiring layer D1h... that are respectively connected to these transistors TRv and TRh.

[0095] An insulating layer 40 is disposed above the peripheral circuit CBA, covering the upper surface of an insulating layer 32 containing multiple semiconductor layers DB. The insulating layer 40 has an area at least larger than the semiconductor layers DB and covers the entire semiconductor substrate SB on which the peripheral circuit CBA is disposed.

[0096] Furthermore, the insulating layer 40, such as an NSG (Nondoped Silicate Glass) layer or a silicon oxide layer, preferably has a lower carbon concentration than other portions of the insulating layer 40, at least from the side in contact with the semiconductor layer DB to a predetermined thickness. The carbon concentration of the insulating layer 40 at the low carbon concentration portion is preferably, for example, 1 × 10⁻⁶. 18 pcs / cm 3 However, the insulating layer 40 can also have a low overall carbon concentration. This allows for the suppression of leakage current from the semiconductor layer DB on which the transistor TRh is located.

[0097] Above the peripheral circuit CBA, a stacked structure LM consisting of multiple word lines WL stacked separately is disposed across an insulating layer 40. More than one select gate line SGS (see reference) can be stacked on the lower layer side of the multiple word lines WL, that is, on the peripheral circuit CBA side. Figure 2 Additionally, one or more select gate lines (SGDs) can be stacked on the upper side of multiple word lines (WL), that is, on the side opposite to the peripheral circuitry (CBA) (see reference). Figure 2 The stacked body LM, which includes multiple word lines such as WL, is covered by an insulating layer 50 and is connected to the peripheral circuit CBA through the insulating layer 50 and the aforementioned insulating layer 40.

[0098] An insulating layer 50 also extends around the stacked body LM. Contacts C3 extending along the stacking direction of the plurality of word lines WL are disposed within the surrounding insulating layer 50. Contacts C3 are electrically connected to a portion of the aforementioned transistor TRv disposed on the semiconductor substrate SB. Thus, the peripheral circuit CBA is electrically connected to the source line SL.

[0099] A storage region MR is disposed in the central part of the stacked body LM in the X direction, and stepped regions SR are disposed at both ends of the stacked body LM in the X direction.

[0100] In the storage region MR, multiple pillars PL are configured to run through word lines WL along the stack-up direction. Multiple storage cells MC are formed at the intersections of the pillars PL and word lines WL (see reference). Figure 2 Select gate lines STD and STS are formed at the intersection of pillar PL and select gate lines SGD and SGS, respectively (see reference). Figure 2 Thus, the semiconductor device 1 is configured, for example, as a three-dimensional non-volatile memory in which memory cells MC are arranged in three dimensions in the memory region MR.

[0101] Thus, the storage region MR is related to the aforementioned storage cell array 510 (refer to...). Figure 2 This is an example of a physical configuration similar to that of a memory cell (MC). Furthermore, the column PL is the aforementioned memory string MS connected in series with the memory cell (MC), etc. (see [reference]). Figure 2 This is an example of a fairly similar physical composition.

[0102] In the physical configuration of the semiconductor device 1, the pillar PL is electrically connected to the sense amplifier module 530 of the peripheral circuit CBA via the bit line BL and the like arranged below the pillar PL.

[0103] Within the stepped region SR, a stepped section SP is provided, in which the ends of multiple word lines WL, etc., are machined into a stepped shape. Consequently, the width of the ends of the multiple word lines WL, etc., widens as they ascend towards the source line SL. Contacts CC are connected to each layer of the multiple word lines WL, etc., within the stepped section SP.

[0104] Through these contacts CC, multiple stacked word lines WL are led out separately. That is, for the memory cell MC contained in the memory region MR in the central part of the extension direction of multiple word lines WL, write voltage and read voltage are applied from these contacts CC via the word lines WL at the same height position as the memory cell MC.

[0105] The various voltages applied from the contacts CC to the memory cells MC are controlled by the line decoder 520 of the peripheral circuit CBA, which is electrically connected to these contacts CC.

[0106] A source line SL is disposed above a laminate LM containing multiple word lines WL, etc. An electrode layer EL is disposed on the source line SL, separated by an insulating layer 60 such as a silicon oxide layer. Multiple plugs PG are disposed in the insulating layer 60, which electrically connect the electrode layer EL to the source line SL. In addition, the electrode layer EL has a pad region PD that penetrates the insulating layer 60 and the source line SL in a portion of the area and is electrically connected to the contact C3.

[0107] With this configuration, a source potential can be applied to the source line SL from outside the semiconductor device 1 via the electrode layer EL.

[0108] Furthermore, some of the aforementioned transistors TRv are connected to contact C3, which is at the same level as the stacked body LM, via contact CSv, wiring layer D0v, path C1v, and wiring layer D1v... Additionally, some of the aforementioned transistors TRh are connected to contact C4, which reaches contact CC, in the stacked body LM, via contact CSh, wiring layer D0h, path C1h, wiring layer D1h...

[0109] At this point, these contacts CSv, wiring layer D0v, path C1v, wiring layer D1v... and contact C3, as well as contact CSh, wiring layer D0h, path C1h, wiring layer D1h... and contact C4 extend within insulating layers 31, 32, and 40. This maintains insulation from surrounding components and suppresses the generation of parasitic capacitances, etc.

[0110] [Semiconductor Device Manufacturing Method] Next, use Figures 6 to 13 The manufacturing method of the semiconductor device 1 according to the embodiment will be described. Figures 6 to 13 This is a cross-sectional view illustrating a portion of the steps in the manufacturing method of the semiconductor device 1 according to the embodiments.

[0111] like Figure 6 As shown in (a), an insulating layer 40 and a semiconductor layer DBb are sequentially formed on a support substrate HN. The support substrate HN is, for example, a semiconductor substrate such as a silicon substrate, the insulating layer 40 is a silicon oxide layer, and the semiconductor layer DBb is a polysilicon layer, etc. However, the semiconductor substrate HN can also be an insulating substrate such as a ceramic substrate or a conductive substrate. Furthermore, the semiconductor layer DBb is the layer that is subsequently patterned to form the semiconductor layer DB of the transistor TRh.

[0112] Furthermore, the insulating layer 40 is preferably formed using a method such as thermal chemical vapor deposition (TCVD) to create a high-quality NSG layer or similar silicon oxide layer with a low carbon concentration. By using thermal CVD or similar methods, a carbon concentration of, for example, 1 × 10⁻⁶ can be formed.18 pcs / cm 3 The following are high-quality NSG layers, etc.

[0113] like Figure 6 As shown in (b), an insulating layer GXb and a conductive layer GEb are sequentially formed on the semiconductor layer DBb. The insulating layer GXb is, for example, a silicon oxide layer, or a high-k (high-dielectric) insulating layer such as a hafnium oxide layer or a zirconium oxide layer, and is the layer of the gate insulating layer GXh that is subsequently patterned to become the transistor TRh. The conductive layer GEb is, for example, a tungsten silicide layer or a tungsten nitride layer, and is the layer of the gate electrode GEh that is subsequently patterned to become the transistor TRh.

[0114] like Figure 6 As shown in (c), the insulating layer GXb and the conductive layer GEb are patterned to form the gate insulating layer GXh and the gate electrode GEh, respectively.

[0115] In addition, using the gate insulating layer GXh and the gate electrode GEh as masks, impurities of a specified conductivity type are injected into the semiconductor layer DBb, and source / drain regions SDh are formed at the lower ends of both sides of the gate insulating layer GXh and the gate electrode GEh in the X direction.

[0116] Additionally, an insulating layer LLb is formed on the semiconductor layer DBb, covering the gate insulating layer GXh and the gate electrode GEh. The insulating layer LLb is a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer, or has a multilayer structure that combines some of these layers, and is the layer of the substrate LLh that is subsequently patterned to become the transistor TRh.

[0117] like Figure 7 As shown in (a), the insulating layer LLb is patterned to form a substrate LLh covering the gate insulating layer GXh and the gate electrode GEh. Additionally, the semiconductor layer DBb is patterned to form semiconductor layers DB, each containing a transistor TRh.

[0118] like Figure 7 As shown in (b), while an insulating layer 32 covering the semiconductor layer DB and the transistor TRh is appropriately formed on the insulating layer 40 of the support substrate HN, contacts CSh, CGh, wiring layer D0h, path C1h, wiring layer D1h, path C2h, and wiring layer D2h are sequentially formed in the insulating layer 32. At this time, wiring layers that intermediately connect the transistor TRv on the semiconductor substrate SB and the contacts C3 formed at the same level as the laminate LM may also be formed in the insulating layer 32.

[0119] like Figure 8As shown, the semiconductor substrate SB on which transistor TRv is formed and the support substrate HN on which transistor TRh is formed are arranged such that transistors TRv and TRh face each other, and the semiconductor substrate SB is bonded to the support substrate HN. Furthermore, the transistor TRv on the semiconductor substrate SB can be formed using the same method as the transistor TRh on the semiconductor layer DB.

[0120] That is, a gate insulating layer GXv and a gate electrode GEv are sequentially formed on a semiconductor substrate SB. The gate insulating layer GXv and the gate electrode GEv are used as a mask to form a source / drain region SDv on the semiconductor substrate SB. A liner LLv is formed covering the gate insulating layer GXv and the gate electrode GEv, thereby forming a transistor TRv.

[0121] In addition, while appropriately forming an insulating layer 31 covering the transistor TRv, contacts CSv, CGv, wiring layer D0v, path C1v, wiring layer D1v, path C2v and wiring layer D2v are sequentially formed in the insulating layer 31.

[0122] like Figure 9 As shown, when the semiconductor substrate SB is bonded to the support substrate HN, insulating layers 31 and 32 formed on the semiconductor substrate SB and the support substrate HN, respectively, are bonded to each other. These insulating layers 31 and 32 can be bonded, for example, by pre-activating their surfaces using plasma treatment or the like.

[0123] In addition, when bonding insulating layers 31 and 32, the semiconductor substrate SB and the support substrate HN are aligned so that the wiring layers D2v and D2h, which are connected to transistors TRv and TRh and respectively led out to the surfaces of insulating layers 31 and 32, overlap each other in the vertical direction.

[0124] After bonding insulating layers 31 and 32, an annealing process is performed, and wiring layers D2v and D2h are bonded by, for example, Cu-Cu bonding. Thus, the support substrate HN and the semiconductor substrate SB are bonded together. The bonded assembly of the support substrate HN and the semiconductor substrate SB is also called a bonded substrate.

[0125] like Figure 10 As shown in (a), the support substrate HN is removed from the bonding substrate of the support substrate HN and the semiconductor substrate SB, exposing the insulating layer 40. After the support substrate HN is removed, the semiconductor substrate SB also functions as a support substrate for the overall structure of supporting transistors TRv, TRh, etc.

[0126] like Figure 10As shown in (b), a contact C3c is formed from the side of the insulating layer 40 exposed after removing the support substrate HN, penetrating the insulating layers 40 and 32 and further reaching the wiring layer D2v that extends in the insulating layer 31 and is electrically connected to the transistor TRv. Additionally, a contact C4 is formed from the side of the insulating layer 40, penetrating the insulating layer 40 and further reaching the wiring layer D1h that extends in the insulating layer 32 and is electrically connected to the transistor TRh. Electrode pads or the like may also be provided at the upper ends of each contact C3c and C4.

[0127] like Figure 11 As shown, a support substrate SS having a multilayer stack LM having pillars PL and contacts CC, and a semiconductor substrate SB having transistors TRv and TRh stacked in multiple layers, are arranged such that the multilayer stack LM faces the transistors TRv and TRh, and these support substrates SS and semiconductor substrates SB are bonded together. Here, the multilayer stack LM having pillars PL and contacts CC can be formed as follows.

[0128] That is, a support substrate SS, such as a semiconductor substrate (e.g., a silicon substrate), an insulating substrate (e.g., a ceramic substrate), or a conductive substrate (e.g., a conductive substrate), is prepared. Furthermore, an insulating layer 60 and a source line SL are sequentially formed on the support substrate SS. Further, multiple sacrificial layers (not shown) are stacked separately on the source line SL. These sacrificial layers are silicon nitride layers, etc., which are subsequently replaced by conductive layers such as tungsten layers to become word lines WL.

[0129] Multiple sacrificial layers are machined into stepped sections SP at both ends in the X direction, and the entire structure is covered by an insulating layer 50. Multiple pillars PL are formed, penetrating the multiple sacrificial layers and reaching the source line SL. Bit lines BL are formed on the insulating layer 50 above the pillars PL and connected to the pillars PL. The multiple sacrificial layers are replaced with conductive layers such as tungsten layers to form a laminate LM having multiple word lines WL, etc. Contacts CC are formed on the stepped sections SP of the laminate LM, penetrating the insulating layer 50 covering the laminate LM and connecting to each word line WL, etc. Contacts C3 are formed on the outer side of the laminate LM in the X direction, penetrating the insulating layer 50 and reaching the source line SL.

[0130] like Figure 12 As shown, the semiconductor substrate SB and the support substrate SS can be bonded using the same method as the bonding of the semiconductor substrate SB and the support substrate HN described above.

[0131] That is, insulating layers 40 and 50 formed on semiconductor substrate SB and support substrate SS respectively are bonded to each other. These insulating layers 40 and 50 can be bonded, for example, by pre-activating their surfaces using plasma treatment or the like.

[0132] In addition, when bonding insulating layers 40 and 50, the semiconductor substrate SB and the support substrate SS are aligned in a vertical direction such that the contacts C3c and C4, which are connected to transistors TRv and TRh and respectively led out to the surface of insulating layer 40, coincide with the contacts C3 and CC formed on the side of the laminate LM.

[0133] After bonding insulating layers 40 and 50, an annealing process is performed, and contacts C3c, C3 and contacts C4, CC are bonded by, for example, Cu-Cu bonding. Thus, the support substrate SS and the semiconductor substrate SB are bonded together.

[0134] like Figure 13 As shown in (a), the support substrate SS is removed, exposing the insulating layer 60. Furthermore, thereafter, in Figure 13 The diagram omitting the structure of the layer below the insulating layer 40 is omitted.

[0135] like Figure 13 As shown in (b), a plurality of plugs PG are formed that penetrate the exposed insulating layer 60 to reach the source line SL. In addition, a portion of the insulating layer 60 and the source line SL is removed to form a recess RS, so that the contact C3 is exposed from the bottom surface of the recess RS.

[0136] like Figure 13 As shown in (c), a conductive layer covering the insulating layer 60 is formed and patterned to form an electrode layer EL. The electrode layer EL is also formed within the aforementioned recess RS, thereby forming a pad region PD that connects to the contact C3.

[0137] Through the above processing, the semiconductor device 1 of the embodiment is manufactured.

[0138] [Summary] Semiconductor devices such as three-dimensional non-volatile memories include peripheral circuits that control the electrical operation of memory cells. These peripheral circuits contain multiple transistors formed on a semiconductor substrate. As the storage capacity of semiconductor devices increases and miniaturization becomes more demanding, the number of transistors in the peripheral circuits increases. Therefore, attempts are made to form transistors on multiple semiconductor substrates separately and then bond these substrates together, thereby constructing a multilayered peripheral circuit with multiple transistors.

[0139] However, when electrically connecting a transistor formed on a semiconductor substrate on the lower layer side, i.e., the side away from the stacked body with pillars, to an electrode layer above the stacked body, it is necessary to form a contact that penetrates the upper semiconductor substrate. In this case, parasitic capacitance is generated between the contact and the semiconductor substrate, which may lead to a decrease in the quality of signal transmission between the contact and the transistor, as well as a decrease in transmission speed.

[0140] Furthermore, when multiple semiconductor substrates on which transistors are formed are bonded together, it is preferable to bond the semiconductor substrates so that the transistors of the upper and lower layers face each other in order to electrically connect the multilayered transistors to each other. In this case, when electrically connecting the transistors formed on the upper semiconductor substrate to the structure on the laminate side, it is also necessary to form contacts that penetrate the upper semiconductor substrate, which may also lead to a decrease in signal transmission quality and a decrease in transmission speed.

[0141] According to the embodiment, the semiconductor device 1 includes a transistor TRv disposed on a semiconductor substrate SB and a transistor TRh disposed on the side of the semiconductor layer DB opposite to the semiconductor substrate SB. Thus, multiple layers of transistors TRv and TRh can be stacked to form a peripheral circuit CBA having a number of transistors TRv and TRh corresponding to the increased storage capacity and miniaturization of the semiconductor device 1.

[0142] According to the embodiment, the semiconductor device 1 includes: a semiconductor layer DB disposed above a semiconductor substrate SB and having an area smaller than that of the semiconductor substrate SB; and a contact C3c extending upward from a transistor TRv through an insulating layer 40 at a position that does not overlap with the semiconductor layer DB in the vertical direction.

[0143] In this way, since the upper-side transistor TRh is formed on a small-area semiconductor layer DB, the transistor TRv formed on the lower-side semiconductor substrate SB of the semiconductor layer DB can be connected to the stacked body LM side via contacts C3c, etc., without making the upper-side semiconductor substrate, etc., penetrate through. Therefore, it is possible to stack multiple transistors TRv and TRh while suppressing the increase of parasitic capacitance.

[0144] According to the semiconductor device 1 of the embodiment, the insulating layer 40 has a carbon concentration of 1×10⁻⁶ at least on the side in contact with the semiconductor layer DB. 18 pcs / cm 3 Therefore, leakage current from the semiconductor layer DB, where the transistor TRh is located, can be suppressed.

[0145] According to the semiconductor device 1 of the embodiment, transistor TRv is a low-voltage MOS transistor, and transistor TRh is a high-voltage MOS transistor. By placing the low-voltage transistor TRv, which is required to operate at high speed in some applications, on a semiconductor substrate SB with a higher carrier mobility, the operating performance of transistor TRv can be improved.

[0146] In addition, in the above embodiment, an insulating layer 40 and a semiconductor layer DBb are sequentially formed on the support substrate HN to form a transistor TRh. However, an SOI (Silicon on Insulator) substrate can also be used to form the transistor TRh. An SOI substrate is a substrate on which a single-crystal silicon layer is formed on a silicon substrate or the like, which is called a processing substrate, with a silicon oxide layer separated by a silicon oxide layer called a BOX (Buried Oxide) layer.

[0147] When using an SOI substrate, a transistor TRh can be formed on a single-crystal silicon layer. In this case, the processing substrate, BOX layer, and single-crystal silicon layer of the SOI substrate correspond to the aforementioned support substrate HN, insulating layer 40, and semiconductor layer DBb, respectively.

[0148] [Variation Example] Next, use Figure 14 The semiconductor device 2 of the modified embodiment will now be described. The semiconductor device 2 of the modified embodiment differs from the one described above in the orientation of transistors TRv and TRh relative to each other.

[0149] Figure 14 This is a cross-sectional view showing a configuration example of the semiconductor device 2 according to a modified embodiment. However, in Figure 14 In the accompanying diagram, some of the shadow lines have been omitted for ease of viewing. Additionally, in... Figure 14 In this document, the same reference numerals are used to indicate the same components as in the embodiments described above, and their descriptions are sometimes omitted.

[0150] like Figure 14 As shown, the modified semiconductor device 2 also includes a peripheral circuit CBAa comprising multiple stacked transistors TRv and TRh. However, an insulating layer 40 is present between transistors TRv and TRh, and transistors TRv and TRh are not opposite each other in the vertical direction.

[0151] That is, the bonding surface between the semiconductor substrate SB on which the transistor TRv is formed and the semiconductor layer DB on which the transistor TRh is formed is the interface between the insulating layer 31 covering the semiconductor substrate SB and the insulating layer 40 disposed on the lower surface of the semiconductor layer DB.

[0152] Furthermore, since these transistors TRv and TRh are oriented vertically in the same direction, when the transistors TRv and TRh are electrically connected to each other, contacts or the like can be provided that penetrate the insulating layer 40. In this case, since there is no semiconductor substrate or the like between these transistors TRv and TRh, the generation of parasitic capacitance can also be suppressed.

[0153] The modified semiconductor device 2 can be obtained, for example, by the following manufacturing method.

[0154] That is, the support substrate HN, on which an insulating layer 40 and a semiconductor layer DB are sequentially formed and a transistor TRh is further formed on the semiconductor layer DB, and the support substrate SS, on which a laminate including pillars PL and contacts CC are formed, are bonded together by joining the insulating layer 32 covering the transistor TRh with the insulating layer 50 covering the laminate LM.

[0155] Additionally, the support substrate HN, which is attached to the support substrate SS, is removed to expose the insulating layer 40. Furthermore, the semiconductor substrate SB, on which the transistor TRv is formed, and the support substrate SS, which has a laminate LM and a transistor TRh, are bonded together by joining the insulating layer 31 covering the transistor TRv to the insulating layer 40 on the support substrate HN side.

[0156] Subsequently, by carrying out the above-described implementation methods... Figure 13 The process shown is used to manufacture a modified semiconductor device 2.

[0157] Thus, by stacking multiple transistors TRv and TRh in multiple stages in such a way that the vertical orientation is the same, these transistors TRv and TRh can also be stacked in more than 3 stages.

[0158] In addition to the above-described embodiments, the semiconductor device 2 according to the modified example also achieves the same effects.

[0159] While several embodiments of the invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope equivalent to the invention as described in the claims. [Explanation of reference numerals in the attached figures]

[0160] 1, 2: Semiconductor devices; 31, 32, 40, 50, 60: Insulating layers; C1h, C1v, C2h, C2v: Paths; C3, C4, CC, CGh, CGv, CSH, CSv: Contacts; CBA, CBAa: Peripheral circuits; D0h~D2h, D0v~D2v: Wiring layers; DB: Semiconductor layer; HN, SS: Support substrate; MC: Memory cell; PL: Pillar; SB: Semiconductor substrate; WL: Word line.

Claims

1. A semiconductor device comprising: Semiconductor substrate; A first transistor is disposed on the semiconductor substrate; A semiconductor layer disposed above the semiconductor substrate, having an area smaller than that of the semiconductor substrate; A second transistor is disposed on the side of the semiconductor layer opposite to the semiconductor substrate; An insulating layer disposed on the semiconductor layer has an area larger than that of the semiconductor layer; as well as The contact extends upward from the first transistor through the insulating layer at a position that does not overlap with the semiconductor layer in the vertical direction.

2. The semiconductor device according to claim 1, wherein, The insulating layer has a carbon concentration of 1 × 10⁻⁶ at least on the side in contact with the semiconductor layer. 18 pcs / cm 3 the following.

3. The semiconductor device according to claim 1, wherein, The first transistor has: First gate electrode; and First gate insulating layer, The second transistor has: A second gate electrode having a gate length longer than the first gate electrode; and The second gate insulating layer is thicker than the first gate insulating layer.

4. The semiconductor device according to claim 1, wherein, The first transistor is a low-voltage MOS transistor. The second transistor is a high-voltage MOS transistor.

5. The semiconductor device according to claim 1, wherein, It also has: A laminate disposed above the insulating layer, wherein a plurality of conductive layers are stacked separately from each other; and A column that extends within the laminate along the lamination direction of the laminate.

6. A semiconductor device comprising: Semiconductor substrate; A first transistor is disposed on the semiconductor substrate; An insulating layer is disposed on the semiconductor substrate and covers the first transistor; A semiconductor layer disposed in the insulating layer opposite to the semiconductor substrate, having an area smaller than that of the semiconductor substrate; A second transistor is disposed on the side of the semiconductor layer opposite to the semiconductor substrate; as well as The contact extends upward from the first transistor through the insulating layer at a position that does not overlap with the semiconductor layer in the vertical direction. The insulating layer has a first portion, the first portion including a surface in contact with the upper surface of the semiconductor layer and having a predetermined layer thickness. The first portion has a lower carbon concentration than the other portions of the insulating layer.

7. The semiconductor device according to claim 6, wherein, The carbon concentration in the first part is 1×10 18 pcs / cm 3 the following.

8. The semiconductor device according to claim 6, wherein, The first transistor has: First gate electrode; and First gate insulating layer, The second transistor has: A second gate electrode having a gate length longer than the first gate electrode; and The second gate insulating layer is thicker than the first gate insulating layer.

9. The semiconductor device according to claim 6, wherein, The first transistor is a low-voltage MOS transistor. The second transistor is a high-voltage MOS transistor.

10. The semiconductor device according to claim 6, wherein, It also has: A laminate disposed above the insulating layer, wherein a plurality of conductive layers are stacked separately from each other; and A column that extends within the laminate along the lamination direction of the laminate.

11. A method for manufacturing a semiconductor device, wherein, A first transistor is formed on a first semiconductor substrate. A first insulating layer covering the first transistor is formed on the first semiconductor substrate. A second semiconductor substrate with a semiconductor layer formed through a second insulating layer is prepared. A second transistor is formed on the semiconductor layer of the second semiconductor substrate, and the semiconductor layer is patterned to have an area smaller than that of the first semiconductor substrate. A third insulating layer is formed on the second semiconductor substrate, covering the second transistor and the patterned semiconductor layer. The first semiconductor substrate and the second semiconductor substrate are bonded together at the first insulating layer and the third insulating layer to form a bonding substrate. Remove the second semiconductor substrate from the bonding substrate. At a location that does not overlap with the semiconductor layer in the vertical direction, a contact is formed that extends from the first transistor through the first insulating layer to the third insulating layer and upwards.

12. The method of manufacturing a semiconductor device according to claim 11, wherein, The second insulating layer has a carbon concentration of 1 × 10⁻⁶ at least on the side in contact with the semiconductor layer. 18 pcs / cm 3 the following.

13. The method of manufacturing a semiconductor device according to claim 11, wherein, The formation of the first transistor includes the following processes: Forming the first gate insulating layer; as well as Form the first gate electrode. The formation of the second transistor includes the following processes: A second gate insulating layer thicker than the first gate insulating layer is formed; and A second gate electrode is formed having a gate length longer than the first gate electrode.

14. The method of manufacturing a semiconductor device according to claim 11, wherein, Also includes: Above the support substrate, a laminate of multiple conductive layers is formed, which are stacked separately from each other; A column formed within the laminate extending along the lamination direction of the laminate; and The second insulating layer side of the first semiconductor substrate having the first transistor and the second transistor is attached to the laminate side of the support substrate having the laminate and the pillar, and the support substrate is removed.

15. The method of manufacturing a semiconductor device according to claim 11, wherein, The second semiconductor substrate, on which the semiconductor layer is formed through the second insulating layer, is an SOI substrate.

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