Parallel gradient calculation chip based on synaptic transistor and packaging method

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a synaptic transistor-based parallel gradient calculation chip and a packaging method.The synaptic transistor-based parallel gradient calculation chip comprises a lower floating gate transistor, a middle rewiring layer, an upper transistor and an oxide layer used for filling a gap, the floating gate transistor comprises a P-type MOS transistor and an N-type MOS transistor, and the P-type MOS transistor comprises a P-type metal oxide semiconductor (MOS) transistor and a P-type metal oxide semiconductor (MOS) transistor; the transistor sequentially comprises an aluminum gate layer, an aluminum oxide medium, an electron transport layer and a light absorption layer from top to bottom, and the right side of the rewiring layer is located below the drain region of the transistor and sequentially comprises a right channel II, a right metal II, a right channel I, a right metal I and a right channel layer from top to bottom. According to the invention, the vertical stacking structure of the floating gate transistor and the optical sensing transistor is constructed, and the middle rewiring layer is utilized to realize efficient ohmic connection and heat dissipation, so that optical sensing, charge injection and nonvolatile storage functions are successfully integrated into a single unit.

Description

Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and in particular to a parallel gradient calculation chip based on synaptic transistors and its packaging method. Background Technology

[0002] In the current field of neuromorphic computing hardware, floating-gate transistors, ferroelectric transistors, and memristors are often used as core devices for realizing artificial synapses, simulating the gradient descent process by adjusting the conductivity value.

[0003] However, existing typical solutions, such as the "floating substrate dual MOS transistor" structure, heavily rely on channel charge modulation for conductance control, and generally suffer from inherent limitations such as a narrow conductance window (typically less than 2 times), high nonlinearity (over 50%), and short weight retention time (only about 1 millisecond). These defects make it difficult to cover coefficient changes over a wide dynamic range when processing high-order polynomial gradient calculations, and require complex off-chip calibration circuitry to compensate for nonlinearity, significantly increasing system latency and power consumption.

[0004] Furthermore, emerging devices such as ferroelectrics or memristors often require high-temperature annealing (above 400°C) in the back-end process, which is incompatible with the back-end metal interconnect layer of the standard 180nm CMOS process, thus restricting their integration and application on existing production lines. Summary of the Invention

[0005] This invention provides a parallel gradient calculation chip and packaging method based on synaptic transistors to solve existing technical problems, thereby solving the problems of narrow conductance window and high nonlinearity of dual MOS transistors on floating substrates.

[0006] To address the aforementioned technical problems, according to one aspect of the present invention, more specifically, a parallel gradient computing chip based on synaptic transistors, comprising a lower floating-gate transistor (serving as a data storage transistor), a middle redistribution layer (the redistribution layer is used to increase the heat dissipation of the device and avoid heat accumulation when the two types of devices are stacked), and an upper... The transistor (as an optical sensing transistor) and the oxide layer for filling the gap, the floating gate transistor including a P-type MOS transistor and an N-type MOS transistor, the The transistor consists of, from top to bottom, an aluminum gate layer, an aluminum oxide dielectric layer, an electron transport layer, and a light absorption layer;

[0007] The redistribution layer is to the right of and located at Below the drain region of the transistor, from top to bottom, are sequentially right channel two, right metal two, right channel one, right metal one, and right channel layer, located to the left of the redistribution layer and situated at... The transistor includes, from top to bottom, a left channel 2 and a left metal 2 below the source region; wherein, the right metal 2 is ohmically connected to the drain region of the light absorption layer through the right channel 2, and the left metal 2 is ohmically connected to the source region of the light absorption layer through the left channel 2.

[0008] The floating gate transistor includes a substrate layer, a well layer, a source region, a drain region, a MOS gate, a floating gate layer, and a silicon oxide layer; wherein, the source region is ohmically connected to right metal one through a right channel layer, and right metal one and right metal two are ohmically connected through right channel one.

[0009] Furthermore, the left metal element is used to connect to the external source voltage, the MOS gate is used to connect to the external gate voltage, the substrate layer is used to connect to the external substrate voltage, and the drain region serves as the output voltage. The output voltage outputs a high or low level to store information.

[0010] Furthermore, silicon oxide layers are deposited on both the upper and lower sides of the floating gate layer, the well layer is located above the substrate layer, and the drain region and source region are located on the left and right sides above the well layer, respectively.

[0011] Furthermore, the well layer in the P-type MOS transistor is made of N-type semiconductor material, and both the source and drain regions are made of P-type semiconductor material;

[0012] The well layer of the N-type MOS transistor is made of P-type semiconductor material, and the source and drain regions are both made of N-type semiconductor material.

[0013] Furthermore, a doped layer is formed inside the well layer and below the source and drain regions by ion implantation;

[0014] In the P-type MOS transistor, the doped layer is made of N-type semiconductor material, and in the N-type MOS transistor, the doped layer is made of P-type semiconductor material.

[0015] Furthermore, the interior of the doped layer is formed with several non-contacting doped particles through ion implantation;

[0016] In the P-type MOS transistor, the doped particles are made of P-type semiconductor material, and in the N-type MOS transistor, the doped particles are made of N-type semiconductor material.

[0017] Furthermore, the doped particles also include contact particles, the bottom end of which is in direct contact with the well layer.

[0018] Furthermore, the doped particles also include through particles, the bottom end of which extends below the well layer and directly contacts the substrate layer.

[0019] Furthermore, an intermediate layer is formed below the doped layer by ion implantation;

[0020] In the P-type MOS transistor, the middle layer is made of N-type semiconductor material, and in the N-type MOS transistor, the middle layer is made of P-type semiconductor material.

[0021] The packaging method for a parallel gradient calculation chip based on synaptic transistors includes the following steps:

[0022] S1. Using 2.5D silicon interposer or 3D TSV technology, the... The parallel gradient calculation chip of transistors is heterogeneously integrated with the CMOS control chip;

[0023] S2. High-density interconnection between the synaptic transistor-based parallel gradient calculation chip and the floating gate transistor is achieved through microbumps and a redistribution layer;

[0024] S3. Using system-in-package technology, the ADC, DAC and power management circuits are integrated on the same package substrate to form an integrated sensing-memory-computing module.

[0025] The parallel gradient calculation chip and packaging method based on synaptic transistors provided by this invention have the following advantages compared with the prior art:

[0026] 1. This invention successfully integrates optical sensing, charge injection, and non-volatile storage functions into a single unit by constructing a vertically stacked structure of floating-gate transistors and optical sensing transistors, and utilizing an intermediate redistribution layer to achieve efficient ohmic connections and heat dissipation. This structure not only achieves high-density integrated sensing and computing, providing a physical basis for parallel gradient calculation, but its unique redistribution layer also effectively dissipates the heat generated by the stacked devices, significantly improving the chip's reliability and operational lifespan, and overcoming the limitations of traditional two-dimensional layouts in terms of integration density and thermal management.

[0027] 2. This invention achieves precise control over the carrier transport path beneath the channel by introducing a specifically distributed doped layer and doped particles into the well layer. This design results in a highly linear relationship between the device's conductivity and the control signal, while significantly expanding the dynamically adjustable range of the conductivity. Its core advantage lies in achieving accurate weight expression without complex off-chip calibration circuitry, greatly improving the accuracy and adaptability of parallel gradient calculations, and effectively addressing the stringent requirements of high-order polynomial calculations on the dynamic range of weights.

[0028] 3. The doped particle variants used in this invention, including contact particles and through particles, optimize the potential distribution and carrier behavior within the device by establishing a direct electrical path from the active region to the well layer or substrate. This design enhances local field-effect modulation capability and heat dissipation efficiency, effectively suppressing performance drift caused by heat accumulation. Its benefits lie in significantly improving the consistency, stability, and anti-interference capability of the performance of individual devices in large-scale synaptic arrays, ensuring long-term stable operation of the system under complex computational tasks.

[0029] 4. This invention implements a vertical bandgap engineering optimization by introducing an intermediate layer beneath the doped layer. This intermediate layer acts as a buffer, precisely controlling the potential gradient from the channel to the substrate, thereby optimizing the device's subthreshold swing and breakdown characteristics. This achieves lower off-state current and a more stable threshold voltage. The core benefit is a significant reduction in the static power consumption of the synaptic device and an extension of the weight retention time, fundamentally contributing to improving the energy efficiency and reliability of the entire computing system.

[0030] 5. This invention utilizes 2.5D / 3D heterogeneous integration and system-in-package (SIP) technology to densely integrate the sensing and computing core, CMOS control logic, and peripheral circuits into a single package. This method constructs ultra-high bandwidth, low-latency inter-chip interconnects and tightly integrates signal conversion, power management, and other modules. Its systemic advantages lie in significantly shortening the data path, reducing transmission power consumption, and compressing system size, ultimately forming a compact and efficient "sensing-memory-computing integrated" solution, achieving a synergistic improvement from underlying device innovation to system-level performance leaps. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the structure of the present invention;

[0032] Figure 2 This is a schematic diagram of the MOS transistor in Embodiment 1 of the present invention;

[0033] Figure 3 This is a schematic diagram of the MOS transistor in Embodiment 2 of the present invention;

[0034] Figure 4 This is a schematic diagram of the MOS transistor in Embodiment 3 of the present invention;

[0035] Figure 5 This is a schematic diagram of the MOS transistor in Embodiment 4 of the present invention.

[0036] In the diagram: 1. Floating gate transistor; 2. Oxide layer; 3. Aluminum gate layer; 4. Aluminum oxide dielectric; 5. Electron transport layer; 6. Light absorption layer; 7. Right channel 2; 8. Right metal 2; 9. Right channel 1; 10. Right metal 1; 11. Right channel layer; 12. Left channel 2; 13. Left metal 2; 101. Substrate layer; 102. Well layer; 103. Doped layer; 104. Source region; 105. Drain region; 106. Doped particles; 107. MOS gate; 108. Floating gate layer; 109. Silicon oxide layer; 110. Contact particles; 111. Through particles; 112. Intermediate layer. Detailed Implementation

[0037] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] like Figure 1 As shown, the packaging method for a parallel gradient calculation chip based on synaptic transistors includes the following steps:

[0039] Step 1: Using 2.5D silicon interposer or 3D TSV technology, the... Heterogeneous integration of a transistor-based parallel gradient computing chip and a CMOS control chip is achieved. Utilizing two advanced heterogeneous integration technologies—2.5D silicon interposer or 3D Through-Silicon Via (TSV)—a high-density three-dimensional integration of the sensing-computing integrated chip, containing optical sensing transistors and floating-gate transistors, with a standard CMOS control chip is achieved. The principle is that the 2.5D interposer provides higher wiring density and signal transmission quality than traditional packaging substrates, while 3D TSV enables vertical interconnection between chips, significantly shortening the interconnection distance. This integration method establishes an ultra-high bandwidth, low-latency communication path between the sensing-computing unit and the control logic. Its advantage lies in successfully decoupling and efficiently combining dedicated, non-standard process synaptic units with mature and stable CMOS control circuits. It fully leverages the advantages of novel synaptic devices in terms of computing density and energy efficiency while utilizing existing CMOS technology for complex logic control and signal processing. Ultimately, it achieves high-performance "sensing-memory-computing" synergy at the system level, significantly improving the system integration and overall energy efficiency of parallel gradient computing.

[0040] Step 2: Achieve high-density interconnection between the synaptic transistor-based parallel gradient calculation chip and the floating-gate transistor using microbumps and a redistribution layer. Microbumps and a redistribution layer are key technologies for achieving ultra-high-density electrical connections within and between chips. The principle is that microbumps provide vertically aligned interconnects with extremely small pitch, while the redistribution layer redistributes I / O interfaces on the chip surface or interposer, directing the originally larger-pitched pads to a high-density array that matches the microbumps. This connection method not only achieves the complex ohmic connection between the floating-gate transistor, redistribution layer, and optical sensing transistor described in claim 1, but also provides an interconnection density far exceeding traditional wire bonding capabilities for the synaptic array and peripheral circuits in system integration. The advantages of this method are that it significantly reduces parasitic resistance and inductance of the interconnects, lowers signal transmission delay and power consumption, and ensures the reliability and integrity of parallel data transmission between massive synaptic units and control circuits, providing a physical basis for the high-throughput data stream necessary for large-scale parallel gradient calculations.

[0041] Step 3: Using system-in-package (SIP) technology, the ADC, DAC, and power management circuits are integrated onto the same package substrate to form a sensing-memory-computing integrated module. This integrates key peripheral circuits such as analog-to-digital converters, digital-to-analog converters, and power management with the core sensing and computing chips within the same package. The principle is to design these chips or devices with different functions as a "system" for overall packaging, interconnecting them through wiring within the package substrate to form a fully functional subsystem. This method highly integrates multiple discrete components that were originally distributed on the PCB board. Its outstanding advantages are significantly reduced system size, shorter transmission paths between analog and digital signals, reduced signal integrity issues, and lower overall power consumption. The resulting "sensing-memory-computing integrated module" is a compact, efficient, and high-performance complete solution. It enables synaptic transistor-based parallel gradient computing chips to quickly and accurately process the entire process from analog signals (such as optical sensing) to digital calculations and weight updates, achieving a key leap from device innovation to system-level energy efficiency and performance improvement.

[0042] Example 1

[0043] like Figure 1 As shown, the parallel gradient computing chip based on synaptic transistors includes a lower floating-gate transistor as a data storage transistor, a middle redistribution layer (the redistribution layer is used to increase the heat dissipation of the device and avoid heat accumulation that can easily occur when the two types of devices are stacked), and an upper... The transistor serves as an optical sensing transistor and an oxide layer 2 for filling gaps. The floating gate transistor includes P-type MOS transistors and N-type MOS transistors, characterized in that: The transistor comprises, from top to bottom, an aluminum gate layer 3, an aluminum oxide dielectric 4, an electron transport layer 5, and a light absorption layer 6;

[0044] The right side of the redistribution layer and located at Below the drain region of the transistor, from top to bottom, are right channel 2 7, right metal 2 8, right channel 1 9, right metal 1 10, and right channel layer 11, and the wiring layer is located to the left of the layer and is located at... The transistor includes, from top to bottom, a left channel 12 and a left metal 13 below the source region; the right metal 8 is ohmically connected to the drain region of the light absorption layer 6 through the right channel 7, and the left metal 13 is ohmically connected to the source region of the light absorption layer 6 through the left channel 12; the floating gate transistor includes a substrate layer 101, a well layer 102, a source region 104, a drain region 105, a MOS gate 107, a floating gate layer 108, and a silicon oxide layer 109; the source region 104 is ohmically connected to the right metal 10 through the right channel layer 11, and the right metal 10 and the right metal 8 are ohmically connected through the right channel 9.

[0045] Silicon oxide layers 109 are deposited on both the top and bottom sides of the floating gate layer 108. The well layer 102 is located above the substrate layer 101. The drain region 105 and the source region 104 are located on the left and right sides above the well layer 102, respectively. The left metal plate 13 is used to connect to the external source voltage, the MOS gate 107 is used to connect to the external gate voltage, the substrate layer 101 is used to connect to the external substrate voltage, and the drain region 105 serves as the output voltage. The high or low level output is used to store information.

[0046] The working principle of this device is as follows:

[0047] After the left metal 13 is connected to the external source voltage, when When the transistor senses light (equivalent to the gate of a MOSFET being energized), at this time... The source and drain regions of the transistor are connected, which means that the right metal element 8 and the left metal element 13 are connected. This allows external source charge to enter the source region 104 of the MOS device 1. Then, a high voltage (e.g., 20V) is applied to the MOS gate 107, and a low voltage (e.g., 0V) is applied to the substrate layer 101. Charge then enters the floating gate layer 108 (this raises the threshold voltage. If the source region 104 is not conductive, no charge enters the floating gate layer 108, and applying a high voltage will not raise the threshold voltage). The drain region 105 and the source region 104 are in a conducting state, and the drain region 105 outputs a high voltage (denoted as 1). However, if a normal voltage (e.g., 3V) is applied to the MOS gate 107, the drain region 105 outputs a low voltage (denoted as 0).

[0048] This embodiment constructs a vertically stacked core structure based on floating-gate transistors and optical sensing transistors. Its innovation lies in achieving ohmic connection and efficient heat dissipation between the upper and lower devices through an intermediate redistribution layer, and utilizing optical sensing transistors ( The photoelectric effect of the transistor (transistor) serves as the programming trigger mechanism for the floating-gate transistor 1. When light shines, the sensing transistor ( When the transistor is turned on, external source charge is injected into the source region of the floating gate transistor 1 through the redistribution layer; then a high voltage is applied to the gate of the floating gate transistor 1, the charge is trapped in the floating gate layer, thereby permanently changing its threshold voltage, and this state (high / low level) is output from the drain region as stored information.

[0049] The advantage of this structure is that it realizes the integrated function of "optical sensing-charge injection-non-volatile storage", providing a high-density integrated sensing and computing basic unit for parallel gradient calculation. At the same time, the redistribution layer effectively avoids the heat accumulation problem of stacked structures, improving the reliability and lifespan of the device.

[0050] Example 2

[0051] like Figure 1 , 2 As shown, the parallel gradient computing chip based on synaptic transistors includes a lower floating-gate transistor as a data storage transistor, a middle redistribution layer (the redistribution layer is used to increase the heat dissipation of the device and avoid heat accumulation that can easily occur when the two types of devices are stacked), and an upper... The transistor serves as both an optical sensing transistor and an oxide layer 2 for filling gaps. Floating gate transistors include P-type MOS transistors and N-type MOS transistors. In a P-type MOS transistor, the well layer 102 is made of N-type semiconductor material, while the source region 104 and drain region 105 are both made of P-type semiconductor material. In an N-type MOS transistor, the well layer 102 is made of P-type semiconductor material, while the source region 104 and drain region 105 are both made of N-type semiconductor material.

[0052] A doped layer 103 is formed inside the well layer 102 and below the source region 104 and the drain region 105 through ion implantation. In a P-type MOSFET, the doped layer 103 is made of N-type semiconductor material, and in an N-type MOSFET, the doped layer 103 is made of P-type semiconductor material. Inside the doped layer 103, several non-contact doped particles 106 are formed through ion implantation. In a P-type MOSFET, the doped particles 106 are made of P-type semiconductor material, and in an N-type MOSFET, the doped particles 106 are made of N-type semiconductor material.

[0053] This embodiment makes key optimizations based on the floating gate transistor structure of Embodiment 1. Its core innovation lies in forming a doped layer and non-contact doped particles below the source and drain regions in the well layer through ion implantation. In P-type / N-type MOS transistors, these doped particles are identical in shape to the source and drain regions, respectively. The principle is that these particles form localized carrier-rich regions or low-resistance paths below the channel, enabling more effective control of the channel electric field and current.

[0054] The advantage of this design is that it significantly improves the electrical conductivity and conductivity window of the device. This is because the doped particles optimize the charge transport path in the channel, reduce the nonlinear effects caused by traditional single-channel modulation, and make the synaptic weights based on this device more accurate and have a larger dynamic range, thereby directly improving the accuracy and dynamic range of parallel gradient calculation.

[0055] Example 3

[0056] like Figure 1 , 3 As shown, the parallel gradient computing chip based on synaptic transistors includes a lower floating-gate transistor as a data storage transistor, a middle redistribution layer (the redistribution layer is used to increase the heat dissipation of the device and avoid heat accumulation that can easily occur when the two types of devices are stacked), and an upper... The transistor serves as both an optical sensing transistor and an oxide layer 2 for filling gaps. Floating gate transistors include P-type MOS transistors and N-type MOS transistors. In a P-type MOS transistor, the well layer 102 is made of N-type semiconductor material, while the source region 104 and drain region 105 are both made of P-type semiconductor material. In an N-type MOS transistor, the well layer 102 is made of P-type semiconductor material, while the source region 104 and drain region 105 are both made of N-type semiconductor material.

[0057] A doped layer 103 is formed inside the well layer 102 and below the source region 104 and the drain region 105 via ion implantation. In a P-type MOSFET, the doped layer 103 is made of N-type semiconductor material, and in an N-type MOSFET, the doped layer 103 is made of P-type semiconductor material. Inside the doped layer 103, a plurality of non-contacting doped particles 106 are formed via ion implantation. In a P-type MOSFET, the doped particles 106 are made of P-type semiconductor material, and in an N-type MOSFET, the doped particles 106 are made of N-type semiconductor material. The doped particles 106 also include contact particles 110, the bottom end of which is in direct contact with the well layer 102.

[0058] This embodiment further develops upon the introduction of doped particles in Embodiment 2. Its key innovation lies in defining some of the doped particles as "contact particles," whose bottom ends are in direct contact with the well layer. This structure alters the potential distribution and carrier recombination behavior between the well layer and the doped region. The working principle is that the contact particles establish a direct electrical connection from the doped region to the well layer, enhancing the local field-effect modulation capability and potentially acting as a "local ground" or shielding layer, stabilizing the electric field beneath the channel.

[0059] The advantage of this design is that it further improves the performance consistency and stability of the device after multiple programming operations and reduces weight drift. This is because the contact particles help dissipate injected charge or stabilize the interface potential, making the electrical characteristics of each device in the large-scale synaptic array more uniform and improving the computational reliability of the overall system.

[0060] Example 4

[0061] like Figure 1 , 4 As shown, the parallel gradient computing chip based on synaptic transistors includes a lower floating-gate transistor as a data storage transistor, a middle redistribution layer (the redistribution layer is used to increase the heat dissipation of the device and avoid heat accumulation that can easily occur when the two types of devices are stacked), and an upper... The transistor serves as both an optical sensing transistor and an oxide layer 2 for filling gaps. Floating gate transistors include P-type MOS transistors and N-type MOS transistors. In a P-type MOS transistor, the well layer 102 is made of N-type semiconductor material, while the source region 104 and drain region 105 are both made of P-type semiconductor material. In an N-type MOS transistor, the well layer 102 is made of P-type semiconductor material, while the source region 104 and drain region 105 are both made of N-type semiconductor material.

[0062] A doped layer 103 is formed inside the well layer 102 and below the source region 104 and the drain region 105 via ion implantation. In a P-type MOSFET, the doped layer 103 is made of N-type semiconductor material, and in an N-type MOSFET, the doped layer 103 is made of P-type semiconductor material. Inside the doped layer 103, a plurality of non-contact doped particles 106 are formed via ion implantation. In a P-type MOSFET, the doped particles 106 are made of P-type semiconductor material, and in an N-type MOSFET, the doped particles 106 are made of N-type semiconductor material. The doped particles 106 also include through-hole particles 111, the bottom end of which extends below the well layer 102 and directly contacts the substrate layer 101.

[0063] This embodiment proposes another variant of the doped particle—the "through-particle"—whose innovation lies in the fact that the bottom end of the particle penetrates the entire well layer and directly contacts the underlying substrate. This is equivalent to establishing a deep ohmic contact or isolation structure between the source / drain regions of the transistor and the common substrate. The working principle is that the through-particle provides a vertical path for charge carriers from the active region directly to the substrate, which not only more effectively dissipates heat and leakage current but also creates better electrical isolation between devices.

[0064] The outstanding advantage of this structure is that it greatly enhances the device's anti-interference capability and heat dissipation efficiency, making it particularly suitable for high-density, large-scale parallel computing chip environments. It can effectively suppress crosstalk and performance degradation caused by substrate coupling or heat concentration, ensuring the long-term stable operation of the system in complex computing tasks.

[0065] Example 5

[0066] like Figure 1 , 5 As shown, the parallel gradient computing chip based on synaptic transistors includes a lower floating-gate transistor as a data storage transistor, a middle redistribution layer (the redistribution layer is used to increase the heat dissipation of the device and avoid heat accumulation that can easily occur when the two types of devices are stacked), and an upper... The transistor serves as both an optical sensing transistor and an oxide layer 2 for filling gaps. Floating gate transistors include P-type MOS transistors and N-type MOS transistors. In a P-type MOS transistor, the well layer 102 is made of N-type semiconductor material, while the source region 104 and drain region 105 are both made of P-type semiconductor material. In an N-type MOS transistor, the well layer 102 is made of P-type semiconductor material, while the source region 104 and drain region 105 are both made of N-type semiconductor material.

[0067] A doped layer 103 is formed inside the well layer 102 and below the source region 104 and the drain region 105 via ion implantation. In a P-type MOSFET, the doped layer 103 is made of N-type semiconductor material, and in an N-type MOSFET, the doped layer 103 is made of P-type semiconductor material. Below the doped layer 103, an intermediate layer 112 is formed via ion implantation. In a P-type MOSFET, the intermediate layer 112 is made of N-type semiconductor material, and in an N-type MOSFET, the intermediate layer 112 is made of P-type semiconductor material.

[0068] The innovation of this embodiment lies in the formation of an additional "intermediate layer" beneath the doped layer through ion implantation. This intermediate layer has the same semiconductor type as the well layer (N-type in P-type MOS and P-type in N-type MOS), creating a more complex internal carrier distribution profile. Its working principle is that the intermediate layer acts as a buffer or transition region, enabling more precise control of the potential gradient from the channel to the substrate and the depletion region width, thereby optimizing the device's subthreshold characteristics and breakdown voltage.

[0069] The core advantage of this design lies in its provision of a sophisticated bandgap engineering approach. Without altering the core process, it optimizes the vertical doping distribution to achieve lower off-state current, higher on / off ratio, and more stable threshold voltage. This is crucial for reducing the static power consumption of synaptic devices and improving weight retention capabilities, resulting in significant improvements in both energy efficiency and reliability of the chip.

[0070] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A parallel gradient calculation chip based on synaptic transistors, comprising a lower floating gate transistor (1), a middle redistribution layer, and an upper... The transistor and the oxide layer (2) for filling the gap, the floating gate transistor (1) comprising a P-type MOS transistor and an N-type MOS transistor, characterized in that: The The transistor comprises, from top to bottom, an aluminum gate layer (3), an aluminum oxide dielectric layer (4), an electron transport layer (5), and a light absorption layer (6). The redistribution layer is to the right of and located at the right side of the redistribution layer. Below the drain region of the transistor, from top to bottom, are right channel two (7), right metal two (8), right channel one (9), right metal one (10), and right channel layer (11), located to the left of the rewiring layer and situated at... The transistor's source region includes, from top to bottom, left channel 2 (12) and left metal 2 (13). The floating gate transistor (1) includes a substrate layer (101), a well layer (102), a source region (104), a drain region (105), a MOS gate (107), a floating gate layer (108), and a silicon oxide layer (109); wherein the source region (104) is ohmically connected to the right metal one (10) through the right channel layer (11), and the right metal one (10) and the right metal two (8) are ohmically connected through the right channel one (9).

2. The parallel gradient calculation chip based on synaptic transistors according to claim 1, characterized in that: The left metal layer (13) is used to connect to the external source voltage, the MOS gate (107) is used to connect to the external gate voltage, the substrate layer (101) is used to connect to the external substrate voltage, and the drain region (105) is used as the output voltage. The output voltage outputs a high level or a low level as the stored information.

3. The parallel gradient calculation chip based on synaptic transistors according to claim 1, characterized in that: Silicon oxide layers (109) are deposited on both the upper and lower sides of the floating gate layer (108). The well layer (102) is located above the substrate layer (101). The drain region (105) and the source region (104) are located on the left and right sides above the well layer (102), respectively.

4. The parallel gradient calculation chip based on synaptic transistors according to claim 1, characterized in that: The well layer (102) in the P-type MOS transistor is made of N-type semiconductor material, and the source region (104) and drain region (105) are both made of P-type semiconductor material; The well layer (102) of the N-type MOS transistor is made of P-type semiconductor material, and the source region (104) and drain region (105) are both made of N-type semiconductor material.

5. The parallel gradient calculation chip based on synaptic transistors according to claim 4, characterized in that: The well layer (102) is doped with a layer (103) formed by ion implantation inside and below the source region (104) and the drain region (105). In the P-type MOS transistor, the doped layer (103) is made of N-type semiconductor material, and in the N-type MOS transistor, the doped layer (103) is made of P-type semiconductor material.

6. The parallel gradient calculation chip based on synaptic transistors according to claim 5, characterized in that: The interior of the doped layer (103) is formed with a number of non-contacting doped particles (106) through ion implantation. In the P-type MOS transistor, the doped particles (106) are made of P-type semiconductor material, and in the N-type MOS transistor, the doped particles (106) are made of N-type semiconductor material.

7. The parallel gradient calculation chip based on synaptic transistors according to claim 6, characterized in that: The doped particles (106) also include contact particles (110), the bottom end of which is in direct contact with the well layer (102).

8. The parallel gradient calculation chip based on synaptic transistors according to claim 6, characterized in that: The doped particles (106) also include through particles (111), the bottom end of which extends below the well layer (102) and is in direct contact with the substrate layer (101).

9. The parallel gradient calculation chip based on synaptic transistors according to claim 5, characterized in that: An intermediate layer (112) is formed below the doped layer (103) by ion implantation. In the P-type MOS transistor, the intermediate layer (112) is made of N-type semiconductor material, and in the N-type MOS transistor, the intermediate layer (112) is made of P-type semiconductor material.

10. A packaging method for a parallel gradient calculation chip based on synaptic transistors, characterized in that, The method for packaging the synaptic transistor-based parallel gradient calculation chip according to claim 1 includes the following steps: S1. Using 2.5D silicon interposer or 3D TSV technology, the... The parallel gradient calculation chip of transistors is heterogeneously integrated with the CMOS control chip; S2. High-density interconnection between the synaptic transistor-based parallel gradient calculation chip and the floating gate transistor (1) is achieved through microbumps and a redistribution layer; S3. Using system-in-package technology, the ADC, DAC and power management circuits are integrated on the same package substrate to form an integrated sensing-memory-computing module.

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