Semiconductor memory device and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor memory device capable of improving data retention characteristics, improving write saturation and reducing erase saturation, and a method of manufacturing the same. A semiconductor memory device according to an embodiment includes a laminate in which a plurality of electrode films and a plurality of first insulating films are alternately laminated in a first direction. The columnar body is provided so as to penetrate the laminated body in the first direction. The aluminum oxide film is provided between the columnar body and the electrode film. The first tetravalent metal oxide is present at the interface between the columnar body and the aluminum oxide film.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0002] Semiconductor memory devices such as NAND flash memory sometimes have a three-dimensional array of memory cells arranged in three dimensions. In such a three-dimensional array, a barrier film is provided between the word line and the charge accumulation layer to suppress back tunneling of charge from the word line to the charge accumulation layer. In such semiconductor memory devices, it is desirable to improve the data retention characteristics in the charge accumulation layer, as well as to increase write saturation and decrease erase saturation. Summary of the Invention

[0003] A semiconductor memory device and its manufacturing method are provided, which can improve data retention characteristics, increase write saturation and reduce erase saturation.

[0004] The semiconductor memory device of this embodiment includes a laminate in which multiple electrode films and multiple first insulating films are alternately stacked in a first direction. A columnar body is disposed through the laminate in the first direction. An aluminum oxide film is disposed between the columnar body and the electrode films. A first tetravalent metal oxide is present at the interface between the columnar body and the aluminum oxide film. Attached Figure Description

[0005] Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device according to this embodiment.

[0006] Figure 2 It is a planar diagram representing a stacked body.

[0007] Figure 3 This is a cross-sectional view illustrating a three-dimensional storage cell.

[0008] Figure 4 This is a cross-sectional view illustrating a three-dimensional storage cell.

[0009] Figure 5 Yes Figure 3 A cross-sectional view illustrating the storage unit in more detail.

[0010] Figure 6 This is a cross-sectional view showing an example of the configuration between the charge trapping film and the electrode film.

[0011] Figure 7 This is a cross-sectional view showing an example of the configuration between the charge trapping film and the electrode film.

[0012] Figure 8 This is a cross-sectional view showing an example of the configuration between the charge trapping film and the electrode film.

[0013] Figure 9 This is a cross-sectional view showing an example of the configuration between the charge trapping film and the electrode film.

[0014] Figure 10 This is a cross-sectional view showing a configuration example where the electrode film is tungsten.

[0015] Figure 11 It is a graph representing the shift amount of IRDR (Infrared Data Retention).

[0016] Figure 12 This is a graph representing the write saturation voltage.

[0017] Figure 13 It means to Figure 6 A cross-sectional view of a configuration example obtained by adding metal oxide 221a_3.

[0018] Figure 14 It means to Figure 9 A cross-sectional view of a configuration example obtained by adding metal oxide 221a_3.

[0019] Figure 15 This is a graph representing the erase saturation voltage.

[0020] Figure 16 This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor memory device according to this embodiment.

[0021] Figure 17 Is following Figure 16 The following is a cross-sectional view illustrating an example of the manufacturing process.

[0022] Figure 18 Is following Figure 17 The following is a cross-sectional view illustrating an example of the manufacturing process.

[0023] Figure 19 Is following Figure 18 The following is a cross-sectional view illustrating an example of the manufacturing process.

[0024] Figure 20 Is following Figure 19 The following is a cross-sectional view illustrating an example of the manufacturing process.

[0025] Figure 21 Is following Figure 20 The following is a cross-sectional view illustrating an example of the manufacturing process.

[0026] Explanation of reference numerals in the attached figures

[0027] 1. Semiconductor memory device

[0028] 20-layer stack

[0029] ST slit

[0030] 2m storage cell array

[0031] 21 Electrode film

[0032] 22 Insulating film

[0033] CL columnar body

[0034] 210 Semiconductor Body

[0035] 220 storage membrane

[0036] 221a_1 metal oxide

[0037] 221a_2 Barrier Insulating Film

[0038] 221 Covering with insulating film

[0039] 222 Charge trapping membrane

[0040] 223 Tunnel insulation film

[0041] 230 core layer Detailed Implementation

[0042] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0043] This embodiment does not limit the invention. The accompanying drawings are schematic or conceptual. In the specification and drawings, the same reference numerals are used to refer to the same elements.

[0044] Figure 1 This is a cross-sectional view showing an example of the configuration of the semiconductor memory device 1 according to this embodiment. Hereinafter, the stacking direction of the laminate 20 will be defined as the Z direction. A direction intersecting or, for example, orthogonal to the Z direction will be defined as the Y direction. A direction intersecting or, for example, orthogonal to both the Z and Y directions will be defined as the X direction. Figure 1 In the diagram, the +Z direction is set to upward to represent semiconductor memory device 1. Figure 5 In subsequent sectional views, the -Z or Y direction is sometimes set as the top to represent the array chip. Furthermore, in this specification, the ±Z direction is an example of the first direction.

[0045] Semiconductor memory device 1 includes an array chip 2 having an array of memory cells and a CMOS chip 3 having CMOS circuitry. The array chip 2 and the CMOS chip 3 are bonded together at a bonding surface B1 and electrically connected to each other via wiring joined at the bonding surface B1. Figure 1 The text indicates that the array chip 2 is set on the CMOS chip 3.

[0046] The CMOS chip 3 includes a substrate 30, transistors 31, vias 32, wiring 33 and 34, and an interlayer insulating film 35.

[0047] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a P-type MOSFET disposed on the substrate 30. The transistor 31, for example, constitutes a CMOS (Complementary MOS) circuit for controlling the memory cell array 2m of the array chip 2. Multiple transistors 31 constitute logic circuits such as a sense amplifier, row decoder, and column decoder. Other semiconductor elements besides the transistors 31, such as resistors and capacitors, may also be formed on the substrate 30.

[0048] Via 32 electrically connects transistor 31 to wiring 33, or wiring 33 to wiring 34. Wiring 33 and 34 form a multilayer wiring structure within interlayer insulating film 35. Wiring 34 is embedded within interlayer insulating film 35 and is exposed substantially coplanarly on the surface of interlayer insulating film 35. Wiring 33 and 34 are electrically connected to transistor 31, etc. For example, metals such as copper or tungsten are used for via 32 and wiring 33 and 34. Interlayer insulating film 35 covers and protects transistor 31, via 32, wiring 33 and 34. For example, an insulating film such as silicon oxide is used for interlayer insulating film 35.

[0049] The array chip 2 includes a stack 20, a columnar layer CL, a source layer BSL, a metal layer 40, a contact plug CCw, a contact plug 29, a bonding pad 50, wiring 23 and 24, a via 28, and an interlayer insulating film 25.

[0050] The stack 20 is disposed above the transistor 31 and is located in the +Z direction relative to the substrate 30. The stack 20 is constructed by alternately stacking multiple electrode films 21 and multiple insulating films 22 along the Z direction. The stack 20, together with the pillar CL, constitutes a memory cell array. For the electrode films 21, a conductive metal such as tungsten is used, for example. For the insulating films 22, a silicon oxide film is used, for example. The insulating films 22 insulate the electrode films 21 from each other. That is, multiple electrode films 21 are stacked in an insulated state. The number of stacks of each electrode film 21 and insulating film 22 is arbitrary. The insulating film 22 can be, for example, a porous insulating film or an air gap.

[0051] One or more electrode films 21 at the upper and lower ends of the stacked body 20 in the Z direction function as the source-side select gate (SGS) and drain-side select gate (SGD), respectively. The electrode film 21 between the source-side select gate (SGS) and the drain-side select gate (SGD) functions as the word line (WL). The word line (WL) is the gate electrode of the memory cell (MC). The source-side select gate (SGS) is the gate electrode of the source-side select transistor (SMT). The drain-side select gate (SGD) is the gate electrode of the drain-side select transistor (SMT). The source-side select gate (SGS) is located in the upper region of the stacked body 20. The drain-side select gate (SGD) is located in the lower region of the stacked body 20. The upper region refers to the region of the stacked body 20 away from the CMOS chip 3 (the side closer to the metal layer 40), and the lower region refers to the region of the stacked body 20 closer to the CMOS chip 3.

[0052] Semiconductor memory device 1 has multiple memory cells MC connected in series between source-side select transistors and drain-side select transistors. The structure formed by the series connection of the source-side select transistors, memory cells MC, and drain-side select transistors is called a "memory string" or "NAND string". The memory string is connected to a bit line BL, for example, via a via 28. The bit line BL is a wiring 23 located below the stack-up 20 and extending in the X direction. Therefore, hereinafter, the bit line BL will also be referred to as bit line 23.

[0053] Multiple columnar bodies CL are provided within the laminate 20. The columnar bodies CL extend within the laminate 20 in a manner that penetrates the laminate 20 in its lamination direction (Z direction), extending from the via 28 connected to the bit line 23 to the source layer BSL. The internal structure of the columnar bodies CL will be described later. Furthermore, in Figure 1 The diagram illustrates the case where the columnar body CL is divided into two segments along the Z-direction. However, as... Figure 5 As shown in A, the columnar body CL can also be formed by dividing it into more than 3 segments.

[0054] in addition, Figure 1 Although not illustrated, multiple gaps ST are provided within the laminate 20 (see reference). Figure 2 The slit ST extends in the Y direction and penetrates the laminate 20 in the Z direction. An insulating film, such as a silicon oxide film, is filled within the slit ST, and the insulating film is plate-shaped. The slit ST electrically divides the electrode film 21 of the laminate 20. Alternatively, an insulating film, such as a silicon oxide film, can be coated on the inner wall of the slit ST, and a conductive material can be embedded inside the insulating film. In this case, the conductive material can also function as source wiring reaching the source layer BSL.

[0055] A source layer BSL is disposed on the laminate 20. The source layer BSL is disposed correspondingly to the laminate 20. The laminate 20 (memory cell array 2m) is disposed on the F1 side of the source layer BSL, and a metal layer 40 is disposed on the opposite side, the F2 side. The source layer BSL is connected to one end of a plurality of pillars CL, imparting a common source voltage to the plurality of pillars CL located in the same memory cell array 2m. That is, the source layer BSL functions as a common source electrode of the memory cell array 2m. For the source layer BSL, a conductive material such as doped polysilicon is used, for example. For the metal layer 40, a metal material with a lower resistance than the source layer BSL, such as copper, aluminum, or tungsten, is used, for example.

[0056] On the other hand, a bonding pad 50 is provided in a region above the source layer BSL surface F2 where the source layer BSL is not located. The bonding pad 50 is connected to metal lines (not shown) and receives power or signals from outside the semiconductor memory device 1. The bonding pad 50 is configured to connect to one end of the contact plug 29 in the Z direction. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact plug 29, wiring 24, and wiring 34. External power supplied from the bonding pad 50 is supplied to the transistor 31. Alternatively, signals are supplied to the transistor 31 via the bonding pad 50.

[0057] Contact plugs CCw are disposed on the periphery of the laminate 20, extending along the Z direction within the interlayer insulating film 25. Contact plugs CCw are electrically connected between the electrode films 21 (word lines WL) and the wiring 24. Contact plugs CCw are disposed at the ends of the laminate 20 where the electrode films 21 are formed into stepped portions 2s, and are electrically connected to each electrode film 21. Contact plugs CCw are provided to transmit word line voltage from the CMOS chip 3 to each electrode film 21. For example, metals such as copper or tungsten are used for contact plugs CCw.

[0058] Contact plug 29 is disposed on the periphery of laminate 20 and extends in the Z direction within interlayer insulating film 25. Contact plug 29 is disposed at least from a lower side of laminate 20 to a higher side of laminate 20.

[0059] Contact plug 29 is electrically connected between bonding pad 50 and wiring 24. Contact plug 29 is used to supply power or signals from bonding pad 50 to array chip 2 or CMOS chip 3. Contact plug 29 may be made of metals such as copper or tungsten. The power supply may be, for example, the power supply voltage VDD, or a reference voltage (e.g., ground voltage) VSS that is lower than the power supply voltage VDD. The signal may be an external control signal, or it may be data being written or read.

[0060] In this embodiment, the array chip 2 and the CMOS chip 3 are formed independently and bonded together at the bonding surface B1. Therefore, no transistor 31 is disposed within the array chip 2. Furthermore, no stacked layer 20 (memory cell array 2m) is disposed within the CMOS chip 3.

[0061] A via 28, wiring 23, and wiring 24 are provided below the laminate 20. Wiring 23 and 24 are embedded within the interlayer insulating film 25. Wiring 24 is exposed substantially coplanarly on the surface of the interlayer insulating film 25. Wiring 23 and 24 are connected to the semiconductor body of the columnar body CL. Figure 3 and Figure 4 Electrical connections such as 210 are used. For vias 28, wiring 23, and wiring 24, metals such as copper or tungsten are used, for example. An interlayer insulating film 25 protects the laminate 20, vias 28, wiring 23, and wiring 24 by covering them. For the interlayer insulating film 25, an insulating film such as silicon oxide is used, for example.

[0062] Interlayer insulating film 25 and interlayer insulating film 35 are bonded at bonding surface B1, and simultaneously, wiring 24 and wiring 34 are bonded at bonding surface B1 in a substantially coplanar manner. Thus, array chip 2 and CMOS chip 3 are electrically connected via wiring 24 and wiring 34.

[0063] Figure 2 This is a plan view of the stack 20. The stack 20 includes a stepped portion 2s and a memory cell array 2m. The stepped portion 2s is provided, for example, at one end of the stack 20. The memory cell array 2m is sandwiched or surrounded by the stepped portion 2s. A slot ST is provided from the stepped portion 2s at one end of the stack 20 through the memory cell array 2m to the stepped portion 2s at the other end of the stack 20. A slot SHE is provided at least in the memory cell array 2m. Compared to the slot ST, the slot SHE is shallower in the Z direction and extends approximately parallel to the slot ST. The slot SHE electrically divides the electrode film 21 on the lower region side of the stack 20 by a gate selector SGD on each drain side. For the slot SHE, an insulating film such as a silicon oxide film is used, for example. Alternatively, the slot ST may also include source wiring that is electrically separated from the electrode film 21 of the stack 20 and electrically connected to the source layer BSL.

[0064] Depend on Figure 2 The portion of the stack 20 sandwiched between the two slots ST is called the block BLK. The block BLK constitutes, for example, the smallest unit of data erasure. Slots SHE are disposed within the block BLK. The stack 20 between slots ST and SHE is called a finger. The drain-side select gate SGD is divided for each finger. Therefore, during data writing and reading, one finger within the block BLK can be selected by the drain-side select gate SGD.

[0065] Figure 3 as well as Figure 4 These are cross-sectional views illustrating a three-dimensional memory cell structure. Multiple columnar bodies CL are disposed within memory vias MH provided in the laminate 20. Each columnar body CL extends along the Z-direction from one end of the laminate 20, penetrating the laminate 20 and extending into the source layer BSL. Each columnar body CL includes a semiconductor body 210, a memory film 220, and a core layer 230. Each columnar body CL includes a core layer 230 disposed at its center, a semiconductor body (semiconductor layer) 210 surrounding the core layer 230, and a memory film 220 surrounding the semiconductor body 210. The semiconductor body 210 extends along the memory vias MH in the Z-direction within the laminate 20, penetrating the laminate 20. The semiconductor body 210 is electrically connected to the source layer BSL. The storage film 220 is disposed between the semiconductor body 210 and the electrode film 21, and has a covering insulating film 221, a charge trapping film 222, and a tunnel insulating film 223. Multiple columnar bodies CL, one selected from each of the finger portions, are transmitted via... Figure 1 The vias 28 are all connected to a bit line 23. The pillars CL are respectively set in a region, for example, the memory cell array 2m.

[0066] Additionally, a metal oxide 221a_1 and a barrier insulating film 221a_2 are disposed between the columnar body CL and the electrode film 21. The metal oxide 221a_1 and the barrier insulating film 221a_2 cover the electrode film 21 (word line WL). Therefore, a metal oxide 221a_1 and a barrier insulating film 221a_2 are also disposed between the electrode film 21 and the insulating film 22. The metal oxide 221a_1 is present at the interface between the barrier insulating film 221a_2 and the covering insulating film 221. The metal oxide 221a_1 is composed of a tetravalent metal oxide, such as any one of TiO2, ZrO2, HfO2, and RfO2. The metal oxide 221a_1 can be a metal oxide with a higher relative permittivity than that of the silicon oxide film. The barrier insulating film 221a_2 is, for example, an aluminum oxide. The barrier insulating film 221a_2 suppresses reverse tunneling of charge from the electrode film 21 to the storage film 220 side. The metal oxide 221a_1 can improve data retention characteristics (e.g., IRDR) and erase saturation voltage, and suppress the degradation of write saturation voltage. The metal oxide 221a_1 will be described in more detail below. It can also be said that the metal oxide 221a_1 and the barrier insulating film 221a_2 constitute part of the storage film 220.

[0067] like Figure 4 As shown, the shape of the storage hole MH in the X-Y plane is, for example, a circle or an ellipse. Correspondingly, the shape of the columnar body CL in the X-Y plane is also, for example, a circle or an ellipse.

[0068] The semiconductor body 210 has a shape, for example, a bottomed cylindrical shape. Polycrystalline silicon is used for the semiconductor body 210, for example. The semiconductor body 210 is, for example, undoped silicon. Alternatively, the semiconductor body 210 can be p-type silicon. The semiconductor body 210 serves as a tunnel for each of the drain-side selection transistors, memory cells MC, and source-side selection transistors. That is, multiple memory cells MC have storage regions between the semiconductor body 210 and the electrode film 21, which forms the word line WL, and are stacked in the Z direction. One end of multiple semiconductor bodies 210 within the same memory cell array 2m is electrically connected to the source layer BSL.

[0069] like Figure 3 As shown, the storage film 220 includes, for example, a cover insulating film 221, a charge trapping film 222, a tunnel insulating film 223, a metal oxide 221a_1, and a barrier insulating film 221a_2. The portion of the storage film 220, excluding the metal oxide 221a_1 and the barrier insulating film 221a_2, is disposed as part of a columnar body CL between the inner wall of the storage via MH (laminated structure 20) and the semiconductor substrate 210. The cover insulating film 221, the charge trapping film 222, and the tunnel insulating film 223 are, for example, cylindrical in shape. Each of the cover insulating film 221, the charge trapping film 222, and the tunnel insulating film 223 extends in the Z direction.

[0070] A cover insulating film 221 is located between the semiconductor body 210 and the laminate 20. The cover insulating film 221 is disposed between the insulating film 22 and the charge trapping film 222, and between the barrier insulating film 221a_2 (or metal oxide 221a_1) and the charge trapping film 222. The cover insulating film 221, for example, comprises silicon oxide. The cover insulating film 221 is used to sandwich the sacrificial film ( Figure 6 When A's 21a) is replaced with electrode film 21 (replacement process), the charge trapping film 222 is protected to prevent it from being etched.

[0071] A charge trapping film 222 is located between the covering insulating film 221 and the semiconductor body 210. The charge trapping film 222 is disposed between the covering insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 may contain, for example, silicon nitride and has trap sites within the film for trapping charges. The portion of the charge trapping film 222 sandwiched between the electrode film 21 (which forms the word line WL) and the semiconductor body 210 serves as a charge trapping section, constituting the storage region of the memory cell MC. The threshold voltage of the memory cell MC varies depending on whether there is charge in the charge trapping section or the amount of charge trapped in the charge trapping section. Thus, the memory cell MC retains information.

[0072] A tunnel insulating film 223 is disposed between the semiconductor substrate 210 and the charge trapping film 222. The tunnel insulating film 223 may comprise, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 acts as a potential barrier between the semiconductor substrate 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor substrate 210 into the charge trapping film 222 (writing operation), and when holes are injected from the semiconductor substrate 210 into the charge trapping film 222 (erasing operation), electrons and holes respectively tunnel through the potential barrier of the tunnel insulating film 223.

[0073] The core layer 230 is embedded within the internal space of the cylindrical semiconductor body 210. The core layer 230 is, for example, columnar. The core layer 230 contains, for example, silicon oxide and has insulating properties.

[0074] Figure 5 To explain in more detail Figure 3 A partial cross-sectional view of the storage cell is shown. The diagram illustrates the charge trapping film 222 and the covering insulating film 221 within the columnar body CL inside the storage aperture MH. Additionally, a barrier insulating film (aluminum oxide film) 221a_2 is disposed between the covering insulating film 221 and the electrode film 21, and between the insulating film 22 and the electrode film 21. A metal oxide 221a_1 is present at the interface between the covering insulating film 221 and the barrier insulating film 221a_2, and at the interface between the insulating film 22 and the barrier insulating film 221a_2.

[0075] The concentration of metal oxide 221a_1 is maximized at the interface between the covering insulating film 221 and the barrier insulating film 221a_2, and at the interface between the insulating film 22 and the barrier insulating film 221a_2. Furthermore, the concentration of metal oxide 221a_1 decreases from the interface between the covering insulating film 221 or the insulating film 22 and the barrier insulating film 221a_2 toward the electrode film 21 or the barrier insulating film 221a_2. Additionally, the concentration of metal oxide 221a_1 decreases from the interface between the covering insulating film 221 or the insulating film 22 and the barrier insulating film 221a_2 toward the covering insulating film 221 or the insulating film 222 of the columnar body CL. In other words, the concentration of metal oxide 221a_1 gradually decreases from the interface between the covering insulating film 221 or the insulating film 22 and the barrier insulating film 221a_2 toward both sides. The metal oxide 221a_1 exists in the range of 0.1 nm to 0.3 nm in a direction that intersects (e.g., orthogonally) with the interface between the barrier insulating film 221a_2 and the covering insulating film 221. The metal oxide 221a_1 may exist as a film or may not be identified as a film but may be detected as a component.

[0076] Here, the structure of the covering insulating film 221, the metal oxide 221a_1, and the barrier insulating film 221a_2 located between the charge trapping film 222 and the electrode film 21 will be described.

[0077] Figures 6-10 This is a cross-sectional view showing an example of the configuration between the charge trapping film 222 and the electrode film 21.

[0078] exist Figure 6 In this example, the laminated film covering the insulating film 221 and the blocking insulating film 221a_2 is disposed between the charge trapping film 222 and the electrode film 21. The thickness of the aluminum oxide film of the blocking insulating film 221a_2 is, for example, about 2.7 nm. Figures 6-9 In this example, electrode film 21 is made of molybdenum. In this case, a titanium nitride film (not shown) serving as a barrier film is not disposed between the blocking insulating film 221a_2 and electrode film 21.

[0079] exist Figure 7 In this example, a laminated film covering the insulating film 221 and the metal oxide 221a_1 is disposed between the charge trapping film 222 and the electrode film 21. Figure 7 In this example, instead of the barrier insulating film 221a_2, a metal oxide 221a_1 is disposed between the covering insulating film 221 and the electrode film 21. The metal oxide 221a_1 is, for example, hafnium oxide (HfO2). The film thickness of the metal oxide 221a_1 is, for example, 5 nm, and can be identified as a film.

[0080] exist Figure 8 In this example, a laminated film covering the insulating film 221, the metal oxide 221a_1, and the barrier insulating film 221a_2 is disposed between the charge trapping film 222 and the electrode film 21. Figure 8 In the example, a barrier insulating film 221a_2 and a metal oxide 221a_1 are provided. The metal oxide 221a_1 is disposed between the aluminum oxide film covering the insulating film 221 and the barrier insulating film 221a_2. The metal oxide 221a_1 is, for example, hafnium oxide (HfO). The thickness of the aluminum oxide film of the barrier insulating film 221a_2 is, for example, about 2.7 nm. The thickness of the metal oxide 221a_1 is, for example, 1 nm, and can be identified as a film.

[0081] Figure 9 Examples and Figure 8Similarly, a laminated film consisting of a covering insulating film 221, a metal oxide 221a_1, and a barrier insulating film 221a_2 is disposed between the charge trapping film 222 and the electrode film 21. The thickness of the aluminum oxide film of the barrier insulating film 221a_2 can be, for example, about 2.7 nm. However, the thickness of the metal oxide 221a_1 is, for example, less than 0.1 nm, and is hardly recognized as a film. The metal oxide 221a_1 can be detected as a component of hafnium oxide (HfO2) detected at the interface between the covering insulating film 221 and the barrier insulating film 221a_2.

[0082] Figure 10 This is a cross-sectional view showing an example of the configuration when the electrode film 21 is tungsten. Figure 10 In this example, a laminated film comprising an insulating film 221, a barrier insulating film 221a_2, and a barrier film 21b is disposed between the charge trapping film 222 and the electrode film 21. In this case, the barrier film 21b is disposed between the aluminum oxide film of the barrier insulating film 221a_2 and the tungsten of the electrode film 21. The barrier film 21b is, for example, made of a titanium nitride film. The barrier film 21b is disposed to improve the adhesion (close contact) between the aluminum oxide film of the barrier insulating film 221a_2 and the tungsten of the electrode film 21. Figure 10 Other components and Figure 6 The composition is the same. Therefore, in this example, metal oxide 221a_1 is not set.

[0083] Figure 11 This is a graph representing the offset of IRDR. The vertical axis of this graph represents the offset of IRDR. Figure 10 The offset (voltage) of the IRDR based on the configuration. That is, subtracting from the offset of each configuration's IRDR. Figure 10 The value is obtained by the offset of the IRDR. The horizontal axis represents... Figures 6-9 Each component has its own structure. The offset of the IRDR represents the change in the data retention state of the memory cell MC after it is heated to, for example, 240 to 250 degrees Celsius (threshold voltage shift). Therefore, when the offset of the IRDR is small, it can be determined that the data retention characteristics are good, and thus preferred.

[0084] exist Figure 6 In its structure, the aluminum oxide film that blocks the insulating film 221a_2 allows oxygen atoms to easily pass from Mo (MoOx), which readily forms an oxide film due to exposure to raw material gases and the atmosphere, toward the insulating film 221. These oxygen atoms react with hydrogen atoms generated during the subsequent hydrogen annealing process to form OH-. + OH +Defects are generated by the reaction between the silicon oxide film covering the insulating film 221 and the electrode film 21. These defects in the insulating film 221 allow electrons in the charge trapping film 222 to easily pass towards the electrode film 21. As a result, the threshold voltage deviation of the memory cell MC is relatively large.

[0085] exist Figure 7 In its composition, the hafnium oxide of metal oxide 221a_1 does not allow oxygen atoms to pass through much even when heated. Therefore, since the insulating film 221 makes it difficult for oxygen atoms to pass through, OH groups are suppressed. + The generation of defects in the insulating film 221 is suppressed. As a result, it has... Figure 7 The offset of the threshold voltage of the memory cell MC is proportional to the value of the memory cell MC. Figure 6 The threshold voltage offset of the memory cell MC is small.

[0086] exist Figure 8 The structure comprises a hafnium oxide metal oxide 221a_1 and an aluminum oxide film 221a_2, which forms a barrier insulating film. The hafnium oxide metal oxide 221a_1 makes it difficult for oxygen atoms to pass through. Therefore, it has… Figure 8 The offset of the threshold voltage of the memory cell MC is proportional to the value of the memory cell MC. Figure 6 The threshold voltage offset of the memory cell MC is small.

[0087] exist Figure 9 The structure comprises a hafnium oxide metal oxide 221a_1 and an aluminum oxide film 221a_2 forming a barrier insulating film. However, the hafnium oxide metal oxide 221a_1 is very thin and is hardly recognized as a film. Therefore, it has... Figure 9 The threshold voltage ratio of the memory cell MC is composed of Figure 7 or Figure 8 The threshold voltage of the memory cell MC is greatly deflected. However, since the hafnium oxide of the metal oxide 221a_1 exists between the aluminum oxide film of the barrier insulating film 221a_2 and the covering insulating film 221, it has... Figure 9 The threshold voltage of the memory cell MC is related to the structure of the memory cell. Figure 6 Compared to the threshold voltage of the memory cell MC, the offset is smaller.

[0088] exist Figure 10 In its configuration, a laminated film comprising an insulating film 221, a barrier insulating film 221a_2, and a barrier film 21b is disposed between the charge trapping film 222 and the electrode film 21. No metal oxide 221a_1 is disposed. However, the electrode film 21 is made of tungsten, which is more difficult to oxidize than molybdenum. Therefore, Figure 10 The threshold voltage of the memory cell MC and Figures 6-9Compared to the threshold voltage of any memory cell MC in the memory, the offset becomes smaller. Furthermore, in Figure 11 In the middle, Figure 10 The IRDR offset formed by these values ​​is set to zero (reference value).

[0089] Thus, when the electrode film 21 is molybdenum, by placing a metal oxide 221a_1 between the charge trapping film 222 and the electrode film 21 to replace the aluminum oxide film blocking the insulating film 221a_2, or by placing the metal oxide 221a_1 together with the aluminum oxide film blocking the insulating film 221a_2, the IRDR offset can be reduced and the data retention characteristics improved. Furthermore, the same effect can be achieved with any tetravalent metal oxide among TiO2, ZrO2, HfO2, and RfO2 as the metal oxide 221a_1.

[0090] Figure 12 This is a graph representing the write saturation voltage. The vertical axis of the graph represents the write saturation voltage. The horizontal axis represents... Figures 6-10 Each component has its own structure. The write saturation voltage is the maximum value of the threshold voltage when data is written to the memory cell MC. When the write voltage applied to the word line WL (electrode film 21) increases, the threshold voltage of the memory cell MC with written data also increases accordingly. However, when the charge amount held in the charge trapping film 222 is saturated, even if the write voltage of the word line WL is increased, the threshold voltage of the memory cell MC will not rise further. Therefore, the threshold voltage of the memory cell MC with written data has a maximum value (peak). This maximum value of the threshold voltage of the memory cell MC is called the "write saturation voltage". For ease of data detection, a high write saturation voltage is preferred.

[0091] exist Figure 6 In this configuration, the aluminum oxide film blocking the insulating film 221a_2 allows oxygen to pass through during the annealing process described later, causing oxidation at the interface between the charge trapping film 222 and the covering insulating film 221, resulting in defects. Therefore, a large amount of charge can be retained at the interface between the charge trapping film 222 and the covering insulating film 221. As a result, the write saturation voltage becomes relatively high.

[0092] exist Figure 7 In its composition, the hafnium oxide of metal oxide 221a_1 minimizes oxygen permeation during the annealing process, thus minimizing defects at the interface between the charge trapping film 222 and the covering insulating film 221. Therefore, it possesses... Figure 7 The write saturation voltage ratio of the memory cell MC has Figure 6 The write saturation voltage of the memory cell MC is low.

[0093] exist Figure 8In its composition, hafnium oxide of metal oxide 221a_1 and aluminum oxide film of barrier insulating film 221a_2 are provided, thus, with Figure 7 Similarly, its structure minimizes oxygen permeability, resulting in fewer defects at the interface between the charge-trapping film 222 and the covering insulating film 221. Therefore, it possesses... Figure 8 The write saturation voltage of the memory cell MC is also higher than that of the one with Figure 6 The write saturation voltage of the memory cell MC, which is composed of [a specific type of cell], is low. It has [a specific characteristic]. Figure 8 The write saturation voltage of the memory cell MC is related to the Figure 7 The write saturation voltages of the memory cells MC are approximately equal.

[0094] exist Figure 9 The structure comprises a hafnium oxide metal oxide 221a_1 and an aluminum oxide film of a barrier insulating film 221a_2. Therefore, it has... Figure 9 The write saturation voltage ratio of the memory cell MC has Figure 6 The write saturation voltage of the memory cell MC is low. However, the hafnium oxide of metal oxide 221a_1 is very thin and is hardly recognized as a film. Therefore, it has... Figure 9 The write saturation voltage ratio of the memory cell MC has Figure 7 or Figure 8 The write saturation voltage of the memory cell MC is high.

[0095] exist Figure 10 In its composition, no metal oxide 221a_1 is provided, but the electrode film 21 is made of tungsten. Figure 10 The write saturation voltage of the memory cell MC and Figure 6 They are the same level (horizontal), compared to Figures 7-9 The write saturation voltage of any memory cell MC is large. This is because annealing is performed after the formation of the aluminum oxide film 221a_2 and before the formation of the barrier film 21b and the electrode film 21. During this annealing stage, Figure 10 Its composition has the same as Figure 6 With the same structure, the charge trapping film 222 is modified through this annealing process, determining the write saturation voltage. Therefore, Figure 10 The write saturation voltage of the memory cell MC becomes the same as Figure 6 Same level.

[0096] Thus, when the metal oxide 221a_1 is thick, oxygen does not pass through it much, and the charge trapping film 222 based on the annealing process is not modified. Consequently, when the metal oxide 221a_1 is thick, the write saturation voltage of the memory cell MC decreases. On the other hand, when the thickness or concentration of the metal oxide 221a_1 becomes thinner, oxygen passes through it to some extent, modifying the charge trapping film 222 based on the annealing process. Therefore, by thinning or diluting the thickness or concentration of the metal oxide 221a_1, the write saturation voltage of the memory cell MC is increased and improved. Furthermore, for the metal oxide 221a_1, the same effect can be obtained regardless of whether it is a tetravalent metal oxide such as TiO2, ZrO2, or RfO2, except for hafnium oxide (HfO2).

[0097] according to Figure 11 as well as Figure 12 By providing a metal oxide 221a_1 between the aluminum oxide film covering the insulating film 221 and the blocking insulating film 221a_2, the IRDR characteristics of the memory cell MC can be improved. On the other hand, since the write saturation voltage of the memory cell MC decreases when the metal oxide 221a_1 is too thick, therefore, as Figure 9 As such, it is preferable that the metal oxide 221a_1 film has a thin film thickness or a low concentration. Through... Figure 9 The configuration enables improvements in both IRDR characteristics and write saturation voltage.

[0098] Figure 13 It means to Figure 6 A cross-sectional view of a configuration example obtained by adding metal oxide 221a_3. In Figure 13 In this example, a laminated film comprising an insulating film 221, a barrier insulating film 221a_2, and a metal oxide film 221a_3 is disposed between the charge trapping film 222 and the electrode film 21. In this example, relative to... Figure 6 The metal oxide 221a_3 differs in that it is disposed between the barrier insulating film 221a_2 and the electrode film 21. The metal oxide 221a_3 is the same as the metal oxide 221a_1, and can be, for example, any tetravalent metal oxide selected from TiO2, ZrO2, HfO2, and RfO2. The metal oxide 221a_3, for example, has a film thickness of 1 nm and can be identified as a film. Figure 13 Other components can be combined with Figure 6 They have the same composition.

[0099] Figure 14 It means to Figure 9 A cross-sectional view of a configuration example obtained by adding metal oxide 221a_3. In Figure 14In this example, a laminated film covering insulating film 221, metal oxide 221a_1, barrier insulating film 221a_2, and metal oxide 221a_3 is disposed between charge trapping film 222 and electrode film 21. In this example, relative to Figure 9 The metal oxide 221a_3 is disposed at the interface between the barrier insulating film 221a_2 and the electrode film 21, which is different in this respect. The metal oxide 221a_3 is the same as the metal oxide 221a_1, and can be, for example, hafnium oxide (HfO2), or any other tetravalent metal oxide selected from TiO2, ZrO2, HfO2, and RfO2. The metal oxide 221a_3, for example, has a film thickness of 1 nm and can be identified as a film. That is, the metal oxide 221a_1 is lower in concentration than the metal oxide 221a_3, or thinner in thickness than the metal oxide 221a_3. Figure 14 Other components can be combined with Figure 9 They have the same composition.

[0100] Figure 15 This is a graph representing the erase saturation voltage. The vertical axis of the graph represents the threshold voltage (erase voltage) of the memory cell MC after erasure. The horizontal axis is the voltage Vera applied to the word line WL (electrode film 21) during the erase operation. The erase saturation voltage is the minimum threshold voltage of the memory cell MC when data has been erased. When the absolute value of the voltage Vera applied to the word line WL (electrode film 21) increases (increasing towards the negative voltage side), the threshold voltage of the memory cell MC that has had its data erased decreases accordingly. However, when all the charge in the charge trapping film 222 is removed, even if the absolute value of the voltage Vera of the word line WL further increases, the threshold voltage of the memory cell MC no longer decreases further. Therefore, the threshold voltage of the memory cell MC that has had its data erased has a minimum value (bottom). This minimum threshold voltage of the memory cell MC is called the "erasure saturation voltage". For ease of data detection, a low erase saturation voltage is preferred.

[0101] Figure 10 The erase voltage is represented by a graph with line L10. Defects with fixed charges are easily generated at the interface between the silicon oxide film covering the insulating film 221 and the aluminum oxide film blocking the insulating film 221a_2. Therefore, during the erase operation, electrons injected from the electrode film 21 to the charge trapping film 222 are trapped by these defects, and the erase saturation voltage deteriorates. As a result, Figure 10 The erase saturation voltage B10 shown is relatively high.

[0102] Figure 13 The erase voltage is represented in a graph by line L13. In this case, the erase saturation voltage B13 is higher than... Figure 10The erase saturation voltage of this structure is low. However, Figure 13 The structure also has an interface between the silicon oxide film covering the insulating film 221 and the aluminum oxide film blocking the insulating film 221a_2. Therefore, during the erasure operation, electrons injected from the electrode film 21 to the charge trapping film 222 are trapped by this defect, thus the erasure saturation voltage and Figure 14 The composition is worse compared to the previous one.

[0103] In contrast, Figure 14 The erase voltage is represented in a graph by line L14. In this case, the erase saturation voltage B14 is greater than... Figure 10 The erase saturation voltage of the structure is more than 2V lower than that of the structure. Figure 13 The erase saturation voltage is also about 0.8V lower. This is because the metal oxide 221a_1 disposed at the interface between the silicon oxide film covering the insulating film 221 and the aluminum oxide film blocking the insulating film 221a_2 suppresses the generation of defects at the interface.

[0104] By configuring the metal oxides 221a_1 and 221a_3 in this way, the erase saturation voltage can be significantly improved. Furthermore, as shown in the reference... Figure 12 As explained, the write saturation voltage deteriorates when the metal oxide 221a_1 is thick. Therefore, the thickness of the metal oxide 221a_1 is preferably as described in the reference. Figure 9 As explained, it is thin. Therefore, it is possible to increase the write saturation voltage and decrease the erase saturation voltage.

[0105] The annealing process used to modify the charge trapping film 222 is performed after the formation of the aluminum oxide film of the barrier insulating film 221a_2 and before the formation of the metal oxide 221a_3. Therefore, Figure 14 The composition of the write saturation voltage and Figure 9 They are roughly the same. Therefore, Figure 14 The structure is more advanced than the write saturation voltage. Figure 7 as well as Figure 8 More advantageous.

[0106] In addition, for Figure 14 The IRDR characteristics of the composition, due to the Figure 9 The composition includes the addition of metal oxide 221a_3, therefore, it is obviously more... Figure 9 The IRDR characteristics of the structure are improved. Therefore, considering the IRDR characteristics and write saturation voltage, then... Figure 14 The composition relative to Figure 9 The configuration is equally preferred or even better. As a result, from the viewpoint of IRDR characteristics, write saturation voltage, and erase saturation voltage, it can be said that... Figure 14 The optimal configuration is as follows. Furthermore, while the electrode film 21 is made of molybdenum, tungsten can also achieve the same effect.

[0107] According to the above records, such as Figure 9 As configured, by placing the metal oxide 221a_1 at the interface between the covering insulating film 221 and the blocking insulating film 221a_2, the IRDR characteristics, write saturation voltage and erase saturation voltage can be improved.

[0108] Moreover, such as Figure 14 As configured, by placing the metal oxide 221a_3 between the aluminum oxide film of the barrier insulating film 221a_2 and the electrode film 21, the IRDR characteristics and the erase saturation voltage can be further improved.

[0109] By reducing the erase saturation voltage, the operating voltage of the word line WL can be reduced. Therefore, the breakdown voltage between adjacent electrode films 21 in the Z direction can be reduced, thus allowing the thickness of the insulating film 22 in the Z direction to be thinner. For example, the thickness of the insulating film 22 in the Z direction can be made less than approximately 40 nm.

[0110] Next, the manufacturing method of the semiconductor memory device according to this embodiment will be described.

[0111] Figures 16-21 This is a cross-sectional view showing an example of the manufacturing process of the semiconductor memory device 1 according to this embodiment.

[0112] First, such as Figure 16 As shown, the stack 20 of the array chip 2 is formed by alternately stacking a material film 21a and an insulating film 22 in the -Z direction. For the material film 21a, a silicon nitride film is used, for example. For the insulating film 22, a silicon oxide film is used, for example.

[0113] Next, using photolithography and etching techniques, multiple memory vias MH are formed, penetrating the stack 20 in the Z direction. Then, as... Figure 17 As shown, columnar bodies CL are formed within multiple storage vias MH. The columnar bodies CL are formed by depositing a covering insulating film 221, a charge trapping film 222, a tunnel insulating film 223, and a semiconductor body 210 on the sidewalls of the stack 20 within the storage vias MH.

[0114] Next, photolithography and etching techniques are used to form the laminate 20. Figure 2 or Figure 5 The slit ST is shown. The slit ST is configured to penetrate the laminate 20 in the Z direction.

[0115] Next, the material film 21a is removed via wet etching through the slit ST. Thus, as... Figure 18 As shown, a space C is formed between adjacent insulating films 22 in the Z direction (where the material film 21a is located).

[0116] Figures 19-21 This represents an enlarged cross-section of part of space C.

[0117] Using ALD (Atomic Layer Deposition), metal oxide 221a_1 is deposited on the space C and the inner wall of the slit ST via a gap ST. Metal oxide 221a_1 is introduced onto the sides of the columnar bodies CL exposed within the space C and the slit ST, and onto the surface of the insulating film 22. Metal oxide 221a_1 can be, for example, any tetravalent metal oxide selected from TiO2, ZrO2, HfO2, and RfO2. Metal oxide 221a_1 has a concentration or thickness (e.g., 0.1 nm) that is not considered a film.

[0118] Next, using the ALD method, an aluminum oxide film of the barrier insulating film 221a_2 is deposited on the space C and the inner wall of the slit ST via the gap ST. The thickness of the aluminum oxide film of the barrier insulating film 221a_2 is, for example, about 2.7 nm.

[0119] Next, to modify the charge trapping film 222, the laminate 20 and the columnar body CL are annealed. The annealing temperature is, for example, 240 to 250 degrees Celsius. Through the annealing process, oxygen passes through the aluminum oxide film that blocks the insulating film 221a_2 and the hafnium oxide film that blocks the metal oxide 221a_1. Furthermore, while the hafnium oxide film is more difficult for oxygen to pass through than the aluminum oxide film, it is thin enough not to be recognized as a film, thus oxygen can pass through the metal oxide 221a_1. As a result, oxygen can oxidize the interface between the charge trapping film 222 and the covering insulating film 221, creating defects. Consequently, the write saturation voltage can be increased.

[0120] Furthermore, the concentration of metal oxide 221a_1 is maximized at the interface between the covering insulating film 221 and the barrier insulating film 221a_2. Through the annealing process, metal oxide 221a_1 diffuses from the interface between the barrier insulating film 221a_2 and the covering insulating film 221, and from the interface between the barrier insulating film 221a_2 and the insulating film 22. The diffusion of metal oxide 221a_1 from the interface between the barrier insulating film 221a_2 and the covering insulating film 221 or the insulating film 22 is, for example, in the range of 0.1 nm to 0.3 nm. Metal oxide 221a_1 can exist as a film, or it can be detected as a component without being identified as a film.

[0121] Next, as Figure 21 As shown, as the material of electrode film 21, metal materials such as molybdenum and tungsten are deposited on the inner wall of space C.

[0122] Next, an insulating film 101, such as a silicon oxide film, is formed on the inner wall of the gap ST.

[0123] Next, a metal film of molybdenum, tungsten, or the like is embedded inside the insulating film 101 within the gap ST. Thus, in Figure 5 Source wiring LI is formed within the gap ST shown, resulting in Figure 3 The structure shown.

[0124] Subsequently, contact portions and multiple wiring layers are formed, thus completing the semiconductor memory device 1 of this embodiment. In this case, the following is obtained: Figure 9 The structure shown.

[0125] In addition, in order to form Figure 14 The structure shown involves forming an aluminum oxide film of barrier insulating film 221a_2 and performing an annealing process, then depositing metal oxide 221a_3 onto the inner walls of space C and slit ST using methods such as ALD. The metal oxide 221a_3 is formed on the aluminum oxide film of barrier insulating film 221a_2 within space C and slit ST. The metal oxide 221a_3, like the metal oxide 221a_1, can be, for example, any tetravalent metal oxide selected from TiO2, ZrO2, HfO2, and RfO2. Subsequently, an electrode film 21 is formed to obtain… Figure 14 The structure shown.

[0126] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents.

Claims

1. A semiconductor memory device comprising: A laminate consisting of multiple electrode films and multiple first insulating films alternately stacked in a first direction; A columnar body is provided such that it penetrates the laminate in the first direction; An aluminum oxide film is disposed between the columnar body and the electrode film; and The first tetravalent metal oxide exists at the interface between the columnar body and the aluminum oxide film.

2. The semiconductor memory device according to claim 1, The columnar body includes: A semiconductor layer is provided such that it extends through the laminate in the first direction; A second insulating film is disposed between the semiconductor layer and the laminate; A third insulating film is disposed between the second insulating film and the semiconductor layer; as well as A fourth insulating film is disposed between the third insulating film and the semiconductor layer. The first tetravalent metal oxide is present at the interface between the aluminum oxide film and the second insulating film.

3. The semiconductor memory device according to claim 2, The concentration of the first tetravalent metal oxide is maximized at the interface between the aluminum oxide film and the second insulating film.

4. The semiconductor memory device according to claim 3, The concentration of the first tetravalent metal oxide decreases from the interface between the aluminum oxide film and the second insulating film toward the electrode film.

5. The semiconductor memory device according to claim 2, The first tetravalent metal oxide exists in a second direction, intersecting the interface between the aluminum oxide film and the second insulating film, within a range of 0.1 nm to 0.3 nm.

6. The semiconductor memory device according to any one of claims 1 to 5, The semiconductor memory device also includes a second tetravalent metal oxide present at the interface between the aluminum oxide film and the electrode film.

7. The semiconductor memory device according to claim 1, The first tetravalent metal oxide is any one of TiO2, ZrO2, HfO2, and RfO2.

8. A method for manufacturing a semiconductor memory device, comprising: Multiple material films and multiple first insulating films are alternately stacked in a first direction to form a laminate; Forming a columnar body through which the laminated body extends in the first direction; Remove the plurality of material films; A first tetravalent metal oxide is introduced into the side of the columnar body exposed after the removal of the plurality of material films; An aluminum oxide film is formed on the side surface of the columnar body; The laminate is subjected to heat treatment; and An electrode film is formed in the space after the removal of the plurality of material films.

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