Semiconductor memory device

Abstract

The invention provides a semiconductor memory device capable of simplifying wiring and reducing power consumption. A semiconductor memory device according to an embodiment includes: a plurality of first data lines and a plurality of first control lines for writing data; a plurality of second data lines and a plurality of second control lines for reading data; and a plurality of memory cells. The first drive line is provided common to the plurality of first control lines and the plurality of second control lines, and transmits a selection voltage for writing data. The plurality of fourth transistors are connected between the plurality of first control lines and the first drive line. The plurality of fifth transistors are connected between the plurality of second control lines and the first drive line. The plurality of third control lines are connected to the gates of the plurality of fourth transistors, respectively. A plurality of fourth control lines are connected to gates of the plurality of fifth transistors, respectively.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device. Background Technology

[0002] Gain-cell memory reads data by amplifying the accumulated charge at a sensing node using transistors. Gain-cell memory is divided into read and write ports, with separate bit lines and word lines for each. This results in a larger number of wires and a more complex wiring structure. Furthermore, the increased number of wires also leads to a greater number of drivers and increased power consumption. Summary of the Invention

[0003] The present invention provides a semiconductor memory device that simplifies wiring and reduces power consumption.

[0004] The semiconductor memory device of this embodiment includes: a plurality of first data lines and a plurality of first control lines for writing data; a plurality of second data lines and a plurality of second control lines for reading data; and a plurality of memory cells. Each memory cell includes: a first transistor, whose gate is connected to any one of the plurality of first control lines and one end is connected to any one of the plurality of first data lines; a second transistor, whose gate is connected to any one of the plurality of second control lines and one end is connected to any one of the plurality of second data lines; and a third transistor, whose gate is connected to the other end of the first transistor, which stores data from the first data lines and whose one end is connected to the other end of the second transistor, thus being in a conduction state corresponding to the data. A first drive line is disposed commonly relative to the plurality of first control lines and the plurality of second control lines, and transmits a selection voltage for writing data. A plurality of fourth transistors are connected between the plurality of first control lines and the first drive lines. A plurality of fifth transistors are connected between the plurality of second control lines and the first drive lines. The plurality of third control lines are each connected to the gate of the plurality of fourth transistors. Multiple fourth control lines are connected to the gates of multiple fifth transistors respectively. Attached Figure Description

[0005] Figure 1 This is a circuit diagram illustrating a configuration example of a single memory cell according to the first embodiment.

[0006] Figure 2 This is a perspective view showing a configuration example of the gain unit memory according to the first embodiment.

[0007] Figure 3 This is a conceptual diagram illustrating the read operation of the gain unit memory in the first embodiment.

[0008] Figure 4 This is a timing diagram illustrating an operational example of the gain unit memory in the first embodiment.

[0009] Figure 5 This is a perspective view showing a configuration example of the gain unit memory according to the second embodiment.

[0010] Figure 6 This is a conceptual diagram illustrating the read operation of the gain unit memory in the second embodiment.

[0011] Figure 7 This is a perspective view showing a configuration example of the gain unit memory in the third embodiment.

[0012] Figure 8 This is a perspective view showing a configuration example of the gain unit memory in the fourth embodiment.

[0013] Figure 9 This is a perspective view showing a configuration example of the gain unit memory in the fifth embodiment. Detailed Implementation

[0014] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments are not intended to limit the present invention. The drawings are schematic or conceptual. In the description and drawings, the same elements are labeled with the same symbols.

[0015] (First Embodiment)

[0016] Figure 1 This is a circuit diagram illustrating a configuration example of a single memory cell according to the first embodiment. The memory cell MC of the gain unit memory includes three transistors MW1, MR1, and MR2. Transistors MW1, MR1, and MR2 include, for example, n-type OSFETs (Oxide Semiconductor Field Effect Transistors).

[0017] The gate of transistor MW1, acting as the first transistor, is connected to the write word line WWL, which serves as the first control line. One electrode of transistor MW1 is connected to the write bit line WBL, which serves as the first data line. The other electrode of transistor MW1 is connected to the gate of transistor MR1. The electrodes on one side and the other side of transistor MW1 function as source or drain electrodes depending on the voltage supplied to transistor MW1. Transistor MW1 receives control from the write word line WWL and connects the write bit line WBL to the gate of transistor MR1 (hereinafter also referred to as the sense node SN), which functions as a sense node SN. When transistor MW1 is in the ON state, the voltage of the write bit line WBL is transmitted to the sense node SN. When transistor MW1 is in the OFF state, the voltage of the sense node SN is stored. In this way, transistor MW1 can write the voltage (data) from the write bit line WBL to the sense node SN, or store the written voltage (data) in the sense node SN.

[0018] The gate of transistor MR1, acting as the third transistor, is connected to the electrode on the other side of transistor MW1, functioning as a sensing node SN. One electrode of transistor MR1 (e.g., the source) is connected to a low-voltage source VSS. The other electrode of transistor MR1 (e.g., the drain) is connected to the electrode on one side of transistor MR2. Transistor MR1 is in an ON state corresponding to the voltage (i.e., data) of the sensing node SN. For example, when a high-level voltage (e.g., data "1") is stored in the sensing node SN, transistor MR1 is ON. When a low-level voltage (e.g., data "0") is stored in the sensing node SN, transistor MR1 is OFF.

[0019] The gate of transistor MR2, acting as the second transistor, is connected to the read word line RWL, which serves as the second control line. One electrode of transistor MR2 is connected to the drain of transistor MR1. The other electrode of transistor MR2 is connected to the read bit line RBL, which serves as the second data line. The electrodes on one side and the other side of transistor MR2 can function as source or drain electrodes depending on the voltage supplied to transistor MR2. Transistor MR2 receives control from the read word line RWL and connects the read bit line RBL to the drain of transistor MR1. Transistor MR1 enters a state (on or off) corresponding to the voltage (data) stored at the sensing node SN. If the read bit line RBL is connected to transistor MR1 when transistor MR2 is on, the charge from the read bit line RBL flows to the low voltage source VSS depending on the state of transistor MR1. When transistor MR1 is on, the charge from the read bit line RBL flows to the low voltage source VSS, and the voltage of the read bit line RBL decreases. When transistor MR1 is off, almost no charge flows from the read bit line RBL to the low voltage source VSS, and the voltage of the read bit line RBL is maintained at a high level. Thus, the voltage based on the data stored at the sensing node SN is transferred to the read bit line RBL.

[0020] The sense amplifier SA, serving as the detection circuit, is connected to the write bit line WBL and the read bit line RBL. The sense amplifier SA latches write data from the outside by applying a voltage corresponding to the write data to the write bit line WBL. Furthermore, the sense amplifier SA detects read data based on the voltage of the read bit line RBL and latches the read data. The read data latched by the sense amplifier SA is then transmitted externally. The sense amplifier SA also pre-charges the write bit line WBL and the read bit line RBL.

[0021] The controller CTL is connected to the write word line WWL and the read word line RWL, and controls the voltage of the write word line WWL and the read word line RWL.

[0022] Write word line (WWL) and write bit line (WBL) are the wiring lines used for writing data. Read word line (RWL) and read bit line (RBL) are the wiring lines used for reading data. Thus, in gain-cell memory, data writing and reading use different word lines and bit lines. Therefore, gain-cell memory can read data while maintaining the data at the sensing node (SN) (non-destructive reading). Furthermore, each memory cell (MC) contains three transistors (MW1, MR1, MR2) and does not have the capacitors that are difficult to miniaturize in DRAM (Dynamic Random Access Memory). Therefore, gain-cell memory offers superior miniaturization capabilities.

[0023] Figure 2 This is a perspective view showing a configuration example of the gain cell memory according to the first embodiment. The gain cell memory of this embodiment includes a three-dimensional memory cell array in which a plurality of memory cells MC are arranged in three dimensions. The plurality of memory cells MC are arranged in a matrix shape having a plurality of rows and a plurality of columns. Rows are the arrangement of the memory cells MC in the X direction. Columns are the arrangement of the memory cells MC in the Z direction. Furthermore, the matrix arrangement of the memory cells MC is in the Y direction. Thus, the memory cell array MCA becomes a three-dimensional array in which a plurality of memory cells MC are arranged in three dimensions. Furthermore, the number of rows, columns, and matrices of the memory cells MC are not particularly limited.

[0024] Multiple write word lines (WWL), serving as multiple first control lines, are configured to correspond to multiple rows of the memory cell MC, respectively. Multiple read word lines (RWL), serving as multiple second control lines, are also configured to correspond to multiple rows of the memory cell MC, respectively. The write word lines (WWL) are used for writing data and extend in the X direction. The read word lines (RWL) are used for reading data and extend in the X direction.

[0025] The drive line WDRV, serving as the first drive line, is configured to be common to the multiple write word lines WWL and multiple read word lines RWL arranged in the Y direction. The drive line WDRV transmits the selection voltage for writing data. The multiple drive lines WDRV extend in the Y direction and are arranged in the Z direction.

[0026] Multiple transistors WT1, acting as multiple fourth transistors, are connected between multiple write word lines WWL and drive lines WDRV. One electrode of each transistor WT1 is connected to one of the multiple write word lines WWL. The other electrode of the multiple transistors WT1 arranged in the Y direction is connected to one drive line WDRV. Furthermore, one electrode and the other electrode of each of transistors WT1, RT1, WT2, WTbl, and RTbl can function as source or drain electrodes depending on the voltage supplied to them.

[0027] Multiple transistors RT1, acting as multiple fifth transistors, are connected between multiple read word lines RWL and drive line WDRV. One electrode of each transistor RT1 is connected to one of the read word lines RWL. The other electrode of the multiple transistors RT1 arranged in the Y direction is commonly connected to one drive line WDRV. Multiple transistors WT1 and RT1 arranged in the Y direction are also commonly connected to one drive line WDRV.

[0028] The write master word line WMWL, serving as the third control line, is commonly connected to the gates of multiple transistors WT1 arranged in the Z direction. That is, the write master word line WMWL is commonly disposed on multiple write word lines WWL arranged in the Z direction. The multiple write master word lines WMWL extend in the Z direction and are arranged in the Y direction. The write master word line WMWL selectively turns on the multiple transistors WT1 connected to it, connecting the drive line WDRV to the corresponding write word line WWL. The multiple write master word lines WMWL arranged in the Y direction are driven independently. Therefore, Figure 2 The transistor WT1 shown is controlled to be either on or off depending on the multiple rows arranged in the Z direction.

[0029] The read master word line RMWL, serving as the fourth control line, is commonly connected to the gates of multiple transistors RT1 arranged in the Z direction. That is, the read master word line RMWL is commonly provided on the multiple read word lines RWL arranged in the Z direction. The multiple read master word lines RMWL extend in the Z direction and are arranged in the Y direction. The common connection of the multiple read master word lines RMWL turns on the multiple transistors RT1 corresponding to these read master word lines RMWL, and connects the drive line WDRV to the multiple read word lines RWL arranged in both the Z and Y directions. The multiple read master word lines RMWL arranged in the Y direction are commonly connected and driven uniformly. Therefore, Figure 2 The transistors RT1 arranged in the Y and Z directions are simultaneously controlled to be either on or off.

[0030] The non-write voltage line VUW, serving as the second drive line, is configured commonly relative to the multiple write word lines WWL arranged in the Y direction. The non-write voltage line VUW transmits a non-selection voltage for which no data is written. The multiple non-write voltage lines VUW extend in the Y direction and are arranged in the Z direction.

[0031] Multiple transistors WT2, acting as multiple seventh transistors, are connected between multiple write word lines WWL and non-write voltage lines VUW. One electrode of each transistor WT2 is connected to one of the write word lines WWL. The other electrode of each transistor WT2, arranged in the Y direction, is connected to a single non-write voltage line VUW. Conversely, multiple read word lines RWL are electrically isolated from the multiple non-write voltage lines VUW. Furthermore, when the non-selection voltage is fixed, the multiple non-write voltage lines VUW can also be short-circuited as a single drive line.

[0032] The non-select main word line bWMWL is connected to the gates of multiple transistors WT2 arranged in the Z direction. Multiple non-select main word lines bWMWL extend in the Z direction and are arranged in the Y direction. The non-select main word line bWMWL turns on the multiple transistors WT2 connected to the write word line WWL corresponding to the memory cell MC that is not being written to, and connects the non-write voltage line VUW to the corresponding write word line WWL.

[0033] The multiple write bit lines (WBL), which are multiple first data lines, are configured to correspond to multiple columns of the memory cell (MC). Similarly, the multiple read bit lines (RBL), which are multiple second data lines, are also configured to correspond to multiple columns of the memory cell (MC). Furthermore, in... Figure 2 The diagram only shows one write bit line (WBL) and one read bit line (RBL). The write bit line (WBL) is used for writing data and extends in the Z direction. The read bit line (RBL) is used for reading data and extends in the Z direction. The read bit line (RBL), write bit line (WBL), write main word line (WMWL), read main word line (RMWL), and non-select main word line (bWMWL) all extend in the Z direction.

[0034] The write global bit line WGBL, which serves as the third data line, is commonly set among multiple write bit lines WBL arranged in the Y direction. These multiple write global bit lines WGBL extend in the Y direction and are arranged in the X direction. Additionally, in Figure 2 In the diagram, only one write global bit line WGBL is shown. The write global bit line WGBL is connected to a write bit line WBL selected from the plurality of write bit lines WBL corresponding to this write global bit line WGBL, and data from the sense amplifier SA is transmitted to this selected write bit line WBL.

[0035] The read global bit lines RGBL, which serve as the fourth data line, are commonly set on multiple read bit lines RBL arranged in the Y direction. These multiple read global bit lines RGBL extend in the Y direction and are arranged in the X direction. Additionally, in Figure 2 In the diagram, only one read global bit line RGBL is shown. The read global bit line RGBL is connected to a read bit line RBL selected from the plurality of read bit lines RBL corresponding to the read global bit line RGBL, and data from the selected read bit line RBL is transmitted to the sense amplifier SA.

[0036] Multiple transistors WTbl are connected between multiple write bit lines WBL and a write global bit line WGBL. One electrode of each WTbl is connected to one of the write bit lines WBL. The other electrode of the multiple WTbl transistors arranged in the Y direction is commonly connected to one write global bit line WGBL. The gates of the multiple WTbl transistors arranged in the X direction are commonly connected to a write select line WSEL. The multiple write select lines WSEL extend in the X direction and are arranged in the Y direction.

[0037] During the write operation, one of the multiple write select lines WSEL is selectively driven. Multiple transistors WTbl connected to the selected write select line WSEL become active, electrically connecting the corresponding write bit line WBL to the write global bit line WGBL. Thus, the multiple transistors WTbl connected to the selected write select line WSEL transmit data from the sense amplifier SA from the corresponding write global bit line WGBL to the write bit line WBL.

[0038] Taking into account the capacitance of the write bit line WBL, transistor WTbl is preferably provided to achieve high-speed operation of the write bit line WBL. However, if the operation speed is not a concern, transistor WTbl can be omitted.

[0039] Multiple transistors RTbl, acting as multiple sixth transistors, are connected between multiple read bit lines RBL and read global bit line RGBL. One electrode of each RTbl is connected to one of the read bit lines RBL. The other electrode of the multiple RTbls arranged in the Y direction is commonly connected to one read global bit line RGBL. The gates of the multiple RTbls arranged in the X direction are commonly connected to the read select line RSEL. The multiple read select lines RSEL extend in the X direction and are arranged in the Y direction.

[0040] During the read operation, one of the multiple read select lines RSEL is selectively driven. Multiple transistors RTbl connected to the selected read select line RSEL become active, electrically connecting the corresponding read bit line RBL to the read global bit line RGBL. Thus, the multiple transistors RTbl connected to the selected read select line RSEL transfer data from the memory cell MC from the corresponding read bit line RBL to the read global bit line RGBL.

[0041] Multiple memory cells (MCs) are configured to correspond to the following intersections: the intersection of a pair of write word lines (WWL) and read word lines (RWL) adjacent to each other in the Y direction, and the intersection of a pair of write bit lines (WBL) and read bit lines (RBL) adjacent to each other in the X direction. Therefore, in this embodiment, when writing data, the memory can write data to one memory cell (MC) by selecting one write word line (WWL) and one write bit line (WBL). Furthermore, when reading data, the memory can read data from one memory cell (MC) by selecting one read word line (RWL) and one read bit line (RBL).

[0042] A layer comprising multiple write word lines (WWL), multiple read word lines (RWL), and multiple memory cells (MC) corresponding to one drive line (WDRV) is considered as one component. In this case, one write master word line (WMWL) is connected to the gates of multiple transistors (WT1) corresponding to the multiple components. Furthermore, one read master word line (RMWL) is connected to the gates of multiple transistors (RT1) corresponding to the multiple components. Further, one non-select master word line (bWMWL) is connected to the gates of multiple transistors (WT2) corresponding to the multiple components. One write master word line (WMWL) is commonly located on the multiple write word lines (WWL) corresponding to the multiple components. One read master word line (RMWL) is commonly located on the multiple read word lines (RWL) corresponding to the multiple components.

[0043] One end of the write word line WWL is connected to the drive line WDRV via transistor WT1, and the other end is connected to the non-write voltage line VUW via transistor WT2. On the other hand, one end of the read word line RWL is connected to the drive line WDRV via transistor RT1, and the other end is not connected to any transistor or drive line.

[0044] Figure 3 This is a conceptual diagram illustrating the read operation of the gain unit memory in the first embodiment. Figure 3 In this context, we select the configuration related to one read global bit line (RGBL) associated with the read operation. In reality, multiple read global bit lines (RGBL) arranged in the X direction simultaneously transmit data from their respective corresponding memory cells (MC). The following refers to... Figure 2 and Figure 3 The reading action is explained.

[0045] During the read operation, the read master word line RMWL is initiated, and multiple transistors RT1 sharing the read master word line RMWL become ON. Figure 2 and Figure 3 In the middle, all transistors RT1 are turned on, driving line WDRV. <0> ~WDRV <3> Connect to multiple read word lines (RWL) of the corresponding components (layers).

[0046] The controller CTL selectively selects one drive line WDRV (e.g., WDLV) from multiple drive lines WDRV. <0> This drives the selected drive line WDRV. <0> The corresponding component (e.g., Figure 2 The bottommost layer is selected. That is, the layer located at the same level as the drive line WDRV. <0> The multiple read word lines RWLsel on the lowest layer are connected and a high-level voltage is applied for reading. This causes the read word lines located at... Figure 2 The data of multiple memory cells MC connected to the multiple read word lines RWLsel at the lowest level are transmitted to the multiple read bit lines RBL respectively.

[0047] In addition, the controller CTL selection Figure 2 One of the multiple read select lines RSEL shown turns on the multiple transistors RTbl connected to the selected read select line RSEL. This connects the multiple read bit lines RBL corresponding to the selected read select line RSEL to their respective read global bit lines RGBL. Consequently, data from the multiple column selection memory cells MCsel is transmitted via their respective read global bit lines RGBL and detected by the sense amplifier SA.

[0048] Figure 3 The image shows a selected read bit line RBLsel and a corresponding global read bit line RGBL. Therefore, in... Figure 3 In this configuration, one read bit line RBLsel, selected from multiple read bit lines RBL, is connected to one global read bit line RGBL. Thus, data from the selected memory cell MCsel is transmitted via the global read bit line RGBL and detected using a sense amplifier SA.

[0049] On the other hand, Figure 3 In this configuration, although the non-selected read bit lines RBLsel (excluding RBLsel) transmit data from memory cells MC, the transistors RTbl corresponding to these non-selected read bit lines RBLsel are disconnected. Therefore, data transmitted to the non-selected read bit lines RBLsel (excluding RBLsel) will not be transmitted to the global read bit line RGBL, preventing data collisions. Furthermore, the gain cell memory enables non-destructive data reading. Therefore, even if data from memory cell MC is transmitted to the non-selected read bit lines RBLsel, there is no problem.

[0050] Figure 4 This is a timing diagram illustrating an operational example of the gain unit memory in the first embodiment. Figure 4The write operation is illustrated. During the write operation, the controller CTL temporarily reads data into the sense amplifier SA, updates the data using the sense amplifier SA, and then writes the updated data back to the memory cell MC. Additionally, the drive line WDRV is selectively configured here. <0> Drive it.

[0051] For example, after the controller CTL receives the activation instruction ACT as instruction CMD at time t0, it starts reading the master word line RMWL. Therefore, the selected drive line (e.g., WDRV) <0> The read word line RWL of the selected drive line is connected to the corresponding component (e.g., the lowest layer). The read bit line RBL reads the data of the memory cell MC corresponding to the selected drive line. At this time, all read bit lines RBL contained in the selected component transmit the data of the memory cell MC to the transistor RTbl.

[0052] In addition, the read selection line RSEL is started at t0. <0> Therefore, the controller CTL selects the same read selection line RSEL at the same time. <0> Connected (arranged in) Figure 2 Multiple transistors RTbl in the X direction (row direction) are driven. This is in conjunction with the read select line RSEL. <0> The multiple read bit lines RBL of the connected columns transmit data to the read global bit line RGBL.

[0053] Next, the data is updated using the sensing amplifier SA.

[0054] Subsequently, after receiving the write command WRT at time t1, the controller CTL initiates the write selection line WSEL. <0> Therefore, the controller CTL transmits data to the write select line WSEL. <0> Multiple write bit lines WBL are connected to write data to the memory cell MC in the selected component. Thus, in the selected component (e.g., the lowest level), data is written to the shared read select line RSEL. <0> and write select line WSEL <0> In the same storage unit MC.

[0055] After receiving the precharge command PRE at time t2, the controller CTL performs precharge by reading bit line RBL and writing bit line WBL.

[0056] Similarly, when the controller CTL starts reading the main word line RMWL during times t3 to t5, it also starts reading the select line RSEL. <1> Then, the write selection line WSEL is started. <1> Therefore, the controller CTL reads the selection line RSEL from the shared library among the selected components. <1> and write select line WSEL <1> The storage unit MC temporarily reads data and writes the data back to the same storage unit MC.

[0057] Similarly, when the controller CTL starts reading the main word line RMWL during times t6 to t8, it also starts reading the selection line RSEL. <2> Then, the write selection line WSEL is started. <2> Therefore, the controller CTL reads the selection line RSEL from the shared library among the selected components. <2> and write select line WSEL <2> The storage unit MC temporarily reads data and writes the data back to the same storage unit MC.

[0058] In summary, when the controller CTL initiates the read master word line RMWL, it also initiates the read select line RSEL. (i is an integer greater than or equal to 0), then start writing to the select line WSEL. Therefore, the controller CTL reads the selection line RSEL from the shared selection line of the selected component. and write select line WSEL The storage unit MC temporarily reads data and writes the data back to the same storage unit MC.

[0059] In this way, the controller CTL can sequentially activate the read select line RSEL after the read master word line RMWL has been activated. and write select line WSEL Therefore, it is unnecessary to start reading the main word line RMWL every time the read select line RSEL and write select line WSEL are started, thus reducing the time required to start reading the main word line RMWL. Additionally, starting the read select line RSEL... and write select line WSEL The order is not limited to the example given, and can be any other order.

[0060] In the reading action, the following was omitted. Figure 4 Write operations (e.g., t1~t2, t4~t5, t7~t8), other operations and Figure 4 The actions shown are the same. Therefore, in the read operation, it is not necessary to start the read main word line RMWL every time the read selection line RSEL is started, which can shorten the time required to start the read main word line RMWL.

[0061] Thus, in this embodiment, the controller CTL selectively drives one drive line (e.g., WDRV). <0> Driven by ) and selecting 1 component (e.g., Figure 2 (The lowest layer). At this time, multiple read bit lines RBL transmit data from multiple memory cells MC located in the selection component. Further, the controller CTL selects one read select line RSEL, turning on multiple transistors RTbl corresponding to one read word line RWL in the selection component. Thus, data is transmitted from the multiple read bit lines RBL corresponding to one read word line RWL in the selection component to their respective read global bit lines RGBL. Therefore, even if the other end of the read word line RWL is not connected to a transistor or drive line, the multiple read global bit lines RGBL can still transmit data from the selected memory cells MC.

[0062] Furthermore, according to this embodiment, the drive line WDRV is provided in a common manner relative to the write word line WWL and the read word line RWL. Additionally, multiple read master word lines RMWL are provided in a common manner. Furthermore, no non-read word lines or transistors are provided at the other end of the read word line RWL. Therefore, not only can non-destructive reading be performed, but wiring is also simplified. With simplified wiring, the number of drivers for driving the wiring voltage is reduced, and power consumption is also reduced.

[0063] In this embodiment, since multiple read main word lines (RMWLs) are set in a common manner, the read bit line (RBL) connected to the read global bit line (RGBL) is selected to choose the read word line (RWL). In this case, when there are many row addresses that require selecting multiple adjacent read word lines (RWLs), only the read bit line (RBL) needs to be selected, without driving multiple adjacent read word lines (RWLs). This reduces the proximity effect of the read word lines (RWLs).

[0064] (Second Implementation)

[0065] Figure 5 This is a perspective view showing a configuration example of the gain cell memory according to the second embodiment. According to the second embodiment, the global read bit line RGBL is commonly connected to a plurality of corresponding read bit lines RBL. No transistor RTbl is disposed between the plurality of read bit lines RBL and the global read bit line RGBL.

[0066] On the other hand, multiple transistors RT2, which are multiple eighth transistors, are connected between multiple read word lines RWL and non-write voltage lines VUW. That is, the other ends of the multiple read word lines RWL are connected to the non-write voltage lines VUW via the multiple transistors RT2. One electrode of each of the multiple transistors RT2 is connected to the multiple read word lines RWL. The other electrode of each of the multiple transistors RT2 is connected to the reference voltage line VUW. Furthermore, in the second embodiment, VUW is also used as a reference voltage source for the read operation, and is therefore called the reference voltage line. The gates of the multiple transistors RT2 are connected to the main read word line bRMWL. Additionally, the electrodes on one side and the other side of each transistor RT2 can function as source electrodes or drain electrodes depending on the voltage supplied to the transistor RT2.

[0067] The read master word line bRMWL is connected to the gates of multiple transistors RT2 arranged in the Z direction. These read master word lines bRMWL extend in the Z direction and are arranged in the Y direction. Each read master word line bRMWL turns on the corresponding transistors RT2, connecting the reference voltage line VUW to the multiple read word lines RWL arranged in the Z direction. The controller CTL can independently drive each read master word line bRMWL according to the address.

[0068] Furthermore, in the second embodiment, the multiple read master word lines RMWL arranged in the Y direction are electrically isolated instead of short-circuited. The controller CTL can drive the multiple read master word lines RMWL independently according to the address. The controller CTL selectively drives the line pairs of read master word lines RMWL and bRMWL located on both sides of the multiple read master word lines RWL in the selected row. Among them, the read master word lines RMWL and bRMWL transmit control signals with opposite logic. Therefore, when one of the transistors RT1 and RT2 is in the on state, the other transistor is in the off state. Thus, the read word line RWL selected for reading is connected to the drive line WDRV, and the unselected read word line RWL is connected to the reference voltage line VUW.

[0069] The other configurations of the second embodiment can be the same as those of the first embodiment.

[0070] Figure 6 This is a conceptual diagram illustrating the read operation of the gain unit memory in the second embodiment. Figure 6 In this context, we select the configuration related to one read global bit line (RGBL) associated with the read operation. In reality, multiple read global bit lines (RGBL) arranged in the X direction simultaneously transmit data from their respective corresponding memory cells (MC). The following refers to... Figure 5 and Figure 6 The reading action is explained.

[0071] During the read operation, the read master word line RMWL is activated, turning on the multiple transistors RT1 that share the read master word line RMWL. In the second embodiment, although the read master word line RMWL is connected to the gates of the multiple transistors RT1 arranged in the Z direction, the multiple read master word lines RMWL arranged in the Y direction are electrically isolated from each other. The same applies to the read master word line bRMWL; that is, although it is connected to the gates of the multiple transistors RT2 arranged in the Z direction, the multiple read master word lines bRMWL arranged in the Y direction are electrically isolated from each other. Therefore, the controller CTL can selectively drive one of the wire pairs of the multiple read master word lines RMWL and bRMWL extending in the Z direction. The wire pairs of the read master word lines RMWL and bRMWL are located on both sides of the multiple read word lines RWL arranged in the Z direction, sharing these multiple read word lines RWL.

[0072] The controller CTL selectively selects one drive line WDRV (e.g., WDLV) from multiple drive lines WDRV. <0> This drives the selected drive line WDRV. <0> The corresponding component (e.g., Figure 5 The bottommost layer is selected. That is, the layer located at the same level as the drive line WDRV. <0> The multiple transistors RT1 at the bottom layer of the connection are subjected to a high-level voltage for reading.

[0073] In addition, such as Figure 6 As shown, the controller CTL, for example, selectively reads the main word line RMWL. <0> bRMWL <0> The line pairs are driven. That is, the main word line RMWL is started. <0> This turns the corresponding transistor RT1 on. Stop reading the main word line bRMWL. <0> This switches the corresponding transistor RT2 to the off state. Thus, selectively switching the transistor located on the read main word line RMWL... <0> bRMWL <0> Multiple read word lines RWL and drive lines WDRV between line pairs <0> ~WDRV <3> Connect. Here, select the drive line WDRV. <0> Transmits a high-level voltage for reading; other non-selected drive lines WDRV <1> ~WDRV <3> A low-level voltage is transmitted for non-read operations. Therefore, the main word line RMWL is used for reading. <0> bRMWL <0> Multiple read word lines RWL between line pairs and drive line WDRV <0> The selected read word line RWLsel transmits a high-level voltage for reading. Data from the selected memory cell MCsel, connected to this selected read word line RWLsel, is transmitted to the read global bit line RGBL via the read bit line RBL. The same reading operation is performed for the other columns, and the data transmitted to the read global bit line RGBL for each column is detected using the corresponding sense amplifier SA.

[0074] On the other hand, the controller CTL, for example, stops reading the master word line RMWL. <1> ~RMWL <3> Start reading the main word line bRMWL <1> ~bRMWL <3> Therefore, the RMWL located on the main word line will be read. <1> ~RMWL <3> bRMWL <1> ~bRMWL <3> The multiple read word lines RWL are connected to the reference voltage line VUW, and become non-selectable.

[0075] Thus, in the second embodiment, the controller CTL selectively controls one drive line WDRV. <0> Drive, and select 1 component (e.g., Figure 5 (The lowest level). Furthermore, the controller CTL selects one read master word line RMWL. <0> bRMWL <0> The line pair. Therefore, it will be connected to one read master word line RMWL. <0> bRMWL <0> The connected transistors RT1 and RT2 are switched on, turning on the drive line WDRV. <0> ~WDRV <3> With reading the main word line RMWL <0> bRMWL <0> The corresponding read word line RWL connection. This allows for selective selection of the read main word line RMWL. <0> bRMWL <0> The line pairs correspond to the multiple read word lines RWL and the drive line WDRV. <0> The corresponding (lowest-level) read word line RWL is driven. The multiple read bit lines RBL corresponding to this selected (lowest-level) read word line RWL transmit the data from the memory cell MC to the corresponding multiple read global bit lines RGBL.

[0076] According to the second embodiment, the controller CTL independently drives the multiple read master word lines RMWL arranged in the Y direction. Furthermore, by configuring the read master word line bRMWL and transistor RT2, a non-read voltage can be applied to the read word line RWL corresponding to the line pair of the non-selected read master word line RMWL and bRMWL based on the selected read master word line bRMWL. Therefore, the transistor between the multiple read bit lines RBL and the read global bit line RGBL can be omitted. Furthermore, the multiple read bit lines RBL arranged in the Y direction can be connected to one read global bit line RGBL in a common manner.

[0077] Furthermore, according to the second embodiment, the drive line WDRV is provided in a common manner relative to the write word line WWL and the read word line RWL. Therefore, similar to the first embodiment, not only is wiring simplified, but power consumption is also reduced.

[0078] (Third Implementation)

[0079] Figure 7 This is a perspective view showing a configuration example of the gain unit memory according to the third embodiment. In the first and second embodiments, the drive line WDRV is conventionally provided relative to read-related configurations such as read word line RWL and write-related configurations such as write word line WWL.

[0080] In contrast, in the third embodiment, the main word line MWL is configured in a common manner with read-related configurations such as the read word line RWL and write-related configurations such as the write word line WWL. The drive lines are divided into read drive line RWDRV and write drive line WWDRV. At the same time, the reference voltage line VUW can also be distinguished according to read-related and write-related configurations. When the reference voltage line VUW is fixed, no special distinction is required.

[0081] The main word line MWL extends in the Z direction and is arranged in the Y direction. Multiple write word lines WWL and multiple read word lines RWL located in multiple components (layers) and arranged in the Z direction share the main word line MWL. Therefore, the main word line MWL is commonly connected to the gates of multiple transistors WT1 and RT1 located in multiple components (layers) and arranged in the Z direction.

[0082] The main word line bMWL extends in the Z direction and is arranged in the Y direction. Multiple write word lines WWL and multiple read word lines RWL arranged in the Z direction share the main word line bMWL. Therefore, the main word line bMWL is commonly connected to the gates of multiple transistors WT2 and RT2 arranged in the Z direction.

[0083] Therefore, when reading and writing are performed, the main word lines MWL and bMWL selectively turn on the corresponding transistors WT1, RT1, WT2, and RT2.

[0084] On the other hand, the drive lines are divided into read drive lines RWDRV and write drive lines WWDRV. Therefore, when reading, any one of the multiple read drive lines RWDRV is selectively driven, and when writing, any one of the multiple write drive lines WWDRV is selectively driven.

[0085] Therefore, the controller CTL can selectively drive one read word line RWL or one write word line WWL from among the multiple read word lines RWL and multiple write word lines WWL connected to the selected master word line MWL and bMWL. When any of the read drive lines RWDRV are selectively driven during a read operation, one read word line RWL can be selectively driven. Similarly, when any of the write drive lines WWDRV are selectively driven during a write operation, one write word line WWL can be selectively driven.

[0086] exist Figure 7 Although the diagrams illustrating the bit line structure and the configuration of memory cells (MCs) are omitted, they can be compared with... Figure 5 The bit line configuration and memory cell MC arrangement shown are the same. The transistors between multiple read bit lines RBL and read global bit lines RGBL can be omitted. Furthermore, multiple read bit lines RBL arranged in the Y direction can be connected to one read global bit line RGBL in a common manner. On the other hand, the transistors between multiple write bit lines WBL and write global bit lines WGBL can be omitted. Furthermore, multiple write bit lines WBL arranged in the Y direction can be connected to one write global bit line WGBL in a common manner. Thus, data from the memory cells MC of multiple columns connected to the selected read word line RWL is transferred to the corresponding column's read global bit line RGBL. Alternatively, data from the write global bit line WGBL is transferred to the memory cells MC of each column connected to the selected write word line WWL.

[0087] Furthermore, in the third embodiment, where the main word line MWL is configured in a common manner with respect to both the read-dependent and write-dependent configurations, similar to the first embodiment, the transistor RT2 and the reference voltage line VUW connected to the read word line RWL can be omitted. In this case, the bit line configuration only needs to be consistent with... Figure 2 The bit lines shown can be configured identically. That is, transistors are placed between the multiple read bit lines RBL and the read global bit line RGBL. Furthermore, transistors are placed between the multiple write bit lines WBL and the write global bit line WGBL.

[0088] According to the third embodiment, the main word line (MWL) is set in a common manner with respect to both the read-dependent and write-dependent configurations. This not only maintains normal operation but also simplifies wiring.

[0089] (Fourth implementation)

[0090] Figure 8 This is a perspective view showing a configuration example of the gain cell memory according to the fourth embodiment. In the fourth embodiment, multiple read main word lines RMWL, bRMWL and multiple write main word lines WMWL, bWMWL extend in the Y direction and are arranged in the Z direction. The read main word lines RMWL are commonly connected to the gates of multiple transistors RT1 arranged in the Y direction. The write main word lines WMWL are commonly connected to the gates of multiple transistors WT1 arranged in the Y direction. The controller CTL selects one component (layer) by selectively driving the read main word lines RMWL, bRMWL or the write main word lines WMWL, bWMWL.

[0091] On the other hand, multiple drive lines WDRV extend in the Z direction and are arranged in the Y direction. The drive lines WDRV are configured in a common manner with respect to the multiple write word lines WWL and multiple read word lines RWL arranged in the Z direction. Simultaneously, the reference voltage line VUW also extends in the Z direction and is arranged in the Y direction. The reference voltage line VUW is configured in a common manner with respect to either the multiple write word lines WWL or the multiple read word lines RWL arranged in the Z direction. The reference voltage line VUW can also be distinguished according to read-dependent and write-dependent configurations. When the reference voltage line VUW is fixed, no special distinction is required.

[0092] In the fourth embodiment, the relationship between the extension directions of the main word lines RMWL, bRMWL, WMWL, bWMWL, the drive line WDRV, and the reference voltage line VUW is the opposite of the relationship between the extension directions of these lines in the second embodiment.

[0093] Therefore, during a read operation, the controller CTL selectively selects one read main word line (RMWL) from multiple read main word lines (RMWL). <0> This drives the process. Therefore, it is connected to the selected read master word line RMWL. <0> The corresponding component (e.g., Figure 8 The bottommost layer is selected. That is, the layer located at the bottom of the read main word line (RMWL) will be selected. <0> The multiple transistors RT1 at the bottom layer are turned on, switching the drive line WDRV to the ON state. <0> ~WDRV <3> Connected to the lowest level multiple read word lines RWL. At this time, for example, on drive line WDRV. <0> When transmitting a high-level voltage for reading, the high-level voltage for reading is selectively applied to the AND drive line WDRV in the multiple read word lines RWL at the lowest level. <0> Connect one read word line RWL.

[0094] exist Figure 8 Although the diagrams illustrating the bit line structure and the configuration of memory cells (MCs) are omitted, they can be compared with... Figure 5 The bit line configuration and memory cell MC arrangement shown are the same. The transistors between multiple read bit lines RBL and read global bit line RGBL can be omitted. Furthermore, multiple read bit lines RBL arranged in the Y direction can be connected to one read global bit line RGBL in a common manner. Thus, data from the memory cells MC of multiple columns connected to the selected read word line RWL is transferred to the read global bit line RGBL of the corresponding column.

[0095] In the write operation, the write word line WWL, write bit line WBL, and memory cell MC are selected in the same way as in the read operation. Therefore, the transistors between multiple write bit lines WBL and the write global bit line WGBL can be omitted. Furthermore, multiple write bit lines WBL arranged in the Y direction can be connected to one write global bit line WGBL. Thus, data from the write global bit line WGBL is transferred to the memory cells MC in each column connected to the selected write word line WWL.

[0096] The other configurations of the fourth embodiment can be the same as those of the second embodiment.

[0097] Furthermore, in the fourth embodiment, when the drive line WDRV is configured to be common to the multiple write word lines WWL and multiple read word lines RWL, similar to the first embodiment, the transistor RT2 connected to the read word line RWL and the reference voltage line VUW can be omitted. That is, the multiple read word lines RWL can also be separated from the reference voltage line VUW. In this case, the bit line configuration only needs to be consistent with... Figure 2 The bit lines shown can be configured identically. That is, transistors are placed between the multiple read bit lines RBL and the read global bit line RGBL. Furthermore, transistors are placed between the multiple write bit lines WBL and the write global bit line WGBL.

[0098] According to the fourth embodiment, the main word line is divided into a read main word line RMWL and a write main word line MWL. On the other hand, the drive line WDRV is provided in a common manner with respect to both the read-related and write-related configurations. This not only maintains normal operation but also simplifies wiring.

[0099] (Fifth Embodiment)

[0100] Figure 9 This is a perspective view showing a configuration example of the gain unit memory according to the fifth embodiment. In the fifth embodiment, the main word line MWL is provided in a common manner with read-related configurations such as the read word line RWL and write-related configurations such as the write word line WWL. The drive lines are divided into read drive line RWDRV and write drive line WWDRV. At the same time, the reference voltage line VUW can also be distinguished according to the read-related configuration and the write-related configuration. When the reference voltage line VUW is fixed, no special distinction is required.

[0101] The main word line MWL extends in the Y direction and is arranged in the Z direction. Multiple write word lines WWL arranged in the Y direction share the main word line MWL with multiple read word lines RWL. Therefore, the main word line MWL is commonly connected to the gates of multiple transistors WT1 and RT1 arranged in the Y direction.

[0102] The main word line bMWL extends in the Y direction and is arranged in the Z direction. Multiple write word lines WWL and multiple read word lines RWL arranged in the Y direction share the main word line bMWL. Therefore, the main word line bMWL is commonly connected to the gates of multiple transistors WT2 and RT2 arranged in the Y direction.

[0103] Therefore, when reading and writing are performed, the main word lines MWL and bMWL selectively turn on the corresponding transistors WT1, RT1, WT2, and RT2.

[0104] On the other hand, the drive lines are divided into read drive lines RWDRV and write drive lines WWDRV. Therefore, during a read operation, any one of the multiple read drive lines RWDRV is selectively driven, and during a write operation, any one of the multiple write drive lines WWDRV is selectively driven. Multiple read word lines RWL arranged in the Z direction share the read drive line RWDRV. Multiple write word lines WWL arranged in the Z direction share the write drive line WWDRV.

[0105] Therefore, the controller CTL can selectively drive one read word line RWL or one write word line WWL from among the multiple read word lines RWL and multiple write word lines WWL connected to the selected master word line MWL and bMWL. When any of the read drive lines RWDRV are selectively driven during a read operation, one read word line RWL can be selectively driven. Similarly, when any of the write drive lines WWDRV are selectively driven during a write operation, one write word line WWL can be selectively driven.

[0106] exist Figure 9 Although the diagrams illustrating the bit line structure and the configuration of memory cells (MCs) are omitted, they can be compared with... Figure 5 The bit line configuration and memory cell MC arrangement shown are the same. The transistors between multiple read bit lines RBL and read global bit lines RGBL can be omitted. Furthermore, multiple read bit lines RBL arranged in the Y direction can be connected to one read global bit line RGBL in a common manner. On the other hand, the transistors between multiple write bit lines WBL and write global bit lines WGBL can be omitted. Furthermore, multiple write bit lines WBL arranged in the Y direction can be connected to one write global bit line WGBL in a common manner. Thus, data from the memory cells MC of multiple columns connected to the selected read word line RWL is transferred to the read global bit line RGBL of the corresponding column. Alternatively, data from the write global bit line WGBL is transferred to the memory cells MC of each column connected to the selected write word line WWL.

[0107] Furthermore, in the fifth embodiment, when multiple read word lines RWL share a read drive line RWDRV and multiple write word lines WWL share a write drive line WWDRV, similar to the first embodiment, the transistor RT2 and the reference voltage line VUW connected to the read word lines RWL can be omitted. That is, the multiple read word lines RWL can also be separated from the reference voltage line VUW. In this case, the bit line configuration only needs to be consistent with... Figure 2 The bit lines shown can be configured identically. That is, transistors are placed between the multiple read bit lines RBL and the read global bit line RGBL. Furthermore, transistors are placed between the multiple write bit lines WBL and the write global bit line WGBL.

[0108] The other configurations of the fifth embodiment can be the same as those of the fourth embodiment. Therefore, the fifth embodiment can achieve the same effects as the fourth embodiment.

[0109] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and their equivalents.

[0110] [Explanation of Symbols]

[0111] MC: Storage Unit

[0112] MW1, MR1, MR2: Transistors

[0113] WWL: Write word line

[0114] RWL: Read word line

[0115] WDRV: Driveline

[0116] VUW: Non-Write Voltage Line

[0117] WT1, RT1, WT2, WTbl, RTbl: Transistors

[0118] WMWL: Write to mainword line

[0119] RMWL: Read main word line

[0120] bWMWL: Non-selectable mainword line

[0121] WBL: Write Bit Line

[0122] RBL: Read bit line

[0123] WGBL: Write Global Bitline

[0124] RGBL: Read global bit lines

[0125] WSEL: Write Select Line

[0126] RSEL: Read selection line.

Claims

1. A semiconductor memory device comprising: Multiple first data lines and multiple first control lines are used for writing data; Multiple second data lines and multiple second control lines are used for data reading; A plurality of memory cells include: a first transistor, the gate of which is connected to any one of the plurality of first control lines, and one end of which is connected to any one of the plurality of first data lines; a second transistor, the gate of which is connected to any one of the plurality of second control lines, and one end of which is connected to any one of the plurality of second data lines; and a third transistor, the gate of which is connected to the other end of the first transistor, storing data from the first data line, and one end of which is connected to the other end of the second transistor, becoming an on state corresponding to the data; The first drive line is configured in common with respect to the plurality of first control lines and the plurality of second control lines, and transmits the selection voltage for writing data; A plurality of fourth transistors are connected between the plurality of first control lines and the first drive lines; A plurality of fifth transistors are connected between the plurality of second control lines and the first drive line; A plurality of third control lines are respectively connected to the gates of the plurality of fourth transistors; and Multiple fourth control lines are respectively connected to the gates of the multiple fifth transistors.

2. The semiconductor memory device according to claim 1, wherein the plurality of first control lines, the plurality of second control lines, and the plurality of memory cells corresponding to one of the first driving lines are considered as a single component. One of the third control lines is connected to the gates of the plurality of fourth transistors corresponding to the plurality of the plurality of the components. One of the fourth control lines is connected to the gate of one of the fifth transistors corresponding to the plurality of the plurality of the components.

3. The semiconductor memory device according to claim 2, wherein one of the third control lines is commonly disposed on the plurality of first control lines corresponding to the plurality of the plurality of the components. One of the fourth control lines is commonly provided on the multiple second control lines corresponding to the multiple components.

4. The semiconductor memory device of claim 1, wherein the plurality of third control lines and the plurality of fourth control lines extend in a first direction in which the plurality of first data lines and second data lines extend. The first drive line extends in a third direction, which intersects with the second direction of the plurality of first control lines and second control lines extending therefrom, as well as the first direction.

5. The semiconductor memory device according to claim 2, further comprising: a fourth data line, commonly disposed corresponding to the plurality of second data lines; and Multiple sixth transistors are connected between the multiple second data lines and the fourth data line.

6. The semiconductor memory device according to claim 5, further comprising: a second driving line, commonly disposed relative to the plurality of first control lines, for transmitting a non-selective voltage for which no data is written; and A plurality of seventh transistors are connected between the plurality of first control lines and the second drive lines; and The plurality of second control lines are separated from the second drive lines.

7. The semiconductor memory device of claim 2, wherein the plurality of the third control lines are each driven independently. Multiple fourth control lines are driven in a common manner.

8. The semiconductor memory device of claim 6, wherein one of the plurality of first driving lines selects a component from the plurality of components. The plurality of second data lines respectively transmit data from the storage units in the selection component. The plurality of sixth transistors corresponding to one of the second control lines in the selection component transmit data from the second data line to the respective plurality of fourth data lines.

9. The semiconductor memory device according to claim 2, further comprising: a fourth data line, commonly connected to the plurality of second data lines; No transistors are disposed between the plurality of second data lines and the fourth data line.

10. The semiconductor memory device according to claim 9, further comprising: a second driving line, disposed commonly relative to the plurality of first control lines and the plurality of second control lines, for transmitting a non-selective voltage for which no data is written; A plurality of seventh transistors are connected between the plurality of first control lines and the second drive lines; and Multiple eighth transistors are connected between the multiple second control lines and the second drive lines.

11. The semiconductor memory device of claim 10, wherein one of the plurality of first driving lines selects a component from the plurality of components. The fifth transistor, corresponding to one of the second control lines in the selection component, connects the first drive line to the second control line. The plurality of second data lines corresponding to one of the second control lines in the selection component transmit data from the storage unit to the plurality of corresponding fourth data lines.

12. The semiconductor memory device of claim 1, wherein the plurality of third control lines and the plurality of fourth control lines extend in a third direction, the third direction intersecting a first direction in which the plurality of first data lines and second data lines extend and a second direction in which the plurality of first control lines and second control lines extend; The first drive line extends in the first direction.

13. A semiconductor memory device comprising: Multiple first data lines and multiple first control lines are used for writing data; Multiple second data lines and multiple second control lines are used for data reading; A plurality of memory cells include: a first transistor, the gate of which is connected to any one of the plurality of first control lines, and one end of which is connected to any one of the plurality of first data lines; a second transistor, the gate of which is connected to any one of the plurality of second control lines, and one end of which is connected to any one of the plurality of second data lines; and a third transistor, the gate of which is connected to the other end of the first transistor, storing data from the first data line, and one end of which is connected to the other end of the second transistor, becoming an on state corresponding to the data; The third control line is configured in common with respect to the plurality of first control lines and the plurality of second control lines; A plurality of first drive lines are configured to correspond to the plurality of first control lines respectively; A plurality of second drive lines are configured to correspond to the plurality of second control lines respectively; A plurality of fourth transistors are connected between the plurality of first drive lines and the plurality of first control lines, and their gates are commonly connected to the third control lines; and A plurality of fifth transistors are connected between the plurality of second drive lines and the plurality of second control lines, and their gates are commonly connected to the third control line.

14. The semiconductor memory device of claim 13, wherein the plurality of first control lines, the plurality of second control lines, and the plurality of memory cells corresponding to one of the first driving lines are considered as a single component. One of the third control lines is commonly connected to the gates of the plurality of fourth transistors and the gates of the plurality of fifth transistors corresponding to the plurality of the plurality of the components.

15. The semiconductor memory device of claim 14, wherein one of the third control lines is commonly disposed on the plurality of the first control lines and the plurality of the second control lines corresponding to the plurality of the components.

16. The semiconductor memory device of claim 13, wherein the third control line extends in a third direction, the third direction intersecting a first direction in which the plurality of first data lines and second data lines extend and a second direction in which the plurality of first control lines and second control lines extend; The plurality of first drive lines and the plurality of second drive lines extend in the first direction.

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