Semiconductor device and data storage system including the same

Abstract

A semiconductor device and a data storage system are provided. The semiconductor device includes: a substrate; a stacked structure including interlayer insulating layers and horizontal electrodes alternately stacked in a vertical direction on the substrate; a vertical pillar spaced apart from the substrate and disposed in a hole through the stack structure; and protruding portions disposed between the vertical pillar and the horizontal electrode and spaced apart from each other in the vertical direction, and the vertical pillar includes: a conductive pillar located in the hole; a first information storage layer covering a side surface and a bottom surface of the conductive pillar and including a ferroelectric layer; and an interface insulating layer covering an outer surface of the first information storage layer, and each of the protruding portions includes a conductive layer disposed between the interface insulating layer and the horizontal electrode.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0125611, filed on September 13, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a data storage system including the semiconductor device. Background Technology

[0004] In electronic systems that require data storage, semiconductor devices capable of storing large amounts of data are needed. Therefore, methods to increase the data storage capacity of semiconductor devices have been investigated. For example, as one method to increase the data storage capacity of semiconductor devices, semiconductor devices comprising memory cells arranged in three dimensions rather than two dimensions have been proposed. Summary of the Invention

[0005] One or more example embodiments provide a semiconductor device that utilizes a ferroelectric layer capable of storing information by utilizing polarization states.

[0006] One or more example embodiments provide a semiconductor device and a data storage system including the semiconductor device.

[0007] According to one aspect of an example embodiment, a semiconductor device includes: a stacked structure including interlayer insulating layers and horizontal electrodes alternately stacked in a vertical direction on a substrate, the stacked structures extending in a first direction perpendicular to the vertical direction and spaced apart from each other in a second direction perpendicular to the first direction; a molded structure including interlayer insulating layers and sacrificial insulating layers alternately stacked in a vertical direction on a substrate, the molded structures extending between the stacked structures in the first direction; vertical pillars disposed in holes through the stacked structures and the molded structures at the boundary between the stacked structures and the molded structures, and spaced apart from the substrate; and protrusions disposed between each of the vertical pillars and the horizontal electrodes, and spaced apart from each other in a vertical direction. Each of the vertical pillars includes: a conductive pillar disposed in the hole; a first information storage layer covering a side surface and a bottom surface of the conductive pillar, and including a ferroelectric layer; and an interface insulating layer covering an outer surface of the first information storage layer. Each of the protrusions includes a conductive layer, in which a portion of the outer surface of the conductive layer contacts one of the horizontal electrodes, and the remainder of the outer surface of the conductive layer contacts one of the sacrificial insulating layers.

[0008] According to another aspect of an example embodiment, a semiconductor device includes: a stacked structure including interlayer insulating layers and horizontal electrodes alternately stacked in a vertical direction on a substrate, the stacked structure extending in a first direction perpendicular to the vertical direction; a molded structure including interlayer insulating layers and sacrificial insulating layers alternately stacked in a vertical direction on a substrate, and disposed adjacent to the stacked structure in a second direction, extending in the first direction, the second direction being perpendicular to both the vertical and first directions; and a vertical structure disposed in a hole through the stacked structure and the molded structure at a boundary between the stacked structure and the molded structure, and spaced apart from the substrate. Each of the vertical structures includes: a conductive pillar disposed in a central region of each of the holes; a first information storage layer surrounding the conductive pillar, having a first thickness, and including a ferroelectric layer; an interface insulating layer surrounding the first information storage layer and having a second thickness less than the first thickness; and conductive layers surrounding the interface insulating layer between the interface insulating layer and the horizontal electrodes, the conductive layers being spaced apart from each other in the vertical direction.

[0009] According to another aspect of an example embodiment, a data storage system includes: a semiconductor device including input / output pads; and a controller electrically connected to the semiconductor device via the input / output pads and configured to control the semiconductor device. The semiconductor device includes: a stacked structure including interlayer insulating layers and horizontal electrodes alternately stacked in a vertical direction on a substrate, the stacked structure extending in a first direction perpendicular to the vertical direction and spaced apart from each other in a second direction perpendicular to the first direction; a molded structure including interlayer insulating layers and sacrificial insulating layers alternately stacked in a vertical direction on a substrate and extending between the stacked structures in the first direction; vertical pillars disposed in holes through the stacked structure and the molded structure and spaced apart from the substrate; and protrusions disposed at the boundary between the stacked structure and the molded structure between each of the vertical pillars and the horizontal electrodes, and spaced apart from each other in a vertical direction. Each of the vertical pillars includes: a conductive pillar disposed in the hole; a first information storage layer covering a side surface and a bottom surface of the conductive pillar and including a ferroelectric layer; and an interface insulating layer covering an outer surface of the first information storage layer. Each of the protrusions includes a conductive layer in which a first portion of the outer surface of the conductive layer contacts one of the horizontal electrodes, and a second portion of the outer surface of the conductive layer contacts one of the sacrificial insulation.

[0010] According to one or more example embodiments, a ferroelectric tunnel junction (including a two-terminal element capable of storing information using a ferroelectric layer as an information storage structure) can be formed as a three-dimensional vertical structure to improve integration. The ferroelectric tunnel junction memory element can be formed in a circular shape to increase the electric field applied to the ferroelectric layer, thereby increasing the memory window size.

[0011] One or more example embodiments provide an optimal structure that simplifies interconnects and improves integration by forming a two-terminal ferroelectric tunnel junction element into a three-dimensional vertical structure.

[0012] The advantages and effects of this application are not limited to those described above. Attached Figure Description

[0013] The above and other aspects, features, and advantages will become clear from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings:

[0014] Figure 1 This is a circuit diagram illustrating a memory cell of a semiconductor device according to an example embodiment;

[0015] Figure 2 This is a plan view illustrating a semiconductor device according to an example embodiment;

[0016] Figure 3 and Figure 4 This is a cross-sectional view of a semiconductor device according to an example embodiment;

[0017] Figure 5 This is a partially enlarged cross-sectional view of a semiconductor device according to an example embodiment;

[0018] Figures 6 to 9 This is a partially enlarged cross-sectional view conceptually illustrating a modified example of a semiconductor device according to an exemplary embodiment;

[0019] Figures 10 to 20 This is a plan view illustrating a modified example of a semiconductor device according to another example embodiment;

[0020] Figure 21 This is a cross-sectional view of a semiconductor device according to another example embodiment;

[0021] Figure 22A , Figure 22B , Figure 22C , Figure 22D , Figure 22E , Figure 22F , Figure 22G and Figure 22H This is a conceptual diagram illustrating an exemplary example of a method for forming a semiconductor device according to an example embodiment;

[0022] Figure 23 This is a schematic diagram illustrating a data storage system including a semiconductor device according to an example embodiment; and

[0023] Figure 24 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to an example embodiment. Detailed Implementation

[0024] In the following description, exemplary embodiments are illustrated with reference to the accompanying drawings. Terms such as “upper,” “intermediate,” and “lower” may be replaced by other terms such as “first,” “second,” and “third,” and may be used to describe components of the specification. Terms such as “first,” “second,” and “third” may be used to describe various components, but these components are not limited thereto, and a “first component” may be named a “second component.” The same components are indicated by the same reference numerals throughout the specification, and repeated descriptions thereof are omitted. It will be understood that when an element or layer is referred to as being “on”, “connected to,” or “coupled to” another element or layer, the element or layer may be directly on, directly connected to, or directly coupled to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on”, “directly connected to,” or “directly coupled to” another element or layer, there are no intermediate elements or layers. The embodiments described herein are exemplary embodiments, and therefore this disclosure is not limited thereto, and may be implemented in various other forms. Each example embodiment provided in the following description is not excluded from being associated with one or more features of another example or another example embodiment that are also provided herein or are not provided herein but are consistent with this disclosure.

[0025] Reference Figures 1 to 5 The following describes a semiconductor device according to an example embodiment. Figure 1 This is a circuit diagram illustrating a memory cell of a semiconductor device according to an example embodiment. Figure 2 This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 3 yes Figure 2 A cross-sectional view of a semiconductor device taken along line I-I'. Figure 4 yes Figure 2 A cross-sectional view of the semiconductor device taken along line II-II', and Figure 5 yes Figure 3 An enlarged cross-sectional view of region "A".

[0026] Reference Figure 1 The semiconductor device 100 according to the example embodiment may include a plurality of memory cells CJ. The memory cells CJ may be arranged in three dimensions in the Z and X directions. The memory cells CJ may include a variable capacitor implementing a ferroelectric tunnel junction. Each of the memory cells CJ may include a dielectric structure located between two conductive layers facing each other. Specifically, one of the two conductive layers (the first conductive layer) may be connected to a first signal line (S11, S12, ...), and the other conductive layer (the second conductive layer) may be connected to a second signal line (S21, S22, ..., S2n).

[0027] Each of the first signal lines (S11, S12, ...) can extend in the Z direction and simultaneously contact the first conductive layer of one column of memory cell CJ. The second signal lines (S21, S22, ..., S2n) can be stacked in the Z direction and spaced apart from each other. Each of the second signal lines (S21, S22, ..., S2n) can extend in the X direction. The second signal lines (S21, S22, ..., S2n) can simultaneously contact the second conductive layer of one row of memory cell CJ. The first signal lines (S11, S12, ...) can be driven as bit lines, and the second signal lines (S21, S22, ..., S2n) can be driven as word lines.

[0028] The unit memory cell CJ that contacts one of the first signal lines (S11, S12, ...) and one of the second signal lines (S21, S22, ..., S2n) may include an information storage structure that serves as a dielectric structure between the first and second conductive layers, such that the polarization direction of the ferroelectric layer in the information storage structure can be changed according to the strength of the electric field between the first and second conductive layers, thereby changing the tunneling current.

[0029] The Z direction can be referred to as and described as the first direction or the vertical direction. The X direction can be perpendicular to the Z direction and can be referred to as and described as the second direction or the first horizontal direction. The Y direction can be perpendicular to both the Z and X directions and can be referred to as and described as the third direction or the second horizontal direction.

[0030] Multiple memory cells CJ in a column aligned in the Z direction can form a single memory cell string CJS, and can be referred to as... Figures 2 to 5 The vertical structure VS.

[0031] Reference Figures 1 to 5 In the vertical structure VS, the multiple memory cells CJ spaced apart from each other in the Z direction may include an information storage structure 140 located between the first conductive layer 130 and the second conductive layer 150, and the information storage structure 140 may include a first information storage layer 141 as a ferroelectric layer FEL and an interface insulating layer 143.

[0032] Ferroelectric layers (FELs) can have a non-centrosymmetric charge distribution in each memory cell (CJ), and therefore can possess spontaneous dipoles (electric dipoles), i.e., spontaneous polarization. Even in the absence of an external electric field, ferroelectric layers (FELs) exhibit residual polarization due to the dipoles. Furthermore, the polarization direction can be switched by an external electric field.

[0033] In this respect, the ferroelectric layer FEL can have a positive or negative polarization state, and the polarization state can be changed by an electric field applied to the ferroelectric layer FEL during programming operations. Even when power is cut off, the polarization state of the ferroelectric layer FEL can be maintained, allowing the semiconductor memory device to operate as a non-volatile memory element. In an example embodiment, the polarization state of the ferroelectric layer FEL can be determined by the voltage difference between the first conductive layer 130 and the second conductive layer 150.

[0034] For example, during programming operations, the polarity of the ferroelectric layer FEL can be changed by the difference between the programming voltage applied to the second conductive layer 150 in the memory cell CJ and the ground voltage applied to the first conductive layer 130. The voltage difference between the programming voltage and the ground voltage can be equal to or greater than the minimum voltage required to change the polarization of the ferroelectric layer FEL, and can be, for example, a high voltage of 20V or greater, but the example embodiment is not limited to the above range.

[0035] During a read operation in which data is read from memory cell CJ, the tunneling current may change due to the altered polarity, and when a detection voltage is applied to the second conductive layer 150 of the selected memory cell CJ, the data stored in the memory cell CJ can be read by measuring the current flowing through the first conductive layer 130.

[0036] The semiconductor device 100 of the example embodiment can be implemented as a vertical structure VS, for example, wherein in Figure 1 The memory cell string CJS is a three-dimensional element that extends in the Z direction.

[0037] Reference Figures 2 to 5 The semiconductor device 100 according to the example embodiment may include a first structure CELL and a second structure PERI. The first structure CELL may be vertically overlapped with the second structure PERI.

[0038] In an example embodiment, the first structure CELL can be a memory region in which three-dimensional memory cells CJ are arranged, and the second structure PERI can be a peripheral circuit region.

[0039] In the example embodiment, the first structure CELL can be referred to as a memory chip structure or a first chip structure, and the second structure PERI can be referred to as a peripheral circuit structure or a second chip structure. Figure 3 and Figure 4 In the example, the first structure CELL is shown as being disposed on the second structure PERI, but the example embodiment is not limited thereto, and the first structure CELL may be disposed below the second structure PERI.

[0040] The second PERI structure may include a first substrate 3, circuit elements 21, a lower interconnect structure 12, and a lower capping layer 15.

[0041] The first substrate 3 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 3 may be configured as a bulk wafer or an epitaxial layer. An active region may be defined on the first substrate 3 by a device isolation layer. A source / drain region 10 including impurities may be disposed in a portion of the active region.

[0042] Circuit element 21 may be located on first substrate 3. Circuit element 21 may include transistors. Each of circuit elements 21 may include a gate stack 9 having a circuit gate dielectric layer 9a, a circuit gate electrode 9b, and source / drain regions 10. Source / drain regions 10 including impurities may be disposed on both sides of the circuit gate electrode 9b in the first substrate 3. Spacer layers may be disposed on both sides of the circuit gate electrode 9b. Circuit gate dielectric layer 9a may include silicon oxide, silicon nitride, or a high-k material. Circuit gate electrode 9b may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten silicon nitride (WSiN), tungsten (W), copper (Cu), aluminum (Al), molybdenum (Mo), and ruthenium (Ru). Circuit gate electrode 9b may include a semiconductor layer, such as a doped polysilicon layer. According to an example embodiment, circuit gate electrode 9b may be formed of two or more layers.

[0043] The lower interconnect structure 12 can be electrically connected to the circuit gate electrode 9b and the source / drain region 10 of the circuit element 21. The lower interconnect structure 12 can include lower contact plugs having a cylindrical or frustoconical shape, and lower interconnect lines having a linear shape in at least one region. Some of the lower contact plugs can be connected to the source / drain region 10, and others can be connected to the circuit gate electrode 9b. The lower contact plugs can electrically connect the lower interconnect lines disposed at a different level from the upper surface of the first substrate 3. The lower interconnect structure 12 can include a conductive material, and can include, for example, tungsten (W), copper (Cu), and aluminum (Al), and each component can also include a diffusion barrier layer, the diffusion barrier layer including at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). According to example embodiments, the number and arrangement of the lower contact plugs and lower interconnect lines included in the lower interconnect structure 12 can be varied.

[0044] The lower capping layer 15 may be disposed on the first substrate 3 to cover the circuit element 21 and the lower interconnect structure 12. The lower capping layer 15 may include multiple insulating layers. The lower capping layer 15 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide.

[0045] The first structure CELL may include a cell region R1 and an extension region R2. The extension region R2 may be located on one side of the cell region R1 in the X direction.

[0046] Cell region R1 is a memory cell region in which a memory cell string CJS is provided, and may be a region in which a vertical structure VS is provided. Extension region R2 may be a region in which multiple contact plugs CS are provided and connected to horizontal electrodes 185 located at different levels.

[0047] The semiconductor device 100 may include a second substrate 201 located in the cell region R1 and the extension region R2, stacked structures GS1, GS2, GS3 and GS4, molded structures MS1 and MS2 extending in the X direction and disposed adjacent to each other in the Y direction on the second substrate 201, and a separation structure SS extending in the X direction through the stacked structures GS1, GS2, GS3 and GS4.

[0048] The semiconductor device 100 may further include a support structure located in the extension region R2, and the cell region R1 and the extension region R2 may include a cell region insulating layer 190, and may include a post 175 and an upper circuit interconnect 170 passing through the cell region insulating layer 190 and performing electrical connections with the vertical structure VS and the contact plug CS. Figure 4 In the diagram, the contact plug CS is shown to extend to different lengths for connection between each horizontal electrode 185 and the contact plug CS, but this disclosure is not limited thereto.

[0049] The second substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). The second substrate 201 may be physically and electrically spaced from the vertical structure VS. For example, the upper surface of the second substrate 201 may be positioned at a lower level than the lower end of the vertical structure VS.

[0050] An etch stop layer 210 may be disposed on the second substrate 201. The etch stop layer 210 may be configured to cover the entire front surface of the second substrate 201 and may include an insulating material. The etch stop layer 210 may include an insulating material having etch selectivity relative to the interlayer insulating layer 120 and the sacrificial insulating layer 118 disposed in the upper portion, but the example embodiment is not limited thereto, and for example, the etch stop layer 210 may be formed of the same material as the interlayer insulating layer 120 and may have a thickness greater than that of the interlayer insulating layer 120.

[0051] The stacked structures GS1, GS2, GS3, and GS4 may include horizontal electrodes 185 having an electrode width W4 in the Y direction, extending in the X direction, and stacked and spaced apart from each other in the vertical direction (Z direction). The stacked structures GS1, GS2, GS3, and GS4 may vertically overlap with a second structure PERI, which can serve as a peripheral circuit structure. The stacked structures GS1, GS2, GS3, and GS4 may have a lower surface in contact with an etch stop layer 210 on the second substrate 201.

[0052] The stacked structures GS1, GS2, GS3, and GS4 may be spaced apart from each other in the Y direction, and the separation distances between the stacked structures GS1, GS2, GS3, and GS4 may be different from each other. For example, the separation distance when the molding structures MS1 and MS2 are disposed between the stacked structures GS1, GS2, GS3, and GS4 may be smaller than the separation distance when the separation structure SS is disposed between the stacked structures GS1, GS2, GS3, and GS4, but this disclosure is not limited thereto.

[0053] The horizontal electrodes 185 may be vertically spaced apart from each other and stacked on the second substrate 201, and may therefore be included in the stacked structures GS1, GS2, GS3, and GS4. The horizontal electrodes 185 may be disposed between the second substrate 201 and the upper interconnect structures 170 and 175. The number of horizontal electrodes 185 in contact with the memory cell CJ may vary depending on the memory capacity of the semiconductor device 100.

[0054] Horizontal electrode 185 can be formed Figure 1 The second signal lines (S21, S22, ..., S2n) shown are electrically connected to the second conductive layer 150 and may be included in word lines. Therefore, the second horizontal electrode 185 may be referred to as some of the word lines, but this disclosure is not limited thereto.

[0055] Interlayer insulating layers 120 may be stacked alternately and repeatedly with spaced horizontal electrodes 185. Interlayer insulating layers 120 may extend together with the interlayer insulating layers 120 of adjacent molded structures MS1 and MS2. Interlayer insulating layers 120 may include insulating materials such as silicon oxide. The uppermost interlayer insulating layer 121 (also referred to as "upper interlayer insulating layer 121") of the interlayer insulating layers 120 may be thicker than the remaining interlayer insulating layers 120.

[0056] The horizontal electrode 185 may include a conductive material. For example, each of the horizontal electrodes 185 may be formed of polycrystalline silicon, W, Ru, Mo, Nb, Ni, Co, Ti, Ta, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or combinations thereof. For example, each of the horizontal electrodes 185 may include a single layer or multiple layers of the above-described materials.

[0057] The molded structures MS1 and MS2 extending in the X direction can be respectively positioned between two adjacent stacked structures GS1, GS2, GS3 and GS4 in the Y direction.

[0058] In the example, the first molded structure MS1 can be disposed between the first stacked structure GS1 and the second stacked structure GS2, and the second molded structure MS2 can be disposed between the third stacked structure GS3 and the fourth stacked structure GS4. In the example, the two stacked structures GS2 and GS3, and a separate structure SS located between the two stacked structures GS2 and GS3, can be disposed in the Y direction between the two adjacent molded structures MS1 and MS2.

[0059] Each of the molded structures MS1 and MS2 may have a molding width W5 in the Y direction and may extend by intersecting with the cell region R1 and the extension region R2 in the X direction. The molded structures MS1 and MS2 may include sacrificial insulating layers 118 stacked and spaced apart from each other in the vertical direction (Z direction). The molding width W5 may be equal to or greater than the electrode width W4, but this disclosure is not limited thereto. The molded structures MS1 and MS2 may vertically overlap with a second structure PERI, which may serve as a peripheral circuit structure. The lower ends of the molded structures MS1 and MS2 may contact the etch stop layer 210, and their upper ends may contact the cell region insulating layer 190.

[0060] The sacrificial insulating layers 118 can be vertically spaced apart and stacked on the second substrate 201, and can be disposed at the same level as the horizontal electrodes 185, and can be disposed between the second substrate 201 and the upper interconnect structures 170 and 175. In the example, the horizontal electrodes 185 of the first stacked structure GS1 and the horizontal electrodes 185 of the second stacked structure GS2 can be spaced apart from each other in the Y direction, and the sacrificial insulating layer 118 of the first molded structure MS1 is inserted between the horizontal electrodes 185 of the first stacked structure GS1 and the horizontal electrodes 185 of the second stacked structure GS2. In the example, the horizontal electrodes 185 of the third stacked structure GS3 and the horizontal electrodes 185 of the fourth stacked structure GS4 can be spaced apart from each other in the Y direction, and the sacrificial insulating layer 118 of the second molded structure MS2 is inserted between the horizontal electrodes 185 of the third stacked structure GS3 and the horizontal electrodes 185 of the fourth stacked structure GS4.

[0061] Interlayer insulation layers 120 may be provided, stacked alternately and repeatedly with sacrificial insulation layers 118. Interlayer insulation layers 120 may extend together with interlayer insulation layers 120 of adjacent stack structures GS1, GS2, GS3, and GS4. Interlayer insulation layers 120 may include insulating materials such as silicon oxide.

[0062] The sacrificial insulating layer 118 may include an insulating material, and may include an insulating material that is etch-selective relative to the interlayer insulating layer 120, and may include silicon nitride or silicon carbonitride, but this disclosure is not limited thereto. The sacrificial insulating layer 118 may be disposed in a region that remains unchanged during the replacement process with the horizontal electrode 185.

[0063] The separation structure SS can be configured to extend in the Z direction through the horizontal electrode 185. The separation structure SS can be connected to the second substrate 201 by passing through the entire horizontal electrode 185 stacked on the second substrate 201. Figure 3 In this example, the separation structure SS is exemplified as having a side surface perpendicular to the bottom surface, but this disclosure is not limited thereto, and the side surface of the separation structure SS may have a shape in which its width decreases toward the second substrate 201 due to a high aspect ratio. Each of the separation structures SS may extend in the X direction to separate the horizontal electrodes 185 from each other in the Y direction, and may thus be divided into a first stacked structure GS1 and a second stacked structure GS2 or a third stacked structure GS3 and a fourth stacked structure GS4. According to the example embodiment, a separation insulating layer 179 may be disposed on the separation structure SS, and a conductive layer may also be disposed in the separation insulating layer 179. The separation insulating layer 179 may comprise an insulating material such as silicon oxide or silicon nitride, and may include, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0064] The separation structure SS has a separation width W6 in the Y direction, and the separation width W6 may be equal to or greater than the electrode width W4 and equal to or less than the molding width W5, but this disclosure is not limited thereto.

[0065] Therefore, as Figure 2 As shown, stacked structures GS1, GS2, GS3, and GS4, molding structures MS1 and MS2, and separation structure SS, which are strip-shaped and extend in the X direction, can extend continuously in the unit region R1 and the extension region R2. Based on the first molding structure MS1 and the second molding structure MS2, which are spaced apart from each other in the Y direction, the stacked structures GS1, GS2, GS3, and GS4 can be disposed on both sides of each molding structure MS1 and MS2, and the separation structure SS can be disposed on both sides of the stacked structures GS1, GS2, GS3, and GS4. Specifically, the first stacked structure GS1 and the second stacked structure GS2 can be disposed on both sides of the first molding structure MS1 in the Y direction, and the third stacked structure GS3 and the fourth stacked structure GS4 can be disposed on both sides of the second molding structure MS2 in the Y direction. Therefore, in each of the stacked structures GS1, GS2, GS3, and GS4, the first molded structure MS1 and the second molded structure MS2 can be disposed on one side in the Y direction, and the separation structure SS can be disposed on the other side. The stacked structures GS1, GS2, GS3, and GS4 can be disposed on both sides of the separation structure SS in the Y direction. The fact that the stacked structures GS1, GS2, GS3, and GS4, as well as the molded structures MS1 and MS2, are disposed on one side in the Y direction can be understood as the horizontal electrodes 185 of the stacked structures GS1, GS2, GS3, and GS4, and the sacrificial insulating layers 118 of the molded structures MS1 and MS2, are continuously disposed in the Y direction, and the interlayer insulating layers 120 disposed at the same level in the Z direction can be continuously disposed between adjacent stacked structures GS1, GS2, GS3, and GS4 and molded structures MS1 and MS2.

[0066] The stacked structures GS1, GS2, GS3 and GS4, the molded structures MS1 and MS2, and the separated structure SS can maintain a uniform width across the cell region R1 and the extension region R2, but this disclosure is not limited thereto.

[0067] Vertical structures VS can be disposed on the second substrate 201 in the boundary region between molded structures MS1 and MS2 and stacked structures GS1, GS2, GS3, and GS4. Each of the vertical structures VS can be configured to contact one of the adjacent molded structures MS1 and MS2 and one of the stacked structures GS1, GS2, GS3, and GS4. Each of the vertical structures VS can form a memory cell string CJS. (Refer to...) Figure 2The vertical structures VS of the first structure CELL can be spaced apart from each other in the X and Y directions and can have a matrix arrangement. In some other examples, the vertical structures VS can be arranged in a zigzag shape in the XY plane. The separation distance I1 of the vertical structures VS in the X direction can be different from the separation distance I2 in the Y direction. For example, the separation distance I1 in the X direction can be greater than the separation distance I2 in the Y direction, but according to the example embodiment, the separation distances I1 and I2 can be equal to each other.

[0068] Each of the above vertical structures VS may include a first conductive layer 130 and an information storage structure 140 disposed in holes that pass through stacked structures GS1, GS2, GS3 and GS4 and molded structures MS1 and MS2, and a protrusion 150 disposed between the first conductive layer 130 and the information storage structure 140 and the horizontal electrode 185 or the sacrificial insulating layer 118.

[0069] The first conductive layer 130 can form a vertical pillar, and the information storage structure 140 can also form a vertical pillar.

[0070] The first conductive layer 130 may be disposed at the center of the hole filled by the vertical structure VS, and may have a cylindrical shape extending in the Z direction. Alternatively, the first conductive layer 130 may have a U-shaped cross-section and may be filled with an insulating material. In the XY plane, the first conductive layer 130 may have a circular, elliptical, or polygonal shape, and the radius d4 of the first conductive layer 130 (i.e., the longest distance d4 from the center (O) of the hole to the outer surface of the first conductive layer 130) may be equal to or less than the first thickness T1 of the first information storage layer 141, and may satisfy, for example, 10 nm or less.

[0071] The first conductive layer 130 may be spaced apart from and electrically insulated from the second substrate 201, and may be connected to a selected signal line of the first signal line (170a: S11, S12...) of the upper circuit interconnect 170 via a corresponding post 175 on the upper surface. The horizontal level of the upper surface of the first conductive layer 130 may be the same as the horizontal level of the upper surface of the upper interlayer insulating layer 121, but this disclosure is not limited thereto.

[0072] The first conductive layer 130 may comprise multiple layers, one of which is a barrier layer on a side surface and a bottom surface, and the barrier layer may be a diffusion barrier layer. The first conductive layer 130 may comprise at least one selected from semiconductors including impurities (e.g., doped silicon), metals (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), conductive oxide semiconductors (e.g., IGZO), transition metals (e.g., titanium (Ti), tantalum (Ta), ruthenium (Ru), molybdenum (Mo), gold (Au), platinum (Pt), etc.), and multi-element conductive materials (e.g., MoS2, MoSe2, WS, etc.). The barrier layer may comprise at least one selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). When the first conductive layer 130 comprises a doped semiconductor, the first conductive layer 130 may be a semiconductor having a polycrystalline structure, such as polycrystalline silicon.

[0073] The information storage structure 140 may surround the first conductive layer 130. The information storage structure 140 may include an insulating material and may have a U-shaped cross-section to cover the side and bottom surfaces of the first conductive layer 130 in the hole.

[0074] The information storage structure 140 may include a first information storage layer 141 and an interface insulation layer 143.

[0075] The first information storage layer 141 may be a ferroelectric layer. The first information storage layer 141 may have polarization characteristics dependent on an electric field, and may possess residual polarization even in the absence of an external electric field through dipoles. The first information storage layer 141 may use the polarization states in the ferroelectric layer to store data. Data can be recorded into the first information storage layer 141 by controlling the polarization states in the ferroelectric layer. The region of the first information storage layer 141 facing the horizontal electrode 185, which may serve as a word line, may be a region used to store information using polarization states.

[0076] The first information storage layer 141 may be a ferroelectric layer comprising Hf-based compounds, Zr-based compounds, and / or Hf-Zr-based compounds. For example, the Hf-based compound may be an HfO-based ferroelectric material, the Zr-based compound may include a ZrO-based ferroelectric material, and the Hf-Zr-based compound may include a hafnium zirconium oxide (HZO)-based ferroelectric material.

[0077] The first information storage layer 141 may include a ferroelectric material doped with impurities (e.g., at least one of Zr, C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr). For example, the ferroelectric layer of the first information storage layer 141 may be a material obtained by doping at least one of Zr, C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr with at least one of HfO2, ZrO2, and HZO. For example, the ferroelectric layer of the first information storage layer 141 may include HfO2, C, Si, Mg, Al, Y, N, Ge, Sn, Gd, La, Sc, and Sr. 1-x Zr x O2 (0≤x≤1), HfO2 doped with (Al, C, N, Gd, Y, Ta, La, Si), or Al 1-x Sc x N(0≤x≤1).

[0078] The ferroelectric layer of the first information storage layer 141 is not limited to the types of materials described above, and may include materials having ferroelectric properties capable of storing information. For example, the ferroelectric layer of the first information storage layer 141 may include BaTiO3, PbTiO3, BiFeO3, SrTiO3, PbMgNdO3, PbMgNbTiO3, PbZrNbTiO3, PbZrTiO3, KNbO3, LiNbO3, GeTe, LiTaO3, KNaNbO3, BaSrTiO3, HF 0.5 Zr 0.5 O2, PbZr x Ti1-xO3(0 <x<1)、Ba(Sr、Ti)O3、Bi 4-x La x Ti3O 12 (0 <x<1)、SrBi2Ta2O9、Pb5Ge5O 11 At least one of SrBi2Nb2O9 and YMnO3. The first information storage layer 141 may be a single layer or multiple layers of the above-mentioned ferroelectric material.

[0079] The first information storage layer 141 may have a first thickness T1. The first thickness T1 may be equal to or greater than the radius d4 of the first conductive layer 130, but this disclosure is not limited thereto. The first thickness T1 may be approximately 10 nm or greater.

[0080] The interface insulating layer 143 can be disposed on the inner surface of each hole in the vertical structure VS, and can therefore be formed to cover the outer surface (i.e., its outer and lower surfaces) of the first information storage layer 141. The interface insulating layer 143 can have a second thickness T2, and the second thickness T2 can be less than the first thickness T1. The second thickness T2 can be 1 / 10 to 1 / 5 of the first thickness T1 (e.g., 1 nm to 2 nm), but this disclosure is not limited thereto.

[0081] When the ratio of the second thickness T2 to the first thickness T1 decreases and the radius d4 of the first conductive layer 130 decreases, the area ratio of the area of ​​the interface insulating layer 143 to the area of ​​the first information storage layer 141 can increase. In this case, the area is defined as the lateral area, and when the area is formed in a ring shape with concentric circles relative to the center (O) of the first conductive layer 130, the area can be defined as the area of ​​the interface of each layer. Therefore, the area of ​​the first information storage layer 141 can be defined as the area of ​​the side surface of the first conductive layer 130 (i.e., the area of ​​the inner surface of the first information storage layer 141), and the area of ​​the interface insulating layer 143 can be defined as the area of ​​the inner surface of the interface insulating layer 143 (the interface between the first information storage layer 141 and the interface insulating layer 143). When the area of ​​the interface insulating layer 143 increases and its thickness decreases, the capacitance of the interface insulating layer 143 increases, and on the other hand, when the area of ​​the first information storage layer 141 decreases and its thickness increases, the capacitance of the first information storage layer 141 decreases. When the capacitance of the first information storage layer 141 decreases, the electric field applied to the first information storage layer 141 increases, and therefore, strong polarization can be induced and the memory window can be enlarged. Conversely, when the capacitance of the interface insulating layer 143 increases, the electric field applied to the interface insulating layer 143 can be reduced to improve its reliability. The memory cell CJ can be implemented using a frame-type, ring-type, or circular ferroelectric tunnel junction (FTJ) with concentricity formed in this way, thereby simultaneously ensuring the memory window and reliability based on changes in the thickness of the first conductive layer 130, the interface insulating layer 143, and the first information storage layer 141.

[0082] The interface insulating layer 143 may be an oxide (specifically, an oxide such as SiO, AlO, LiO, HfO, ZrO, TaO, WO, or TiO), and may include at least one of oxides of nitride such as SiON and AlON, and a high-k dielectric. The high-k dielectric may be a dielectric having a dielectric constant higher than that of silicon oxide.

[0083] A plurality of protrusions 150 surrounding the first conductive layer 130 and the information storage structure 140 may be spaced apart from each other in the Z direction, and each of the protrusions 150 may be formed in a frame shape or a ring shape at different levels. Each of the protrusions 150 may include a second conductive layer 150, and Figure 3 and Figure 5Each of the protruding portions 150 in the structure may be referred to as a second conductive layer 150. The second conductive layer 150 may include a semiconductor material containing impurities as a conductive material. For example, the second conductive layer 150 may include at least one of doped silicon, doped polycrystalline silicon, and oxide semiconductors. The oxide semiconductor may be indium gallium zinc oxide (IGZO), but the example embodiments are not limited thereto. For example, the oxide semiconductor may include indium tin oxide (ITO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), and indium zinc oxide (InZnO). At least one of the following: indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO).

[0084] The second conductive layer 150 may include a metallic material. The second conductive layer 150 may include multiple layers, similar to the first conductive layer 130, where one layer is a barrier layer, and the barrier layer may be a diffusion barrier layer. The second conductive layer 150 may include at least one material selected from metals (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), transition metals (e.g., titanium (Ti), tantalum (Ta), ruthenium (Ru), molybdenum (Mo), gold (Au), platinum (Pt), etc.), and multi-element conductive materials (MoS2, MoSe2, WS, etc.). The barrier layer may include at least one material selected from titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN).

[0085] The interface insulating layer 143 may be spaced apart from the horizontal electrode 185, and the second conductive layer 150 is interposed between the interface insulating layer 143 and the horizontal electrode 185. Specifically, the inner surface of the second conductive layer 150 may contact the interface insulating layer 143, and the outer surface of the second conductive layer 150 may contact the horizontal electrode 185 and / or the sacrificial insulating layer 118. For example, the second conductive layer 150 may have a frame shape or annular shape in the XY plane. In the example, the outer surface of each of the protrusions 150 may include a portion that contacts the sacrificial insulating layer 118 and a portion that contacts the horizontal electrode 185. In the example, the second conductive layer 150 of the vertical structure VS that contacts the first stacked structure GS1 may be spaced apart by the sacrificial insulating layer 118 of the first molded structure MS1 from the second conductive layer 150 of the vertical structure VS that contacts the second stacked structure GS2 in the next row. The interlayer insulating layer 120 of the first molded structure MS1 may vertically overlap with some portions of each of the second conductive layers 150 of the vertical structure VS of the first stacked structure GS1, and may vertically overlap with some portions of each of the second conductive layers 150 of the vertical structure VS of the second stacked structure GS2. For example, the interlayer insulating layer 120 of the first molded structure MS1 and the stacked structure GS1 adjacent to the interlayer insulating layer 120 of the first molded structure MS1 may protrude further toward the vertical structure VS than the sacrificial insulating layers 118 and the horizontal electrodes 185 disposed above and below in the Z direction, and may contact the interface insulating layer 143 of the vertical structure VS between the protrusions 150 disposed above and below in the Z direction.

[0086] The upper surface of each second conductive layer 150 may be disposed at the same level as the upper surface of the horizontal electrode 185 that contacts each second conductive layer 150, and the lower surface of the second conductive layer 150 may be disposed at the same level as the lower surface of the horizontal electrode 185 that contacts the second conductive layer 150, but this disclosure is not limited thereto.

[0087] That is, the protrusion 150 can be configured to surround the first conductive layer 130 and the information storage structure 140 at each level corresponding to the horizontal electrode 185 and the sacrificial insulating layer 118. The protrusion 150 can be configured to overlap with the interlayer insulating layers 120 in the upper and lower portions in the Z direction, such that adjacent protrusions 150 can be physically and electrically disconnected from each other.

[0088] The area of ​​the outer surface of the portion of the second conductive layer 150 that contacts the horizontal electrode 185 can be equal to or less than half the area of ​​the outer surface of the second conductive layer 150, and the horizontal electrode 185 can be configured to overlap with a row of the vertical structure VS in the Y direction by a length d2 less than the total radius d1 of the vertical structure VS. For example, the horizontal electrode 185 can be configured to overlap with a row of the vertical structure VS in the Y direction by a length d2 less than the total radius d1 of the vertical structure VS and greater than half the total radius d1, but this disclosure is not limited thereto. That is, when the length of the stacked structures GS1, GS2, GS3 and GS4 in the Y direction is the electrode width W4, the electrode width W4 can include a length d2 that overlaps with the vertical structure VS and a length d3 that does not overlap with the vertical structure VS. On the outer surface of the second conductive layer 150, the area of ​​the outer surface of the portion that contacts the sacrificial insulating layer 118 can be greater than the area of ​​the outer surface of the portion that contacts the horizontal electrode 185, but 1 / 4 or more of the total area of ​​the second conductive layer 150 can contact the horizontal electrode 185 to maintain electrical connection with the horizontal electrode 185.

[0089] The vertical structure VS can be arranged in a circular or polygonal form on the XY plane, wherein the first conductive layer 130 has a predetermined radius d4 in the center (O) of the hole, and the information storage structure 140 can surround the side surface of the first conductive layer 130, and the first information storage layer 141 can be arranged with a first thickness T1. An interface insulating layer 143 can surround the outer surface of the first information storage layer 141 in the vertical structure VS with a second thickness T2, and a second conductive layer 150 can surround the outer surface of the interface insulating layer 143 in the vertical structure VS. Therefore, each of the layers 141, 143, and 150 surrounding the first conductive layer 130 can be formed in a ring shape with concentricity (O) relative to the center (O) of the first conductive layer 130. Therefore, the diameter of each of the layers 141, 143, and 150 can be determined according to the stacking order and stacking thickness. The diameter of the information storage structure 140 can be the same as the first width W1 (the diameter of the interface insulating layer 143). The diameter of the second conductive layer 150 on its outer side can be a second width W2 that is greater than the first width W1, and the diameter of the first information storage layer 141 on its inner side can be a third width W3 that is less than the first width W1. When the first conductive layer 130 is square or polygonal, each of the layers 141, 143, and 150 can have a frame shape, and the relationship between the maximum diameters of each frame can be similar to that described above.

[0090] In this case, in a ring with concentricity (O), due to the radius d4 of the first conductive layer 130 and the first thickness T1 of the first information storage layer 141, the area of ​​the inner surface of the first information storage layer 141 can be different from the area of ​​its outer surface.

[0091] That is, the area of ​​the inner surface of the first information storage layer 141 in contact with the first conductive layer 130 is smaller than the area of ​​the outer surface of the first information storage layer 141 in contact with the interface insulating layer 143, and the difference between the areas of the inner and outer surfaces increases with the increase of its thickness. Therefore, the area of ​​the first information storage layer 141 can have a smaller value relative to the area of ​​the interface insulating layer 143. Therefore, the capacitance of the first information storage layer 141 can be set to be smaller to increase the magnitude of the applied electric field, and thus, its polarization can be formed more clearly.

[0092] In the vertical structure VS, the ferroelectric tunnel junction elements included in the memory cell CJ can be disposed in the region corresponding to each horizontal electrode 185 to form a single memory cell string CJS. In a memory cell string CJS, the first conductive layer 130 can be connected to each other to form a vertical column, and the second conductive layer 150 can be physically and electrically separated from each other, so that different voltages can be received by or applied to each horizontal electrode 185.

[0093] The first conductive layer 130 and the second conductive layer 150 may comprise the same metallic material and may also comprise the same semiconductor material. Alternatively, when the first conductive layer 130 comprises a metallic material, the second conductive layer 150 may comprise a semiconductor material. The selection of materials for the first conductive layer 130 and the second conductive layer 150 can be implemented in various ways within a range of conductive materials, and can be implemented in various ways as long as the structure in which the first information storage layer 141 is disposed toward the first conductive layer 130 and the interface insulating layer 143 is disposed toward the second conductive layer 150 is satisfied.

[0094] The vertical structure VS can pass through the horizontal electrode 185, can extend in a vertical direction (Z direction) perpendicular to the upper surface of the second substrate 201, and can be cylindrical with inclined side surfaces, in which the width of the inclined side surfaces becomes narrower as the vertical structure VS approaches the second substrate 201, depending on the aspect ratio. The second width W2 of the upper surface of the vertical structure VS can be greater than the width of the lower surface of the vertical structure VS.

[0095] In the extension region R2, each of the stacked structures GS1, GS2, GS3, and GS4 may have a stepped structure in which the horizontal electrode 185 exposes the pad area GP, allowing the horizontal electrodes 185 and contact plugs CS at different levels to be physically and electrically connected to each other. When a stepped structure exists in which the horizontal electrode 185 exposes the pad area GP in the extension region R2, the adjacent molded structures MS1 and MS2 may also have the same stepped structure.

[0096] The contact plug CS can extend in the Z direction and can have sloping side surfaces such that its width becomes narrower as the contact plug CS approaches the second substrate 201. The contact plug CS can electrically connect the horizontal electrode 185 to the lower interconnect structure 12 in the first structure PERI. The contact plug CS can be physically and electrically connected to the horizontal electrode 185 in each pad region GP, ​​thus applying an electrical signal to the horizontal electrode 185. The contact plug CS can contact the pad region GP of the horizontal electrode 185 while partially recessed into its pad region GP, ​​but this disclosure is not limited thereto. For this purpose, the pad region GP of the horizontal electrode 185 can be formed thicker than other portions, but this disclosure is not limited thereto. According to an example embodiment, the contact plug CS can be configured to extend into the second substrate 201 through a region in which the horizontal electrode 185 forms a stepped structure, but this disclosure is not limited thereto.

[0097] The contact plug CS may include a metallic material, and may include, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or combinations thereof.

[0098] The second structure CELL may also include a cell region insulating layer 190 located on the upper interlayer insulating layer 121. The cell region insulating layer 190 may include an insulating material and may include, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0099] The second structure CELL may further include: a post 175 that passes through the cell region insulating layer 190 and is electrically connected to the first conductive layer 130 of the vertical structure VS; and an upper circuit interconnect 170 that is electrically connected to the post 175 on the cell region insulating layer 190. The upper circuit interconnect 170 may include, for example, a bit line BL as a first signal line 170a (S11, S12, ...), and may include a word line WL as a second signal line 170b (S11, S12, ...) in the extended region R2.

[0100] The post 175 can pass through the unit region insulation layer 190 and can have a width that decreases as the post 175 approaches the first conductive layer 130, and can be configured such that its lower surface can contact the upper surface of the first conductive layer 130 and the width of its lower surface can be smaller than the width of the upper surface of the first conductive layer 130.

[0101] Upper interconnect structures 170 and 175 can electrically connect the vertical structure VS to the circuit element 12. Upper interconnect structures 170 and 175 can include conductive materials, and can include, for example, tungsten (W), copper (Cu), and aluminum (Al), and each component can also include a diffusion barrier layer, comprising at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and tungsten nitride (WN). According to example embodiments, the number of layers and arrangement of upper interconnect structures 170 and 175 can be varied.

[0102] like Figures 2 to 5 As shown, the vertical structure VS can have a symmetrical shape with the center (O) of the hole as the axis, and the first conductive layer 130 has a cylindrical shape in the vertically cut cross-section based on the line connecting the center (O), and each layer around the first conductive layer 130 (specifically, the first information storage layer 141 and the interface insulating layer 143) can be formed in a U-shape symmetrical about the center (O). In this specification, the first information storage layer 141 can be referred to as the ferroelectric layer 141.

[0103] Because the unit memory cell CJ includes a ring-shaped information storage structure 140 located between the first conductive layer 130 and the second conductive layer 150, the area of ​​each layer can be determined based on the thickness and arrangement order of each layer. Therefore, the capacitance of the thick ferroelectric layer 141 near the center (O) can be further reduced, and the capacitance of the interface insulating layer 143, which surrounds the ferroelectric layer with a thin thickness and is disposed further away from the center (O) than the ferroelectric layer 141, can be further increased. In this way, the desired capacitance can be satisfied based on the thickness and arrangement order of each layer, thereby improving the storage function of the memory cell CJ.

[0104] The first conductive layer 130 and the information storage structure 140 can extend between multiple unit memory cells CJ of the memory cell string CJS forming the line, so that the first conductive layer 130 and the information storage structure 140 can be connected to each other. However, due to the voltage applied to the second conductive layer 150, the polarization of the ferroelectric layer of the corresponding unit information storage structure 140 can be formed differently for each unit memory cell CJ, so that the allocated information can be stored in each unit memory cell CJ.

[0105] In the following text, we will refer to the following respectively. Figures 6 to 9Various modifications to the components of the above-described exemplary embodiments are described below. The description of these modifications will focus on the modified or replaced components. Here, the components may be directly referenced without separate detailed description, or the description may be omitted. Furthermore, the modified or replaced components described below can improve at least one of the contact area, reliability, performance, and productivity of the semiconductor device. Additionally, the modified or replaced components described below are described with reference to the following figures; however, the modified or replaced components may be combined with each other or with the components described above to form a semiconductor device according to the exemplary embodiments.

[0106] Figures 6 to 9 yes Figure 3 A magnified view of part of the letter "A".

[0107] Reference Figure 6 In the exemplary semiconductor device 100a, the aforementioned protrusion may be replaced by a protrusion comprising a third conductive layer 145, an interface insulating layer 143, and a second conductive layer 150.

[0108] A third conductive layer 145 may be included in the protruding portion and may be disposed between the first information storage layer 141 and the interface insulating layer 143. The third conductive layer 145 may be arranged in a ring shape on the outer surface of the first information storage layer 141, which includes a vertical post, and may be configured such that its inner surface contacts the first information storage layer 141 and its outer surface contacts the interface insulating layer 143. Additionally, the interface insulating layer 143 may be bent such that its upper and lower surfaces are surrounded by the interface insulating layer 143, and may extend downwards while surrounding the third conductive layer 145. The third conductive layer 145 may include a conductive material and may include a semiconductor material containing impurities as the conductive material. For example, the third conductive layer 145 may include at least one of doped silicon, doped polysilicon, and oxide semiconductors. The oxide semiconductor may be IGZO (indium gallium zinc oxide), but the example embodiment is not limited thereto. For example, oxide semiconductors may include indium tin oxide (ITO), indium tin gallium oxide (ITGO), indium aluminum zinc oxide (IAZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), zinc tin oxide (ZTO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium silicon oxide (IGSO), indium oxide (InO), tin oxide (SnO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), and indium zinc oxide (InZnO). At least one of the following: indium gallium zinc oxide (InGaZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), zinc tin oxide (ZnSnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and indium gallium silicon oxide (InGaSiO).

[0109] The third conductive layer 145 may include a metallic material. Specifically, the third conductive layer 145 may include at least one selected from metals (e.g., tungsten, copper, aluminum, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), transition metals (e.g., titanium (Ti), tantalum (Ta), ruthenium (Ru), molybdenum (Mo), gold (Au), platinum (Pt), etc.), and multi-element conductive materials (MoS2, MoSe2, WS, etc.).

[0110] The third conductive layer 145 may include the same material as the first conductive layer 130 or the second conductive layer 150, and may be used as a floating electrode.

[0111] Reference Figure 7In the exemplary semiconductor device 100b, the information storage structure 140 of the vertical structure VS described above may further include a first insulating layer 147. The first insulating layer 147 may be disposed between the first conductive layer 130 and the first information storage layer 141, and may comprise the same material as the interface insulating layer 143, but this disclosure is not limited thereto. The first insulating layer 147 may also have a thickness smaller than the first thickness T1 of the first information storage layer 141, and may be formed in a U-shape around the side and bottom surfaces of the first conductive layer 130.

[0112] Reference Figure 8 In the exemplary semiconductor device 100c, Figure 7 The information storage structure 140 of the semiconductor device 100b may further include a second information storage layer 149. The second information storage layer 149 may be disposed between the first insulating layer 147 and the first information storage layer 141, and may have a thickness smaller than the first thickness T1 of the first information storage layer 141, and may be formed in a U-shape around the side surface and the lower surface of the first insulating layer 147.

[0113] The second information storage layer 149 may be a charge trapping layer capable of storing data using charge traps. The second information storage layer 149 may include at least one of SiO, SiN, SiON, SiO / SiN, SiO / SiON, SiO / AlO, SiO / HfO, SiO / SiN / SiO, and SiO / nanocrystalline materials. Here, expressions such as SiO / SiN may refer to a stacked structure of SiN and SiO material layers. The second information storage layer 149 may include at least one of Si(O)N and (Hf, Zr, Al, C, N, Gd, Y, Ti, La, Ta) doped Si(O)N. When the information storage structure 140 of the semiconductor device 100c includes a second information storage layer 149 in addition to the first information storage layer 141, the memory window can be further increased.

[0114] Reference Figure 9 The first information storage layer 141 included in the information storage structure 140 of the semiconductor device 100d can have an extended width in the portion contacting the protruding portion. Specifically, when the protruding portion includes an annular third conductive layer 145, the outer surface portion of the first information storage layer 141 in contact with the third conductive layer 145 can protrude outward toward the third conductive layer 145. Therefore, a protruding region may be included, in which the outer surface portion in contact with the third conductive layer 145 protrudes outward more than the outer surface portion in contact with the interface insulating layer 143. Therefore, the outer surface of the first information storage layer 141 can have repeating protruding regions in the portion overlapping with the horizontal electrode 185 or the sacrificial insulating layer 118.

[0115] Therefore, the inner surface of the first information storage layer 141 may further include a recessed region RS located in the region corresponding to the protruding region. The shape of the recessed region RS on the inner surface of the first information storage layer 141 may not precisely match the protruding region on its outer surface, and the recessed region RS on the inner surface may be formed with a concave tip, but is not limited thereto. Although the shapes of the inner and outer surfaces are discontinuous, the first information storage layer 141 may still meet a predetermined thickness T1 or greater. In addition to... Figures 5 to 9 In addition to those shown, the semiconductor device 100d may also include additional insulating layers.

[0116] In the following text, reference will be made to Figures 10 to 20 Describe various modification examples. Figures 10 to 20 It shows Figure 2 A modified example of the top view of the semiconductor device 100, which can be understood as a modified example in which the length (i.e., width) of the stacked structures GS1, GS2, GS3 and GS4 and the molded structures MS1 and MS2 in the Y direction are modified differently. Figures 10 to 20 It also shows applications that can be used Figure 2 The top view shows the upper circuit interconnect 170 to illustrate the connection between the upper circuit interconnect 170, which serves as the first signal lines (S11, S12, ...) in the respective semiconductor devices 100e to 100o, and the horizontal insulating layers 185 of the stacked structures GS1, GS2, GS3, and GS4, which serve as the second signal lines (S21, S22, ..., S2n). Hereinafter, the upper circuit interconnect 170 may be described as a bit line (BL, 170), but this disclosure is not limited thereto.

[0117] Reference Figure 10 In the semiconductor device 100e, bit lines 170 are provided that are simultaneously connected to the first conductive layer 130 of the vertical structure VS forming each column of the vertical structure VS forming a matrix. Therefore, each bit line 170 can simultaneously contact the column of the vertical structure VS through each post 175 to apply a signal or read current.

[0118] The stacked structures GS1, GS2, GS3, and GS4 of the semiconductor device 100e can be formed linearly in the X direction, but can have a first width W4 in the Y direction within the cell region R1, and a second width W7 in the Y direction within the extension region R2. The second width W7 of the extension region R2 can be greater than the first width W4 of the cell region R1, and the second width W7 of the stacked structures GS1, GS2, GS3, and GS4 on both sides of the molded structure MS1 or MS2 can have a form that extends toward the molded structures MS1 and MS2. Therefore, the width of the molded structures MS1 and MS2 in the cell region R1 can be greater than the width of the molded structures MS1 and MS2 in the extension region R2.

[0119] In this way, the side surfaces of the stacked structures GS1, GS2, GS3 and GS4 that contact the separate structure SS can extend straight in the X direction without bending, but the side surfaces of the stacked structures GS1, GS2, GS3 and GS4 that contact the molded structures MS1 and MS2 can have bending, in which the width is extended from the first width W4 to the second width W7, thereby implementing stacked structures GS1, GS2, GS3 and GS4 with a larger width in the extension region R2.

[0120] The larger stacked structures GS1, GS2, GS3 and GS4 in the extended region R2 ensure a larger area of ​​the pad region GP of the contact plug CS, thereby preventing misalignment.

[0121] Furthermore, because the stacked structures GS1, GS2, GS3 and GS4 have a larger width in the extension region R2, when the stacked structures GS1, GS2, GS3 and GS4 form steps in the extension region R2, the stacked structures GS1, GS2, GS3 and GS4 can be formed not only with stepped portions in the X direction, but also with stepped portions in the Y direction, making it possible to implement various types of stepped shapes.

[0122] Reference Figure 11 In the semiconductor device 100f, the separation structure SS may be provided only in the cell region R1, and the separation structure SS may not be provided in the extension region R2. Therefore, two stacked structures GS2 facing each other with the separation structure SS inserted therebetween can be merged in the extension region R2 to contact the horizontal electrode 185 of each layer through a contact plug CS. That is, the horizontal electrode 185 contacting a contact plug CS can form a single plate with a third width W8 in the extension region R2, and can be separated into two regions with a first width W4 by the separation structure SS in the cell region R1, and can thus contact each of the vertical structures VS in each row.

[0123] Therefore, the two rows of the vertical structure VS can simultaneously receive electrical signals conducted by a contact plug CS, but the bit lines 170 passing through the two rows of the vertical structure VS can be assigned two per column and can be physically and electrically connected to the alternating rows through the posts 175, thus forming a one-to-one correspondence.

[0124] Reference Figure 12In the semiconductor device 100g, the molded structures MS1 and MS2 can be disposed only in the cell region R1, and the molded structures MS1 and MS2 can be disposed outside the extension region R2. Therefore, two stacked structures GS1 facing each other with the molded structures MS1 and MS2 inserted therebetween can be merged in the extension region R2 to contact the horizontal electrode 185 of each layer via a contact plug CS. That is, the horizontal electrode 185 contacting the contact plug CS can form a plate with a fourth width W9 in the extension region R2, and can be divided into two regions with a first width W4 by the molded structures MS1 and MS2 in the cell region R1, and can thus contact the vertical structure VS of each row respectively.

[0125] Therefore, the two rows of the vertical structure VS can simultaneously receive electrical signals conducted by a single contact plug CS. However, the bit lines 170 passing through the two rows of the vertical structure VS can be assigned two per column and can be physically and electrically connected to the alternating rows via posts 175, thus forming a one-to-one correspondence. In this case, the separated structures SS have the same width and can extend continuously in the X direction from the cell region R1 to the extension region R2, but this disclosure is not limited thereto.

[0126] Reference Figure 13 In the semiconductor device 100h, two of the stacked structures GS1 to GS8 can be disposed on opposite sides of one row of the vertical structure VS. That is, for the stacked structures GS1 to GS8 disposed on one side of the vertical structure VS, it is also possible to... Figure 2 The semiconductor device 100 is provided with stacked structures GS1 to GS8 that are in contact with each second conductive layer 150 from the other side.

[0127] The separate structure SS and the stacked structures GS1 to GS8 on both sides of the separate structure SS can also be disposed in the region having molded structures MS1 to MS4 formed therein, such that the two stacked structures GS1 to GS8, which are separated from each other relative to the single vertical structure VS, can contact their sides. Each of the stacked structures GS1 to GS8 can receive an electrical signal through each contact plug CS, and therefore, even when the horizontal electrode 185 of the stacked structures GS1 to GS8 and the second conductive layer 150 of the vertical structure VS have poor contact and no electrical signal is applied, the horizontal electrode 185 and the second conductive layer 150 on the other side can contact each other, thereby minimizing their defects. In this case, bit lines 170 can be assigned to each of the vertical structures VS in each row, but this disclosure is not limited thereto.

[0128] Reference Figure 14 In the semiconductor device 100i, a setting is provided Figure 13In the semiconductor device 100h, two of the stacked structures GSa to GSb on both sides of a row of the vertical structure VS can be merged in the extension region R2 and thus included in a single stacked structure (GS1 to GS4). In the cell region R1, two stacked structures GSa to GSb located on both sides of the vertical structure VS can be provided, each of the vertical structure VS having a fifth width W10, and the two stacked structures GSa to GSb can be connected to each other in the extension region R2 to form a single stacked structure GS1 to GS4 having a sixth width W11 greater than the fifth width W10, thereby receiving signals through a contact plug CS.

[0129] Therefore, the number of contact plugs CS can be reduced, and in this case, bit lines 170 can be assigned one by one to each vertical structure VS of the column, but this disclosure is not limited thereto.

[0130] Reference Figure 15 In semiconductor device 100j, Figure 14 In the semiconductor device 100i, two stacked structures GSa to GSb disposed on both sides of a vertical structure VS in one row, and two stacked structures GSc to GSd disposed on both sides of a vertical structure VS in an adjacent row, can be merged in an extension region R2 and thus included in a single stacked structure GS1 or GS2. In cell region R1, two spaced-apart stacked structures GSa to GSb can be disposed on both sides of the vertical structure VS, and in extension region R2, four stacked structures GSa to GSd can be connected to each other and thus included in a single stacked structure GS1 or GS2, allowing signals to be applied to both rows of the vertical structure VS through a contact plug CS.

[0131] Therefore, the number of contact plugs CS can be reduced, and in this case, the bit lines 170 passing through the two rows of the vertical structure VS can be assigned two per column and can be physically and electrically connected to the alternating rows, thus forming a one-to-one correspondence.

[0132] exist Figure 15 In the unit region R1, the molding structures MS1 to MS4 can be disposed between two stacked structures GSa to GSb that are in contact with a vertical structure VS, and the separation structure SS can be disposed between two stacked structures GSa to GSb that are in contact with different vertical structures VS respectively.

[0133] exist Figure 15In the extended region R2, the side surfaces of the merged stacked structures GS1 and GS2 are shown as straight extensions without bending portions, but this disclosure is not limited thereto, and the width of the merged stacked structures GS1 and GS2 in the extended region R2 in the Y direction may have bending portions, so that the width can be reduced to a certain extent.

[0134] Reference Figure 16 In the semiconductor device 100k, the molded structures MS1 and MS2 and the stacked structures GS1, GS2 and GS3 can be alternately arranged without the separation structure SS. That is, the stacked structures GS1, GS2 and GS3 extending in the X direction can be alternately arranged with the molded structures MS1 and MS2 in the Y direction to simultaneously contact the vertical structures VS of two adjacent rows.

[0135] Therefore, two adjacent rows of vertical structures VS can simultaneously contact a horizontal electrode 185, and a signal can be applied to both rows of the vertical structure VS through a contact plug CS.

[0136] Therefore, the two rows of the vertical structure VS can simultaneously receive electrical signals through one row of the contact plug CS, but the bit lines 170 passing through the two rows of the vertical structure VS can be assigned two per column and can be physically and electrically connected to the alternating rows through the post 175, thus forming a one-to-one correspondence. In this case, the molded structures MS1 and MS2 can have the same width and can be continuously extended from the cell region R1 to the extension region R2 in the X direction, and the stacked structures GS1, GS2 and GS3 can also have the same seventh width W12 and can be continuously extended from the cell region R1 to the extension region R2 in the X direction, but this disclosure is not limited thereto.

[0137] Reference Figure 17 The semiconductor device 100l can be configured such that the stacked structures GS1, GS2, GS3 and GS4 and the discrete structure SS are arranged alternately in the Y direction without a molded structure.

[0138] Specifically, the vertical structure VS of each row can penetrate the corresponding stacked structures GS1, GS2, GS3 and GS4, and the horizontal electrodes 185 of the stacked structures GS1, GS2, GS3 and GS4 can contact the entire outer surface of the second conductive layer 150 of the vertical structure VS in each horizontal row.

[0139] Therefore, the reliability of the electrical connection between the vertical structure VS of each row and the horizontal electrode 185 of the stacked structures GS1, GS2, GS3, and GS4 can be ensured. A corresponding stacked structure GS1, GS2, GS3, and GS4 can be set for each of the vertical structures VS in each row, and each of the stacked structures GS1, GS2, GS3, and GS4 can have a higher density than... Figure 2 The stacked structures GS1, GS2, GS3, and GS4 have a large width W13 in the Y direction, allowing them to completely penetrate the vertical structure VS. In this case, the width W13 in the Y direction can be set to have a larger width in the extension region R2, but this disclosure is not limited thereto. Bit lines 170 can be assigned one by one to the vertical structure VS of each column.

[0140] Reference Figure 18 The semiconductor device 100m can be constructed to enable Figure 17 Each of the stacked structures GS1, GS2, GS3, and GS4 in the semiconductor device 100l may have a width W13 in the Y direction within the cell region R1, but may have a width W14 smaller than W13 within the extension region R2. That is, the distance between each pad region GP in the extension region R2 can be sufficiently ensured, thereby minimizing short circuits with each adjacent stacked structure GS1, GS2, GS3, and GS4. In this case, bit lines 170 may be assigned one by one to each vertical structure VS in each column, but this disclosure is not limited thereto.

[0141] Reference Figure 19 In the semiconductor device 100n, it is possible to Figure 17 In the semiconductor device 100m, the width W15 of the extended stacked structures GS1 and GS2 in the Y direction is such that both rows of the vertical structure VS are simultaneously penetrated.

[0142] Because the two rows of the vertical structure VS are in contact with the stacked structures GS1 and GS2 simultaneously, the number of contact plugs CS can be reduced, and two bit lines 170 passing through the two rows of the vertical structure VS are assigned to each column and can be physically and electrically connected to the alternating rows, thus forming a one-to-one correspondence.

[0143] Reference Figure 20 The semiconductor device 100o can be configured such that each of the stacked structures GS1 and GS2 can have a width W15 in the Y direction in the cell region R1, but can have a width W15 in the extension region R2 than the width W15 in the extension region R2. Figure 19The semiconductor device 100n has a width W15 and a smaller width W16. That is, the distance between each pad region GP in the extended region R2 can be sufficiently ensured, thereby minimizing the risk of short circuits with adjacent stacked structures GS1 and GS2. In this case, two bit lines 170 passing through the two rows of the vertical structure VS can be assigned to each column and can be physically and electrically connected to the alternating rows, thus forming a one-to-one correspondence. The electrical connections and configurations of the stacked structures GS1 and GS2, the contact plugs CS, and the bit lines 170 can be modified in various ways.

[0144] exist Figures 10 to 20 In this embodiment, the upper circuit interconnect 170 electrically connected to the first conductive layer 130 of the vertical structure VS is described as a bit line (BL, 170), and the horizontal electrode 185 connected to the second conductive layer 150 is described as being used as a word line. However, this disclosure is not limited thereto, and the upper circuit interconnect 170 electrically connected to the first conductive layer 130 can be used as a word line, and the horizontal electrode 185 connected to the second conductive layer 150 can be used as a bit line.

[0145] In the following text, refer to Figure 21 Another bonding structure of semiconductor device 100p will be described.

[0146] Reference Figure 21 The semiconductor device 100p may include a first structure PERI comprising a substrate 3 and a second structure CELL comprising a second substrate 201. The second structure CELL may be disposed below the first structure PERI.

[0147] In an example embodiment, instead, the second structure CELL can be positioned above the first structure PERI.

[0148] Reference above Figures 2 to 20 The description of the first structure PERI can be applied to the first structure PERI. However, the lower bonding structure 80 can also be applied to the first structure PERI.

[0149] The lower bonding structure 80 can be connected to the lower interconnect structure 12. The lower bonding structure 80 may include a lower bonding via, a lower bonding pad 84, and a lower bonding insulating layer 86. The lower bonding via can be connected to the lower interconnect structure 12. The lower bonding pad 84 can be connected to the lower bonding via. The lower bonding via and the lower bonding pad 84 may include conductive materials, and may include, for example, tungsten (W), copper (Cu), and aluminum (Al), and each of the components may also include a diffusion barrier layer. The lower bonding insulating layer 86 may also serve as a diffusion barrier layer for the lower bonding pad 84, and may include at least one of SiCN, SiO, SiN, SiOC, SiON, and SiOCN. The lower bonding insulating layer 86 may have a thickness thinner than, but is not limited to, the thickness of the lower bonding pad 84.

[0150] The formation of the lower capping layer 15 can be part of each operation that forms the lower interconnect structure 12 and the lower bonding structure 80.

[0151] It may include a second structure CELL, a vertical structure VS above the second substrate 201, a contact plug CS for electrical connection with the peripheral circuit region PERI, stacked structures GS1, GS2, GS3 and GS4, upper interconnect structures 170 and 175 above the molded structures MS1 and MS2, and an upper bonding structure 180 connected to the upper interconnect structures 170 and 175.

[0152] The upper bonding structure 180 can be connected to the upper interconnects 170 and 175. For example, the upper circuit interconnect 170 can be electrically connected to the upper bonding structure 180. The upper bonding structure 180 may include an upper bonding via, an upper bonding pad 184, and an upper bonding insulating layer 186. The upper bonding via can be connected to the upper circuit interconnect 170. The upper bonding pad 184 can be connected to the upper bonding via. The upper bonding via and the upper bonding pad 184 may include conductive materials, such as tungsten (W), copper (Cu), and aluminum (Al), and each of the components may also include a diffusion barrier layer. The upper bonding insulating layer 186 may also be used as a diffusion barrier layer for the upper bonding pad 184 and may include at least one of SiCN, SiO, SiN, SiOC, SiON, and SiOCN. The upper bonding insulating layer 186 may have a thickness thinner than that of the upper bonding pad 184, but is not limited thereto.

[0153] The lower bonding structure 80 and the upper bonding structure 180 can be in direct contact and bonded or connected via a hybrid bonding process. For example, the lower bonding pad 84 can contact the upper bonding pad 184 and can be bonded to the upper bonding pad 184 via a copper-to-copper bonding process, and the lower bonding insulating layer 86 can contact the upper bonding insulating layer 186 and can be bonded to the upper bonding insulating layer 186 via a dielectric-to-dielectric bonding process. The lower bonding structure 80, together with the upper bonding structure 180, can provide an electrical connection path between the second structure PERI and the first structure CELL.

[0154] Next, refer to Figures 22A to 22H This section will describe an example of a method for forming a semiconductor device according to an example embodiment. Figures 22A to 22H It shows along Figure 2 A cross-sectional view of the region cut by line I-I' is provided to illustrate an example of a method for forming a semiconductor element according to an exemplary embodiment.

[0155] Reference Figure 22ACircuit elements 21, lower interconnect structure 12, lower bonding structure 18 and lower capping layer 15 that can be included in the second structure PERI can be formed on the first substrate 3.

[0156] A device isolation layer 8 can be formed in the first substrate 3, and a circuit gate dielectric layer 9a and a circuit gate electrode 9b can be sequentially formed on the first substrate 3. The device isolation layer 8 can be formed, for example, in a shallow trench device isolation (STI) process. The circuit gate dielectric layer 9a can be formed on the first substrate 3, and the circuit gate electrode 9b can be formed on the circuit gate dielectric layer 9a. Atomic layer deposition (ALD) or chemical vapor deposition (CVD) can be used to form the circuit gate dielectric layer 9a and the circuit gate electrode 9b. The circuit gate dielectric layer 9a can be formed of silicon oxide, and the circuit gate electrode 9b can be formed of at least one of polysilicon and metal silicide layers, but this disclosure is not limited thereto. Spacer layers can be formed on the two sidewalls of the circuit gate dielectric layer 9a and the circuit gate electrode 9b, and impurities can be implanted into the active region of the first substrate 3 on both sides of the circuit gate electrode 9b, thus forming source / drain regions 10.

[0157] The lower contact plug in the lower interconnect structure 12 can be formed by the following steps: forming a portion of the lower capping layer 15, etching and removing the portion, and filling the removed portion with a conductive material. The lower interconnect can be formed, for example, by depositing a conductive material thereon and subsequently patterning the conductive material.

[0158] The lower capping layer 15 can be formed from multiple insulating layers. Therefore, a second PERI structure can be formed.

[0159] Reference Figure 22B A molded structure MS can be formed on the second substrate 201, and a vertical hole OP1 for forming a vertical structure VS and a separation opening OP2 for forming a separation structure SS can be formed in the molded structure MS. The second substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0160] An etch stop layer 210 may be formed on the second substrate 201. The etch stop layer 210 may comprise an insulating material and may be formed by depositing a material having etch selectivity relative to the sacrificial insulating layer 118 and the interlayer insulating layer 120 across the entire surface of the second substrate 201. In this case, the etch stop layer 210 may comprise carbon oxides and oxynitrides, but may be implemented as a polymer resin layer. The etch stop layer 210 may have a thickness greater than that of the interlayer insulating layer 120 and may be formed comprising the same material as the interlayer insulating layer 120, but this disclosure is not limited thereto.

[0161] The sacrificial insulating layer 118 and the interlayer insulating layer 120 can be alternately stacked on the etch stop layer 210 to form a molded structure MS.

[0162] A vertical hole OP1 can be formed corresponding to the vertical structure VS of the molded structure MS passing through the sacrificial insulation layer 118 and the interlayer insulation layer 120, in conjunction with the separated structure SS (see...). Figure 3 In the corresponding region, a separation opening OP2 can be formed through the molded structure MS that passes through the sacrificial insulating layer 118 and the interlayer insulating layer 120. The sacrificial insulating layer 118 may be a layer in which a portion is replaced by a horizontal electrode 185 in a subsequent process. An upper interlayer insulating layer 121 can be formed in the upper part of the sacrificial insulating layer 118 and the interlayer insulating layer 120.

[0163] Anisotropic etching can be performed to etch a portion of the etch stop layer 210 from the upper interlayer insulating layer 121, thereby forming a vertical hole OP1 and a separation opening OP2. In this case, the sacrificial insulating layer 118 and the interlayer insulating layer 120 can be sequentially removed using a mask layer to form the vertical hole OP1, and a high aspect ratio contact (HARC) etching can be applied to it according to its depth. The anisotropic etching can be controlled to proceed only to the upper part or a portion of the etch stop layer 210, and the etch stop layer 210 may not be completely removed and may be retained so that the second substrate 201 located in the lower part is not exposed.

[0164] Therefore, the lower surface of the vertical hole OP1 can be disposed within the thickness of the etch stop layer 210. In this case, a separation opening OP2 can also be formed, and the separation opening OP2 can be etched deeper than the vertical hole OP1 to expose the second substrate 201, but this disclosure is not limited thereto, and the separation opening OP2 can be formed to the same depth as the vertical hole OP1. Figure 4 As shown, the molded structure MS can be etched to expose the pad region GP with a stepped shape.

[0165] Reference Figure 22C A separation sacrificial structure 117 can be formed to fill the separation opening OP2, and some of the sacrificial insulation layer 118 can be removed in the vertical hole OP1.

[0166] Specifically, the separation sacrificial structure 117 may include a semiconductor material such as polycrystalline silicon. According to an example embodiment, the separation sacrificial structure 117 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0167] The sacrificial insulating layer 118 exposed in the vertical hole OP1 can be selectively etched to form the recessed portion OP3. Isotropic etching can be performed by applying an etchant that can selectively remove only a portion of the sacrificial insulating layer 118 exposed on the side surface inside the vertical hole OP1 to remove a portion of the sacrificial insulating layer 118 in each layer of the vertical hole OP1. Therefore, the sacrificial insulating layer 118 exposed inside the vertical hole OP1 can be removed from the side surface of the vertical hole OP1 to a predetermined depth, thus forming the recessed portion OP3.

[0168] like Figure 22D As shown, an initial second conductive layer 150P can be formed, which forms a second conductive layer 150 for forming protrusions 150 in the vertical holes OP1. That is, at least one of polysilicon, metal, transition metal and metal nitride that can be included in the second conductive layer 150 can fill all the recessed portions OP3 and can be deposited thick enough to cover the side surface of each vertical hole OP1.

[0169] like Figure 22E As shown, the deposited initial second conductive layer 150P can be locally isotropically etched until the side surface of the vertical hole OP1 is exposed, thereby forming a protruding portion 150 that fills the recessed portion OP3. That is, the initial second conductive layer 150P can be retained only in the recessed portion OP3, thereby forming second conductive layers 150 spaced apart from each other in the Z direction. The etch stop layer 210 located below the vertical hole OP1 can be exposed by locally isotropic etching.

[0170] Reference Figure 22F An interface insulating layer 143 can be formed to cover the side and bottom surfaces of the vertical hole OP1, and the interior of the vertical hole OP1 can be filled to form a filled sacrificial structure 119.

[0171] An interface insulating layer 143 can be formed by depositing an insulating material over its entire surface, and the insulating material can be conformally deposited at a second thickness T2 to simultaneously cover the inner surface of the second conductive layer 150 and the side surface of the interlayer insulating layer 120.

[0172] A filled sacrificial structure 119 may be formed on the interface insulating layer 143 to cover the vertical hole OP1, and may include the same material as the separated sacrificial structure 117, but this disclosure is not limited thereto.

[0173] As in Figure 6In the process of including a third conductive layer 145, the recessed portion OP3 can be formed to have a greater depth, and isotropic etching can be performed such that the second conductive layer 150 retains only a portion of the depth of the recessed portion OP3, and an interface insulating layer 143 can be formed to cover the remaining recessed portion OP3. After stacking the third conductive layer 145 to cover all the recessed portions OP3 present on the interface insulating layer 143, the third conductive layer 145 can be formed by local isotropic etching so that the third conductive layer 145 is included in the protrusion.

[0174] Reference Figure 22G The separation sacrificial structure 117 filling the separation opening OP2 can be removed, and a tunnel portion TL can be formed by removing the sacrificial insulating layer 118 to a predetermined depth via the exposed separation opening OP2. The depth of the tunnel portion TL can be adjusted according to the etching time and etchant, and the tunnel portion TL can be formed until the protrusion 150 of the vertical structure VS is exposed, specifically until a portion of the second conductive layer 150 is exposed. Therefore, a tunnel portion TL from which the sacrificial insulating layer 118 is removed can be formed on one side of the vertical hole OP1 included in the vertical structure VS, and the sacrificial insulating layer 118 can be retained on the other side, allowing the molded structure MS to be maintained.

[0175] like Figure 22H As shown, a horizontal electrode 185 can be formed, and a first information storage layer 141 can be formed in the vertical hole OP1.

[0176] A horizontal electrode 185 can be formed by filling the tunnel portion TL with conductive material through the separation opening OP2, thereby forming a stacked structure GS. A separation insulating layer 179 can be embedded in the separation opening OP2 to form a separation structure SS.

[0177] The conductive material may include metals, polycrystalline silicon, or metal silicides. After the horizontal electrode 185 is formed, the conductive material deposited in the separation opening OP2 can be removed by another process, and then an insulating material can be filled therein to form the separation structure SS.

[0178] Then, the filling sacrificial structure 119 can be removed, and a ferroelectric layer for forming the first information storage layer 141 can be deposited on the interface insulating layer 143 in the exposed vertical hole OP1. The ferroelectric layer can be deposited at a first thickness T1, and a conformal ferroelectric layer can be deposited on the interface insulating layer 143 in the vertical hole OP1, thereby forming the ferroelectric layer according to the example embodiment. Figure 9 The concave area RS and the protruding area.

[0179] like Figure 3As shown, a first conductive layer 130 can be formed by filling the interior of a vertical hole OP1 with a conductive material on the first information storage layer 141. In forming the first conductive layer 130, it can be formed by first forming a barrier layer on the entire side and lower surfaces of the first information storage layer 141 and then filling its interior with a conductive material, but this disclosure is not limited thereto. According to an example embodiment, the barrier layer may not be formed on its lower surface.

[0180] Conductive materials may include metals, polycrystalline silicon, or metal silicides.

[0181] When the vertical hole OP1 is filled with the first conductive layer 130, a vertical structure VS can be formed, including the first conductive layer 130, the information storage structure 140, and the protrusion 150. For example... Figure 3 As shown, the vertical structure VS can be covered, a cell region insulating layer 190 can be formed, a contact plug CS can be formed in the extension region R2, and upper interconnect structures 170 and 175 can be formed, thus completing the semiconductor device 100. In the first structure CELL, the pillar 175 can be formed to be connected to the vertical structure VS and the contact plug CS, respectively.

[0182] Refer to respectively Figure 23 and Figure 24 A data storage system including a semiconductor device is described according to an example embodiment.

[0183] Figure 23 This is a schematic diagram illustrating a data storage system including a semiconductor device according to an example embodiment.

[0184] Reference Figure 23 The data storage system 1000 according to an example embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100 to control the semiconductor device 1100. The data storage system 1000 may be a storage device including the semiconductor device 1100 or an electronic device including the storage device. For example, the data storage system 1000 may be a solid-state drive (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including the semiconductor device 1100.

[0185] In an example embodiment, the data storage system 1000 may be an electronic system for storing data.

[0186] Semiconductor device 1100 may be a non-volatile memory device. For example, semiconductor device 1100 may be a device similar to the one described above. Figures 1 to 21 The semiconductor device is consistent with the description. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F.

[0187] The first structure 1100F may be a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F may include the peripheral circuit structure PERI described above (see [link to documentation]). Figure 3 The circuit element 21 mentioned above (see above) Figure 3 () can be a transistor including decoder circuit 1110, page buffer 1120 and logic circuit 1130.

[0188] The second structure 1100S can be a memory structure including bit line BL, word line WL, and memory cell CJ located between bit line BL and word line WL.

[0189] In the second structure 1100S, each of the memory cell strings CJS may include a ferroelectric tunnel junction FTJ disposed between the bit line BL and the word line WL as a unit memory cell CJ. The number of unit memory cells CJ may be modified differently depending on the example embodiment.

[0190] like Figure 3 As described herein, a plurality of ferroelectric tunnel junctions (FTJs) may include a first conductive layer 130 and a second conductive layer 150 respectively connected to word line WL and bit line BL, and a first information storage layer 141 having ferroelectric material between the first conductive layer 130 and the second conductive layer 150 and an interface insulating layer 143.

[0191] The word line WL can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first structure 1100F to the second structure 1100S.

[0192] Bit line BL can be electrically connected to page buffer 1120.

[0193] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations for at least one memory cell CJ among the memory cells CJ. The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130.

[0194] Semiconductor device 1100 may further include input / output pads 1101. Semiconductor device 1100 can communicate with controller 1200 via input / output pads 1101 electrically connected to logic circuit 1130. Input / output pads 1101 can be electrically connected to logic circuit 1130 via input / output interconnects 1135 extending from first structure 1100F to second structure 1100S. Therefore, controller 1200 can be electrically connected to semiconductor device 1100 via input / output pads 1101 and can control semiconductor device 1100.

[0195] The controller 1200 may include a processor 1210, an FTJ controller 1220, and a host interface 1230. According to an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0196] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can control FTJ controller 1220 to access semiconductor device 1100. FTJ controller 1220 may include FTJ interface 1221 for processing communication with semiconductor device 1100. Through FTJ interface 1221, control commands for controlling semiconductor device 1100, data to be recorded in ferroelectric tunnel junction (FTJ) of semiconductor device 1100, data to be read from memory cell CJ of semiconductor device 1100, etc., can be transmitted. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When receiving control commands from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control commands.

[0197] Figure 24 This is a perspective view schematically illustrating a data storage system including semiconductor devices according to an example embodiment.

[0198] Reference Figure 24 The data storage system 2000 according to an example embodiment may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 formed on the motherboard 2001.

[0199] The motherboard 2001 may include a connector 2006 having a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host via any of the following interfaces: USB, Peripheral Component Interconnect High Speed ​​(PCI High Speed), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Memory (UFS). In an example embodiment, the data storage system 2000 may operate via power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) configured to distribute power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0200] The controller 2002 can record data in or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0201] DRAM 2004 can be a buffer memory used to mitigate the speed difference between the semiconductor package 2003, which serves as data storage space, and an external host. The DRAM 2004 included in the data storage system 2000 can also be used as a cache memory and can provide space for temporary data storage during control operations of the semiconductor package 2003. When the data storage system 2000 includes DRAM 2004, in addition to the FTJ controller for controlling the semiconductor package 2003, the controller 2002 may also include a DRAM controller for controlling the DRAM 2004.

[0202] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each be a semiconductor package including a plurality of semiconductor chips 2200. Each of the semiconductor chips 2200 may include components as described above. Figures 1 to 21 The description is consistent with that of semiconductor devices.

[0203] Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 located on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 and the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0204] The package substrate 2100 may be a printed circuit board including pads 2130 on the package. Each of the semiconductor chips 2200 may include input / output pads 2210.

[0205] In an example embodiment, the connection structure 2400 may be a bonding wire electrically connecting the input / output pads 2210 and the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wires and may be electrically connected to the on-package pads 2130 of the package substrate 2100. According to the example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure including through-silicon vias (TSVs) instead of the bonding wire connection structure 2400.

[0206] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate insert substrate, different from the main substrate 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other via interconnects formed on the insert substrate.

[0207] In this specification, the first signal lines (S11, S12, ...) are described as bit lines, and the second signal lines (S21, S22, ..., S2n) are described as word lines. However, the first signal lines (S11, S12, ...) and the second signal lines (S21, S22, ..., S2n) are conductive signal lines used to apply voltage to each unit memory cell CJ, and are not limited to their names. In fact, the first signal lines (S11, S12, ...) may be referred to as word lines, and the second signal lines (S21, S22, ..., S2n) may be referred to as bit lines.

[0208] Although various aspects of exemplary embodiments have been specifically shown and described, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: A stacked structure comprising interlayer insulating layers and horizontal electrodes alternately stacked in a vertical direction on a substrate, the stacked structure extending in a first direction perpendicular to the vertical direction and spaced apart from each other in a second direction perpendicular to the first direction; A molded structure comprising interlayer insulating layers and sacrificial insulating layers alternately stacked on the substrate in the vertical direction, the molded structure extending in the first direction between the stacked structures; A vertical column is disposed at the boundary between the stacked structure and the molded structure in a hole passing through the stacked structure and the molded structure, and is spaced apart from the substrate; as well as The protruding portions are disposed between each of the vertical columns and the horizontal electrode, and are spaced apart from each other in the vertical direction. Each of the vertical columns includes: A conductive post, which is placed in the hole; A first information storage layer, covering the side and bottom surfaces of the conductive pillars, and including a ferroelectric layer; and An interface insulating layer covers the outer surface of the first information storage layer, and each of the protrusions includes a conductive layer, wherein a portion of the outer surface of the conductive layer contacts one of the horizontal electrodes, and the remainder of the outer surface of the conductive layer contacts one of the sacrificial insulating layers.

2. The semiconductor device according to claim 1, wherein, The thickness of the first information storage layer in the horizontal direction perpendicular to the vertical direction is greater than the thickness of the interface insulating layer in the horizontal direction.

3. The semiconductor device according to claim 1, wherein, The radius of the conductive post along the first direction is equal to or less than the thickness of the first information storage layer along the first direction.

4. The semiconductor device according to claim 1, wherein, The conductive pillars and the conductive layer are made of different materials.

5. The semiconductor device according to claim 1, wherein, The conductive pillars comprise a metallic material, and the conductive layer comprises a semiconductor material.

6. The semiconductor device according to claim 1, wherein, Each of the vertical columns includes: A second information storage layer is located between the conductive pillar and the first information storage layer; and A first insulating layer is located between the conductive pillar and the second information storage layer, and The second information storage layer is a charge trapping layer.

7. The semiconductor device according to claim 1, wherein, Each of the protruding portions also includes a floating electrode located between the first information storage layer and the conductive layer.

8. The semiconductor device according to claim 7, wherein, The interface insulating layer extends from the portion between the interlayer insulating layer and the first information storage layer between the conductive layer and the floating electrode, and The conductive layer and the floating electrode are spaced apart from each other by the interface insulating layer.

9. The semiconductor device according to claim 1, wherein, The outer surface of the first information storage layer includes a protruding region that protrudes outward toward the protruding portion, and the inner surface of the first information storage layer includes a recessed region located in the region corresponding to the protruding region.

10. The semiconductor device according to claim 1, wherein, Each of the conductive pillars and the conductive layer comprises at least one of a metallic material, a metal nitride, a semiconductor material, and an intermetallic compound.

11. The semiconductor device of claim 1, further comprising an etch stop layer comprising an insulating material located between the substrate and the stacked structure. in, The vertical pillar is spaced apart from the substrate by the etch stop layer.

12. The semiconductor device according to claim 1, further comprising: The first conductive line is located on the stacked structure; as well as A column that electrically connects the first conductive wire and the conductive column between the first conductive wire and the conductive column.

13. A semiconductor device, comprising: A stacked structure comprising interlayer insulating layers and horizontal electrodes alternately stacked in a vertical direction on a substrate, the stacked structure extending in a first direction perpendicular to the vertical direction; A molded structure comprising an interlayer insulating layer and a sacrificial insulating layer alternately stacked on the substrate in the vertical direction, and disposed adjacent to the stacked structure in a second direction, and extending in the first direction, the second direction being perpendicular to the vertical direction and the first direction; as well as A vertical structure is disposed at the boundary between the stacked structure and the molded structure in a hole passing through the stacked structure and the molded structure, and is spaced apart from the substrate. Each of the vertical structures includes: A conductive post is disposed in the central region of each of the holes; A first information storage layer surrounds the conductive pillar, has a first thickness, and includes a ferroelectric layer; An interface insulating layer surrounds the first information storage layer and has a second thickness less than the first thickness; and A conductive layer surrounds the interface insulating layer between the interface insulating layer and the horizontal electrode, the conductive layers being spaced apart from each other in the vertical direction.

14. The semiconductor device according to claim 13, wherein, Each of the horizontal electrodes is in contact with 1 / 2 or less of the outer surface of each of the conductive layers.

15. The semiconductor device according to claim 13, wherein, The conductive post passes through the hole. Wherein, the first information storage layer and the interface insulating layer surround the conductive pillar and extend continuously in the vertical direction, and The conductive layers surround the interface insulating layer at different levels along the vertical direction, and each of the conductive layers forms a ring and is separated from the other layers of the conductive layer.

16. The semiconductor device according to claim 13, wherein, The first information storage layer includes an inner surface in contact with the conductive pillar and an outer surface in contact with the interface insulating layer, and The area of ​​the inner surface is smaller than the area of ​​the outer surface.

17. The semiconductor device according to claim 13, wherein, The radius of the conductive pillar is equal to or less than the first thickness of the first information storage layer.

18. The semiconductor device according to claim 13, wherein, The stacked structure includes: A first region, wherein the vertical structure is disposed in the first region; and The second region, which extends together with the first region in the first direction, includes contact structures connected to each of the horizontal electrodes, and In the first region, the conductive post of the vertical structure is connected to the first signal line, and in the second region, the contact structure is connected to the second signal line.

19. The semiconductor device according to claim 18, wherein, The width of the stacked structure in the first region in the second direction is smaller than the width of the stacked structure in the second region in the second direction.

20. A data storage system, comprising: A semiconductor device, including input / output pads; as well as A controller, which is electrically connected to the semiconductor device via the input / output pads and is configured to control the semiconductor device. The semiconductor device includes: A stacked structure comprising interlayer insulating layers and horizontal electrodes alternately stacked in a vertical direction on a substrate, the stacked structure extending in a first direction perpendicular to the vertical direction and the stacked structures being spaced apart from each other in a second direction perpendicular to the first direction; A molded structure comprising interlayer insulating layers and sacrificial insulating layers alternately stacked on the substrate in the vertical direction, and extending between the stacked structures in the first direction; Vertical pillars, disposed in holes passing through the stacked structure and the molded structure, and spaced apart from the substrate; and The protruding portions are disposed at the boundary between the stacked structure and the molded structure between each of the vertical pillars and the horizontal electrode, and are spaced apart from each other in the vertical direction. Each of the vertical columns includes: A conductive post, which is placed in the hole; A first information storage layer, covering the side and bottom surfaces of the conductive pillars, and including a ferroelectric layer; and An interface insulating layer covers the outer surface of the first information storage layer, and each of the protrusions includes a conductive layer, wherein a first portion of the outer surface of the conductive layer contacts one of the horizontal electrodes, and a second portion of the outer surface of the conductive layer contacts one of the sacrificial insulating layers.

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