MOSFET device and manufacturing method thereof
By progressive etching and multilayer P-type doped ion implantation in SiC MOSFET devices to form a uniform P-type protective layer, the problem of electric field concentration at the bottom of the trench is solved, and the reliability of the device is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-13
AI Technical Summary
Existing SiC MOSFET devices are prone to generating spike electric fields at the bottom of the trench, which leads to premature breakdown of the gate oxide layer. Existing P-type protective layer processes cannot completely cover the gate trench defects, making it difficult to achieve uniform electric field dispersion and affecting device reliability.
The first trench and multiple layers of the second trench are formed by stepwise etching, and P-type doped ions are implanted to form the first and second ion implantation regions of the stack. After high-temperature annealing, they are connected to form a P-type protective layer with uniform doping concentration, which completely covers the gate trench.
This achieves uniform electric field dispersion, protects the gate oxide layer, and improves device reliability.
Smart Images
Figure CN121665610A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor power device technology, and in particular to a MOSFET device and its manufacturing method. Background Technology
[0002] A silicon carbide metal-oxide-semiconductor field-effect transistor (SiC MOSFET) is a MOSFET manufactured using silicon carbide (SiC) semiconductor material. Compared to traditional silicon (Si) MOSFETs, SiC MOSFETs have lower on-resistance, lower switching losses, and higher high-temperature performance, making them increasingly outstanding in high-temperature, high-frequency, and high-voltage applications.
[0003] Among them, trench-type SiC MOSFET devices have become one of the research hotspots for SiC power devices due to their advantages of low specific on-resistance and high cell density. However, trench-type SiC MOSFET devices are prone to generating "spiking electric fields" at the bottom corner of the trench, which causes the local electric field intensity to far exceed the tolerance limit of the gate oxide layer, resulting in premature breakdown of the gate oxide layer and a high risk of device failure.
[0004] To address this issue, the industry has attempted to form a P-type protective layer at the bottom of the trench to reduce the electric field strength. However, the P-type protective layer formed by existing processes may have breaks or be unable to completely cover the gate trench defects in the depth direction, making it impossible to achieve uniform electric field dispersion and thus failing to truly protect the gate oxide layer and improve device reliability.
[0005] It should be noted that the information disclosed in this background section is intended only to enhance the understanding of the overall background of the present invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention
[0006] To address the defects in the P-type protective layer formed by the existing process, this invention provides a method for manufacturing a MOSFET device, which includes the following steps: A substrate is provided, and a first epitaxial layer and a second epitaxial layer are sequentially grown on the upper surface of the substrate; a mask is deposited on the surface of the second epitaxial layer according to a trench pattern, and a first etching is performed to form a first trench; P-type doped ions are implanted in the first trench to form a first ion implantation region. Etching is performed again to form a second trench. P-type doped ions are implanted into the second trench to form a second ion implantation region. This step is repeated a preset number of times. The mask is then removed and a high-temperature annealing process is performed to connect the first ion implantation region with the multilayer second ion implantation region to form a P-type protective layer. The device undergoes gate oxidation to form a gate oxide layer, followed by polysilicon deposition and filling into the gate trench to form the gate.
[0007] The first trench and multiple second trenches are formed by stepwise etching, and P-type doped ion implantation is performed on the first trench and each second trench to form a stacked first ion implantation region and multiple second ion implantation regions. After high-temperature annealing, the first ion implantation region and the multiple second ion implantation regions are interconnected to form a P-type protective layer with uniform doping concentration that can completely cover the gate trench in the depth direction, so as to truly achieve uniform electric field dispersion, protect the gate oxide layer and improve device reliability.
[0008] On the other hand, the present invention also provides a MOSFET device, which is fabricated using the MOSFET device manufacturing method of the above embodiments, so as to achieve uniform dispersion of electric field at the bottom of the gate trench, thereby protecting the gate oxide layer and improving device reliability.
[0009] Based on the above, the present invention provides a MOSFET device and its manufacturing method, which, compared with the prior art, forms a first trench and multiple layers of second trenches by progressive etching, and performs P-type doped ion implantation on the first trench and each second trench to form a stacked first ion implantation region and multiple layers of second ion implantation regions. After high-temperature annealing, the first ion implantation region and the multiple layers of second ion implantation regions are interconnected to form a P-type protective layer with uniform doping concentration and capable of completely covering the gate trench in the depth direction, thereby truly achieving uniform electric field dispersion and achieving the purpose of protecting the gate oxide layer and improving device reliability. Attached Figure Description
[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Unless otherwise specified, the positional relationships in the drawings described below are based on the direction in which the components are drawn in the figures.
[0011] Figure 1 This is a schematic flowchart of a MOSFET device manufacturing method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a MOSFET device according to an embodiment of the present invention; Figures 3-9 This is a schematic diagram of the structure of a MOSFET device at various stages of the manufacturing process according to an embodiment of the present invention.
[0012] Figure label: 10-Substrate, 20-First epitaxial layer, 30-Second epitaxial layer, 40-Gate trench, 50-P-type protective layer, 60-P-type base region, 70-N+ source region, 80-Gate oxide layer, 90-Gate, 100-ILD layer, 110-Source, 120-Drain, 41-First trench, 42-Second trench, 51-First ion implantation region, 52-Second ion implantation region. Detailed Implementation
[0013] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0014] In the description of this invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance, or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof mean "at least comprising."
[0015] To address the defects in the P-type protective layer formed by the existing process, or to achieve at least one or more of the aforementioned advantages, an embodiment of the present invention provides a method for manufacturing a MOSFET device, the method comprising the following steps: A substrate is provided, and a first epitaxial layer and a second epitaxial layer are sequentially grown on the upper surface of the substrate; a mask is deposited on the surface of the second epitaxial layer according to a trench pattern, and a first etching is performed to form a first trench; P-type doped ions are implanted in the first trench to form a first ion implantation region. Etching is performed again to form a second trench. P-type doped ions are implanted into the second trench to form a second ion implantation region. This step is repeated a preset number of times. The mask is then removed and a high-temperature annealing process is performed to connect the first ion implantation region with the multilayer second ion implantation region to form a P-type protective layer. The device undergoes gate oxidation to form a gate oxide layer, followed by polysilicon deposition and filling into the gate trench to form the gate.
[0016] The first trench and multiple second trenches are formed by stepwise etching, and P-type doped ion implantation is performed on the first trench and each second trench to form a stacked first ion implantation region and multiple second ion implantation regions. After high-temperature annealing, the first ion implantation region and the multiple second ion implantation regions are interconnected to form a P-type protective layer with uniform doping concentration that can completely cover the gate trench in the depth direction, so as to truly achieve uniform electric field dispersion, protect the gate oxide layer and improve device reliability.
[0017] Furthermore, it also includes the following steps: A mask is deposited on the surface of the second epitaxial layer according to the P-type base region pattern, and P-type doped ions are implanted to form the P-type base region. The mask is then removed. A mask is deposited on the surface of the second epitaxial layer according to the N+ source region pattern, and N-type doped ions are implanted to form the N+ source region. The mask is then removed. A mask is deposited on the surface of the second epitaxial layer according to the P+ ohmic contact region pattern, and P-type doped ions are implanted to form ohmic contact regions. The mask is then removed.
[0018] Furthermore, it also includes the following steps: An ILD layer is grown on the upper surface of the device. An ohmic contact region is formed by etching, depositing Ni, and annealing. Then, a source electrode is formed by depositing metal and etching. At the same time, a drain electrode is formed on the lower surface of the device, thus completing the fabrication of the MOSFET device.
[0019] Furthermore, the high-temperature annealing process includes the following steps: depositing a carbon protective film on the upper surface of the device to avoid and remove it after high-temperature annealing.
[0020] Furthermore, the depth of the first trench is greater than the depth of the second trench.
[0021] Furthermore, the depth of the first trench is 0.7–1.2 μm.
[0022] Furthermore, the depth of the second trench is 0.15–0.35 μm.
[0023] Furthermore, the concentration of P-type doped ions implanted in the first trench and the second trench is 5E16 to 9E18 atoms / cm³.
[0024] Furthermore, the preset number of times is 3 to 5 times.
[0025] Furthermore, this application also provides a MOSFET device, which is fabricated using the MOSFET device manufacturing method described in the above embodiments.
[0026] The technical solution of this application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of this application and through various specific implementation methods.
[0027] Example 1 This embodiment provides a method for manufacturing a MOSFET device. Please refer to [link / reference]. Figures 1-9 , Figure 1 This is a schematic flowchart of a MOSFET device manufacturing method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a MOSFET device according to an embodiment of the present invention; Figures 3-9 This is a schematic diagram of the structure of a MOSFET device at various stages of the manufacturing process according to an embodiment of the present invention.
[0028] As shown in the figure, the manufacturing method includes the following steps: A substrate 10 is provided, and a first epitaxial layer 20 and a second epitaxial layer 30 are sequentially grown on the upper surface of the substrate 10. A mask is deposited on the surface of the second epitaxial layer 30 according to a trench pattern, and a first etching is performed to form a first trench 41. P-type doped ions are implanted in the first trench 41 to form a first ion implantation region 51.
[0029] In this embodiment, an N+ type SiC substrate with excellent conductivity is preferred as the substrate to provide a stable current path for the device. A first epitaxial layer 20 and a second epitaxial layer 30 are sequentially grown on the substrate 10 using a low-pressure chemical vapor deposition process.
[0030] In specific implementation, such as Figure 3 As shown, the first epitaxial layer 20 can be an N-type drift layer, providing basic breakdown voltage capability for the device. Preferably, the thickness of the first epitaxial layer 20 can be 5–10 μm, and the doping concentration is 5E15–7E17 atoms / cm³.
[0031] The second epitaxial layer 30 can be an N-type drift region. Preferably, the thickness of the second epitaxial layer 30 can be 0.5 to 1.5 μm, and its doping concentration is lower than that of the first epitaxial layer 20, specifically 5E15 to 1.2E16 atoms / cm³. Its low doping characteristics can reduce carrier scattering, reduce device conduction loss, and lay the foundation for the formation of subsequent superjunction structures.
[0032] A thick mask (not shown) is deposited on the surface of the second epitaxial layer 30 according to a preset trench pattern. The mask can be a photoresist mask or a hard mask made of SiO2 or Si3N4. The hard mask is prepared by plasma-enhanced chemical vapor deposition and plays a precise masking role during ion implantation. Preferably, the thickness of the thick mask can be 200-500 nm.
[0033] like Figure 4 As shown, a dry etching process is used to form the first trench 41. Preferably, the depth of the first trench 41 can be 0.7–1.2 μm. P-type ions at a dose of 5E16–9E18 atoms / cm³ are implanted into the first trench 41 using an ion implanter to form the first ion implantation region 51. Preferably, the P-type ions can be Al ions.
[0034] The etching process is repeated to form a second trench 42. P-type doped ions are implanted into the second trench 42 to form a second ion implantation region 52. This process is repeated a preset number of times. The mask is then removed and a high-temperature annealing process is performed to connect the first ion implantation region 51 with the multilayer second ion implantation region 52 to form a P-type protective layer 50.
[0035] In specific implementation, such as Figures 5-8 As shown, after forming the first ion implantation region 51, a second trench 42 is formed by dry etching, with the depth of the second trench 42 being less than the depth of the first trench 41. Specifically, the depth of the second trench 42 can be 0.15–0.35 μm. P-type ions with a dosage of 5E16–9E18 atoms / cm³ are implanted into the second trench 42 using an ion implanter to form the second ion implantation region 52.
[0036] The above steps are repeated a preset number of times to form a multilayer second ion implantation region 52, and the surface mask is removed by wet etching. Then, the first ion implantation region 51 and the multilayer second ion implantation region 52 are interconnected by high-temperature annealing to form a P-type protective layer 50 with uniform doping concentration that completely covers the gate trench 40 at the bottom of the gate trench 40.
[0037] Preferably, the preset number of times can be 3 to 5. The applicant's research found that the conventional depth of the gate trench 40 of the SiC MOSFET device is about 1 μm. After P-type doped ion implantation, due to the scattering effect, P-type ions are only present in a radius of 0.15 to 0.35 μm at the sidewall implantation point of the gate trench 40, resulting in a break in the depth direction, or the gate trench 40 cannot be completely covered.
[0038] In this embodiment, the preset number of etching cycles is 3 to 5, meaning that after etching, the depth of the gate trench 40 is 1.2 to 2.9 μm, which is better than the conventional 1 μm for improving withstand voltage. At the same time, multiple etching and ion implantation help to form a continuous first ion implantation region 51 and a multilayer second ion implantation region 52. After high-temperature annealing, a P-type protection zone with uniform doping concentration and completely covering the gate trench 40 in the depth direction is formed, effectively reducing the electric field strength at the corner of the gate trench 40.
[0039] This gradual etching of the first trench 41 and multiple layers of the second trench 42 to form a gate trench 40 of 1.2 to 2.9 μm is beneficial for providing withstand voltage. The P-type protective layer formed by adapting the P-type doping ion implantation of the first trench 41 and each of the second trenches 42 is more uniform in doping concentration and can completely cover the gate trench 40 in the depth direction compared with the P-type protective layer formed by the existing process. This can truly achieve uniform electric field dispersion, thereby protecting the gate oxide layer 80 and improving device reliability.
[0040] Preferably, depending on the functional requirements of the device, the manufacturing method further includes the following steps: A mask is deposited on the surface of the second epitaxial layer 30 according to the P-type base region pattern, and P-type doped ions are implanted to form the P-type base region 60, and then the mask is removed. A mask is deposited on the surface of the second epitaxial layer 30 according to the N+ source region pattern, and N-type doped ions are implanted to form the N+ source region 70, and then the mask is removed. A mask is deposited on the surface of the second epitaxial layer 30 according to the P+ ohmic contact region pattern, and P-type doped ion implantation is performed to form ohmic contact regions (not shown in the figure), and then the mask is removed.
[0041] In specific implementation, such as Figure 7 As shown, a dedicated mask can be deposited sequentially for precise ion implantation according to the functional requirements of the device. For example, a mask (not shown) is first deposited according to the P-type base region pattern, and Al ions at a dose of 2E12 to 6E12 atoms / cm³ are implanted using an ion implanter to form the P-type base region 60. The P-type base region 60 is used to control the on and off states of the device channel.
[0042] After removing the P-type base mask, a mask is deposited according to the N+ source region pattern (not shown in the figure), and N ions with a dose of 3E14 to 8E14 atoms / cm³ are implanted through an ion implanter to form the N+ source region, which serves as the current injection terminal of the device.
[0043] After removing the N+ source mask again, a mask is deposited according to the P+ ohmic contact pattern (not shown). Al ions with an implantation dose of 3E14 to 8E14 atoms / cm³ are injected to form the P+ ohmic contact region (not shown), which effectively reduces the contact resistance between the source 110 and the P-type base region 60.
[0044] Furthermore, to address the surface degradation caused by Si desorption and surface atom migration during high-temperature annealing, a carbon film with a thickness of 50–200 nm and a purity ≥99.9% can be deposited on the device surface as a protective layer using chemical vapor deposition (CVD). The device is then placed in an inert gas atmosphere such as argon or nitrogen and subjected to high-temperature annealing at 1800–2000 °C for 10–30 minutes. The gas purity is ≥99.999%, and the annealing pressure is controlled at 1–5 atm. This process effectively activates implanted impurity ions and repairs lattice damage. After annealing, the carbon film is removed by dry etching to prevent residual carbon film from affecting subsequent process steps.
[0045] The device is subjected to gate oxidation to form a gate oxide layer 80, and then polysilicon is deposited and filled into the gate trench 40 to form a gate 90.
[0046] In specific implementation, such as Figure 9 As shown, a dry oxidation process can be used to oxidize the gate of the device. The oxidation temperature can be 1000–1200℃, and the oxidation time can be 30–60 min, to form a dense gate oxide layer 80 on the inner wall of the gate trench 40. The dry oxidation process can effectively improve the breakdown field strength and stability of the gate oxide layer. Preferably, the thickness of the gate oxide layer 80 can be 10–30 nm.
[0047] Furthermore, an N-type doped polysilicon is deposited at 550–650°C using a low-pressure chemical vapor deposition process to fill the gate trench 40 and cover the device surface. The polysilicon surface is then planarized using a chemical mechanical polishing process to make it flush with the surface of the second epitaxial layer 30. Finally, excess polysilicon outside the gate trench 40 is removed using a photolithography etching process, ultimately forming the gate 90. Preferably, the polysilicon doping concentration can be 1E19–1E20 atoms / cm³.
[0048] Based on the above, the MOSFET device manufacturing method may further include the following steps: An ILD (Inter Layer Dielectric) layer 100 is grown on the upper surface of the device. An ohmic contact region (not shown) is formed by etching, depositing Ni, and annealing. A source 110 is formed by depositing metal and etching. At the same time, a drain 120 is formed on the lower surface of the substrate 10, thus completing the fabrication of the MOSFET device.
[0049] In specific implementation, Figure 9 Taking the direction shown as an example, a 1 μm thick ILD layer 100 is grown on the upper surface of the device using plasma-enhanced chemical vapor deposition. The material of the ILD layer 100 can be SiO2 or Si3N4, which is used to isolate the gate 90 and the source 110 to prevent short circuits between the electrodes.
[0050] Contact holes (not shown) are formed at predetermined positions in the ILD layer 100 using photolithography etching. A 50–100 nm thick layer of Ni metal is deposited using electron beam evaporation or sputtering. After annealing at 400–500 °C for 10–20 min, Ni reacts with SiC to form an ohmic contact region, ensuring extremely low contact resistance.
[0051] Al or Al-Cu alloy with a thickness of 1–3 μm is deposited using a sputtering process, and the source electrode 110 is formed by photolithography etching. After the source electrode 110 is fabricated, it undergoes a plasma cleaning process for 5–10 minutes to remove the oxide layer and contaminants on the metal surface.
[0052] Preferably, the passivation layer (not shown) can also be prepared by coating or vapor deposition. The passivation layer can be a polyimide or SiO2-Si3N4 stack with a thickness of 1-5 μm. It is formed by photolithography etching to create a suitable passivation structure to protect the device surface from external environmental corrosion.
[0053] Furthermore, the lower surface of the substrate 10 is thinned to a predetermined thickness by mechanical grinding to reduce the impact of substrate resistance on device conduction losses. Preferably, the predetermined thickness can be 50–100 μm.
[0054] The lower surface of the substrate 10 is polished to ensure uniformity of subsequent metal evaporation. Grinding impurities and oxide layers on the back side are removed, and then Ni, Au, or a Ni-Au alloy is evaporated using an electron beam evaporation process. The alloy is then subjected to an alloying treatment at 400–600°C for 5–15 minutes to form the drain 120. This completes the fabrication of the MOSFET device. Preferably, the thickness of the drain 120 can be 2–5 μm, and the crystallinity of the drain 120 after metal alloying is ≥90%, ensuring the low resistance characteristics of the drain 120.
[0055] The MOSFET device prepared based on the manufacturing method provided in this embodiment can form a P-type protective layer 50 with uniform doping concentration at the bottom of the gate trench 40 and completely covering the gate trench 40 in the depth direction, so as to truly achieve uniform dispersion of electric field, protect the gate oxide layer 80 and improve device reliability.
[0056] Example 2 This application also provides a MOSFET device, which is fabricated using the MOSFET device manufacturing method of the above embodiment, to form a P-type protective layer 50 with uniform doping concentration at the bottom of the gate trench 40 and capable of completely covering the gate trench 40 in the depth direction, so as to achieve uniform dispersion of electric field at the bottom of the gate trench 40, thereby achieving the purpose of protecting the gate oxide layer and improving device reliability.
[0057] In summary, the MOSFET device and its manufacturing method provided by this invention, compared with the prior art, form a first trench and multiple layers of second trenches through stepwise etching, and perform P-type doped ion implantation on the first trench and each second trench to form a stacked first ion implantation region and multiple layers of second ion implantation regions. After high-temperature annealing, the first ion implantation region and the multiple layers of second ion implantation regions are interconnected to form a P-type protective layer with uniform doping concentration that can completely cover the gate trench in the depth direction, thereby truly achieving uniform electric field dispersion and achieving the purpose of protecting the gate oxide layer and improving device reliability.
[0058] Although terms such as first trench, second trench, first ion implantation region, and second ion implantation region are frequently used herein, the possibility of using other terms is not excluded. These terms are used merely for the convenience of describing and explaining the essence of the invention; interpreting them as any additional limitation would contradict the spirit of the invention.
[0059] Furthermore, those skilled in the art should understand that although many problems exist in the prior art, each embodiment or technical solution of the present invention can be improved in only one or a few aspects, without necessarily solving all the technical problems listed in the prior art or the background art simultaneously. Those skilled in the art should understand that any content not mentioned in a claim should not be construed as a limitation on that claim.
[0060] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for manufacturing a MOSFET device, characterized in that: Includes the following steps: A substrate is provided, and a first epitaxial layer and a second epitaxial layer are sequentially grown on the upper surface of the substrate; a mask is deposited on the surface of the second epitaxial layer according to a trench pattern, and a first etching is performed to form a first trench; P-type doped ions are implanted in the first trench to form a first ion implantation region. Etching is performed again to form a second trench. P-type doped ions are implanted into the second trench to form a second ion implantation region. This step is repeated a preset number of times. The mask is then removed and a high-temperature annealing process is performed to connect the first ion implantation region with the multilayer second ion implantation region to form a P-type protective layer. The device undergoes gate oxidation to form a gate oxide layer, followed by polysilicon deposition and filling into the gate trench to form the gate.
2. The MOSFET device manufacturing method according to claim 1, characterized in that: It also includes the following steps: A mask is deposited on the surface of the second epitaxial layer according to the P-type base region pattern, and P-type doped ions are implanted to form the P-type base region. The mask is then removed. A mask is deposited on the surface of the second epitaxial layer according to the N+ source region pattern, and N-type doped ions are implanted to form the N+ source region. The mask is then removed. A mask is deposited on the surface of the second epitaxial layer according to the P+ ohmic contact region pattern, and P-type doped ions are implanted to form ohmic contact regions. The mask is then removed.
3. The MOSFET device manufacturing method according to claim 1, characterized in that: It also includes the following steps: An ILD layer is grown on the upper surface of the device. An ohmic contact region is formed by etching, depositing Ni, and annealing. Then, a source electrode is formed by depositing metal and etching. At the same time, a drain electrode is formed on the lower surface of the device, thus completing the fabrication of the MOSFET device.
4. The MOSFET device manufacturing method according to claim 1, characterized in that: High-temperature annealing includes the following steps: depositing a carbon protective film on the surface of the device and removing it after high-temperature annealing.
5. The MOSFET device manufacturing method according to claim 1, characterized in that: The depth of the first trench is greater than the depth of the second trench.
6. The method for manufacturing a MOSFET device according to claim 5, characterized in that: The depth of the first trench is 0.7 to 1.2 μm.
7. The method for manufacturing a MOSFET device according to claim 6, characterized in that: The depth of the second trench is 0.15–0.35 μm.
8. The method for manufacturing a MOSFET device according to claim 1, characterized in that: The concentration of P-type doped ions implanted in the first and second trenches is 5E16 to 9E18 atoms / cm³.
9. The method for manufacturing a MOSFET device according to claim 1, characterized in that: The preset number of times is 3 to 5.
10. A MOSFET device, characterized in that: It is prepared using the MOSFET device manufacturing method as described in any one of claims 1 to 9.