Trench gate MOSFET and preparation method thereof, and chip

Abstract

The invention belongs to the technical field of power devices, and provides a trench gate MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), a preparation method thereof and a chip, and the trench gate MOSFET is formed on a P-type shielding region at the bottom of a gate oxide layer with a concave trench, an N-type point doping region is formed in the P-type shielding region, and a gate material layer is formed in the groove of the gate oxide layer. The field oxide layer and the gate oxide layer form a closed structure wrapping the gate material layer, a PN junction is formed between the P-type shielding region and the N-type drift region, and a PN junction is formed between the P-type shielding region and the N-type point doping region, so that the area of a depletion region can be increased under the condition of reverse bias of the device, the breakdown voltage is improved, and the purpose of optimizing the static quality factor is achieved.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a trench gate MOSFET and its fabrication method and chip. Background Technology

[0002] Due to their excellent material properties, including wide bandgap, high critical electric field and good thermal conductivity, silicon carbide (SiC) trench-gate metal-oxide-semiconductor field-effect transistors (TG-MOSFETs) have very high gate density without being limited by the parasitic JFET channels in planar SiC MOSFETs, thus reducing the contribution of channel resistance to the total on-resistance. Compared to conventional planar MOSFETs, TG-MOSFETs can significantly reduce the specific on-resistance of devices by accommodating more channels on a given chip area and completely eliminating the JFET effect. However, for conventional SiC trench MOSFETs in reverse blocking mode, the high electric field in the gate oxide layer at the bottom of the trench is a major problem, which causes the breakdown voltage (VBR) to be limited by gate oxide collapse at a voltage far below the inherent breakdown capability of the drift region semiconductor junction. Summary of the Invention

[0003] To address the aforementioned technical problems, this application provides a trench gate MOSFET, its fabrication method, and a chip, aiming to improve the breakdown voltage of the device and optimize its static quality factor.

[0004] A first aspect of this application provides a trench gate MOSFET, the trench gate MOSFET comprising: A silicon carbide substrate and a buffer layer, wherein the buffer layer is formed on the front side of the silicon carbide substrate; An N-type drift region with concave grooves is formed on the buffer layer; A current spreading layer is formed on both sides of the N-type drift region; A P-type well region is formed on the current spreading layer; A P-type shielding region is formed at the bottom of the groove in the N-type drift region; wherein at least one N-type doped region is formed within the P-type shielding region. A gate oxide layer with concave trenches is formed on the P-type shielding region, and the height of the gate oxide layer is greater than the sum of the heights of the first current spreading layer and the first P-type well region. The N-type heavily doped region is formed on the P-type well region and located on both sides of the gate oxide layer; A p-type heavily doped region is formed on the p-type well region and located next to the n-type heavily doped region; A gate material layer is formed within a groove in the gate oxide layer; A field oxide layer, together with the gate oxide layer, forms a closed structure that encloses the gate material layer; The source layer is in contact with the P-type well region, the N-type heavily doped region, both sides of the gate oxide layer, and the field oxide layer; A drain layer is formed on the back side of the silicon carbide substrate.

[0005] In some embodiments, the P-type shielding region is a concave structure or an arc shape, and the width of the P-type shielding region gradually increases from the drain layer to the source layer.

[0006] In some embodiments, the width of the P-type shielding region is smaller than the width of the bottom of the gate oxide layer.

[0007] In some embodiments, the N-type doped region is opposite to the gate material layer.

[0008] In some embodiments, the thickness of the two ends of the P-type shielding region is greater than the sidewall thickness of the gate oxide layer.

[0009] In some embodiments, the doping density of the N-type doped region gradually decreases from the source layer to the drain layer.

[0010] In some embodiments, the distance between the outer edge of the N-type doped region and the P-type shielding region is greater than the thickness of the gate oxide layer.

[0011] In some embodiments, the doping concentration of the P-type shielding region exhibits a gradient distribution.

[0012] A second aspect of this application also provides a method for fabricating a trench gate MOSFET, the method comprising: A buffer layer, an N-type drift region, a current spreading layer, a P-type well doped layer, and an N-type doped layer are sequentially formed on the front side of a silicon carbide substrate. Under the cover of a first mask, a first trench is etched along the central region of the N-type doped layer, extending into the N-type drift region. The P-type well doped layer has a concave structure, and the N-type doped layer is located within the groove of the P-type well doped layer. A current spreading layer, a P-type well region, a heavily doped P-type region, and a heavily doped N-type region are formed on both sides of the first trench, respectively. Remove the first mask and fill the first trench with a first dielectric material; wherein the first dielectric material covers the surface areas of the first trench and the P-type well region and the N-type heavily doped region; A second mask is applied to the first dielectric material, and the first dielectric material is etched according to the pattern of the second mask to form a first dielectric material layer at the bottom and sidewalls of the first trench; wherein the thickness of the first dielectric material layer is less than the thickness of the current spreading layer. P-type doped ions are injected along the trench direction of the first trench, so that the P-type doped ions pass through the first dielectric material layer to form a P-type shielding region in the N-type drift region. The first dielectric material is deposited to cover the first trench, a third mask is deposited on the first dielectric material, and the first dielectric material is etched according to the pattern of the second mask to form a second dielectric material layer at the bottom and sidewalls of the first trench; wherein the thickness of the second dielectric material layer is greater than the thickness of the first dielectric material layer. N-type doped ions are injected along the trench direction of the first trench, so that the N-type doped ions pass through the second dielectric material layer to form an N-type doped region in the P-type shielding region. Remove the second dielectric material layer and activate the P-type shielding region and the N-type doped region; A gate oxide layer is formed at the bottom and sidewalls of the first trench, a gate material layer is formed by filling it with polysilicon material, and a field oxide layer is formed on the gate material layer. Then, a source material is deposited to form a source layer that contacts the P-type well region, the N-type heavily doped region, both sides of the gate oxide layer, and the field oxide layer. The field oxide layer and the gate oxide layer form a closed structure that encloses the gate material layer.

[0013] A third aspect of this application also provides a chip including a trench gate MOSFET as described in any of the above embodiments.

[0014] The beneficial effects of the embodiments of this application are as follows: by forming a gate oxide layer with concave trenches on the bottom of the P-type shielding region and forming an N-type doped region in the P-type shielding region, forming a gate material layer in the trench of the gate oxide layer, and forming a closed structure with the field oxide layer and the gate oxide layer to enclose the gate material layer, a PN junction is formed between the P-type shielding region and the N-type drift region, and a PN junction is formed between the P-type shielding region and the N-type doped region, thereby increasing the depletion region area under reverse bias, thereby improving the breakdown voltage and achieving the purpose of optimizing the static quality factor. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a trench gate MOSFET provided in an embodiment of this application; Figure 2 This is a schematic diagram of the doping concentration of the trench gate MOSFET provided in the embodiments of this application; Figure 3 This is a schematic diagram of the electric field of the trench gate MOSFET provided in an embodiment of this application; Figure 4 This is a schematic diagram of the electric field distribution curve provided in an embodiment of this application; Figure 5 This is a schematic diagram of the fabrication method of the trench gate MOSFET provided in the embodiments of this application; Figure 6 This is a partial schematic diagram of the method for fabricating a trench gate MOSFET provided in an embodiment of this application; Figure 7 This is a partial schematic diagram of the method for fabricating a trench gate MOSFET provided in an embodiment of this application; Figure 8 This is a partial schematic diagram of the method for fabricating a trench gate MOSFET provided in an embodiment of this application; Figure 9 This is a partial schematic diagram of the method for fabricating a trench gate MOSFET provided in an embodiment of this application; Figure 10 This is a partial schematic diagram of the method for fabricating a trench gate MOSFET provided in an embodiment of this application; Figure 11 This is a partial schematic diagram of the method for fabricating a trench gate MOSFET provided in an embodiment of this application; Figure 12 This is a partial schematic diagram of the method for fabricating a trench gate MOSFET provided in an embodiment of this application. Detailed Implementation

[0016] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0017] Compared to conventional planar MOSFETs, TG-MOSFETs can significantly reduce the specific on-resistance of devices by accommodating more channels on a given chip area and completely eliminating the JFET effect. However, for conventional SiC trench MOSFETs in reverse blocking mode, the high electric field in the gate oxide layer at the bottom of the trench is a major problem, which causes the breakdown voltage (VBR) to be limited by gate oxide collapse at a voltage far below the inherent breakdown capability of the drift region semiconductor junction.

[0018] In an N-type epitaxial drift region of a certain thickness grown on a SiC substrate, the increased area of ​​the P-type shielding region beneath the gate oxide layer reduces the area of ​​the N-type drift region, thus reducing the area of ​​the depletion region. During reverse bias operation, although the addition of a shielding layer prevents the collapse of the gate oxide layer at the bottom of the trench and improves the device's withstand voltage through the accumulated collapse electric field of the PN junction, the optimal static quality factor (FOM = BV) for device design remains a challenge. 2 / Ron) makes the static quality factor as high as possible, and the general focus is on how to increase the breakdown voltage (BV) or reduce the on-resistance (Ron) of the device.

[0019] To address the aforementioned technical problems, this application provides a trench gate MOSFET, see [link to relevant documentation]. Figure 1 As shown, the trench gate MOSFET in this embodiment includes: a drain layer 720, a silicon carbide substrate 100, a buffer layer 200, an N-type drift region 300, a current spreading layer 511, a P-type well region 521, a gate oxide layer 610, a gate material layer 600, a P-type shielding region 400, an N-type doped region 410, an N-type heavily doped region 531, a P-type heavily doped region 532, a field oxide layer 620, a source layer 710, and a drain layer 720.

[0020] In this embodiment, the drain layer 720, silicon carbide substrate 100, buffer layer 200, and N-type drift region 300 are stacked. The N-type drift region 300 has a concave structure, and a current spreading layer 511 and a P-type well region 521 are sequentially formed on the first and second sides of the N-type drift region 300. A P-type shielding region 400 is formed at the bottom of the groove of the N-type drift region 300, and an N-type doped region 410 is formed inside the P-type shielding region 400. A PN junction is formed at the boundary between the N-type doped region 410 and the P-type shielding region 400. The gate oxide layer 610 has a concave structure, and the gate oxide layer 610 and the field oxide layer 620 form a closed structure that encloses the gate material layer 600. The P-type heavily doped region 532 is located on the P-type well region 521 and next to the N-type heavily doped region 531. The main function of the P-type heavily doped region 532 is to connect the P-type well region 521 and reduce the ohmic contact resistance between it and the source contact.

[0021] The spacing between the two sides of the gate oxide layer 610 gradually increases from the bottom to the opening. The height of the gate oxide layer 610 is greater than the sum of the heights of the current extension layer 511 and the P-type well region 521. The source layer 710 is in contact with the P-type well region 521, the N-type heavily doped region 531, the two sides of the gate oxide layer 610, and the field oxide layer 620.

[0022] In the trench gate MOSFET of this embodiment, an innovative structure is formed on the bottom of the gate oxide layer 610 with a concave trench on the P-type shielding region 400, and an N-type doped region 410 is formed in the P-type shielding region 400. The N-type doped ions are implanted into the central region of the P-type shielding region 400 at the bottom center of the trench of the SiC trench gate MOSFET device, and two new PN junctions are formed on both sides of the central region of the P-type shielding region 400. A PN junction is formed between the P-type shielding region 400 and the N-type drift region 300, and another PN junction is formed between the P-type shielding region 400 and the N-type doped region 410. During the turn-on process of the T-MOSFET device with a forward bias applied to the gate, the novel structure formed by the N-type doped ions implanted in the region within the P-type shielding region 400 does not affect the JFET region and the N-type drift region in the original device structure. Therefore, it does not cause any impact deterioration to the device's on-resistance or the gate charge Qg generated during high-frequency operation. In the turn-off process of the novel T-MOSFET device in this embodiment, the reverse bias caused by the positive voltage applied to the drain is increased by the PN junction formed in the region within the P-type shielding region 400, which provides more depletion region area to improve the breakdown electric field that the device can withstand, thereby improving the device's withstand voltage and reliability.

[0023] The P-type shielding region 400 contacts the bottom edge region of the gate oxide layer 610. The gate material layer 600 is formed within the groove of the gate oxide layer 610. The field oxide layer 620 and the gate oxide layer 610 form a closed structure enclosing the gate material layer 600. In this embodiment, by improving the device's breakdown voltage, the epitaxial thickness can be reduced if a fixed breakdown voltage is maintained in the epitaxial design, effectively reducing the device's epitaxial cost. For the cost required for mass production, the cost of reducing the epitaxial thickness is less than the cost of adding an additional N-type nitrogen ion implantation process. Therefore, it helps reduce device development and mass production costs. Furthermore, this novel T-MOSFET device structure design can effectively improve the static quality factor. For example, taking a 1200V device as an example, the trench gate MOSFET optimization characteristics in this embodiment are estimated to be over 23%.

[0024] Combination Figure 2 As shown, with Figure 2 The structural schematic diagram (a) is the reference structure diagram, in which nitrogen-free ions are implanted into the SiC surface adjacent to the gate oxide layer 610 at the bottom of the trench. The schematic diagram (d) is a comparison of the depth concentration distribution curves of the doped activated ions in the reference structure.

[0025] See Figure 2The structural schematic diagrams (b) and (c) clearly show the N-type doped region 410 formed within the P-type shielding region 400. Schematic diagrams (e) and (f) show the depth concentration distribution curves of the doped activated ions in structural schematic diagrams (b) and (c), respectively. There is an N-type activated nitrogen ion concentration distribution below the center of the gate oxide layer 610 at the bottom of the trench.

[0026] Figure 2 The schematic diagram (e) shows the depth concentration distribution curves of activated P-type aluminum ions (Al), N-type nitrogen atoms (N), and net doped activated ions (J) in the region below the center of the gate oxide layer at the bottom of the trench in the structural schematic diagram (b). The schematic diagram (f) shows the depth concentration distribution curves of activated P-type aluminum ions (Al), N-type nitrogen atoms (N), and net doped activated ions (J) in the region below the center of the gate oxide layer 610 at the bottom of the trench in the structural schematic diagram (c).

[0027] Comparing the curve distributions in schematic diagrams (e) and (f), it is clear that in schematic diagrams (b) and (c), there is a PN junction at the junction of the bottom of the P-type shielding region 400 and the N-type drift region 300. When the device is under reverse bias operation, the depletion region will extend and expand from this point to both sides in the upward and downward directions. The lower epitaxial N-type concentration is lower, so the depletion region area is larger than that of the upper P-type shielding region 400. Compared with schematic diagram (d), schematic diagrams (e) and (f) clearly show that another PN junction appears in the central region within the P-type shielding region 400. This will cause the depletion regions near the two PN junctions to extend upwards and downwards respectively under reverse bias operation. The concentration of N-type doped ions epitaxially below the P-type shielding region 400 (i.e., the N-type drift region 300 near the lower side of the P-type shielding region 400) is lower, so the area of ​​the depletion region is larger than that of the depletion region within the P-type shielding region 400. By increasing the area of ​​the depletion region, the breakdown voltage (i.e., the breakdown voltage) is improved, thereby achieving the goal of optimizing the static quality factor.

[0028] Taking N-type doped ions (including nitrogen ions) as an example and P-type doped ions (including aluminum ions) as an example, let's compare... Figure 2 As shown in the structural schematics (b) and (c), as the implantation energy of N-type doped ions increases, their implantation depth moves towards the bottom of the P-type shielding region 400, and the doping concentration of nitrogen and aluminum ions corresponding to the PN junction is relatively shallow (as shown by point A in schematic (f)). This indicates that the device has a larger charge depletion area during reverse bias operation, which helps to further improve the breakdown voltage and further achieve the goal of improving and optimizing the static quality factor.

[0029] In some embodiments, Figure 3 The schematic structure (a) in the diagram is the reference structure (BSL). Under reverse bias operation of the device, Figure 3 In the schematic structures (b) and (c), the electric field near the PN junction inside the P-type shielding region 400 is significantly increased. Furthermore, as shown... Figure 3 As shown in schematic structures (a) and (b), the maximum electric field distribution in the N-type drift region (as shown by the red curve in schematic graph (d)) is located at the PN junction interface below the P-type shielding region. When the nitrogen ion injection energy is increased to form a structure as shown in schematic structure (c), the location of the maximum electric field in the PN junction interface region below the N-type drift region and the P-type shielding region shifts upwards towards the gate oxide layer at the bottom of the trench, and the maximum electric field value increases from the original 3.05E6 V / cm (as shown by the green curve in schematic graph (d)) to 3.15E6 V / cm (as shown by the blue curve in schematic graph (d)). This further expands the area under the electric field distribution curve, thus significantly increasing the breakdown voltage that the device can withstand.

[0030] Combination Figure 4 As shown, when the implantation energy remains constant, a further increase in the nitrogen ion implantation dose, from 1.8E14 to 2.7E14, causes the P-type shielding region below the gate oxide layer at the bottom center of the trench to transform into an N-type region. This results in the gate oxide layer at this location no longer being protected by the P-type shielding region, causing the original cumulative collapse mechanism to transform into oxide layer collapse, leading to a significant decrease in BV. Since nitrogen ion implantation does not affect the JFET regions flowing to both sides of the trench or the N-type drift region when the device is forward-biased, the on-state voltage (Ron) and Qg do not change significantly, and therefore, there is no deterioration in the dynamic quality factor.

[0031] In some embodiments, combined with Figure 1 As shown, the gate oxide layer 610 has a concave structure, and the vertical cross-section of the outer side surface of the gate oxide layer 610 can be stepped.

[0032] In this embodiment, the outer surface of the first side of the gate oxide layer 610 contacts the current spreading layer 511, the P-type well region 521, and the heavily doped N-type region 531 on the first side of the N-type drift region 300. The outer surface of the first side of the gate oxide layer 610 can be stepped. The outer surface of the second side of the gate oxide layer 610 contacts the current spreading layer 511, the P-type well region 521, and the heavily doped N-type region 531 on the second side of the N-type drift region 300. The outer surface of the second side of the gate oxide layer 610 is also stepped. This allows for a gradual reduction in the width of the trench gate, minimizing the width of the central oxide layer at the bottom, which helps reduce the gate leakage charge Qgd of the device.

[0033] In some embodiments, the gate oxide layer 610 has a concave structure, and the vertical cross-section of the outer side surface of the gate oxide layer 610 is arc-shaped.

[0034] In this embodiment, the outer surface of the first side of the gate oxide layer 610 contacts the first side of the N-type drift region 300 and the current spreading layer 511, P-type well region 521, and N-type heavily doped region 531 thereon. The outer surface of the first side of the gate oxide layer 610 is arc-shaped. The outer surface of the second side of the gate oxide layer 610 contacts the second side of the N-type drift region 300 and the current spreading layer 511, P-type well region 521, and N-type heavily doped region 531 thereon. The outer surface of the second side of the gate oxide layer 610 is arc-shaped. In this way, the interface between the two sides of the gate oxide layer 610 and the contacting areas can change slowly and continuously, eliminating doping corners, avoiding electric field accumulation, and facilitating the gradual reduction of the trench gate width, so that the width of the central oxide layer at the bottom is minimized, which is beneficial to reducing the gate leakage charge Qgd of the device.

[0035] In some embodiments, the width of the P-type shielding region 400 is less than or equal to the width of the bottom of the gate oxide layer 610.

[0036] In some embodiments, a plurality of N-type doped regions 410 may be formed within the P-type shielding region 400, and the plurality of N-type doped regions 410 are opposite to the gate material layer.

[0037] In some embodiments, the width of the P-type shielding region 400 gradually decreases in the direction from the drain layer 720 to the source layer 710.

[0038] In some embodiments, the width of the N-type doped region 410 gradually decreases from the source layer 710 toward the drain layer 720.

[0039] In some embodiments, the doping density of the N-type doped region 410 gradually decreases from the source layer 710 toward the drain layer 720.

[0040] In some embodiments, the distance between the outer edge of the N-type doped region 410 and the P-type shielding region 400 is greater than the thickness of the gate oxide layer 610.

[0041] In some embodiments, the gate oxide layer 610 has a concave structure, the inner wall of the groove of the gate oxide layer 610 is arc-shaped, and the bottom of the gate oxide layer 610 is arc-shaped.

[0042] In this embodiment, the inner wall of the groove of the gate oxide layer 610 is in contact with the gate material layer 600. By setting the inner wall of the groove of the gate oxide layer 610 to be arc-shaped, the angle change of the interface between the gate oxide layer 610 and the gate material layer 600 can be reduced, the electric field accumulation in the N-type drift region 300 can be reduced, and the width of the trench gate can be reduced step by step, so that the width of the central oxide layer at the bottom is minimized, which is beneficial to reducing the gate leakage charge Qgd of the device.

[0043] In some embodiments, isolation protective layers may be provided at the two bottom corners of the gate oxide layer 610, respectively. The isolation protective layers are respectively attached to the bottom sides of the gate oxide layer 610, and the interface between the isolation protective layer and the N-type drift region 300 is arc-shaped.

[0044] In this embodiment, the width of the gate oxide layer 610 gradually increases from the drain layer 720 to the source layer 710. The bottom of the gate oxide layer 610 is close to the drain layer 720. By setting the interface between the isolation protection layer and the N-type drift region 300 to be arc-shaped, the angle change of the interface between the gate oxide layer 610 and the N-type drift region 300 can be reduced, the electric field accumulation in the N-type drift region 300 can be reduced, and the width of the trench gate can be reduced step by step, so that the width of the central oxide layer at the bottom is minimized, which is beneficial to reducing the gate drain charge Qgd of the device.

[0045] In some embodiments, the gate oxide layer 610 has a concave structure, and the first side and the second side of the gate oxide layer 610 extend outward at their opening positions, respectively. The left extension portion does not exceed the left boundary of the left N-type heavily doped region 531, and the right extension portion does not exceed the right boundary of the right N-type heavily doped region 531.

[0046] In some embodiments, the thickness of the gate oxide layer 610 gradually increases from the drain layer 720 toward the source layer 710, thereby increasing the electric field distribution in the current spread layer 511, P-type well region 521, N-type heavily doped region 531, and N-type heavily doped region 531. This helps to reduce the electric field accumulation in the N-type drift region 300 and also facilitates the gradual reduction of the trench gate width, minimizing the width of the central oxide layer at the bottom, which helps to reduce the gate drain charge Qgd of the device.

[0047] In some embodiments, the width between the two sidewalls of the gate oxide layer 610 gradually increases from the drain layer 720 toward the source layer 710, thereby the electric field distribution in the current spread layer 511, P-type well region 521, N-type heavily doped region 531, and N-type heavily doped region 531 is beneficial to reduce the electric field accumulation in the N-type drift region 300, and can also facilitate the gradual reduction of the trench gate width, so that the width of the bottom central oxide layer is minimized, which is beneficial to reduce the gate drain charge Qgd of the device.

[0048] In some embodiments, the thickness of the isolation protection layer gradually decreases in the longitudinal direction from the drain layer 720 to the source layer 710. This helps to reduce the electric field accumulation in the N-type drift region 300 and also facilitates the gradual reduction of the width of the trench gate, so that the width of the central oxide layer at the bottom is minimized, which helps to reduce the gate drain charge Qgd of the device.

[0049] In some embodiments, the gate oxide layer 610 has a concave structure, the inner wall of the groove of the gate oxide layer 610 is stepped, and the bottom of the gate oxide layer 610 is arc-shaped.

[0050] In some embodiments, the protective layer may be a silicon oxide layer.

[0051] In some embodiments, the gate oxide layer 610 has a symmetrical structure.

[0052] In some embodiments, the interface between the gate oxide layer 610 and the gate material layer 600 is stepped.

[0053] In this embodiment, the inner diameter of the groove in the gate oxide layer 610 gradually decreases from the source layer 710 to the drain layer 720, and the inner wall of the groove in the gate oxide layer 610 has a stepped structure.

[0054] In some embodiments, the two sides of the gate oxide layer 610 have a stepped structure.

[0055] In this embodiment, the inner wall of the groove of the gate oxide layer 610 has a stepped structure, and the outer surfaces of both sides of the gate oxide layer 610 also have a stepped structure.

[0056] In some embodiments, the two sides of the gate oxide layer 610 have a multi-level stepped structure. The boundary of the isolation protective layer on the first side of the gate oxide layer 610 is flush with the boundary of the middle step on the first side of the gate oxide layer 610, so that the shape of the first side of the isolation protective layer matches that of the gate oxide layer 610, and avoids the formation of corners between the isolation protective layer and the bottom of the first side of the gate oxide layer 610, which would cause electric field accumulation.

[0057] In some embodiments, the isolation protective layer located on the second side of the gate oxide layer 610 is flush with the boundary of the intermediate step on the second side of the gate oxide layer 610, so that the isolation protective layer located on the second side of the gate oxide layer 610 matches the shape of the gate oxide layer 610, and avoids the formation of corners between the isolation protective layer and the bottom of the second side of the gate oxide layer 610, which would cause electric field accumulation.

[0058] In some embodiments, combined with Figure 1 As shown, the two ends of the P-type shielding region 400 are attached to the bottom sides of the gate oxide layer 610 at the bottom of the trench. The P-type shielding region 400 is arc-shaped, and the two ends of the P-type shielding region 400 are respectively attached to the isolation protection layer on the bottom sides of the gate oxide layer 610. This can further reduce the electric field concentration effect in the bottom corner area of ​​the gate, avoid high electric field collapse, reduce the gate leakage current phenomenon of the device, and improve the reliability of the device.

[0059] In some embodiments, the top of the first-side step of the gate oxide layer 610 is formed on the upper surface of the N-type heavily doped region 531 on the first side.

[0060] In this embodiment, the first side of the gate oxide layer 610 has a stepped structure. The lower surface of the top of the first step of the gate oxide layer 610 is in contact with the upper surface of the N-type heavily doped region 531, and the top of the first step of the gate oxide layer 610 is not in contact with the P-type well region 521.

[0061] In some embodiments, the top of the second-side step of the gate oxide layer 610 is formed on the upper surface of the N-type heavily doped region 531 on the second side.

[0062] In this embodiment, the second side of the gate oxide layer 610 has a stepped structure. The lower surface of the top of the second step of the gate oxide layer 610 is in contact with the upper surface of the N-type heavily doped region 531 on the second side, and the top of the second step of the gate oxide layer 610 is not in contact with the P-type well region 521 on the second side.

[0063] In some embodiments, the interface between the gate material layer 600 and the field oxide layer 620 is arc-shaped, with the apex of the arc close to the P-type shielding region 400.

[0064] In some embodiments, the P-type well region 521 has an L-shaped structure; the N-type heavily doped region 531 is formed on the horizontal portion of the P-type well region 521.

[0065] In this embodiment, an N-type heavily doped region 531 in contact with the first side of the gate oxide layer 610 is formed by implanting N-type dopant ions into the region of the first P-well region 251 near the gate oxide layer 610, and an N-type heavily doped region 531 in contact with the second side of the gate oxide layer 610 is formed by implanting N-type dopant ions into the region of the second P-well region 252 near the gate oxide layer 610, thereby forming an L-shaped P-well region 521.

[0066] In some embodiments, the doping concentration of the P-type shielding region 400 exhibits a gradient distribution.

[0067] This application also provides a method for fabricating a trench gate MOSFET, which is used to fabricate the trench gate MOSFET in any of the above embodiments. See [link to previous document]. Figure 5 As shown, the preparation method in this embodiment includes steps S100 to S800.

[0068] In step S100, combined Figure 6 As shown, a buffer layer 200, an N-type drift region 300, a current spreading layer 510, a P-type well doped layer 520, and an N-type doped layer 530 are sequentially formed on the front side of the silicon carbide substrate 100. Under the cover of the first mask 101, a first trench extending into the N-type drift region 300 is formed by etching along the central region of the N-type doped layer 530.

[0069] In this embodiment, combined with Figure 6As shown in the schematic structure (a), the P-type well doped layer 520 has a concave structure, and the N-type doped layer 530 is located in the groove of the P-type well doped layer 520. Under the cover of the first mask 101, a first trench is etched along the central region of the N-type doped layer 530, extending into the N-type drift region 300. The first trench divides the current spreading layer 510 into left and right opposite current spreading layers 511, divides the P-type well doped layer 520 into left and right opposite P-type well regions 521, and divides the N-type doped layer 530 into left and right heavily doped N-type regions 531. The heavily doped P-type region 532 is located on the P-type well region 521 and is located beside the heavily doped N-type region 531. Figure 6 The schematic structure (b) is shown in the figure.

[0070] In some embodiments, N-type dopant ions can be sequentially implanted onto the front side of the silicon carbide substrate 100 via epitaxial growth or ion implantation to form a buffer layer 200, an N-type drift region 300, and a current spreading layer 510. Then, P-type dopant ions are implanted to form a P-type well doped layer 520, and N-type dopant ions are implanted into a predetermined region of the P-type well doped layer 520 to form an N-type doped layer 530. Figure 2 The schematic structure (a) is shown in the figure.

[0071] In step S200, combined Figure 6 As shown, the first mask 101 is removed, and the first dielectric material 621 is filled into the first trench.

[0072] In this embodiment, the first dielectric material 621 covers the surface areas of the first trench, the P-type well region 521, and the N-type heavily doped region 531.

[0073] In step S300, combined Figure 7 As shown, a second mask 102 is applied to the first dielectric material 621, and the first dielectric material 621 is etched according to the pattern of the second mask 102 to form a first dielectric material layer 622 at the bottom and sidewalls of the first trench, as shown. Figure 7 The schematic structure (b) is shown in the figure. Then the second mask 102 is removed, as shown in the figure. Figure 7 The schematic structure (c) is shown in the figure.

[0074] In this embodiment, the thickness of the first dielectric material layer 622 is less than the thickness of the current spreading layer 511.

[0075] In some embodiments, the thickness of the first dielectric material layer 622 is less than 1 μm.

[0076] In step S400, combined Figure 8As shown, P-type doped ions are injected along the trench direction of the first trench, so that the P-type doped ions pass through the first dielectric material layer 622 to form a P-type shielding region 400 within the N-type drift region 300, as shown. Figure 8 The schematic structure is shown in (a).

[0077] In step S500, the first dielectric material 623 is deposited to cover the first trench, as follows: Figure 8 As shown in schematic structure (b), a third mask 103 is covered on the first dielectric material 623, as follows. Figure 8 As shown in schematic structure (c), the first dielectric material 623 is etched according to the pattern of the second mask to form a second dielectric material layer 624 at the bottom and sidewalls of the first trench, as follows. Figure 9 The schematic structure is shown in (a).

[0078] In this embodiment, the thickness of the second dielectric material layer 624 is greater than the thickness of the first dielectric material layer 622.

[0079] In step S600, the third mask 103 is removed, as follows: Figure 9 As shown in schematic structure (b), N-type doped ions are then injected along the trench direction of the first trench, so that the N-type doped ions pass through the second dielectric material layer 624 to form an N-type doped region 410 within the P-type shielding region 400, as shown in the schematic structure (b). Figure 9 The schematic structure (c) is shown in the middle.

[0080] In this embodiment, since the thickness of the second dielectric material layer 624 is greater than the thickness of the first dielectric material layer 622, after the inner wall of the first trench is covered by the second dielectric material layer 624, its ion implantation width becomes smaller, thereby the area for implanting N-type doped ions is smaller, making the distance between the outer edge of the N-type doped region 410 and the P-type shielding region 400 greater than a certain threshold.

[0081] In some embodiments, the doping concentration of the P-type shielding region 400 exhibits a gradient distribution.

[0082] In some embodiments, the closer a region within the P-type shielding region 400 is to the N-type doped region 410, the higher its doping concentration.

[0083] In step S700, the second dielectric material layer is removed, such as... Figure 10 As shown in schematic structure (a), the P-type shielding region 400 and the N-type doped region 410 are activated.

[0084] In this embodiment, annealing can be used to activate the dopant ions in the P-type shielding region 400 and the N-type doped region 410, so that a PN junction is formed at the junction of the P-type shielding region 400 and the N-type doped region 410.

[0085] In some embodiments, the second dielectric material layer 624 may be silicon oxide.

[0086] In step S800, a gate oxide layer 610 is formed at the bottom and sidewalls of the first trench, such as... Figure 10 The schematic structure (b) is shown in the diagram. Combined with... Figure 11 As shown, a gate material layer 600 is formed by filling polysilicon material, and a field oxide layer 620 is formed on the gate material layer 600. Then, a source material is deposited to form a source layer 710 that contacts the P-type well region 521, the N-type heavily doped region 531, the two sides of the gate oxide layer 610, and the field oxide layer 620.

[0087] In this embodiment, the field oxide layer 620 and the gate oxide layer 610 form a closed structure that encloses the gate material layer 600.

[0088] In some embodiments, combined with Figure 10 As shown in schematic structures (b) and (c), after etching away the second dielectric material layer 624, a gate oxide layer 610 can be formed on the device surface, the bottom of the trench, and the inner wall by a thermal oxidation process, and an N-type polysilicon material can be deposited to form a gate material layer 600 as shown in schematic structure (c). The N-type polysilicon material outside the trench is removed by an etching process, as shown in schematic structure (c). Figure 11 As shown in the schematic structure (a), a field oxide layer 620 is formed by depositing field oxide material, as shown in the figure. Figure 11 As shown in the schematic structure (b), the field oxide layer 620 and the gate oxide layer 610 are etched under the cover of the fourth mask 104, as follows. Figure 11 The schematic structure (c) in the diagram and as shown in the diagram Figure 12 As shown in the schematic structure (a), after etching is completed, the fourth mask 104 is removed.

[0089] This application also provides a chip including a trench gate MOSFET as described in any of the above embodiments.

[0090] In this embodiment, the chip includes a chip substrate, and the trench gate MOSFET can be disposed on the chip substrate as described in any of the above embodiments.

[0091] In one specific application embodiment, other related semiconductor devices can also be integrated on the chip substrate to form an integrated circuit with the trench gate MOSFET.

[0092] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0093] The beneficial effects of the embodiments of this application are as follows: by forming a gate oxide layer with concave trenches on the bottom of the P-type shielding region and forming an N-type doped region in the P-type shielding region, forming a gate material layer in the trench of the gate oxide layer, and forming a closed structure with the field oxide layer and the gate oxide layer to enclose the gate material layer, a PN junction is formed between the P-type shielding region and the N-type drift region, and a PN junction is formed between the P-type shielding region and the N-type doped region, thereby increasing the depletion region area under reverse bias, thereby improving the breakdown voltage and achieving the purpose of optimizing the static quality factor.

[0094] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0095] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0096] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0097] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0098] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A trench gate MOSFET, characterized in that, The trench gate MOSFET includes: A silicon carbide substrate and a buffer layer, wherein the buffer layer is formed on the front side of the silicon carbide substrate; An N-type drift region with concave grooves is formed on the buffer layer; A current spreading layer is formed on both sides of the N-type drift region; A P-type well region is formed on the current spreading layer; A P-type shielding region is formed at the bottom of the groove in the N-type drift region; wherein at least one N-type doped region is formed within the P-type shielding region. A gate oxide layer with concave trenches is formed on the P-type shielding region, and the height of the gate oxide layer is greater than the sum of the heights of the current spreading layer and the P-type well region; The N-type heavily doped region is formed on the P-type well region and located on both sides of the gate oxide layer; A p-type heavily doped region is formed on the p-type well region and located next to the n-type heavily doped region; A gate material layer is formed within a groove in the gate oxide layer; A field oxide layer, together with the gate oxide layer, forms a closed structure that encloses the gate material layer; The source layer is in contact with the P-type well region, the N-type heavily doped region, both sides of the gate oxide layer, and the field oxide layer; A drain layer is formed on the back side of the silicon carbide substrate.

2. The trench gate MOSFET as described in claim 1, characterized in that, The P-type shielding area has a concave or arc-shaped structure.

3. The trench gate MOSFET as described in claim 1, characterized in that, The width of the P-type shielding region gradually increases from the drain layer to the source layer.

4. The trench gate MOSFET as claimed in claim 1, characterized in that, The width of the P-type shielding region is smaller than the width of the bottom of the gate oxide layer.

5. The trench gate MOSFET as claimed in claim 1, characterized in that, The N-type doped region is opposite to the gate material layer.

6. The trench gate MOSFET as claimed in claim 1, characterized in that, The doping density of the N-type doped region gradually decreases from the source layer to the drain layer.

7. The trench gate MOSFET according to any one of claims 1-6, characterized in that, The distance between the outer edge of the N-type doped region and the P-type shielding region is greater than the thickness of the gate oxide layer.

8. The trench gate MOSFET according to any one of claims 1-6, characterized in that, The doping concentration of the P-type shielding region exhibits a gradient distribution.

9. A method for fabricating a trench gate MOSFET, characterized in that, The preparation method includes: A buffer layer, an N-type drift region, a current spreading layer, a P-type well doped layer, an N-type doped layer, and a heavily P-type doped region are sequentially formed on the front side of a silicon carbide substrate. Under the cover of a first mask, a first trench is etched along the central region of the N-type doped layer to penetrate into the N-type drift region. The first trench divides the current spreading layer into oppositely arranged current spreading layers, the P-type well doped layer into oppositely arranged P-type well regions, and the N-type doped layer into oppositely arranged heavily N-type doped regions. The heavily P-type doped region is located on the P-type well region and is located next to the heavily N-type doped region. Remove the first mask and fill the first trench with a first dielectric material; wherein the first dielectric material covers the surface areas of the first trench and the P-type well region and the N-type heavily doped region; A second mask is applied to the first dielectric material, and the first dielectric material is etched according to the pattern of the second mask to form a first dielectric material layer at the bottom and sidewalls of the first trench; wherein the thickness of the first dielectric material layer is less than the thickness of the current spreading layer. P-type doped ions are injected along the trench direction of the first trench, so that the P-type doped ions pass through the first dielectric material layer to form a P-type shielding region in the N-type drift region. The first dielectric material is deposited to cover the first trench, a third mask is deposited on the first dielectric material, and the first dielectric material is etched according to the pattern of the second mask to form a second dielectric material layer at the bottom and sidewalls of the first trench; wherein the thickness of the second dielectric material layer is greater than the thickness of the first dielectric material layer. N-type doped ions are injected along the trench direction of the first trench, so that the N-type doped ions pass through the second dielectric material layer to form an N-type doped region in the P-type shielding region. Remove the second dielectric material layer and activate the P-type shielding region and the N-type doped region; A gate oxide layer is formed at the bottom and sidewalls of the first trench, a gate material layer is formed by filling it with polysilicon material, and a field oxide layer is formed on the gate material layer. Then, a source material is deposited to form a source layer that contacts the P-type well region, the N-type heavily doped region, both sides of the gate oxide layer, and the field oxide layer. The field oxide layer and the gate oxide layer form a closed structure that encloses the gate material layer.

10. A chip, characterized in that, Including the trench gate MOSFET as described in any one of claims 1-8.

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