SONOS memory and manufacturing method thereof
By employing an asymmetric structure in the selector threshold voltage regulation region of the SONOS memory, the problems of GIDL leakage and channel control capability were solved, thereby optimizing memory performance and controlling costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2026-03-13
AI Technical Summary
Existing SONOS memories suffer from severe gate-induced drain leakage (GIDL) during process node shrinkage, which affects memory performance. Furthermore, the existing asymmetric threshold voltage regulation region may reduce channel control capability.
The selector transistor threshold voltage adjustment region employs an asymmetric structure. By forming asymmetric first and second threshold voltage injection regions in the semiconductor substrate, combined with an improved process defined by the photomask, the channel leakage current and GIDL leakage current of the selector transistor are adjusted, thereby increasing the channel control capability.
It effectively reduces GIDL leakage current while maintaining or improving channel control capabilities, reduces process costs, and achieves performance optimization on existing platforms, making it suitable for mass production.
Smart Images
Figure CN121665638A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a silicon-oxygen-nitrogen-oxygen-silicon (SONOS) memory. This invention also relates to a method for manufacturing a SONOS memory. Background Technology
[0002] like Figure 1 The diagram shows a schematic of the storage transistor in a conventional SONOS memory. Unlike floating-gate memory, which stores charge in a polysilicon floating gate, the most significant feature of SONOS memory is that the semiconductor substrate 101 and the polysilicon gate 103 are separated by an ONO stacked gate structure 102. From bottom to top, the ONO stacked gate structure 102 consists of a silicon dioxide tunneling layer 102a, a silicon nitride storage layer 102b, and a silicon dioxide blocking layer 102c. Charge is stored in the silicon nitride storage layer 102b within the ONO stacked gate structure 102. The polysilicon gate 103 and the ONO stacked gate structure 102 together form the gate structure 104. A sidewall 105 is formed on the side of the gate structure 104, and a lightly doped drain region 106 self-aligned with the side of the gate structure 104 is formed in the semiconductor substrate 101 on both sides of the gate structure 104; a heavily doped source region 107 and a drain region 108 self-aligned with the corresponding sidewall 105 are formed in the semiconductor substrate 101 on both sides of the gate structure 104.
[0003] SONOS uses a thinner tunnel oxide layer, i.e. Figure 1 The silicon dioxide tunneling layer 102a shown has superior characteristics such as fast write / erase speed, low voltage required for programming / erase, and low power consumption. Its good compatibility with CMOS device processes makes the cost of embedding memory IP low, and it is recognized as one of the most valuable memory technologies in the industry.
[0004] A 2-transistor (2T) SONOS memory cell consists of a storage transistor and a select transistor, exhibiting excellent scalability. Size reduction allows for lower programming / erase voltages, increased programming / erase speeds, and higher storage density. However, during process development, miniaturization introduces significant gate-induced drain (GIDL) leakage. For example, as process nodes shrink, a 20%-40% reduction in gate length, gate oxide thickness, and side gate width (all strongly correlated with GIDL) can lead to a 1-2 order of magnitude increase in GIDL leakage in SONOS memory cells. Therefore, new structures or process parameters are needed to improve the storage performance of small-size SONOS memories. Summary of the Invention
[0005] The technical problem to be solved by this invention is to provide a SONOS memory that can realize an asymmetric structure of the threshold voltage adjustment region of the select transistor, thereby reducing the GIDL leakage current of the device; at the same time, it can also realize independent adjustment of the doping of the threshold voltage injection region located in the channel region, thereby increasing the channel control force, effectively reducing the channel leakage current, and preventing the channel leakage current from increasing when reducing the GIDL leakage current of the device through the asymmetric threshold voltage adjustment region. To this end, this invention also provides a method for manufacturing a SONOS memory.
[0006] To solve the above-mentioned technical problems, the SONOS memory provided by the present invention includes a selection tube and a storage tube in its storage unit.
[0007] In the memory cell, the first gate structure of the select transistor and the second gate structure of the memory transistor are both formed on the top surface of the cell well region doped with the second conductivity type, and the cell well region is formed in a selected region of the semiconductor substrate.
[0008] The threshold voltage adjustment region of the selector transistor has an asymmetrical structure, and the threshold voltage adjustment region includes:
[0009] A first threshold voltage injection region doped with a second conductivity type is formed in a surface region of a selected area of the unit well region. The formation region of the first threshold voltage injection region is located in the formation region of the select transistor and includes at least the region covered by the first gate structure.
[0010] A second threshold voltage injection region, doped with a second conductivity type, is formed in a selected area of the surface region of the unit well region. The formation region of the second threshold voltage injection region is located in the formation region of the source region of the select transistor and is self-aligned with the first side of the first gate structure. The first side of the first gate structure is the side adjacent to the source region of the select transistor.
[0011] A further improvement is that the first gate structure includes a first gate dielectric layer and a first polysilicon gate stacked sequentially.
[0012] The second gate structure includes a silicon dioxide tunneling layer, a silicon nitride storage layer, a silicon dioxide barrier layer, and a second polysilicon gate, which are stacked sequentially.
[0013] A further improvement is that the memory cell includes a first source / drain region, a second source / drain region, and a third source / drain region heavily doped with a first conductivity type.
[0014] The first source-drain region serves as the drain region of the storage transistor, the second source-drain region serves as both the source region of the storage transistor and the drain region of the select transistor, and the third source-drain region serves as the source region of the select transistor.
[0015] A further improvement is that two adjacent storage cells form a storage cell combination.
[0016] In the memory cell combination, the two first gate structures share a third source-drain region.
[0017] The formation region of the first threshold voltage injection region includes the formation regions of the two first gate structures and the formation region of the third source / drain region.
[0018] A further improvement is that, in the memory cell assembly, an active electrode line is also formed on top of the third source-drain region.
[0019] The second threshold voltage injection region of the two memory cells is located in the surface region of the cell well region between the source line and the first gate structures on both sides.
[0020] The first threshold voltage injection regions of the two memory cells are integral structures and located in the surface region of the cell well region between the second sides of the two first gate structures, wherein the second side of the first gate structure is a side adjacent to the drain region of the select transistor.
[0021] A further improvement is that the source wire is made of polycrystalline silicon.
[0022] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type.
[0023] The injected impurities in the unit well region include boron or boron fluoride.
[0024] The injected impurities in the first threshold voltage injection region include boron or boron fluoride.
[0025] The injected impurities in the second threshold voltage injection region include boron or boron fluoride.
[0026] The injection dose in the unit well region is an order of magnitude smaller than the injection dose in the first threshold voltage injection region.
[0027] The injection dose in the first threshold voltage injection region and the injection dose in the second threshold voltage injection region are of the same order of magnitude.
[0028] To solve the above-mentioned technical problems, the manufacturing method of the SONOS memory provided by the present invention includes a selection transistor and a storage transistor in the memory cell; and includes the following forming steps:
[0029] A second conductivity type doped cell well region is formed in a selected region of the semiconductor substrate; in the memory cell, the formation regions of the select transistor and the memory transistor are both located on the cell well region.
[0030] Photolithography opens a first opening region, which defines the formation region of a first threshold voltage injection region. The formation region of the first threshold voltage injection region is located in the formation region of the select transistor and includes at least the region covered by the first gate structure of the select transistor.
[0031] A first threshold voltage injection is performed to dope with a second conductivity type, and a first threshold voltage injection region is formed in the surface region of the unit well region of the first opening region.
[0032] A gate structure is formed on the top surface of the cell well region, the gate structure including a first gate structure of the select transistor and a second gate structure of the memory transistor.
[0033] Photolithography opens a second opening region, which exposes the formation region of the first gate structure and the formation region of the second threshold voltage injection region, the formation region of the second threshold voltage injection region being located in the formation region of the source region of the select transistor.
[0034] A second threshold voltage injection is performed to dope with a second conductivity type, and a second threshold voltage injection region is formed in the surface region of the cell well region in the second opening region and not covered by the first gate structure. The second threshold voltage injection region and the side of the source region of the first gate structure are self-aligned.
[0035] The second threshold voltage injection region is located in the cell well region on the source region side of the formation region of the select transistor and is self-aligned with the first side surface of the select transistor. The first side surface of the first gate structure is the side surface adjacent to the source region of the select transistor. The first threshold voltage injection region and the second threshold voltage injection region form part of the threshold voltage adjustment region of the select transistor, and the threshold voltage adjustment region of the select transistor has an asymmetrical structure.
[0036] A further improvement is that the first gate structure includes a first gate dielectric layer and a first polysilicon gate stacked sequentially.
[0037] The second gate structure includes a silicon dioxide tunneling layer, a silicon nitride storage layer, a silicon dioxide barrier layer, and a second polysilicon gate, which are stacked sequentially.
[0038] A further improvement is that the first opening region and the second opening region use the same photomask definition.
[0039] A further improvement is that, after the gate structure is formed, it further includes:
[0040] Source-drain regions, a first source-drain region, and a second source-drain region are formed in the formation region of the memory cell by performing source-drain injection with heavy doping of the first conductivity type.
[0041] The first source-drain region serves as the drain region of the storage transistor, the second source-drain region serves as both the source region of the storage transistor and the drain region of the select transistor, and the third source-drain region serves as the source region of the select transistor.
[0042] A further improvement is that two adjacent storage cells form a storage cell combination.
[0043] In the memory cell combination, the two first gate structures share a third source-drain region.
[0044] The formation region of the first threshold voltage injection region includes the formation regions of the two first gate structures and the formation region of the third source / drain region.
[0045] A further improvement is that, in the memory cell assembly, an active electrode line is also formed on top of the third source-drain region.
[0046] The first opening regions of the two memory cells are merged together and located between the second sides of the two first gate structures, the second sides of the first gate structures being the sides adjacent to the drain region of the select transistor.
[0047] The second threshold voltage injection region of the two memory cells is located in the surface region of the cell well region between the source line and the first gate structures on both sides.
[0048] The first threshold voltage injection regions of the two memory cells are integral structures and located in the surface region of the cell well region between the second sides of the two first gate structures.
[0049] A further improvement is that the source wire is made of polycrystalline silicon.
[0050] A further improvement is that the first threshold voltage injection region is used to adjust the channel leakage current of the selector. When the channel leakage current of the selector exceeds the required value, the injection dose of the first threshold voltage injection region is reduced to reduce the channel leakage current of the selector to the required value range.
[0051] The second threshold voltage injection region is used to adjust the threshold voltage of the selector while reducing GIDL leakage current; when the GIDL leakage current of the selector increases, the injection dose of the second threshold voltage injection region is increased to reduce the GIDL leakage current of the selector to the required value range.
[0052] A further improvement is that, when the channel leakage current of the selector exceeds the required value, the method further includes: increasing the injection dose of the unit well region to reduce the channel leakage current of the selector to the required value range.
[0053] A further improvement is that the first conductivity type is N-type and the second conductivity type is P-type.
[0054] The injected impurities in the unit well region include boron or boron fluoride.
[0055] The injected impurities in the first threshold voltage injection region include boron or boron fluoride.
[0056] The injected impurities in the second threshold voltage injection region include boron or boron fluoride.
[0057] The injection dose in the unit well region is an order of magnitude smaller than the injection dose in the first threshold voltage injection region;
[0058] The injection dose in the first threshold voltage injection region and the injection dose in the second threshold voltage injection region are of the same order of magnitude.
[0059] The threshold voltage adjustment region of the present invention includes a first threshold voltage injection region and a second threshold voltage injection region. The combination of the two makes the threshold voltage adjustment region an asymmetric structure. The second threshold voltage injection region is used to realize the asymmetric structure of the threshold voltage adjustment region. The setting of the second threshold voltage injection region can reduce the area of the overlapping region between the first gate structure and the source region and the doping concentration of the first conductivity type in the overlapping region, thus reducing the GIDL leakage current of the device.
[0060] In existing technologies, asymmetric threshold voltage adjustment regions often affect the threshold voltage of the select transistor, thereby reducing the control capability of the channel. While reducing GIDL leakage current, this often causes the channel leakage current to rise rapidly. Unlike existing technologies, this invention introduces a first threshold voltage injection region. The formation region of the first threshold voltage injection region includes the coverage area of the first gate structure of the select transistor. Therefore, by adjusting the injection dose of the first threshold voltage injection region, the doping concentration of the channel region at the bottom of the first gate structure can be controlled independently. Ultimately, this increases the channel control capability of the select transistor and effectively reduces channel leakage current.
[0061] In this invention, by utilizing the blocking effect of the first gate structure itself on threshold voltage injection, the invention enables the opening regions before the injection of the first threshold voltage injection region and the second threshold voltage injection region to be defined by the same photomask. However, in terms of process, the first threshold voltage injection region needs to be placed before the formation of the gate structure and the second threshold voltage injection region needs to be placed after the formation of the gate structure. Therefore, although this invention adds one threshold voltage injection, it does not require an additional photomask, thus reducing process costs.
[0062] In this invention, the unit well region can also be used to adjust the channel leakage current of the selector. By increasing the injection dose of the unit well region, the channel leakage current of the selector can be reduced, which can provide an adjustment means for the channel leakage current of the selector using an asymmetric threshold voltage adjustment region. Attached Figure Description
[0063] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
[0064] Figure 1 This is a schematic diagram of the storage tube structure of an existing SONOS memory;
[0065] Figure 2 This is a schematic diagram of the storage unit combination of the SONOS memory according to an embodiment of the present invention;
[0066] Figure 3A This is a schematic diagram of the device structure when forming the first threshold voltage injection region in the manufacturing method of the SONOS memory according to an embodiment of the present invention;
[0067] Figure 3B This is a schematic diagram of the device structure when forming the second threshold voltage injection region in the manufacturing method of the SONOS memory according to an embodiment of the present invention. Detailed Implementation
[0068] like Figure 2 The diagram shown is a structural schematic of the storage unit combination of the SONOS memory according to an embodiment of the present invention; the storage unit of the SONOS memory according to an embodiment of the present invention includes a select transistor and a storage transistor. Figure 2The image shows two storage cells, with regions 303a and 303b forming the storage cells, respectively.
[0069] The two storage cells have the same structure. Taking the storage cell in region 303a as an example, the region where the select tube is formed is region 301, and the region where the storage tube is formed is region 302.
[0070] In the memory cell, the first gate structure 203 of the select transistor and the second gate structure 204 of the memory transistor are both formed on the top surface of the unit well region 202 doped with the second conductivity type, and the unit well region 202 is formed in a selected region of the semiconductor substrate 201.
[0071] Figure 2 In the diagram, the first gate structure 203 is also represented by SG, and the second gate structure is also represented by CG.
[0072] In this embodiment of the invention, the first gate structure 203 includes a first gate dielectric layer (not shown) and a first polysilicon gate (not shown) stacked sequentially.
[0073] The second gate structure 204 includes a silicon dioxide tunneling layer (not shown), a silicon nitride storage layer (not shown), a silicon dioxide barrier layer (not shown), and a second polysilicon gate (not shown) stacked sequentially.
[0074] The threshold voltage adjustment region of the selector transistor has an asymmetrical structure, and the threshold voltage adjustment region includes:
[0075] A first threshold voltage injection region 207, doped with a second conductivity type, is formed in a surface region of a selected area of the unit well region 202. The formation region of the first threshold voltage injection region 207 is located in the formation region of the select transistor and includes at least the region covered by the first gate structure 203.
[0076] A second threshold voltage injection region 208, doped with a second conductivity type, is formed in a selected area of the surface region of the unit well region 202. The formation region of the second threshold voltage injection region 208 is located in the formation region of the source region of the select transistor and is self-aligned with the first side of the first gate structure 203. The first side of the first gate structure 203 is the side adjacent to the source region of the select transistor.
[0077] In this embodiment of the invention, the memory cell includes a first source / drain region (not shown), a second source / drain region (not shown), and a third source / drain region (not shown) heavily doped with a first conductivity type.
[0078] The first source-drain region serves as the drain region of the storage transistor, the second source-drain region serves as both the source region of the storage transistor and the drain region of the select transistor, and the third source-drain region serves as the source region of the select transistor.
[0079] Figure 2 In region 303a, the first source / drain region is self-aligned to the left of the second gate structure 204 in region 302, and the top of the first source / drain region is connected to the bit line BL via a connection structure 206.
[0080] The second source / drain region is self-aligned and formed between the first gate structure 203 and the second gate structure 204.
[0081] In region 303a, the third source / drain region is self-aligned and formed to the right of the first gate structure 203 in region 301; the top of the third source / drain region is connected to the source line 205. The source line 205 is also denoted by SL.
[0082] like Figure 2 As shown, two adjacent storage cells form a storage cell combination.
[0083] In the memory cell assembly, the two first gate structures 203 share a third source-drain region. The source line 205 at the top of the third source-drain region is also shared.
[0084] like Figure 2 As shown in the embodiment of the present invention, the formation region of the first threshold voltage injection region 207 includes the formation regions of the two first gate structures 203 and the formation region of the third source / drain region.
[0085] The second threshold voltage injection region 208 of the two memory cells is located in the surface region of the cell well region 202 between the source line 205 and the first gate structures 203 on both sides.
[0086] The first threshold voltage injection region 207 of the two memory cells is an integral structure and is located in the surface region of the cell well region 202 between the second sides of the two first gate structures 203, where the second side of the first gate structure 203 is the side adjacent to the drain region of the select transistor.
[0087] Figure 2The positions of the first threshold voltage injection region 207 and the second threshold voltage injection region 208 are configured such that they can share the same photomask. Ion implantation of the first threshold voltage injection region 207 only needs to be performed before the gate structure is formed, and ion implantation of the second threshold voltage injection region 208 only needs to be performed after the gate structure is formed. The gate structure here includes the first gate structure 203 and the second gate structure 204. In this embodiment, the source line 205 is made of polysilicon. The connection structure 206 is also made of polysilicon. Thus, ion implantation of the second threshold voltage injection region 208 is performed after the gate structure, the source line 205, and the connection structure 206 are all formed.
[0088] In this embodiment of the invention, the channel conductivity type is N-type, both the storage transistor and the select transistor are N-type devices, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the channel conductivity type can also be P-type, the first conductivity type is P-type, and the second conductivity type is N-type.
[0089] The following explanation uses an N-type channel conductivity type as an example:
[0090] The injected impurities in the unit well region 202 include boron or boron fluoride.
[0091] The implanted impurities in the first threshold voltage injection region 207 include boron or boron fluoride.
[0092] The implanted impurities in the second threshold voltage injection region 208 include boron or boron fluoride.
[0093] The injection dose of the unit well region 202 is an order of magnitude smaller than the injection dose of the first threshold voltage injection region 207.
[0094] The injection dose of the first threshold voltage injection region 207 and the injection dose of the second threshold voltage injection region 208 are of the same order of magnitude.
[0095] In some embodiments, the injection dose of the unit well region 202 is on the order of 10. -12 cm⁻², for example, the injection dose of the unit well region 202 is 3.6E12cm⁻². -2 about;
[0096] The injection dose in the first threshold voltage injection region 207 is on the order of 10. -13 cm-2.
[0097] The threshold voltage adjustment region of this invention includes a first threshold voltage injection region 207 and a second threshold voltage injection region 208. The combination of the two makes the threshold voltage adjustment region an asymmetric structure. The second threshold voltage injection region 208 is used to realize the asymmetric structure of the threshold voltage adjustment region. The setting of the second threshold voltage injection region 208 can reduce the area of the overlapping region between the first gate structure 203 and the source region and the doping concentration of the first conductivity type in the overlapping region, thus reducing the GIDL leakage current of the device.
[0098] In existing technologies, asymmetric threshold voltage adjustment regions often affect the threshold voltage of the select transistor, thereby reducing the control capability of the channel. While reducing GIDL leakage current, this often causes the channel leakage current to rise rapidly. Unlike existing technologies, this embodiment of the invention introduces a first threshold voltage injection region 207. The formation region of the first threshold voltage injection region 207 includes the coverage area of the first gate structure 203 of the select transistor. Therefore, by adjusting the injection dose of the first threshold voltage injection region 207, the doping concentration of the channel region at the bottom of the first gate structure 203 can be controlled independently. Ultimately, this increases the channel control capability of the select transistor and effectively reduces channel leakage current.
[0099] In this embodiment of the invention, by utilizing the blocking effect of the first gate structure 203 itself on threshold voltage injection, the present invention enables the opening regions before injection of the first threshold voltage injection region 207 and the second threshold voltage injection region 208 to adopt the same photomask definition. However, in terms of process, the first threshold voltage injection region 207 needs to be placed before the gate structure is formed and the second threshold voltage injection region 208 needs to be placed after the gate structure is formed. Therefore, although the embodiment of the present invention adds one threshold voltage injection, it does not require an additional photomask, thus reducing process costs.
[0100] In this embodiment of the invention, the unit well region 202 can also be used to adjust the channel leakage current of the selector. By increasing the injection dose of the unit well region 202, the channel leakage current of the selector can be reduced, which can provide an adjustment means for the channel leakage current of the selector using an asymmetric threshold voltage adjustment region.
[0101] like Figure 3A The diagram shown is a schematic representation of the device structure during the formation of the first threshold voltage injection region in the manufacturing method of the SONOS memory according to an embodiment of the present invention; as shown... Figure 3B The diagram shown is a schematic representation of the device structure during the formation of the second threshold voltage injection region in the manufacturing method of the SONOS memory according to an embodiment of the present invention. In the manufacturing method of the SONOS memory according to an embodiment of the present invention, the memory cell of the SONOS memory includes a select transistor and a memory transistor; the method includes the following forming steps:
[0102] Step S101, as follows Figure 3AAs shown, a second conductivity type doped cell well region 202 is formed in a selected region of the semiconductor substrate 201; in the memory cell, the formation regions of the select transistor and the memory transistor are both located on the cell well region 202.
[0103] Step S102, as follows Figure 3A As shown, photolithography opens the first opening region 402, and photolithography is performed to form a photoresist pattern 401. The photoresist pattern 401 has the opened first opening region 402. The first opening region 402 defines the formation region of the first threshold voltage injection region 207. The formation region of the first threshold voltage injection region 207 is located in the formation region of the select transistor and includes at least the region covered by the first gate structure 203 of the select transistor.
[0104] Step S103, as follows Figure 3A As shown, a first threshold voltage injection is performed to dope with a second conductivity type, and a first threshold voltage injection region 207 is formed in the surface region of the unit well region 202 in the first opening region 402.
[0105] The first threshold voltage injection is shown as arrow 403.
[0106] Step S104, as follows Figure 3B As shown, a gate structure is formed on the top surface of the cell well region 202, the gate structure including the first gate structure 203 of the select transistor and the second gate structure 204 of the memory transistor.
[0107] In the method of this embodiment of the invention, the first gate structure 203 includes a first gate dielectric layer and a first polysilicon gate stacked sequentially.
[0108] The second gate structure 204 includes a silicon dioxide tunneling layer, a silicon nitride storage layer, a silicon dioxide barrier layer, and a second polysilicon gate, which are stacked sequentially.
[0109] Step S105, as follows Figure 3B As shown, photolithography opens the second opening region 404, that is, photolithography is performed to form a photoresist pattern 401a. The photoresist pattern 401a has an open second opening region 404. The second opening region 404 exposes the formation region of the first gate structure 203 and the formation region of the second threshold voltage injection region 208. The formation region of the second threshold voltage injection region 208 is located in the formation region of the source region of the select transistor.
[0110] In the method of this embodiment of the invention, the first opening region 402 and the second opening region 404 adopt the same photomask definition.
[0111] Step S106, as follows Figure 3BAs shown, a second threshold voltage injection region 208 is formed in the surface region of the cell well region 202 in the second opening region 404 and not covered by the first gate structure 203, and the second threshold voltage injection region 208 and the source region side of the first gate structure 203 are self-aligned.
[0112] The second threshold voltage injection region 208 is located on the source region side of the formation region of the select transistor in the cell well region 202 and is self-aligned with the first side of the select transistor. The first side of the first gate structure 203 is the side adjacent to the source region of the select transistor.
[0113] The first threshold voltage injection region 207 and the second threshold voltage injection region 208 are used as components of the threshold voltage adjustment region of the selector, and the threshold voltage adjustment region of the selector is made into an asymmetrical structure.
[0114] After the gate structure is formed, it also includes:
[0115] A first source / drain region, a second source / drain region, and a third source / drain region are formed in the formation region of the memory cell by performing source / drain implantation with heavy doping of the first conductivity type. The first source / drain region, the second source / drain region, and the third source / drain region are formed in self-alignment between the corresponding gate structures.
[0116] The first source-drain region serves as the drain region of the storage transistor, the second source-drain region serves as both the source region of the storage transistor and the drain region of the select transistor, and the third source-drain region serves as the source region of the select transistor.
[0117] like Figure 2 As shown, two adjacent storage cells form a storage cell combination.
[0118] In the memory cell combination, the two first gate structures 203 share a third source-drain region.
[0119] The formation region of the first threshold voltage injection region 207 includes the formation regions of the two first gate structures 203 and the formation region of the third source / drain region.
[0120] In the method of this embodiment of the invention, in the memory cell assembly, an active electrode line 205 is also formed on top of the third source-drain region.
[0121] The top of the first source / drain region is connected to the bit line BL via a connection structure 206.
[0122] The source line 205 is made of polycrystalline silicon. The connection structure 206 is also made of polycrystalline silicon.
[0123] The first opening regions 402 of the two memory cells are merged together and located between the second sides of the two first gate structures 203, the second sides of the first gate structures 203 being the sides adjacent to the drain region of the select transistor.
[0124] The second threshold voltage injection region 208 of the two memory cells is located in the surface region of the cell well region 202 between the source line 205 and the first gate structures 203 on both sides.
[0125] The first threshold voltage injection region 207 of the two memory cells is an integral structure and is located in the surface region of the cell well region 202 between the second sides of the two first gate structures 203.
[0126] In the method of this embodiment of the invention, the first threshold voltage injection region 207 is used to adjust the channel leakage current of the selection tube. When the channel leakage current of the selection tube exceeds the required value, the injection dose of the first threshold voltage injection region 207 is reduced so that the channel leakage current of the selection tube is reduced to the required value range.
[0127] The second threshold voltage injection region 208 is used to adjust the threshold voltage of the selector while reducing GIDL leakage current; when the GIDL leakage current of the selector increases, the injection dose of the second threshold voltage injection region 208 is increased to reduce the GIDL leakage current of the selector to the required value range.
[0128] When the channel leakage current of the selector exceeds the required value, the method further includes: increasing the injection dose of the unit well region 202 to reduce the channel leakage current of the selector to the required value range.
[0129] In the method of this embodiment, the channel conductivity type is N-type, both the storage transistor and the select transistor are N-type devices, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the method can also be: the channel conductivity type is P-type, the first conductivity type is P-type, and the second conductivity type is N-type.
[0130] The following explanation uses an N-type channel conductivity type as an example:
[0131] The injected impurities in the unit well region 202 include boron or boron fluoride.
[0132] The implanted impurities in the first threshold voltage injection region 207 include boron or boron fluoride.
[0133] The implanted impurities in the second threshold voltage injection region 208 include boron or boron fluoride.
[0134] The injection dose of the unit well region 202 is an order of magnitude smaller than the injection dose of the first threshold voltage injection region 207.
[0135] The injection dose of the first threshold voltage injection region 207 and the injection dose of the second threshold voltage injection region 208 are of the same order of magnitude.
[0136] In some embodiments, the injection dose of the unit well region 202 is on the order of 10. -12 cm⁻², for example, the injection dose of the unit well region 202 is 3.6E12cm⁻². -2 about.
[0137] The injection dose in the first threshold voltage injection region 207 is on the order of 10. -13 cm-2.
[0138] The SONOS memory device, i.e. flash memory device fabrication method of the present invention, does not require additional development processes or additional photomasks. By using the threshold voltage adjustment region (RVTN) formation process after polysilicon (poly) formation, i.e. after the gate structure is formed, the threshold voltage (Vt) of the select transistor is adjusted by using asymmetric ion implantation (IMP) conditions, while reducing GIDL leakage current.
[0139] However, GIDL leakage and channel leakage have a relative effect: under asymmetric conditions, GIDL leakage is effectively suppressed, while channel leakage increases rapidly. Therefore, embodiments of the present invention, by reusing the RVTN mask after the formation of the core well region (CPW) following the well, increase the Vt IMP injection dose, adjust the doping concentration in the channel region, and increase channel control, can effectively reduce channel leakage.
[0140] Furthermore, embodiments of the present invention can further increase the boron (B) IMP dose of the CPW, which can reduce channel leakage current without increasing the Vt of the selector.
[0141] This invention, through RVTN multiplexing and adjusting the IMP dose to construct an asymmetric scheme, can reduce GIDL leakage caused by size miniaturization during process development to approximately 25% of the original level. While reducing leakage current, it has minimal impact on the source-drain saturation current (Idsat), achieving a balance between leakage improvement and performance optimization. Furthermore, the method of this invention can be developed on existing platforms without additional process development or photomasks, saving costs, providing stability and controllability, and making it suitable for mass production.
[0142] In the manufacturing process of the memory in this embodiment of the invention, an RVTN layer is applied after the well to increase its IMP dose, adjust the channel concentration, and increase the channel control force, which can effectively reduce channel leakage. After poly, the RVTN mask is reused, and the GIDL leakage is reduced while adjusting the selector transistor Vt through asymmetric IMP. Simultaneously, the CPW B IMP dose is increased to reduce channel leakage.
[0143] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.
Claims
1. A SONOS memory, characterized in that, The SONOS memory's storage unit includes a select transistor and a storage transistor; In the memory cell, the first gate structure of the select transistor and the second gate structure of the memory transistor are both formed on the top surface of the unit well region doped with the second conductivity type, and the unit well region is formed in a selected region of the semiconductor substrate; The threshold voltage adjustment region of the selector transistor has an asymmetrical structure, and the threshold voltage adjustment region includes: A first threshold voltage injection region doped with a second conductivity type is formed in a surface region of a selected region of the unit well region. The formation region of the first threshold voltage injection region is located in the formation region of the select transistor and includes at least the region covered by the first gate structure. A second threshold voltage injection region, doped with a second conductivity type, is formed in a selected area of the surface region of the unit well region. The formation region of the second threshold voltage injection region is located in the formation region of the source region of the select transistor and is self-aligned with the first side of the first gate structure. The first side of the first gate structure is the side adjacent to the source region of the select transistor.
2. The SONOS memory as described in claim 1, characterized in that: The first gate structure includes a first gate dielectric layer and a first polysilicon gate stacked sequentially; The second gate structure includes a silicon dioxide tunneling layer, a silicon nitride storage layer, a silicon dioxide barrier layer, and a second polysilicon gate, which are stacked sequentially.
3. The SONOS memory as described in claim 2, characterized in that: The memory cell includes a first source / drain region, a second source / drain region, and a third source / drain region heavily doped with a first conductivity type. The first source-drain region serves as the drain region of the storage transistor, the second source-drain region serves as both the source region of the storage transistor and the drain region of the select transistor, and the third source-drain region serves as the source region of the select transistor.
4. The SONOS memory as described in claim 3, characterized in that: Two adjacent storage cells form a storage cell combination; In the memory cell combination, the two first gate structures share a third source-drain region; The formation region of the first threshold voltage injection region includes the formation regions of the two first gate structures and the formation region of the third source / drain region.
5. The SONOS memory as described in claim 4, characterized in that: In the memory cell assembly, an active electrode line is also formed on top of the third source-drain region; The second threshold voltage injection region of the two memory cells is located in the surface region of the cell well region between the source line and the first gate structures on both sides; The first threshold voltage injection regions of the two memory cells are integral structures and located in the surface region of the cell well region between the second sides of the two first gate structures, wherein the second side of the first gate structure is a side adjacent to the drain region of the select transistor.
6. The SONOS memory as described in claim 5, characterized in that: The source wire is made of polycrystalline silicon.
7. The SONOS memory according to any one of claims 1-6, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; The injected impurities in the unit well region include boron or boron fluoride; The implanted impurities in the first threshold voltage injection region include boron or boron fluoride; The implanted impurities in the second threshold voltage injection region include boron or boron fluoride; The injection dose in the unit well region is an order of magnitude smaller than the injection dose in the first threshold voltage injection region; The injection dose in the first threshold voltage injection region and the injection dose in the second threshold voltage injection region are of the same order of magnitude.
8. A method for manufacturing a SONOS memory, characterized in that, The SONOS memory cell includes a select transistor and a storage transistor; the formation steps are as follows: A second conductivity type doped cell well region is formed in a selected region of the semiconductor substrate; in the memory cell, the formation regions of the select transistor and the memory transistor are both located on the cell well region; Photolithography opens a first opening region, which defines the formation region of a first threshold voltage injection region. The formation region of the first threshold voltage injection region is located in the formation region of the select transistor and includes at least the region covered by the first gate structure of the select transistor. A first threshold voltage injection region is formed in the surface region of the unit well region of the first opening region by performing a second conductivity type doping; A gate structure is formed on the top surface of the cell well region, the gate structure including a first gate structure of the select transistor and a second gate structure of the memory transistor; Photolithography opens a second opening region, which exposes the formation region of the first gate structure and the formation region of the second threshold voltage injection region, the formation region of the second threshold voltage injection region being located in the formation region of the source region of the select transistor; A second threshold voltage injection is performed to dope the second conductivity type and a second threshold voltage injection region is formed in the surface region of the unit well region in the second opening region and not covered by the first gate structure; the second threshold voltage injection region is located in the unit well region on the source region side of the formation region of the select transistor and is self-aligned with the first side of the select transistor, and the first side of the first gate structure is the side adjacent to the source region of the select transistor; The first threshold voltage injection region and the second threshold voltage injection region are used as components of the threshold voltage adjustment region of the selector, and the threshold voltage adjustment region of the selector is made into an asymmetrical structure.
9. The method for manufacturing a SONOS memory as described in claim 8, characterized in that: The first gate structure includes a first gate dielectric layer and a first polysilicon gate stacked sequentially; The second gate structure includes a silicon dioxide tunneling layer, a silicon nitride storage layer, a silicon dioxide barrier layer, and a second polysilicon gate, which are stacked sequentially.
10. The method for manufacturing a SONOS memory as described in claim 9, characterized in that: The first opening region and the second opening region are defined using the same photomask.
11. The method for manufacturing a SONOS memory as described in claim 10, characterized in that, After the gate structure is formed, it also includes: Source-drain regions, a first source-drain region, and a third source-drain region are formed in the formation region of the memory cell by performing source-drain injection with heavy doping of the first conductivity type. The first source-drain region serves as the drain region of the storage transistor, the second source-drain region serves as both the source region of the storage transistor and the drain region of the select transistor, and the third source-drain region serves as the source region of the select transistor.
12. The method for manufacturing a SONOS memory as described in claim 11, characterized in that: Two adjacent storage cells form a storage cell combination; In the memory cell combination, the two first gate structures share a third source-drain region; The formation region of the first threshold voltage injection region includes the formation regions of the two first gate structures and the formation region of the third source / drain region.
13. The method for manufacturing a SONOS memory as described in claim 12, characterized in that: In the memory cell assembly, an active electrode line is also formed on top of the third source-drain region; The first opening regions of the two memory cells are merged together and located between the second sides of the two first gate structures, wherein the second side of the first gate structure is the side adjacent to the drain region of the select transistor; The second threshold voltage injection region of the two memory cells is located in the surface region of the cell well region between the source line and the first gate structures on both sides; The first threshold voltage injection regions of the two memory cells are integral structures and located in the surface region of the cell well region between the second sides of the two first gate structures.
14. The method for manufacturing a SONOS memory as described in claim 13, characterized in that: The source wire is made of polycrystalline silicon.
15. The method for manufacturing a SONOS memory as described in claim 1, characterized in that: The first threshold voltage injection region is used to adjust the channel leakage current of the selector. When the channel leakage current of the selector exceeds the required value, the injection dose of the first threshold voltage injection region is reduced to reduce the channel leakage current of the selector to the required value range. The second threshold voltage injection region is used to adjust the threshold voltage of the selector while reducing GIDL leakage current; when the GIDL leakage current of the selector increases, the injection dose of the second threshold voltage injection region is increased to reduce the GIDL leakage current of the selector to the required value range.
16. The method for manufacturing the SONOS memory as described in claim 15, characterized in that: When the channel leakage current of the selector exceeds the required value, the method further includes: increasing the injection dose of the unit well region to reduce the channel leakage current of the selector to the required value range.
17. The method for manufacturing a SONOS memory as described in any one of claims 8-16, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; The injected impurities in the unit well region include boron or boron fluoride; The implanted impurities in the first threshold voltage injection region include boron or boron fluoride; The implanted impurities in the second threshold voltage injection region include boron or boron fluoride; The injection dose in the unit well region is an order of magnitude smaller than the injection dose in the first threshold voltage injection region; The injection dose in the first threshold voltage injection region and the injection dose in the second threshold voltage injection region are of the same order of magnitude.