Package of GaN / SiC cascode power device

Abstract

The invention discloses a GaN / SiC cascode power device formed by a first transistor group and a second transistor group. The first transistor group is provided with one or more low-voltage normally-off GaN high electron mobility transistors. The second transistor group has one or more high voltage normally open SiC junction field effect transistors. The backbone layer mechanically supports the respective transistors in the two transistor groups and provides electrical connections between the respective transistors. The backbone layer is formed by embedding a network of conductive traces on or within an insulative rigid layer. Respective transistors are mounted on the backbone layer and electrically connected through a conductive trace network. Advantageously, there is no bond wire when providing an internal connection between the two transistor groups. The interconnection inductance is significantly reduced, thereby suppressing switching loss and switching oscillation and overstress caused by the switching loss and the switching oscillation to the power device during the switching process.

Description

[0001] abbreviation

[0002] Al2O3 aluminum oxide

[0003] AlN aluminum nitride

[0004] AMB Active Metal Brazing

[0005] DBC Direct Bonded Copper

[0006] DPC Direct Copper Plating

[0007] GaN (Gallium Nitride)

[0008] HEMT (High Electron Mobility Transistor)

[0009] HV High Voltage

[0010] JFET (Junction Field-Effect Transistor)

[0011] LV low voltage

[0012] MOS (Metal Oxide Semiconductor)

[0013] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)

[0014] PCB Printed Circuit Board

[0015] Si3N4 silicon nitride

[0016] SiC silicon carbide Technical Field

[0017] This disclosure generally relates to GaN / SiC cascode power devices. More specifically, this disclosure relates to packaging GaN / SiC cascode power devices to minimize parasitic inductance. Background Technology

[0018] GaN / SiC cascode devices employ a normally-on (HV) SiC JFET to block high voltage and a normally-off (LV) GaNHEMT to provide the gate current. These devices have recently been proposed and have demonstrated superior switching and static performance compared to SiC MOSFETs. Compared to the best commercially available SiC MOSFETs, GaN / SiC cascode devices replace the low-mobility SiC MOS channels with high-quality, high-mobility GaN two-dimensional electron gas channels, resulting in faster switching speeds and lower conduction losses.

[0019] To fully utilize the fast switching potential of GaN / SiC power devices, it is necessary to minimize parasitic inductance to mitigate switching oscillations and suppress switching losses. For GaN / SiC cascode devices, parasitic interconnect inductance is the most critical inductance because the switching oscillations caused by parasitic interconnect inductance can cause gate overstress in JFETs, thereby affecting the reliability of cascode power devices. Please see J.SHU, Z.ZHENG, and KJCHEN, “Protecting SiC JFET from Gate Overstress in GaN / SiC Cascode Device without Compromising Switching Performance,” IEEE Transactions on Power Electronics, pp. 5567-5575, May 2024, doi: 10.1109 / TPEL.2024.3354833, and J.Shu et al., “3D Co-packaging of GaN / SiC Cascode Device for High-Frequency Power Switching Operation,” 2024, 36. th International Symposium on Power Semiconductor Devices and ICs (ISPSD) (36th International Conference on Power Semiconductor Devices and Integrated Circuits ISPSD, 2024), June 2024, pp. 486-489. doi:10.1109 / ISPSD59661.2024.10579564, both publications are incorporated herein by reference.

[0020] US Patent No. 9960153 discloses a power device composed of a JFET and a MOSFET connected in a common-source, common-gate coupling manner, wherein the JFET is formed by having two JFETs connected in parallel. When packaging this power device, the JFET and MOSFET components are physically connected by bonding wires, which introduces a considerable amount of inductance.

[0021] GaN / SiC cascode power devices offer switching speeds far exceeding those of all commercially available power devices, with minimal parasitic inductance. Furthermore, unlike traditional vertical silicon MOSFETs, GaN HEMTs are inherently planar structures, promising unprecedented new packaging solutions. Therefore, the industry urgently needs a novel GaN / SiC cascode power device packaging technology to reduce inductance. Summary of the Invention

[0022] A first aspect of this disclosure is to provide a GaN / SiC cascode power device. The GaN / SiC cascode power device includes a first transistor group, a second transistor group, and a backbone layer. The first transistor group consists of one or more LV normally-off GaN HEMTs. The second transistor group consists of one or more HV normally-on SiC JFETs. The backbone layer mechanically supports corresponding transistors in the first and second transistor groups and provides electrical connections between the corresponding transistors. Specifically, the backbone layer is formed by forming a conductive trace network on or within an insulating rigid layer. The corresponding transistors are mounted on the backbone layer and electrically connected through the conductive trace network.

[0023] In some embodiments, the first transistor group and the second transistor group are arranged face-to-face, such that the first transistor group and the second transistor group are located on two opposite sides of the backbone layer. The insulating rigid layer includes one or more vias, such that at least one conductive trace in the conductive trace network extends through the one or more vias for electrical connection between the first transistor group and the second transistor group.

[0024] In some embodiments, the first transistor group and the second transistor group are arranged side by side, such that the first transistor group and the second transistor group are located on the same side of the backbone layer.

[0025] In some embodiments, the second transistor group is further limited to a plurality of HV normally-on SiC JFETs. A conductive trace network is configured to electrically connect the plurality of HV normally-on SiC JFETs in parallel to improve the current capacity that the GaN / SiC cascode power device can handle.

[0026] In some embodiments, the first transistor group is further limited to a plurality of LV normally-off GaN HEMTs. A conductive trace network is configured to electrically connect the plurality of LV normally-off GaN HEMTs in parallel to improve the current capacity that the GaN / SiC cascode power device can handle.

[0027] In some embodiments, the first transistor group is further limited to a plurality of LV normally-off GaN HEMTs, and the second transistor group is further limited to a plurality of HV normally-on SiC JFETs. A conductive trace network is configured to electrically connect the plurality of LV normally-off GaN HEMTs in parallel and the plurality of HV normally-on SiC JFETs in parallel to improve the current capacity that the GaN / SiC cascode power device can handle.

[0028] In some embodiments, the first transistor group is further limited to a single LV normally-off GaN HEMT, and the second transistor group is further limited to a single HV normally-on SiC JFET.

[0029] In some embodiments, the GaN / SiC cascode power device further includes one or more peripheral blocks. Each of these peripheral blocks comprises one or more electronic components electrically connected to the first transistor group via a conductive trace network. Each of these electronic components may be a gate driver, a controller, or a passive electronic component.

[0030] In some embodiments, the one or more peripheral blocks are integrated with the first transistor group.

[0031] In some embodiments, the backbone layer is implemented as a DBC layer, AMB layer, DPC layer, insertion layer, or redistribution layer.

[0032] In some embodiments, the rigid insulating layer is composed of AlN, Al2O3, Si3N4, epoxy resin, polymer or other insulating materials.

[0033] A second aspect of this disclosure is to provide a power module. The power module includes a plurality of power devices forming a half-bridge circuit, a bidirectional switch, or other circuitry. Each of the plurality of power devices is configured as any embodiment of the GaN / SiC cascode power device described above. Furthermore, the respective insulating rigid layers of the respective power devices are planarly connected to form a single insulating sheet.

[0034] In some embodiments, the single insulating sheet is made of AlN, Al2O3, Si3N4, epoxy resin, polymer or other insulating materials.

[0035] A third aspect of this disclosure is to provide a GaN / SiC cascode power device comprising an LV normally-off GaN HEMT and an HV normally-on SiC JFET, without the need for a backbone layer to mount the LV normally-off GaN HEMT and the HV normally-on SiC JFET. In this GaN / SiC cascode power device, the first pad pattern of the LV normally-off GaN HEMT matches the second pad pattern of the HV normally-on SiC JFET. The LV normally-off GaN HEMT is directly attached to the HV normally-on SiC JFET, wherein the first and second pad patterns are aligned to form the GaN / SiC cascode power device.

[0036] Other aspects of this disclosure are disclosed as shown in the following embodiments. Attached Figure Description

[0037] Detailed description of the embodiments is given with reference to the accompanying drawings. The drawings are provided for illustrative purposes only and depict only exemplary embodiments of the present disclosure. The drawings are intended to aid in understanding the present disclosure and should not be construed as limiting the breadth, scope, or applicability of the disclosure. Unless otherwise stated, the drawings are not drawn to scale. For ease of explanation, certain portions of the drawings may be exaggerated and should not be considered limiting unless otherwise stated.

[0038] Figure 1 A typical circuit model of a GaN / SiC cascode power device is shown, which is formed by connecting an HV SiC JFET and an LVGaN HEMT in a cascode configuration.

[0039] Figure 2 A first GaN / SiC cascode power device is shown packaged according to one of the disclosed packaging solutions, wherein the HV SiC JFET and LV GaN HEMT are arranged face-to-face.

[0040] Figure 3A A second GaN / SiC cascode power device is shown, based on the stacked GaN / SiC cascode power device model shown in the first GaN / SiC cascode power device.

[0041] Figure 3B A third GaN / SiC cascode power device is shown, based on the stacked GaN / SiC cascode power device model used in the second GaN / SiC cascode power device.

[0042] Figure 4A fourth GaN / SiC cascode power device is shown packaged according to one of the disclosed packaging solutions, wherein the fourth GaN / SiC cascode power device is based on the stacked GaN / SiC cascode device model shown in the first GaN / SiC cascode power device.

[0043] Figure 5 A fifth GaN / SiC cascode power device is shown packaged according to one of the disclosed packaging solutions, wherein the fifth GaN / SiC cascode power device is based on the stacked GaN / SiC cascode device model shown in the first GaN / SiC cascode power device.

[0044] Figure 6 A sixth GaN / SiC cascode power device is shown packaged according to one of the disclosed packaging solutions, wherein the HV SiC JFET and LV GaN HEMT are arranged side by side.

[0045] Figure 7 A seventh GaN / SiC cascode power device is shown packaged according to one of the disclosed packaging solutions, wherein the seventh GaN / SiC cascode power device is based on the planar GaN / SiC cascode device model shown in the sixth GaN / SiC cascode power device.

[0046] Figure 8 An eighth GaN / SiC cascode power device is shown packaged according to one of the disclosed packaging solutions, wherein the eighth GaN / SiC cascode power device is based on the planar GaN / SiC cascode device model shown in the sixth GaN / SiC cascode power device.

[0047] Figure 9 A ninth GaN / SiC cascode power device is shown packaged according to one of the parallel packaging solutions disclosed herein.

[0048] Figure 10 The tenth GaN / SiC cascode power device is shown packaged according to one of the disclosed parallel packaging solutions.

[0049] Figure 11 An eleventh GaN / SiC cascode power device packaged according to one of the disclosed parallel packaging solutions is shown.

[0050] Figure 12 A power module implemented using several GaN / SiC cascode power devices disclosed herein is shown.

[0051] Figure 13A twelfth GaN / SiC cascode power device is shown packaged according to one of the disclosed packaging solutions, wherein the twelfth GaN / SiC cascode power device is formed by directly connecting an LV GaN HEMT and an HV SiC JFET without an adapter layer in between. Detailed Implementation

[0052] This disclosure relates to a packaging technique for GaN / SiC cascode power devices or power modules. Advantageously, in this packaging solution, no bonding wires are used when providing an internal connection between the HV normally-on SiC JFET and the LV normally-off GaN HEMT. The interconnect inductance in the GaN / SiC cascode power device is significantly reduced. By reducing the interconnect inductance, switching losses and switching oscillations, as well as the overstress they cause to the power device during switching, are advantageously suppressed.

[0053] The packaging solution will first be described and explained below, and then embodiments of this disclosure will be developed based on the packaging solution.

[0054] In the following description, the DBC layer will be used as an example of any "backbone layer" that provides electrical insulation and selective electrical connections between electronic components mounted on the aforementioned backbone layer. The backbone layer can be fabricated based on any insulating substrate, such as AlN, Al2O3, Si3N4, epoxy resin, polymers, etc. In some practical applications, the DBC layer can be replaced by an AMB layer, DPC layer, insertion layer, or redistribution layer, depending on the process preferred for the application. The connection between the chip and the backbone layer can be soldered, sintered, or any other technique, depending on the preferences of the specific application.

[0055] In the accompanying drawings, the stacked configuration shown does not indicate the actual vertical position of each component. In other words, the drawn stacked configuration can also be flipped when embedded into the lead frame of a commercial or novel packaging solution.

[0056] For ease of explanation, Figure 1 A typical circuit model of a GaN / SiC cascode power device 100 is shown, which consists of an HV normally-on SiC JFET 101 and an LV normally-off GaN HEMT 102 connected in a cascode configuration. Regarding this cascode connection, the source of the HV normally-on SiC JFET 101 is connected to the drain of the LV normally-off GaN HEMT 102. The connection point between the source of the HV normally-on SiC JFET 101 and the drain of the LV normally-off GaN HEMT 102 is referred to as point M 105. The gate of the HV normally-on SiC JFET 101 is connected to the source of the LV normally-off GaN HEMT 102. The packaging scheme requires that the parasitic interconnect inductance (which includes L...) be...S-D 103 and L G-S 104) Minimize in order to achieve fast switching of GaN / SiC cascode power devices and suppress their switching losses.

[0057] Figure 2 A first GaN / SiC cascode power device 200 is shown packaged according to one of the disclosed packaging solutions. Figure 2 A cross-sectional and three-dimensional view of the power device 200 is shown. In the power device 200, an LV normally-off GaN HEMT 201, a DBC layer 202, and an HV normally-on SiC JFET 205 are stacked together. The interconnection between the LV GaN HEMT 201 and the HV SiC JFET 205 is achieved through a metal pattern 203 on the DBC layer 202 and metal vias 204 within the DBC layer 202. Each metal via 204 is formed by depositing metal in a via 234 in the substrate of the DBC layer 202. The substrate of the DBC layer 202 can be AlN, Si3N4, Al2O3, epoxy resin, polymer, or other materials with electrical insulating capabilities. The metal material of the pattern 203 and the via 204 can be any conductive metal, such as copper. Connections between the chip and the backbone layer can be established by soldering, silver sintering, copper sintering, etc. Peripheral components such as gate drivers, controllers, and passive components can be monolithically integrated into the GaN HEMT 201.

[0058] Figure 3A and 3B A second GaN / SiC cascode power device 300a and a third GaN / SiC cascode power device 300b are shown, both based on the stacked GaN / SiC cascode device model shown in the first GaN / SiC cascode power device 200. In these two power devices 300a and 300b, the stacked GaN / SiC cascode device can be embedded into the leadframe of any commercial or novel packaging solution, such as TO247, TO263, PCB embedded packages, etc.

[0059] In the second GaN / SiC cascode power device 300a, the drain terminal 301 of the power device 300a can be directly attached to the lead frame for power dissipation and electrical connection purposes. The gate terminal 302 and the source terminal 303 of the power device 300a can be connected to the lead frame via one or more bonding wires (e.g., bonding wire 304) or copper clips.

[0060] In the third GaN / SiC cascode power device 300b, the substrate of HEMT 201 can be connected to the source terminals of HEMT 201 via GaN vias, allowing the source terminals of the third GaN / SiC cascode power device 300b to be formed on the back substrate of HEMT 201. Therefore, the source terminal bonding wires 304 or copper clips of the third GaN / SiC cascode power device 300b can be connected to the substrate of HEMT 201.

[0061] The M point of each of the second and third GaN / SiC cascode power devices 300a and 300b can also be connected to the external pads of the packaged solution under consideration using bonding wires or copper clips.

[0062] Figure 4 A fourth GaN / SiC cascode power device 400 packaged according to one of the disclosed packaging solutions is shown. The power device 400 is based on the stacked GaN / SiC cascode device model shown in the first GaN / SiC cascode power device 200. The drain terminal 301 of the power device 400 can be directly attached to the leadframe for power dissipation and electrical connection purposes. The gate terminal 302 and source terminal 303 of the power device 400 can be connected to the leadframe via a metal via 401 through the DBC layer 202. The M-point 105 of the fourth GaN / SiC cascode power device 400 can also be connected to an external pad of the considered packaging solution via a via through the DBC layer 202.

[0063] Figure 5 A fifth GaN / SiC cascode power device 500, packaged according to one of the disclosed packaging solutions, is shown. The power device 500 is based on the stacked GaN / SiC cascode device model shown in the first GaN / SiC cascode power device 200. Figure 5 A cross-sectional and three-dimensional view of the power device 500 is shown. One or more peripheral blocks 501 (including but not limited to gate drivers, controllers, capacitors, and resistors) can be connected to the same DBC layer 202 or another DBC layer. The drain terminal 301 of the power device 500 can be directly attached to the lead frame for power dissipation and electrical connection purposes. The gate terminal 302, source terminal 303, and M-point 105 of the fifth GaN / SiC cascode power device 500 can be connected to the lead frame via wire bonding or through metal vias in the DBC layer 202. The substrate of the HEMT 201 can be connected to the source terminal of the HEMT 201 via GaN vias, such that the back substrate of the HEMT 201 can be the source terminal of the fifth GaN / SiC cascode power device 500.

[0064] Figure 6The sixth GaN / SiC cascode power device 600 is shown packaged according to one of the disclosed packaging solutions. Figure 6 The diagram shows a cross-sectional and three-dimensional view of the power device 600. In the power device 600, the LV GaN HEMT 201 and HV SiC JFET 205 can be arranged side by side and located on the same side of the DBC layer 202. Peripheral components (such as gate drivers, controllers, and passive components) can be monolithically integrated into the LV normally-off GaN HEMT 201.

[0065] Figure 7 A seventh GaN / SiC cascode power device 700, packaged according to one of the disclosed packaging solutions, is shown. Power device 700 is based on the planar GaN / SiC cascode device model shown in the sixth GaN / SiC cascode power device 600. The HEMT 201 and JFET 205 of power device 700 are located on the same side of DBC layer 202 and can be embedded in the leadframe of any commercial or novel packaging solution, such as TO247, TO263, PCB embedded packages, etc. DBC layer 202 can be directly attached to the leadframe. The connection between the GaN / SiC cascode device (formed by two transistors 201 and 205) and the leadframe of the commercial packaging solution can be a bonding wire, copper clip, or a via through DBC layer 202. The substrate of HEMT201 can be connected to the source terminal of HEMT201 through GaN vias, so that the back substrate of HEMT201 can be the source terminal of the seventh GaN / SiC cascode power device 700.

[0066] Figure 8 An eighth GaN / SiC cascode power device 800, packaged according to one of the disclosed packaging solutions, is shown. The power device 800 is based on the planar GaN / SiC cascode device model shown in the sixth GaN / SiC cascode power device 600. The LV GaN HEMT 201 and HV SiC JFET 205 can be arranged side-by-side and placed on the same side of the DBC layer 202. One or more peripheral blocks 501 (e.g., gate drivers, resistors, and capacitors) can also be packaged on the same DBC layer 202 or another DBC layer. Connections between different blocks and devices are achieved through metal patterning or wire bonding on the DBC layer 202.

[0067] Figure 9A ninth GaN / SiC cascode power device 900 is shown packaged according to one of the parallel packaging solutions disclosed herein. The power device 900 includes an LV GaN HEMT 201 and one or more HV SiC JFETs (e.g., a first HV SiC JFET 901 and / or a second HV SiC JFET 902). The LV GaN HEMT 201 can be connected to one or more SiC JFETs 901, 902 via a DBC layer 202. The LV GaN HEMT 201 and one or more SiC JFETs 901, 902 can be arranged face-to-face or side-by-side on the same side of the DBC layer 202. Peripheral components (e.g., gate drivers and passive components) can be integrated into the LV GaN HEMT 201. The power device 900 can be embedded in the leadframe of any commercial or novel packaging solution, such as TO247, TO263, and PCB-embedded packages. The connection between the power device 900 and the lead frame of the commercial packaging solution can be a bonding wire, a copper clip, or a via through the DBC layer 202.

[0068] Figure 10 A tenth GaN / SiC cascode power device 1000, packaged according to one of the disclosed parallel packaging solutions, is shown. The power device 1000 includes one or more LV GaN HEMTs (e.g., a first LV GaN HEMT 1001 and / or a second LV GaN HEMT 1002) and one or more HV SiC JFETs (e.g., a first HV SiC JFET 901 and / or a second HV SiC JFET 902). One or more LV GaN HEMTs 1001, 1002 can be connected to one or more SiC JFETs 901, 902 via a DBC layer 202. One or more LV GaN HEMTs 1001, 1002 and one or more SiC JFETs 901, 902 can be arranged face-to-face or side-by-side on the same side of the DBC layer 202. Peripheral components (e.g., gate drivers and passive components) can be integrated into one or more LV GaN HEMTs 1001, 1002. The power device 1000 can be embedded in the leadframe of any commercial or novel packaging solution, such as TO247, TO263, PCB embedded packages, etc. The connection between the power device 1000 and the leadframe of the commercial packaging solution can be a bonding wire, a copper clip, or a via through the DBC layer 202.

[0069] Figure 11An eleventh GaN / SiC cascode power device 1100 is shown packaged according to one of the disclosed parallel packaging solutions. The eleventh GaN / SiC cascode power device 1100 is formed from a tenth GaN / SiC cascode power device 1000, which further includes one or more peripheral blocks 501 such as gate drivers or passive components (resistors, capacitors, etc.). The one or more peripheral blocks 501 may be connected to the same DBC layer 202.

[0070] Figure 12 This diagram illustrates one implementation of multiple GaN / SiC cascode power devices (e.g., first power device 1201 and second power device 1202) in a power module 1200. The multiple GaN / SiC cascode power devices 1201 and 1202 can be implemented on the same DBC layer 202 to form the power module 1200, such as a half-bridge or bidirectional switch. Connections between the multiple GaN / SiC cascode power devices 1201 and 1202 can be achieved via bonding wires or metal patterns on the DBC layer 202. Peripheral blocks can be integrated with an LV GaN HEMT or connected to the DBC layer 202 as discrete components. Connections between the individual GaN / SiC cascode power devices and the leadframe of a commercially available packaging solution can be via bonding wires, copper clips, or metal vias.

[0071] Figure 13 A twelfth GaN / SiC cascode power device 1300 is shown packaged according to one of the disclosed packaging solutions. The power device 1300 includes an LV GaN HEMT 210 and an HV SiC JFET 205, with no adapter DBC layer between the HEMT 210 and JFET 205. The pad layouts of the LV GaN HEMT 210 and HV SiC JFET 205 can be designed to match each other (i.e., positionally aligned), thus omitting the adapter DBC layer. One or more LV GaN HEMTs 201 can be directly attached to one or more HV SiC JFETs 205. Peripheral components such as gate drivers and passive components can be integrated into the LV GaN HEMT. The GaN / SiC cascode device can be embedded in the leadframe of any commercial or novel packaging solution, such as TO247, TO263, PCB embedded packages, etc. The connection between the power device 1300 and the leadframe of the commercial packaging solution can be a bonding wire, copper clip, or metal via.

[0072] The embodiments of this disclosure are developed based on the details, examples, applications, etc. of the various power devices, power modules, and packaging solutions summarized above, as follows.

[0073] The first aspect of this disclosure is to provide a thirteenth GaN / SiC cascode power device. The thirteenth GaN / SiC cascode power device encompasses various implementations of the first to eleventh GaN / SiC cascode power devices 200, 300a, 300b, 400, 500, 600, 700, 800, 900, 1000, and 1100. Therefore, embodiments of the thirteenth GaN / SiC cascode power device include the first to eleventh GaN / SiC cascode power devices 200, 300a, 300b, 400, 500, 600, 700, 800, 900, 1000, and 1100.

[0074] For example, the thirteenth GaN / SiC cascode power device includes a first transistor group, a second transistor group, and a backbone layer. The first transistor group consists of one or more LV normally-off GaN HEMTs. The second transistor group consists of one or more HV normally-on SiC JFETs. The backbone layer is used to mechanically support the corresponding transistors in the first and second transistor groups and to provide electrical connections between the corresponding transistors. The backbone layer is intended to perform the same function as the DBC layer 202 as detailed above. The backbone layer is formed by embedding a conductive trace network on or within an insulating rigid layer. The corresponding transistors are mounted on the backbone layer and the electrical connections between the corresponding transistors are completed through the conductive trace network. If the thirteenth GaN / SiC cascode power device adopts a planar GaN / SiC cascode device model, the conductive trace network performs the same function as the metal pattern 203; or if the thirteenth GaN / SiC cascode power device adopts a stacked GaN / SiC cascode device model, the conductive trace network performs the same function as the metal pattern 203 plus the metal via 204.

[0075] In one method of implementing a thirteenth-generation GaN / SiC cascode power device, a first transistor group and a second transistor group are arranged face-to-face, such that the first and second transistor groups are located on two opposite sides of a backbone layer. An insulating rigid layer includes one or more vias, such that at least one conductive trace in a conductive trace network extends through the one or more vias to achieve an electrical connection between the first and second transistor groups. Individual vias in the insulating rigid layer perform the same function as vias 234 formed in the substrate of the DBC layer 202. It should be noted that individual vias differ from each metal via 204 in the DBC layer 202 in that each metal via 204 is a metal conductor penetrating the DBC layer 202, while individual vias are hollow channels penetrating the insulating rigid layer and allowing conductive traces in the conductive trace network to pass through them.

[0076] In another method for realizing the thirteenth GaN / SiC cascode power device, the first transistor group and the second transistor group are arranged side by side, such that the first transistor group and the second transistor group are located on the same side of the backbone layer.

[0077] In one option, the second transistor group is further limited to a plurality of HV normally-on SiC JFETs. Furthermore, a conductive trace network is configured to electrically connect the plurality of HV normally-on SiC JFETs in parallel to enhance the current capacity that the GaN / SiC cascode power device can handle.

[0078] In another option, the first transistor group is further limited to a plurality of LV normally-off GaN HEMTs. Furthermore, a conductive trace network is configured to electrically connect the plurality of LV normally-off GaN HEMTs in parallel to improve the current capacity that the GaN / SiC cascode power device can handle.

[0079] In another option, the first transistor group is further limited to a plurality of LV normally-off GaN HEMTs, while the second transistor group is further limited to a plurality of HV normally-on SiC JFETs. Furthermore, the conductive trace network is configured to electrically connect the plurality of LV normally-off GaN HEMTs in parallel and the plurality of HV normally-on SiC JFETs in parallel to improve the current capacity that the GaN / SiC cascode power device can handle.

[0080] In an additional option, the first transistor group is further limited to a single LV normally-off GaN HEMT, and the second transistor group is further limited to a single HV normally-on SiC JFET.

[0081] In some embodiments, the thirteenth GaN / SiC cascode power device further includes one or more peripheral blocks. Each of the one or more peripheral blocks comprises one or more electronic components electrically connected to the first transistor group via a conductive trace network. Each of the one or more electronic components may be a gate driver, a controller, or a passive electronic component.

[0082] In some embodiments, one or more peripheral blocks are integrated with the first transistor group.

[0083] In some embodiments, the backbone layer is implemented as a DBC layer, AMB layer, DPC layer, insertion layer, or redistribution layer.

[0084] In some embodiments, the rigid insulating layer is composed of AlN, Al2O3, Si3N4, epoxy resin, polymer or other insulating materials.

[0085] A second aspect of this disclosure is to provide a first power module. The disclosed first power module summarizes the power module 1200 as described above. Embodiments of the first power module include the power module 1200.

[0086] Exemplarily, the first power module includes a plurality of power devices. Specifically, each of the respective power devices is any embodiment of the thirteenth GaN / SiC cascode power device disclosed above. Furthermore, the respective insulating rigid layers of the respective power devices are planarly connected to form a single insulating sheet. The first power module can be manufactured by implementing the respective power devices using a single insulating sheet instead of multiple insulating rigid layers.

[0087] In some embodiments, a single insulating sheet is made of AlN, Al2O3, Si3N4, epoxy resin, polymer or other insulating materials.

[0088] A third aspect of this disclosure is to provide a fourteenth GaN / SiC cascode power device. The fourteenth GaN / SiC cascode power device encompasses various implementations of the twelfth GaN / SiC cascode power device 1300. Embodiments of this fourteenth GaN / SiC cascode power device include the twelfth GaN / SiC cascode power device 1300.

[0089] For example, the fourteenth GaN / SiC cascode power device includes an LV normally-off GaN HEMT and an HV normally-on SiC JFET. The first pad pattern of the LV normally-off GaN HEMT matches (i.e., is positionally aligned) with the second pad pattern of the HV normally-on SiC JFET. Furthermore, the LV normally-off GaN HEMT is directly attached to the HV normally-on SiC JFET, with the first and second pad patterns aligned to form the fourteenth GaN / SiC cascode power device. Therefore, in the fourteenth GaN / SiC cascode power device, a backbone layer is not required for mounting the LV normally-off GaN HEMT and the HV normally-on SiC JFET.

[0090] This disclosure may be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, this embodiment is to be regarded in all respects as illustrative rather than restrictive. The scope of the invention is defined by the appended claims rather than the foregoing description, and all modifications falling within the meaning and scope of the equivalents of the claims are intended to be covered within the invention.

Claims

1. A GaN / SiC cascode power device, comprising: The first transistor group consists of one or more low-voltage LV normally off GaN high electron mobility transistors (HEMTs). The second transistor group consists of one or more high-voltage HV normally open SiC junction field-effect transistors (JFETs); as well as A backbone layer is used to mechanically support corresponding transistors in a first transistor group and a second transistor group and to provide electrical connections between the corresponding transistors. The backbone layer is formed by embedding a conductive trace network on or inside an insulating rigid layer. The corresponding transistors are mounted on the backbone layer and the electrical connections between the corresponding transistors are completed through the conductive trace network.

2. The GaN / SiC cascode power device according to claim 1, wherein: The first transistor group and the second transistor group are arranged face-to-face, such that the first transistor group and the second transistor group are located on two opposite sides of the backbone layer; and The insulating rigid layer includes one or more vias, such that at least one conductive trace in the conductive trace network extends through the one or more vias for an electrical connection between the first transistor group and the second transistor group.

3. The GaN / SiC cascode power device according to claim 1, wherein, The first transistor group and the second transistor group are arranged side by side, such that the first transistor group and the second transistor group are located on the same side of the backbone layer.

4. The GaN / SiC cascode power device according to claim 1, wherein: The second transistor group is further limited to consisting of multiple HV normally-on SiC JFETs; and The conductive trace network is configured to electrically connect the plurality of HV normally open SiC JFETs in parallel to improve the current capacity that the GaN / SiC cascode power device can handle.

5. The GaN / SiC cascode power device according to claim 1, wherein: The first transistor group is further limited to consisting of multiple LV normally-off GaN HEMTs; and The conductive trace network is configured to electrically connect the plurality of LV normally off GaN HEMTs in parallel to improve the current capacity that the GaN / SiC cascode power devices can handle.

6. The GaN / SiC cascode power device according to claim 1, wherein: The first transistor group is further limited to consisting of multiple LV normally-off GaN HEMTs; The second transistor group is further limited to consisting of multiple HV normally-on SiC JFETs; and The conductive trace network is configured to electrically connect the plurality of LV normally-off GaN HEMTs in parallel and the plurality of HV normally-on SiC JFETs in parallel, thereby increasing the current capacity that the GaN / SiC cascode power devices can handle.

7. The GaN / SiC cascode power device according to claim 1, wherein: The first transistor group is further limited to consisting of a single LV normally-off GaN HEMT; and The second transistor group is further limited to a single HV normally-on SiC JFET.

8. The GaN / SiC cascode power device according to claim 1 further includes one or more peripheral blocks, wherein, Each of the one or more peripheral blocks consists of one or more electronic components electrically connected to the first transistor group via a network of conductive traces.

9. The GaN / SiC cascode power device according to claim 8, wherein, The one or more peripheral blocks are integrated with the first transistor group.

10. The GaN / SiC cascode power device according to claim 8, wherein, Each of the one or more electronic components is a gate driver, a controller, or a passive electronic component.

11. The GaN / SiC cascode power device according to claim 1, wherein, The backbone layer is implemented as a direct bonded copper (DBC) layer, an active metal brazing (AMB) layer, a direct copper plating (DPC) layer, an insertion layer, or a redistribution layer.

12. The GaN / SiC cascode power device according to claim 1, wherein, The rigid insulating layer is composed of AlN, Al2O3, Si3N4, epoxy resin, polymer or other insulating materials.

13. A power module comprising a plurality of power devices, wherein: Each of the plurality of power devices is configured as a GaN / SiC cascode power device according to claim 1; and The corresponding rigid insulating layers of the respective power devices are connected in planar connection to form a single insulating sheet.

14. The power module according to claim 13, wherein, The individual insulating sheet is composed of AlN, Al2O3, Si3N4, epoxy resin, polymer or other insulating materials.

15. A GaN / SiC cascode power device, comprising: Low-voltage LV normally-off GaN high electron mobility transistor (HEMT); as well as High-voltage HV normally open SiC junction field-effect transistor (JFET); The first pad pattern of the LV normally off GaN HEMT matches the second pad pattern of the HV normally on SiC JFET, and the LV normally off GaN HEMT is directly attached to the HV normally on SiC JFET. The first pad pattern and the second pad pattern are aligned to form the GaN / SiC cascode power device.

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