Semiconductor device

Abstract

The invention provides a semiconductor device which suppresses an increase in manufacturing cost and an increase in chip size. The semiconductor device includes: a first resistor; a first switching element having a first end connected to the first resistor, and a second end and a gate connected to each other; a second switching element having a first end to which a voltage lower than the first voltage is input and a gate connected to the second end and the gate of the first switching element; a level shifter to which a first voltage, a voltage at a first terminal of the second switching element, and a first signal are input, and which has first and second output terminals; a first capacitor having a first end connected to the first output end and a second end connected to the first node; a third switching element having a first end connected to the first node and a gate controlled in accordance with a signal output to the second output end; and a fourth switching element having a first terminal controlled according to a signal output to the first node, a gate connected to the second output terminal, and a second terminal to which the first voltage is input.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2024-159185 (filed on September 13, 2024). This application incorporates all contents of the basic application by reference to that basic application. Technical Field

[0003] This embodiment relates to a semiconductor device. Background Technology

[0004] Semiconductor devices for supplying voltage to a load are known. Such semiconductor devices include charge pumps for boosting the voltage. Summary of the Invention

[0005] This embodiment provides a semiconductor device that suppresses the increase in manufacturing costs and the increase in chip size.

[0006] The semiconductor device of the embodiment includes: a first resistor having a first terminal and a second terminal to which a first voltage is input; a first switching element having a first terminal connected to the second terminal of the first resistor, a second terminal connected to both the first and second resistors, and a gate; a second switching element having a first terminal to which a second voltage lower than the first voltage is input, a gate connected to the second terminal and the gate of the first switching element, and a second terminal grounded; a level shifter having a first input terminal to which the first voltage is input, a second input terminal connected to the first terminal of the second switching element, a third input terminal to which a first signal is input, a first output terminal, and a second output terminal; and a first capacitor having a first terminal connected to the first output terminal of the level shifter, and a second terminal connected to the first output terminal of the level shifter. The level shifter comprises a second terminal connected to a node; a third switching element having a first terminal connected to the first node and a gate controlled in accordance with the signal output to the second output terminal of the level shifter; and a fourth switching element having a first terminal controlled according to the signal output to the first node, a gate connected to the second output terminal of the level shifter together with the gate of the third switching element, and a second terminal to which the first voltage is input. The level shifter is configured to output a second signal that is level-shifted to a voltage higher than the first signal from the first output terminal based on the first voltage, the second voltage, and the first signal, and to output a third signal that is an inverted signal of the second signal from the second output terminal. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating an example of the configuration of a semiconductor device in an implementation.

[0008] Figure 2 This is a circuit diagram illustrating an example of the configuration of a semiconductor device for implementing an embodiment.

[0009] Figure 3 This is a timing diagram used to illustrate the operation of the semiconductor device in the implementation method.

[0010] Figure 4 It is a circuit diagram that illustrates the operation of a semiconductor device in an embodiment and represents a portion of the semiconductor device.

[0011] Figure 5 It is a circuit diagram that illustrates the operation of a semiconductor device in an embodiment and represents a portion of the semiconductor device. Detailed Implementation

[0012] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same function and configuration will be labeled with the same reference numerals as in the accompanying drawings.

[0013] 1 Implementation Method

[0014] The semiconductor device of the embodiment will be described.

[0015] First, the configuration of the semiconductor device in the embodiment will be explained.

[0016] use Figure 1 An overview of the configuration of the semiconductor device in the embodiment will be described. Figure 1 This is a block diagram illustrating an example of the configuration of a semiconductor device in an embodiment.

[0017] Semiconductor device 1 is, for example, an IC (Integrated Circuit) chip. Semiconductor device 1 generates voltage Vout based on voltage Vin supplied from an external power source 2 and a signal clk1. Voltage Vout is a voltage higher than voltage Vin (Vout > Vin). Signal clk1 is a clock signal. The "L" level voltage of signal clk1 is, for example, voltage VSS. Voltage VSS is ground voltage. The "H" level voltage of signal clk1 is, for example, voltage VDD. Voltage VDD is a voltage higher than voltage VSS (VDD > VSS). As described above, semiconductor device 1 is configured to boost voltage Vin using a clock signal. Then, semiconductor device 1 outputs voltage Vout to load 3.

[0018] Semiconductor device 1 includes terminals PVin, Pclk, and PVout.

[0019] Terminal PVin is connected, for example, to an external power source 2 of the semiconductor device 1. Voltage Vin is supplied from the power source 2 to terminal PVin.

[0020] For example, a signal clk1 is supplied to terminal Pclk from an external circuit of semiconductor device 1. Furthermore, in this embodiment, an example is shown where the signal clk1 is input from outside semiconductor device 1, but this is not a limitation. The signal clk1 can also be generated through an internal configuration of semiconductor device 1.

[0021] Terminal PVout is connected to load 3. Voltage Vout is supplied from terminal PVout to load 3.

[0022] Next, use Figure 2 The circuit configuration of semiconductor device 1 will be described. Figure 2 This is a circuit diagram illustrating an example of the configuration of a semiconductor device for implementing an embodiment.

[0023] Semiconductor device 1 includes switching elements Q1, Q2, Q3, Q4, Q5, Q6, Q7 and Q8, resistors R1 and R2, operational amplifier AMP, level shifter LS, capacitors CP1 and CP2, and circuits C1 and C2.

[0024] Switching elements Q2, Q3, Q6, and Q8 are, for example, N-type MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). Switching element Q2 is, for example, an N-type MOSFET with a higher breakdown voltage than switching elements Q3, Q6, and Q8. Switching elements Q1, Q4, Q5, and Q7 are, for example, P-type MOSFETs. Switching elements Q1 and Q4 are, for example, P-type MOSFETs with a higher breakdown voltage than switching elements Q5 and Q7.

[0025] One end of resistor R1 is connected to terminal PVin. The other end of resistor R1 is connected to node N1. Resistor R1 is a resistor whose resistance value varies with temperature. For example, resistor R1 is configured such that its resistance value decreases as the temperature increases. Resistor R1 is, for example, a polycrystalline resistor (polycrystalline silicon resistor).

[0026] Furthermore, resistor R1 is configured such that the voltage at node N1 is equal to the voltage (Vin-VDD).

[0027] One end of the switching element Q1 is connected to node N1. The gate and the other end of the switching element Q1 are connected together.

[0028] One end of the switching element Q2 is connected to the gate of the switching element Q1 and the other end.

[0029] The operational amplifier AMP has a non-inverting input terminal (+), an inverting input terminal (-), and an output terminal. The non-inverting input terminal (+) of the operational amplifier AMP is supplied with a temperature-independent voltage Vref. This voltage Vref is, for example, a voltage lower than (Vin - VDD) (Vref < (Vin - VDD)). The inverting input terminal (-) of the operational amplifier AMP is connected to the other end of the switching element Q2. The output terminal of the operational amplifier AMP is connected to the gate of the switching element Q2. The operational amplifier AMP compares the magnitude of the voltage Vref at the non-inverting input terminal (+) with the voltage at the inverting input terminal (-) (the voltage at the other end of the switching element Q2). When the voltage at the other end of the switching element Q2 is higher than the voltage Vref, a low voltage is output from the output terminal of the operational amplifier AMP. When the voltage at the other end of the switching element Q2 is lower than the voltage Vref, a high voltage is output from the output terminal of the operational amplifier AMP. Through these operations, the operational amplifier AMP is configured such that the voltage at the other end of the switching element Q2 is the same as the temperature-independent voltage Vref.

[0030] One end of resistor R2 is connected to the other end of switching element Q2 and the inverting input terminal (-) of operational amplifier AMP. The other end of resistor R2 is grounded. Like resistor R1, resistor R2 is a temperature-dependent resistor. Like resistor R1, resistor R2 may be configured such that its resistance decreases with increasing temperature. Like resistor R1, resistor R2 may be a polycrystalline resistor (polysilicon resistor). Since the voltage applied to resistor R2 is a temperature-independent voltage Vref, the higher the temperature, the greater the current flowing through resistor R2. This current also flows through resistor R1, therefore the voltage applied to resistor R1 is temperature-independent. Thus, the voltage at node N1 is configured as a temperature-independent voltage (Vin - VDD).

[0031] In the above configuration, the part including the switching element Q2, the operational amplifier AMP, and the resistor R2 functions as a current source.

[0032] One end of switching element Q3 is connected to terminal PVin. The other end of switching element Q3 is connected to node N2. The gate of switching element Q3 is connected to node N1.

[0033] One end of switching element Q4 is connected to node N2. The other end of switching element Q4 is grounded. The gate of switching element Q4 is connected to the gate of switching element Q1 and the other end of switching element Q1.

[0034] In the configuration described above, the portion including switching elements Q1 and Q4 is configured such that the voltage VN1 at node N1 is equal to the voltage VN2 at node N2. That is, voltages VN1 and VN2 are equal to the voltage (Vin - VDD).

[0035] Furthermore, in the above configuration, switching element Q3 functions as a pull-up circuit for node N2. Additionally, switching element Q4 functions as a pull-down circuit for node N2.

[0036] To further elaborate, for example, if voltage VN2 is lower than voltage VN1 (voltage (Vin-VDD)) due to various influences, switching element Q3 operates as a pull-up circuit. Thus, voltage VN2 becomes the same as voltage VN1 (voltage (Vin-VDD)). Conversely, for example, if voltage VN2 is higher than voltage VN1 (voltage (Vin-VDD)) due to various influences, switching element Q4 operates as a pull-down circuit. Thus, voltage VN2 becomes the same as voltage VN1 (voltage (Vin-VDD)).

[0037] Furthermore, the section including switching elements Q1, Q3, and Q4 functions as a buffer circuit capable of driving large currents. Thus, the current flowing through switching element Q3 and the current flowing through switching element Q4 can, for example, be larger than the current flowing through resistor R1 and the current flowing through switching element Q2, and are configured as voltage sources (voltage (Vin-VDD)) with low impedance at node N2.

[0038] The level shifter LS includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The first input terminal of the level shifter LS is connected to terminal PVin. Thus, a voltage Vin is input to the level shifter LS. The second input terminal of the level shifter LS is connected to node N2. Thus, a voltage VN2, equal to the voltage (Vin-VDD), is input to the level shifter LS. A signal clk1 is input to the third input terminal of the level shifter LS. The level shifter LS uses the input voltages Vin and VN2, and the signal clk1, as described above, to generate signals clk2 and clk2b. Signals clk2 and clk2b are clock signals. Signal clk2b is the inverted version of signal clk2. The generation of signals clk2 and clk2b will be described later. Signal clk2 is output from the first output terminal of the level shifter LS. Signal clk2b is output from the second output terminal of the level shifter LS.

[0039] More specifically, regarding the generation of signals clk2 and clk2b, the level shifter LS generates signals clk2 and clk2b by making the "H" level voltage (high voltage) of signals clk2 and clk2b equal to the voltage Vin. Alternatively, the level shifter LS generates signals clk2 and clk2b by making the "L" level voltage (low voltage) of signals clk2 and clk2b equal to the voltage (Vin-VDD).

[0040] Circuit C1 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of circuit C1 is connected to the first output terminal of level shifter LS. The second input terminal of circuit C1 is connected to terminal PVin. The third input terminal of circuit C1 is connected to node N2. Circuit C1 generates a signal clk2' based on signal clk2. Signal clk2', like signal clk2, is a clock signal generated in a manner where a voltage at "H" level becomes voltage Vin, and a voltage at "L" level becomes voltage (Vin-VDD). Signal clk2' is output from the output terminal of circuit C1. Circuit C1 may have, for example, a configuration of two inverter circuits connected in series. With this configuration, circuit C1 is configured, for example, to supply sufficient current for driving the charge pump when the clock signal generated by level shifter LS is supplied to the charge pump described later.

[0041] Circuit C2 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of circuit C2 is connected to the second output terminal of the level shifter LS. The second input terminal of circuit C2 is connected to terminal PVin. The third input terminal of circuit C2 is connected to node N2. Circuit C2 generates a signal clk2b' based on the signal clk2b. Like signal clk2b, signal clk2b' is a clock signal generated in a manner where a voltage at "H" level becomes voltage Vin, and a voltage at "L" level becomes voltage (Vin-VDD). Signal clk2b' is the inverted signal of signal clk2b. Signal clk2b' is output from the output terminal of circuit C2. Circuit C2, for example, has a configuration similar to circuit C1, consisting of two inverter circuits connected in series. With this configuration, circuit C2, like circuit C1, is designed, for example, to supply sufficient current to drive the charge pump when the clock signal generated by the level shifter LS is supplied to the charge pump.

[0042] One end of capacitor CP1 is connected to the output terminal of circuit C1. The other end of capacitor CP1 is connected to node N3. With the above configuration, a signal based on signal clk2' can be supplied to node N3 via capacitor CP1.

[0043] One end of capacitor CP2 is connected to the output terminal of circuit C2. The other end of capacitor CP2 is connected to node N4. With the above configuration, a signal based on signal clk2b' can be supplied to node N4 via capacitor CP2.

[0044] One end of switching element Q5 is connected to node N3. The gate of switching element Q5 is connected to node N4. The other end of switching element Q5 is connected to terminal PVout. Switching element Q5 is configured to be in the on state when a voltage Vin is applied to node N4. Additionally, switching element Q5 is configured to be in the off state when a voltage (Vin+VDD) is applied to node N4.

[0045] One end of switching element Q6 is connected to node N3. The gate of switching element Q6 is connected to node N4 together with the gate of switching element Q5. The other end of switching element Q6 is connected to terminal PVin. Switching element Q6 is configured to be in the on state when a voltage (Vin+VDD) is applied to node N4. Additionally, switching element Q6 is configured to be in the off state when a voltage Vin is applied to node N4.

[0046] One end of switching element Q7 is connected to node N4. The gate of switching element Q7 is connected to node N3. The other end of switching element Q7, together with the other end of switching element Q5, is connected to terminal PVout. Switching element Q7 is configured to be in a conducting state when a voltage Vin is applied to node N3. Additionally, switching element Q7 is configured to be in a disconnected state when a voltage (Vin+VDD) is applied to node N3.

[0047] One end of switching element Q8 is connected to node N4. The gate of switching element Q8 is connected to node N3 together with the gate of switching element Q7. The other end of switching element Q8 is connected to terminal PVin. Switching element Q8 is configured to be in a conducting state when a voltage (Vin+VDD) is applied to node N3. Additionally, switching element Q8 is configured to be in a disconnected state when a voltage Vin is applied to node N3.

[0048] Switching elements Q5 to Q8, along with capacitors CP1 and CP2, function as charge pumps.

[0049] Next, use Figure 3 , Figure 4 and Figure 5 The operation of the semiconductor device 1 in the embodiment will be explained. Figure 3 This is a timing diagram used to illustrate the operation of the semiconductor device in the implementation method. Figure 3 The diagram shows the signals clk1, clk2, and clk2b during the operation of semiconductor device 1, the voltage VN3 at node N3, and the voltage VN4 at node N4. Figure 4 and Figure 5 It is a circuit diagram that illustrates the operation of a semiconductor device in an embodiment and represents a portion of the semiconductor device.

[0050] When the semiconductor device 1 is operating, as described above, the input signal clk1 is used as a clock signal. The period T1 during which the signal clk1 is at the "H" level and the period T2 during which the signal clk1 is at the "L" level have, for example, the same length.

[0051] In semiconductor device 1, with the configuration described above, signals clk2 and clk2b, which are inverted signals, are generated based on signal clk1 and voltage Vin. Signal clk2 has a "H" level during period T1 and a "L" level during period T2. Signal clk2b has a "L" level during period T1 and a "H" level during period T2. Furthermore, the voltages of signals clk2' and clk2b', based on signals clk2 and clk2b, change in the same way as signals clk2 and clk2b, and therefore are not shown in the figure.

[0052] Furthermore, during the period when signals clk2 and clk2' are at "H" level and signals clk2b and clk2b' are at "L" level, through the operation of the charge pump described later, voltage VN3 becomes voltage (Vin+VDD) via capacitor CP1. On the other hand, voltage VN4 is set to voltage Vin.

[0053] Furthermore, during the period when signals clk2 and clk2' are at "L" level and signals clk2b and clk2b' are at "H" level, through the operation of the charge pump described later, voltage VN4 becomes voltage (Vin + VDD) via capacitor CP2. On the other hand, voltage VN3 becomes voltage Vin.

[0054] use Figure 4 The operation of the charge pump during period T1 is explained.

[0055] Through the capacitor CP1 charged by the operation of period T2 (described later) and the signal clk2' set as voltage Vin, voltage VN3 becomes voltage (Vin+VDD). As a result, switching element Q7 becomes off and switching element Q8 becomes on. Therefore, voltage VN4 is the same as voltage Vin. Therefore, switching element Q5 becomes on and switching element Q6 becomes off. As described above, during period T1, a voltage approximately equal to voltage (Vin+VDD) is supplied to terminal PVout via the on-state switching element Q5.

[0056] In addition, the voltage Vin input via terminal PVin is used to charge capacitor CP2 based on the signal clk2b' which is a voltage (Vin-VDD) via the on-state switching element Q8.

[0057] use Figure 5 The operation of the charge pump during period T2 is explained.

[0058] Through the capacitor CP2 charged during operation T1, and the signal clk2b' which is the voltage Vin, voltage VN4 becomes voltage (Vin+VDD). Consequently, switching element Q5 is in the off state, and switching element Q6 is in the on state. Therefore, voltage VN3 is equal to voltage Vin. Therefore, switching element Q7 is in the on state, and switching element Q8 is in the off state. As described above, during operation T2, a voltage approximately equal to voltage (Vin+VDD) is supplied to terminal PVout via the on-state switching element Q7.

[0059] In addition, the voltage Vin input via terminal PVin is used to charge capacitor CP1 via the on-state switching element Q6 based on the signal clk2' which is a voltage (Vin-VDD).

[0060] As described above, during the operation of semiconductor device 1, voltage (Vin+VDD) is output from terminal PVout to load 3.

[0061] According to an embodiment of the semiconductor device 1, the semiconductor device 1 includes a resistor R1, switching elements Q1, Q4, Q5 and Q6, a level shifter LS, and a capacitor CP1. Resistor R1 has a first terminal for receiving an input voltage Vin. Switching element Q1 has a first terminal connected to a second terminal of resistor R1, a second terminal connected to both terminals, and a gate. Switching element Q4 has a first terminal for receiving an input voltage (Vin-VDD), a gate connected to the second terminal and gate of switching element Q1, and a second terminal grounded. Level shifter LS has a first input terminal for receiving the input voltage Vin, a second input terminal connected to the first terminal of switching element Q4, a third input terminal for receiving an input signal clk1, a first output terminal, and a second output terminal. Based on voltage Vin, voltage (Vin-VDD), and signal clk1, level shifter LS outputs a signal clk2, shifted to a voltage higher than signal clk1, from the first output terminal, and outputs a signal clk2b, which is an inverted signal, from the second output terminal. Capacitor CP1 has a first terminal connected to the first output terminal of level shifter LS and a second terminal connected to node N3. Switching element Q5 has a first terminal connected to node N3 and a gate connected to the second output terminal of level shifter LS. Switching element Q6 has a first terminal connected to node N3, a gate connected to the second output terminal of level shifter LS along with the gate of switching element Q5, and a second terminal connected to the input voltage Vin. With this configuration, the increase in manufacturing cost and chip size can be suppressed.

[0062] If further explained, when the "L" level voltage of the clock signal used to charge the capacitor of the charge pump is ground (in the comparative example), the potential difference between one end of the capacitor becomes larger compared to when the capacitor is charged using a clock signal with an "L" level voltage higher than ground. Therefore, a high-voltage capacitor is provided in the semiconductor device of the comparative example. However, providing a high-voltage capacitor leads to increased production costs and chip size.

[0063] According to the embodiment, a signal clk2' generated in a manner where the "H" level is voltage Vin and the "L" level is a voltage higher than voltage VSS (Vin-VDD) is input to the other end of capacitor CP1. This suppresses the increase in the potential difference between one end and the other end of capacitor CP1. Therefore, it is possible to suppress the increase in the cost and size of the capacitor.

[0064] 2 Other

[0065] In the above embodiment, the semiconductor device 1 is described as having a charge pump with a first stage (stage) including switching elements Q5 to Q8, but it is not limited to this. The semiconductor device 1 may also have a charge pump with multiple stages.

[0066] Although not shown, for example, in the case where the semiconductor device 1 is equipped with a charge pump having two stages, the semiconductor device 1 also includes switching elements Q9, Q10, Q11, and Q12, and capacitors CP3 and CP4. The switching elements Q9, Q10, Q11, and Q12, and capacitors CP3 and CP4 have the same configuration as the switching elements Q5 to Q8 and capacitors CP1 and CP2.

[0067] One end of capacitor CP3 is connected to the output terminal of circuit C1 in the same way as capacitor CP1. The other end of capacitor CP3 is connected to node N5.

[0068] One end of capacitor CP4 is connected to the output terminal of circuit C2 in the same way as capacitor CP2. The other end of capacitor CP4 is connected to node N6.

[0069] One end of switching element Q9 is connected to node N5. The gate of switching element Q9 is connected to node N6. The other end of switching element Q9 is connected to terminal PVout.

[0070] One end of switching element Q10 is connected to node N5. The gate of switching element Q10 is connected to node N6 together with the gate of switching element Q9. The other end of switching element Q10 is connected to the other ends of switching elements Q5 and Q7. In other examples, the other ends of switching elements Q5 and Q7 are connected to terminal PVout via a stage of a charge pump containing switching elements Q9, Q10, Q11, and Q12.

[0071] One end of switching element Q11 is connected to node N6. The gate of switching element Q11 is connected to node N5. The other end of switching element Q11, together with the other end of switching element Q9, is connected to terminal PVout.

[0072] One end of switching element Q12 is connected to node N6. The gate of switching element Q12 is connected to node N5 together with the gate of switching element Q11. The other end of switching element Q12 is connected to the other end of switching elements Q5 and Q7 together with the other end of switching element Q10.

[0073] In the configuration described above, switching elements Q5 to Q8 and capacitors CP1 and CP2 function as the first stage of the charge pump. Additionally, switching elements Q9 to Q12 and capacitors CP3 and CP4 function as the second stage of the charge pump.

[0074] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as described in the claims and its equivalents.

[0075] While several embodiments of the invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the scope of the invention as described in the claims and its equivalents.

[0076] [Explanation of reference numerals in the attached figures]

[0077] 1…semiconductor device, 2…power source, 3…load, Q1~Q8…switching element, LS…level shifter, R1, R2…resistor, AMP…operational amplifier, CP1, CP2…capacitor, C1, C2…circuit.

Claims

1. A semiconductor device, characterized in that, have: The first resistor has a first terminal and a second terminal that are subjected to a first voltage input. The first switching element has a first end connected to the second end of the first resistor, a second end connected to the second end of the first resistor, and a gate; The second switching element has a first terminal that receives a second voltage lower than the first voltage, a gate connected to the second terminal and the gate of the first switching element, and a second terminal that is grounded. A level shifter has a first input terminal for receiving the first voltage, a second input terminal connected to a first terminal of the second switching element, a third input terminal for receiving the first signal, a first output terminal, and a second output terminal; The first capacitor has a first end connected to the first output terminal of the level shifter and a second end connected to the first node; The third switching element has a first terminal connected to the first node and a gate that is controlled in accordance with the signal output to the second output terminal of the level shifter; as well as The fourth switching element has a first terminal controlled according to a signal output to the first node, a gate connected to the second output terminal of the level shifter together with the gate of the third switching element, and a second terminal input with the first voltage. The level shifter is configured as follows: Based on the first voltage, the second voltage, and the first signal, a second signal that has been level-shifted to a voltage higher than the first signal is output from the first output terminal, and a third signal that is the inverted signal of the second signal is output from the second output terminal.

2. The semiconductor device according to claim 1, characterized in that, It also includes a first current source, which has a first end connected to the second end and gate of the first switching element and a second end grounded.

3. The semiconductor device according to claim 2, characterized in that, The first current source includes: The fifth switching element has a first end and a second end connected to the second end and the gate of the first switching element; An operational amplifier having a non-inverting input terminal for receiving a third input voltage, an inverting input terminal connected to the second terminal of the fifth switching element, and an output terminal connected to the gate of the fifth switching element; and The second resistor has a first terminal connected to the second terminal of the fifth switching element and the inverting input terminal of the operational amplifier, and a second terminal grounded.

4. The semiconductor device according to claim 3, characterized in that, It also includes a sixth switching element, which has a first end connected to a first end of the first resistor, a gate connected to a second end of the first resistor and a first end of the first switching element, and a second end connected to a first end of the second switching element and a second input end of the level shifter.

5. The semiconductor device according to claim 4, characterized in that, The current flowing through the sixth switching element is greater than the current flowing through the first resistor.

6. The semiconductor device according to claim 3, characterized in that, The first resistor and the second resistor are configured such that the resistance value decreases as the temperature increases.

7. The semiconductor device according to claim 1, characterized in that, It also has: The second capacitor has a first end connected to the second output terminal of the level shifter and a second end connected to the second node; The fifth switching element has a first terminal connected to the second node and a gate controlled according to a signal output to the first node; as well as The sixth switching element has a first terminal controlled according to a signal output to the second node, a gate connected to the first node together with the gate of the fifth switching element, and a second terminal connected to the second terminal of the fourth switching element. The gates of the third and fourth switching elements are connected to the second node.

8. The semiconductor device according to claim 7, characterized in that, The first switching element, the fourth switching element, and the sixth switching element are N-type transistors. The second, third, and fifth switching elements are P-type transistors.

9. The semiconductor device according to claim 1, characterized in that, The first signal, the second signal, and the third signal are clock signals.

10. The semiconductor device according to claim 9, characterized in that, In the second signal and the third signal, the high voltage state is the state with the first voltage, and the low voltage state is the state with the second voltage.

11. The semiconductor device according to claim 1, characterized in that, It also includes a first circuit, which has: a first input terminal connected to the first output terminal of the level shifter; and a second input terminal to which the first voltage is input. The third input terminal is connected together with the second input terminal of the level shifter to the first terminal of the second switching element; And the output terminal is connected to the first end of the first capacitor, and the first circuit supplies drive current to the first node through the first capacitor.

12. The semiconductor device according to claim 11, characterized in that, The first circuit has two inverter circuits connected in series.

13. The semiconductor device according to claim 3, characterized in that, The third voltage is a temperature-independent voltage.

14. The semiconductor device according to claim 1, characterized in that, The first voltage and the first signal are voltages supplied from outside the semiconductor device.

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