Stacked semiconductor device and manufacturing method thereof

Abstract

A stacked semiconductor device and a method of manufacturing the same are provided. The stacked semiconductor device includes: a substrate; a first source / drain region on the substrate; and a second source / drain region vertically above the first source / drain region, the second source / drain region vertically overlapping a first portion of the first and second portions of the first source / drain region, wherein a first portion of the top surface of the substrate vertically below the first portion of the first source / drain region is coplanar or aligned with a second portion of the top surface of the substrate vertically below the second portion of the first source / drain region.

Description

Technical Field

[0001] The apparatuses and methods consistent with this disclosure relate to semiconductor devices, and more specifically, to stacked semiconductor devices and methods of manufacturing the same, the stacked semiconductor device including a first transistor and a second transistor formed vertically above the first transistor. Background Technology

[0002] In response to the increasing demand for integrated circuits with high device density and performance, stacked semiconductor devices have been introduced. A stacked semiconductor device may include a first transistor at a first level and a second transistor at a second level above the first level, wherein each of the two transistors may be a field-effect transistor (FET), such as a fin field-effect transistor (FinFET), a nanosheet transistor, a fork-plate transistor, or any other type of FET.

[0003] FinFETs have one or more fin structures protruding from a substrate as channel structures and gate structures surrounding at least three surfaces of each fin structure. Nanosheet transistors are characterized by one or more nanosheet channel layers stacked or arranged vertically on a substrate as channel structures and gate structures surrounding all four surfaces of each nanosheet channel layer. Nanosheet transistors are also known as gate-all-around (GAA) transistors or multi-bridge channel field-effect transistors (MBCFETs). Forked transistors are combinations of two nanosheet transistors with an insulating backbone structure between them. In a forked transistor, the nanosheet channel layer of each nanosheet transistor is formed on each side of the insulating backbone structure and extends parallel to the backbone structure through the gate structure.

[0004] In stacked semiconductor devices, a first transistor and a second transistor perpendicularly above it can be formed with different dimensions (e.g., different widths of the channel structure and source / drain regions) to facilitate contact structure formation and achieve optimal device performance. However, due to the complex device structure and high aspect ratio, the formation of stacked semiconductor devices presents various challenges that adversely affect device performance.

[0005] The information disclosed in this background section was already known or derived by the inventor before or during the implementation of embodiments of this application, or it is technical information acquired during the implementation of embodiments. Therefore, it may contain information that does not form prior art already known to the public. Summary of the Invention

[0006] This disclosure provides a method for fabricating a stacked semiconductor device using a dummy channel stack that prevents substrate patterning to avoid the formation of source / drain regions within the substrate at the lower stack, thereby preventing or reducing current leakage from the source / drain regions into the substrate. The method may further utilize a barrier layer to further prevent or reduce current leakage from the source / drain regions into the substrate. This disclosure also provides stacked semiconductor devices fabricated using these methods.

[0007] According to one aspect of this disclosure, a stacked semiconductor device is provided, which may include: a substrate; a first source / drain region on the substrate; and a second source / drain region vertically above the first source / drain region, the second source / drain region vertically overlapping a first portion of a first portion and a second portion of the first source / drain region, wherein a first portion of the top surface of the substrate vertically below the first portion of the first source / drain region is coplanar or aligned with a second portion of the top surface of the substrate vertically below the second portion of the first source / drain region.

[0008] According to one aspect of this disclosure, a stacked semiconductor device is provided, which may include: a first source / drain region on a substrate; a second source / drain region vertically above the first source / drain region, the second source / drain region vertically overlapping a first portion of a first portion and a second portion of the first source / drain region; and a barrier layer on the second portion of the first portion and the second portion of the top surface of the substrate, the second portion of the substrate being vertically below the second portion of the first source / drain region.

[0009] According to one aspect of this disclosure, a method of manufacturing a stacked semiconductor device is provided, the method comprising: forming a first source / drain region on a substrate; and forming a second source / drain region vertically above the first source / drain region, wherein forming the first source / drain region and the second source / drain region is performed such that: the second source / drain region vertically overlaps with a first portion of a first portion and a second portion of the first source / drain region; and a first portion of the top surface of the substrate vertically below the first portion of the first source / drain region is coplanar or aligned with a second portion of the top surface of the substrate vertically below the second portion of the first source / drain region.

[0010] According to one aspect of this disclosure, forming a first source / drain region and a second source / drain region may include: forming a first channel stack and a second channel stack above the first channel stack, such that the second channel stack vertically overlaps with a first portion of a first portion and a second portion of the first channel stack; patterning the second channel stack and the second portion of the first channel stack to form a first space vertically above the first portion of the first channel stack and expose the second portion of the top surface of the substrate; forming a dummy channel stack on the second portion of the top surface of the substrate; and patterning the first channel stack and the dummy channel stack to form a second space and expose the first portion and the second portion of the top surface of the substrate, wherein the first source / drain region is formed in the second space, and the second source / drain region is formed in the first space.

[0011] According to one aspect of this disclosure, a method of manufacturing a stacked semiconductor device is provided, the method comprising: forming a barrier layer on a second portion of a first portion and a second portion of a top surface of a substrate; forming a first source / drain region on the first portion and the second portion of the top surface of the substrate having the barrier layer thereon; and forming a second source / drain region vertically above the first source / drain region, wherein the formation of the first source / drain region and the second source / drain region is performed such that the second source / drain region vertically overlaps with the first portion of the first portion and the second portion of the first source / drain region. Attached Figure Description

[0012] Exemplary embodiments of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figures 1A to 1B arrive Figures 9A to 9B An intermediate semiconductor device is shown after corresponding steps in the fabrication of a stacked semiconductor device according to one or more embodiments, wherein a first field-effect transistor (FET) at a first level and a second FET at a second level above the first level have channel structures of different widths and source / drain regions of different widths.

[0014] Figures 1A to 9A This is a plan view of the intermediate semiconductor device 10', and Figures 1B to 9B They are Figures 1A to 9A A cross-sectional view of the intermediate semiconductor device 10' taken along lines I-I' and / or II-II' shown therein.

[0015] Figures 10A to 10B arrive Figures 17A to 17B An intermediate semiconductor device is shown after the corresponding steps of fabricating a stacked semiconductor device using a dummy channel stack, according to one or more embodiments.

[0016] Figures 10A to 17AIt is a plan view of the intermediate semiconductor device 20', and Figures 10B to 17B They are Figures 10A to 17A A cross-sectional view of the intermediate semiconductor device 20' taken along lines I-I' and / or II-II' shown therein.

[0017] Figures 18A to 18B arrive Figures 24A to 24B An intermediate semiconductor device is shown after corresponding steps in fabricating a stacked semiconductor device using dummy channel stacking and barrier layers, according to one or more embodiments.

[0018] Figures 18A to 24A It is a plan view of the intermediate semiconductor device 30', and Figures 18B to 24B They are Figures 18A to 24A A cross-sectional view of the intermediate semiconductor device 30' taken along lines I-I' and / or II-II' shown therein.

[0019] Figure 25A and Figure 25B A flowchart illustrating the fabrication of a stacked semiconductor device using dummy channel stacks and barrier layers according to one or more embodiments is shown.

[0020] Figure 26 This illustrates a combination of one or more embodiments. Figures 17A to 17B and Figures 24A to 24B A schematic block diagram of an electronic device comprising one or more stacked semiconductor devices. Detailed Implementation

[0021] All embodiments of this disclosure described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto and may be implemented in various other forms. Each embodiment provided in the following description does not exclude association with one or more features of another example or embodiment also provided herein or not provided herein but consistent with this disclosure. For example, even if a matter described in a particular example or embodiment is not described in a different example or embodiment, that matter may be understood to be related to or combined with a different example or embodiment unless otherwise mentioned in its description. Furthermore, it should be understood that all descriptions of the principles, aspects, examples, and embodiments of this disclosure are intended to cover their structural and functional equivalents. Moreover, these equivalents should be understood to include not only currently known equivalents but also equivalents to be developed in the future, that is, all devices for performing the same function, regardless of their structure. For example, the channel layer, sacrificial layer, and isolation layer described herein may take different types or forms, provided that this disclosure is applicable.

[0022] It will be understood that when an element, component, layer, pattern, structure, region, etc. of a semiconductor device (hereinafter collectively referred to as an “element”) is said to be “above”, “on top of”, “on”, “below”, “under”, “below”, “under”, “connected to”, or “linked to” another element of a semiconductor device, it may be directly above, directly above, directly on, directly below, directly below, directly connected to, or directly linked to another element, or there may be (multiple) intermediary elements. In contrast, when an element of a semiconductor device is referred to as being "directly above," "directly above," "directly on," "directly below," "directly below," "directly below," "directly connected to," or "directly linked to" another element of the semiconductor device, there is no intermediary element. Throughout this disclosure, the same reference numerals refer to the same elements.

[0023] Spatial relative terms, such as “above,” “over,” “upper,” “top,” “lower,” “below,” “below,” “left,” “right,” “lower left,” “lower right,” “upper left,” “upper right,” “center,” “middle,” etc., may be used herein for ease of description to describe the relationship between one element and another(s) of the elements shown in the figure. It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are also intended to cover different orientations of the semiconductor device in use or operation. For example, if the semiconductor device in the figure is flipped, an element described as “below” or “below” another element would be oriented as “above” the other element. Thus, the term “below” can cover both upper and lower orientations. Semiconductor devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly. As another example, elements referred to as “left” and “right” elements may be “right” and “left” elements when the device or structure including these elements is oriented differently. Therefore, the “left” element and the “right” element of the structure can also be referred to as the “first” element and the “second” element of the structure, respectively, as long as their structural relationship is clearly understood in the context of the description.

[0024] It will be understood that although the terms “first,” “second,” “third,” “fourth,” “fifth,” “sixth,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, a first element described in the description of an embodiment may be referred to as a second element in another embodiment or in the description of one or more claims, and vice versa.

[0025] As used in this article, expressions such as "at least one of..." modify the entire list of elements when they follow a list of elements, without modifying any individual elements of the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0026] In the description herein, degree terms including "substantially" or "approximately" may be used. In one or more examples, when a specified parameter X can be substantially the same as parameter Y, the term "substantially" can be understood as the difference between X and Y being within 10% of Y. In one or more examples, when a specified parameter is approximately X, the term "approximately" can be understood as being within 10% of X. However, when the term "same" is used to compare the parameters of two or more elements, the term can encompass parameters that are "substantially the same".

[0027] It will be understood that when the term "contact" is used to describe two metallic elements (e.g., a metal wire and a via structure), a barrier metal layer may be formed therebetween, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), or platinum nitride (PtN), but not limited thereto. Furthermore, it will be understood that when the metal contact structure is described as being formed on the surface of the source / drain region or on the surface contacting the source / drain region, a silicide layer may be formed therebetween, such as cobalt silicide (CoSi2), nickel silicide (NiSi2), titanium silicide (TiSi2), or tungsten silicide (WSi2), but not limited thereto.

[0028] It will also be understood that even if a step or operation in the manufacture of an apparatus or structure is later than another step or operation described, that step or operation may be performed earlier than the other step or operation, unless the other step or operation is described as being performed before that step or operation.

[0029] This document describes numerous embodiments with reference to cross-sectional views (which are schematic) of the embodiments (and intermediate structures). Thus, variations relative to the illustrated shapes will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments should not be construed as limited to the specific shapes of the areas shown herein, but rather include, for example, deviations in shape due to manufacturing processes. The various areas shown in the figures are schematic in nature, and their shapes are not intended to represent the actual shapes of areas of the device, nor are they intended to limit the scope of this disclosure. Furthermore, in the figures, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0030] For the sake of brevity, conventional elements, structures, or layers of semiconductor devices, including nanosheet transistors, and the materials forming them, may or may not be described in detail herein. For example, when a particular isolation layer or structure of a semiconductor device is not a novel feature of the embodiment, that layer or structure and the materials forming it may be omitted herein. Furthermore, when the materials forming known structural elements of a semiconductor device are not a novel feature of the embodiment, the description of these materials may be omitted herein. Here, the term "isolation" refers to electrical insulation or separation between structures, layers, components, or regions in a given device or structure.

[0031] Figures 1A to 1B arrive Figures 9A to 9B An intermediate semiconductor device is shown after corresponding steps in the fabrication of a stacked semiconductor device according to one or more embodiments, wherein a first field-effect transistor (FET) at a first level and a second FET at a second level above the first level have channel structures of different widths and source / drain regions of different widths.

[0032] Figures 1A to 9A This is a plan view of the intermediate semiconductor device 10', and Figures 1B to 9B They are Figures 1A to 9A A cross-sectional view of the intermediate semiconductor device 10' taken along lines I-I' and / or II-II' shown therein.

[0033] refer to Figure 1A and Figure 1B An intermediate semiconductor device 10' can be formed by epitaxially growing multiple semiconductor layers (nanosheet layers) on a substrate 101.

[0034] A semiconductor layer, referred to as a nanosheet, can be epitaxially grown in the D3 direction from an active pattern 101A formed in the upper portion of a substrate 101, in the following sequence: a first channel stack CS1 comprising alternating vertically stacked first sacrificial layers 111 and 112 and an intermediate sacrificial layer 115', and a second channel stack CS2 comprising alternating vertically stacked second sacrificial layers 121 and 122 on the intermediate sacrificial layer 115'. Although the substrate 101 including the active pattern 101A can be formed of silicon (Si), silicon germanium (SiGe), silicon carbide (SiC), or combinations thereof, the active pattern 101A can be doped with impurities to promote the epitaxial growth of the semiconductor layer.

[0035] Epitaxy of the semiconductor layers can be performed such that channel layers 112 and 122 are formed of silicon (Si), and sacrificial layers 111, 115', and 121 are formed of silicon-germanium (SiGe) having corresponding Ge concentrations. The intermediate sacrificial layer 115' may have a higher Ge concentration than the first sacrificial layer 111 and the second sacrificial layer 121. For example, the intermediate sacrificial layer 115' may have a Ge concentration of 40-45%, and the first sacrificial layer 111 and the second sacrificial layer 121 may have a Ge concentration of 25-30%.

[0036] Here, sacrificial layers 111, 115' and 121 are referred to as such because in subsequent steps of fabricating the stacked semiconductor device from the intermediate semiconductor device 10', these layers will be removed and replaced by other layers or structures.

[0037] Before the first channel stack CS1 and the second channel stack CS2 are formed on the active pattern 101A, shallow trenches extending along the D1 direction can be formed on the upper left and upper right portions of the substrate 101 by, for example, dry etching (e.g., reactive ion etching (RIE)). The shallow trenches can be filled with a low-k dielectric material (such as silicon oxide (e.g., SiO2) or silicon nitride (SiN, Si3N4, etc., but not limited thereto) to form shallow trench isolation (STI) structures 103 therein. The active pattern 101A can be formed between the STI structures along the D2 direction.

[0038] Here, direction D1 refers to the length of the channel through which current flows between the two source / drain regions connected by the channel structure, direction D2 is the channel width direction or cell height direction, and direction D3 is the channel thickness direction. Directions D1 and D2 can each be referred to as the horizontal direction, and direction D3 can be referred to as the vertical direction.

[0039] The formation of the STI structure 103 in this step can be performed, for example, by chemical vapor deposition (CVD), but is not limited thereto. The STI structure 103 can isolate the active pattern 101A from adjacent active patterns or other circuit elements.

[0040] refer to Figure 2A and Figure 2B The intermediate semiconductor device 10' can be patterned such that the second channel stack CS2 has a smaller width than the first channel stack CS1 having an intermediate sacrificial layer 115' thereon.

[0041] The patterning operation in this step can be performed, for example, by dry etching, such that the first channel stack CS1, including the first sacrificial layer 111 and the first channel layer 112, is partially overlapped along the D3 direction by the second channel stack CS2, including the second sacrificial layer 121 and the second channel layer 122. Furthermore, a patterning operation can be performed such that the left surfaces of the first channel stack CS1, the intermediate sacrificial layer 115', and the second channel stack CS2 are perpendicularly aligned or coplanar, while the right surface of the second channel stack CS2 overlaps with or meets the top surface of the intermediate sacrificial layer 115' (below which the first channel stack CS1 is). Therefore, the second channel stack CS2 can have a width along the D2 direction smaller than that of the first channel stack CS1 and the intermediate sacrificial layer 115' thereon. For example, the second sacrificial layer 121 and the second channel layer 122 can each have a width along the D2 direction smaller than that of the first sacrificial layer 111 and the first channel layer 112, respectively.

[0042] As will be described later, in this step, the second channel stack CS2 is formed to have a smaller width than the first channel stack CS1, which is intended to facilitate subsequent steps ( Figures 7A to 7B and Figures 8A to 8B In the second source / drain region formed by the second channel layer 122 of the second channel stack CS2, the width of the second source / drain region is smaller than that of the first source / drain region formed by the first channel layer 112 of the first channel stack CS1, thereby promoting the formation of a source / drain contact structure on the top surface of the first source / drain region.

[0043] Conversely, the second channel stack CS2 can be formed with a greater number of channel layers than the first channel stack CS1, such that the second channel layer 122 can have the same or substantially the same effective channel width (W) as the first channel layer 112. eff Furthermore, the second source / drain region formed by the second channel layer 122 may have the same or substantially the same volume as the first source / drain region formed by the first channel layer 112.

[0044] By patterning the first channel stack CS1 and the second channel stack CS2 in this way, the stacked semiconductor device manufactured by the intermediate semiconductor device 10' can achieve optimal device performance depending on the functional type of the stacked semiconductor.

[0045] refer to Figure 3A and Figure 3BMultiple dummy gate structures 150' can be formed to surround the intermediate semiconductor device 10' obtained in the previous steps.

[0046] like Figure 3B As shown, the dummy gate structure 150' can surround a first channel stack CS1 and a second channel stack CS2 having an intermediate sacrificial layer 115' therebetween. The dummy gate structure 150' can be formed, for example, by depositing polycrystalline silicon (p-Si) or amorphous silicon (a-Si) on the channel stacks CS1 and CS2 having the intermediate sacrificial layer 115' therebetween via, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or a combination thereof, followed by photolithography / mask / etching operations.

[0047] Each of the dummy gate structures 150' is a temporary placeholder to define the area for the gate structure and the channel structure surrounded by the gate structure for subsequent steps.

[0048] refer to Figure 4A and Figure 4B The intermediate sacrificial layer 115' can be removed and replaced by an intermediate isolation layer 115 surrounding the first channel stack CS1 and the second channel stack CS2.

[0049] The removal of the intermediate sacrificial layer 115' can be performed, for example, by wet etching using an etchant such as an ammonia-peroxide mixture, which removes the intermediate sacrificial layer 115' of SiGe with a high Ge concentration (40-45%), while the first channel layer 112 and the second channel layer 122 of silicon (Si) and the first sacrificial layer 111 and the second sacrificial layer 121 of SiGe with a low Ge concentration (25-30%) are not etched by the etchant or are etched to a minimal degree.

[0050] Furthermore, insulating materials such as SiBCN, SiCN, SiOC, SiOCN, SiN, and Si3N can fill the space where the intermediate sacrificial layer 115' is removed, thereby forming an intermediate insulating layer 115. The formation of the intermediate insulating layer 115 can be performed, for example, by CVD, ALD, or PEALD. In this case, the intermediate insulating layer 115 can be extended to conformally surround the outer contours of the first channel stack CS1 and the second channel stack CS2, as well as the top surface of the STI structure 103.

[0051] The intermediate isolation layer 115 can be formed to isolate the channel structure to be formed by stacking CS1 from the first channel and the channel structure to be formed by stacking CS2 from the second channel.

[0052] refer to Figure 5A and Figure 5BThe upper portion of the second channel stack CS2 and the intermediate isolation layer 115 thereon can be patterned based on the dummy gate structure 150' to provide space S2, in which subsequent steps will be performed. Figure 8A and Figure 8B The second source / drain region is formed in the upper source / drain region.

[0053] It should be understood here that in this step, the upper portion of the second channel stack CS2 and the intermediate isolation layer 115 thereon can be removed only along the D1 direction between and on the sides of the dummy gate structure 150', as shown below. Figure 5A As shown, the first channel stack CS1 and the second channel stack CS2, which are surrounded by or below the dummy gate structure 150', may therefore not be patterned.

[0054] When the upper portion of the second channel stack CS2 and the intermediate isolation layer 115 thereon is patterned, the right side portion of the first channel stack CS1 that is not vertically overlapped by the second channel stack CS2 and the lower portion of the intermediate isolation layer 115 surrounding the right side portion of the first channel stack CS1 can also be patterned, such as... Figure 5B As shown in the diagram. This is because when a patterning operation is performed along the D3 direction to form space S2 from the top surface T2 of the upper portion of the intermediate isolation layer 115 exposed upwards, the top surface T1 of the lower portion of the intermediate isolation layer 115, which is also exposed upwards, can also undergo a patterning operation. The patterning operation in this step can be performed, for example, by dry etching (e.g., reactive ion etching), but is not limited thereto.

[0055] Removing the right-side portion of the first channel stack CS1 exposes a portion of the top surface T3 of the substrate 101 (e.g., the top surface of a portion of the active pattern 101A) and the top surface T4 of the lower portion of the intermediate isolation layer 115. At this time, due to the difference in etch selectivity or etch rate between the first channel stack CS1 and the second channel stack CS2 and the intermediate isolation layer 115, and as... Figure 4B The height difference between the top surfaces T1 and T2 of the intermediate isolation layer 115 shown allows the retention of residue RE2 in the upper portion of the intermediate isolation layer 115 and residue RE1 in the lower portion of the intermediate isolation layer 115, as shown. Figure 5B As shown.

[0056] refer to Figure 6A and Figure 6B The lower portion of the first channel stack CS1 and the intermediate isolation layer 115 thereon can be patterned to provide space S1 in subsequent steps ( Figure 7A and Figure 7B In the space S1, the first source / drain region will be formed as the lower source / drain region.

[0057] It should be understood here that, in this step, the lower portion of the first channel stack CS1 and the intermediate isolation layer 115 thereon can be removed only along the D1 direction between and on the sides of the dummy gate structures 150', as follows: Figure 6A As shown, the second channel stack CS2 and the first channel stack CS1, therefore, surrounded by or below the dummy gate structure 150', can therefore not be patterned. Thus, the portions of the first channel stack CS1 and the second channel stack CS2 surrounded by or below the dummy gate structure 150' can form a first channel structure CH1 surrounding or below each of the dummy gate structures 150' and a second channel structure CH2 thereon. These two channel structures CH1 and CH2 can be... Figure 6B It is shown in the middle with a dashed line. Figure 6B It shows along Figure 6A A sectional view of line I-I'.

[0058] Simultaneously, when the first channel stack CS1 is removed to form the space S1, a portion of the substrate 101 (e.g., the right side portion of the active pattern 101A exposed in the previous step) can also be removed to form a recess R1 in the substrate 101 (e.g., the active pattern 101A). This is because when the patterning operation is performed along the D3 direction to form the space S1 from the top surface T4 of the lower portion of the upward-exposed intermediate isolation layer 115, the top surface T3 of the upward-exposed substrate 101 can also undergo this patterning operation.

[0059] At this time, when the first channel stack CS1 is removed, the residues RE1 and RE2 of the intermediate isolation layer 115 can also be removed. However, the intermediate isolation layer 150 remaining on the left side surface of the first channel stack CS1 may not be fully patterned, but rather due to the difference in etch selectivity or etch rate between the first channel stack CS1 and the intermediate isolation layer 115, and as well as... Figure 5B The height difference between the portions of the intermediate isolation layer 115 shown, the lower portion of which can be retained as residue RE3.

[0060] refer to Figure 7A and Figure 7B The first source / drain region 113 can be in the previous step ( Figure 6A and Figure 6B The space S1 obtained by patterning the first channel stack CS1 is formed by the first channel structure CH1 including the first channel layer 112.

[0061] The first source / drain region 113 can be epitaxially grown primarily along the D1 direction from the first channel layer 112 of the first channel structure CH1 surrounded by or below the dummy gate structure 150', while the first sacrificial layer 111 of the first channel structure CH1 is covered by inner spacers formed on its side surfaces. When the epitaxial growth of the first source / drain region 113 is performed, the epitaxial structure forming the first source / drain region 113 can be in situ doped with n-type impurities such as phosphorus (P), arsenic (As), antimony (Sb), or p-type impurities such as boron (B), gallium (Ga), or indium (In).

[0062] However, when in Figure 6A and Figure 6B When the first source / drain region 113 is epitaxially grown from the first channel layer 112 in the intermediate semiconductor device 10' shown, the epitaxial structure can be overgrown to form a portion 113S of the first source / drain region 113 in the recess R1 in the upper portion of the substrate 101 (e.g., in the right-hand portion of the active pattern 101A), as shown. Figure 7B As shown, when a portion 113S of the first source / drain region 113 containing impurities is formed inside the substrate 101 (e.g., active pattern 110A), current leakage from the first source / drain region 113 to the substrate 101 including the active pattern 101A may occur or increase when the stacked semiconductor device manufactured by the intermediate semiconductor device 10' is turned on. Such current leakage will become a cause of performance degradation of the stacked semiconductor device.

[0063] refer to Figure 8A and Figure 8B The second source / drain region 123 can be added in the previous step ( Figure 5A and Figure 5B The space S2 obtained by patterning the second channel stack CS2 is formed by the second channel structure CH2 including the second channel layer 122.

[0064] The second source / drain region 123 can be epitaxially grown primarily along the D1 direction from the second channel layer 122 of the second channel structure CH2 surrounded by or below the dummy gate structure 150', while the second sacrificial layer 121 of the second channel structure CH2 is covered by an inner spacer formed on its side surface. When the epitaxial growth of the second source / drain region 123 is performed, the epitaxial structure forming the second source / drain region 123 can be in situ doped with p-type impurities such as boron (B), gallium (Ga), or indium (In) or n-type impurities such as phosphorus (P), arsenic (As), or antimony (Sb).

[0065] With the formation of the first source / drain region 113 and the second source / drain region 123, an isolation structure 160 can be formed around the first source / drain region 113 and the second source / drain region 123 to isolate the first source / drain region 113 and the second source / drain region 123 from each other or from other circuit elements. The isolation structure 160 can be formed, for example, by depositing a low-k material such as silicon oxide (e.g., SiO2) using CVD, PVD, PECVD, etc.

[0066] As previously described, due to the channel width difference, the second source / drain region 123 grown from the second channel layer 122 can have a smaller width than the first source / drain region 113 grown from the first channel layer 112. Furthermore, the second source / drain region 123 can only partially overlap with the first source / drain region 113 in the D3 direction. For example, the right side portion of the first source / drain region 113 may not overlap with the second source / drain region 123, such that the left surfaces of the two source / drain regions 113 and 123 are aligned or coplanar with each other in the D3 direction, while their right surfaces are not aligned or coplanar. Utilizing this width difference between the two source / drain regions 113 and 123, the stacked semiconductor device to be completed from the intermediate semiconductor device 10' can facilitate the formation of source / drain contact structures on the top surface of the first source / drain region 113 that does not overlap with the second source / drain region 123, and achieve optimal device performance depending on the functional type of the stacked semiconductor device.

[0067] refer to Figure 9A and Figure 9B The dummy gate structure 150' and the first sacrificial layer 111 and the second sacrificial layer 121 included in the first channel structure CH1 and the second channel structure CH2, respectively, can be replaced by the gate structure 150 to form a stacked semiconductor device 10.

[0068] The dummy gate structure 150' and the first sacrificial layer 111 and the second sacrificial layer 121 can be removed, for example, by wet etching (but not limited thereto), to release the first channel layer 112 and the second channel layer 122 from the first sacrificial layer 111 and the second sacrificial layer 121. Furthermore, the space provided by removing the dummy gate structure 150' and the first sacrificial layer 111 and the second sacrificial layer 121 can be filled with metal or a metal alloy, for example, by atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), CVD, PVD, or combinations thereof (but not limited thereto), to form the gate structure 150.

[0069] Therefore, the gate structure 150, the first channel structure CH1 including the first channel layer 112 and the first source / drain region 113 can form a first FET at a first level of the stacked semiconductor device 10, and the gate structure 150, the second channel structure CH2 including the second channel layer 122 and the second source / drain region 123 can form a second FET at a second level of the stacked semiconductor device 10.

[0070] However, return to reference Figure 7A and Figure 7B The portion 113S of the first source / drain region 113 formed in the recess R1 can adversely affect the performance of the stacked semiconductor device 10 by leaking current into the substrate 101. For example, if the first FET of the stacked semiconductor device 10 is an n-type pull-down transistor or a transfer gate transistor to form a static random access memory (SRAM), current leakage from the first source / drain region 113 to the substrate 101 can slow down the read / write speed of the SRAM.

[0071] The following implementation is provided to address current leakage from the first source / drain region 113 formed in the substrate 101 as described above.

[0072] Figures 10A to 10B arrive Figures 17A to 17B An intermediate semiconductor device is shown after the corresponding steps of fabricating a stacked semiconductor device using a dummy channel stack, according to one or more embodiments.

[0073] Figures 10A to 17A It is a plan view of the intermediate semiconductor device 20', and Figures 10B to 17B They are Figures 10A to 17A A cross-sectional view of the intermediate semiconductor device 20' taken along lines I-I' and / or II-II' shown therein.

[0074] refer to Figure 10A and Figure 10B The intermediate semiconductor device 20' obtained in this step can be used with Figure 5A and Figure 5B The intermediate semiconductor device 10' shown is the same as or similar to that shown; therefore, for the sake of brevity, the details of obtaining it can be omitted here. Figure 10A and Figure 10B The description of the corresponding steps of the intermediate semiconductor device 20' shown.

[0075] The intermediate semiconductor device 20' may include a first channel stack CS1 and a second channel stack CS2. The first channel stack CS1 is formed on an active pattern 201A of the substrate 201, and an STI structure 203 is located on the side of the active pattern 201A. The second channel stack CS2 is formed above the first channel stack CS1. The first channel stack CS1 may include a first sacrificial layer 211 and a first channel layer 212, and the second channel stack CS2 may include a second sacrificial layer 221 and a second channel layer 222. The intermediate semiconductor device 20' may also include a dummy gate structure 250' and a patterned intermediate isolation layer 215 including residues RE1 and RE2.

[0076] Additionally, in the intermediate semiconductor device 20' of this step, a space S2 obtained by removing the upper portion of the second channel stack CS2 and the intermediate isolation layer 215 can be formed. Furthermore, in the intermediate semiconductor device 20' of this step, the right side portion of the first channel stack CS1 and the lower portion of the intermediate isolation layer 215 thereon can be removed to expose the top surface T3 of the active pattern 201A and the top surface T4 of the patterned intermediate isolation layer 215.

[0077] refer to Figure 11A and Figure 11B The protective layer 216 can be formed on the top surface of the intermediate semiconductor device 20', in addition to the dummy gate structure 250' obtained in the previous steps.

[0078] The protective layer 216 can be formed by depositing an isolation material such as silicon nitride (e.g., SiN or Si3N4) on the top surface T4 of the intermediate isolation layer 215, the top surface T3 of the active pattern 201A, and the top surface of the STI structure 203 exposed upward between the dummy gate structures 250', for example by atomic layer deposition (ALD), plasma enhanced ALD (PEALD), or combinations thereof (but not limited to), on the top surface T4 of the intermediate isolation layer 215, the top surface T3 of the active pattern 201A, and the top surface of the STI structure 203 exposed upward between the dummy gate structures 250'.

[0079] Protective layer 216 can be used to protect intermediate isolation layer 215 and STI structure 203 from subsequent steps ( Figure 13A and 13B The impact of the epitaxial process performed in ).

[0080] refer to Figure 12A and Figure 12B The protective layer 216 formed on the top surface T3 of the active pattern 201A can be removed to expose that portion of the top surface of the active pattern 201A upwards.

[0081] The selective removal of the protective layer 216 in this step can be performed by, for example, dry etching, ashing, stripping, etc. (but not limited to), to expose the top surface T3 of the active pattern 201A so that it can be used in the next step. Figure 13A and Figure 13B In this process, an epitaxial process is performed on the exposed top surface T3 of the active pattern 201A. At this time, the selective removal operation can also remove the protective layer 216 formed on the top surface T4 of the STI structure 203 and the intermediate isolation layer 215, except for the protective layer 216 on the residues RE1 and RE2.

[0082] refer to Figure 13A and Figure 13B The dummy channel stack 201B can be grown from the top surface T3 of the active pattern 201A of the substrate 101, such that the top surface T5 of the dummy channel stack 201B is at the same level as or higher than the top surface T4 of the patterned intermediate isolation layer 215.

[0083] The dummy channel stack 201B can be an epitaxial structure grown from the active pattern 201A on the lateral side of the first channel stack CS1. The dummy channel stack 201B can be formed to prevent the active pattern 201A from being patterned in the next step when the first channel stack CS1, the lower portion of the intermediate isolation layer 215, and the protective layer 216 thereon are patterned to form the space S1 for the first source / drain region 113. When the dummy channel stack 201B is formed on the active pattern 201A, the dummy channel stack 201B, instead of the active pattern 201A, can be patterned together with the first channel stack CS1, the lower portion of the intermediate isolation layer 215, and the protective layer 216 thereon. Therefore, the active pattern 201A below the dummy channel stack 201B can be left unetched to form recesses (such as...). Figure 6A and Figure 6B The depression R1 shown in the figure.

[0084] To achieve this objective, by controlling the amount of epitaxial elements, the epitaxial temperature, and / or the duration of epitaxy, a dummy channel stack 201B can be grown from the top surface T3 of the active pattern 201A to have a height similar to or corresponding to that of the first channel stack CS1 having a patterned intermediate isolation layer 215 and a protective layer 216. For example, the dummy channel stack 201B can be grown such that its top surface T5 is at or above the level of the top surface T4 of the patterned intermediate isolation layer 215, but is not limited thereto. Furthermore, the dummy channel stack 201B can be grown from a material such as Si, SiGe, or a combination thereof, which is the same as or similar to the material forming the first channel stack CS1 including the first channel layer 212 and the first sacrificial layer 211. The dummy channel stack 201B may be undoped.

[0085] refer to Figure 14A and Figure 14BThe lower portion of the first channel stack CS1 and the intermediate isolation layer 215 and the protective layer 216 thereon can be patterned together with the dummy channel stack 201B to provide space S1 in which the first source / drain region, which will be formed as the lower source / drain region in the next step, will be formed.

[0086] It should be understood that in this step, such as Figure 14A As shown, the lower portion of the first channel stack CS1 and the intermediate isolation layer 215 and the protective layer 216 thereon can be removed only along the D1 direction between and on the sides of the dummy gate structures 250'. Therefore, the first channel stack CS1 and the second channel stack CS2 surrounded by or below the dummy gate structures 250' do not need to be patterned. Thus, these portions of the first channel stack CS1 and the second channel stack CS2 surrounded by or below the dummy gate structures 250' can form a first channel structure CH1 surrounded by or below each of the dummy gate structures 250' and a second channel structure CH2 above it. These two channel structures CH1 and CH2 can be... Figure 14B It is shown in the middle with a dashed line. Figure 14B It shows along Figure 14A A sectional view of line I-I'.

[0087] With Figure 6A and Figure 6B Similar to the patterning operation performed on intermediate semiconductor device 10' shown, the patterning operation performed on intermediate semiconductor device 20' in this step can be performed such that the first channel layer 212 is fully exposed in space S1 along the D1 direction, thereby facilitating the epitaxial growth of the first source / drain region from the first channel layer 212 in the next step. However, with Figure 6A and Figure 6B Unlike the intermediate semiconductor device 10', the patterning operation in this step may not remove a portion of the substrate 201 (e.g., the right-hand portion of the active pattern 201A) to form a recess in the active pattern 201A (such as recess R1 in the active pattern 101A, as shown in the image). Figure 6B (As shown). This is because the dummy channel stack 201B formed on the top surface T3 of the active pattern 201A in the previous step can prevent the formation of such a depression in the active pattern 201A.

[0088] Furthermore, the dummy channel stack 201B can be patterned together with the first channel stack CS1, the lower portion of the intermediate isolation layer 215, and the protective layer 216 thereon at substantially the same etch rate. Therefore, when the first channel stack CS1 is removed to expose the top surface T3 of the active pattern 201A, the dummy channel stack 201B can also be removed to expose the top surface T3 of the active pattern 201A below it.

[0089] At this time, when the first channel stack CS1 is removed, the residues RE1 and RE2 of the intermediate isolation layer 215 can also be removed. However, the intermediate isolation layer 215 remaining on the left side surface of the first channel stack CS1 may not be fully patterned, but due to the difference in etch selectivity or etch rate between the first channel stack CS1 and the intermediate isolation layer 215, as well as the height difference between portions of the intermediate isolation layer 215, its lower portion may remain as residue RE3, such as... Figure 14B As shown. In addition, after the first channel stack CS1 is patterned, a portion of the protective layer 216 may also be retained on the left side surface of the residue RE3 of the intermediate isolation layer 215.

[0090] refer to Figure 15A and Figure 15B The first source / drain region 213 can be in the previous step ( Figure 14A and Figure 14B The space S1 obtained by patterning the first channel stack CS1 is formed by the first channel structure CH1 including the first channel layer 212.

[0091] The first source / drain region 213 can be epitaxially grown primarily along the D1 direction from the first channel layer 212 of the first channel structure CH1 surrounded by or below the dummy gate structure 250', while the first sacrificial layer 211 of the first channel structure CH1 is covered by an inner spacer formed on its side surface. When the epitaxial growth of the first source / drain region 213 is performed, the epitaxial structure forming the first source / drain region 213 can be in situ doped with n-type impurities such as phosphorus (P), arsenic (As), antimony (Sb), or p-type impurities such as boron (B), gallium (Ga), or indium (In).

[0092] However, with Figure 7A and Figure 7B Unlike the intermediate semiconductor device 10' shown, no portion of the first source / drain region 213 is formed inside the substrate 201 (e.g., active pattern 201A) because of the previous steps ( Figure 13A and Figure 13BThe dummy channel stack 201B formed in the intermediate semiconductor device 20' does not have a depression similar to the depression R1 formed in the substrate 101 of the intermediate semiconductor device 10'. Therefore, current leakage similar to that that can be generated from a portion 113S of the first source / drain region 113 formed inside the substrate 101 can be prevented or reduced in the stacked semiconductor device made of the intermediate semiconductor device 20'.

[0093] refer to Figure 16A and Figure 16B The second source / drain region 223 can be added in the previous steps ( Figure 10A and Figure 10B The space S2 obtained by patterning the second channel stack CS2 is formed by the second channel structure CH2 including the second channel layer 222.

[0094] The formation of the second source / drain region 223 can be applied to, for example, Figure 8A and Figure 8B The formation of the second source / drain region 123 of the intermediate semiconductor device 10' shown is performed in the same or similar manner, and therefore its repeated description can be omitted herein. An isolation structure 260 may be formed around the first source / drain region 213 and the second source / drain region 223 to isolate the first source / drain region 213 and the second source / drain region 223 from each other or from other circuit elements.

[0095] refer to Figure 17A and Figure 17B The dummy gate structure 250' and sacrificial layers 211 and 221 included in the channel structures CH1 and CH2, respectively, can be replaced by the gate structure 250 to form a stacked semiconductor device 20.

[0096] The formation of the gate structure 250 can be used in applications such as Figure 9A and Figure 9B The gate structure 150 of the intermediate semiconductor device 10' shown is formed in the same or similar manner, therefore, its repeated description can be omitted herein.

[0097] However, return to reference Figures 13A to 13B arrive Figures 15A to 15B Because of the dummy channel stack 201B grown from the substrate 201, the substrate 201 does not need to be patterned when the first channel stack CS1 is removed. Therefore, any portion of the first source / drain region 213 can be left unformed within the substrate 201, thereby preventing or reducing current leakage from the first source / drain region 213 to the substrate 201. Thus, the stacked semiconductor device 20 can prevent device performance degradation caused by current leakage.

[0098] Figures 18A to 18B arrive Figures 24A to 24BAn intermediate semiconductor device is shown after corresponding steps in fabricating a stacked semiconductor device using dummy channel stacking and barrier layers, according to one or more embodiments.

[0099] Figures 18A to 24A It is a plan view of the intermediate semiconductor device 30', and Figures 18B to 24B They are Figures 18A to 24A A cross-sectional view of the intermediate semiconductor device 30' taken along lines I-I' and / or II-II' shown therein.

[0100] refer to Figure 18A and Figure 18B The intermediate semiconductor device 30' obtained in this step can be used with Figure 12A and Figure 12B The intermediate semiconductor device 20' shown is the same as or similar to that shown; therefore, for the sake of simplicity, the details of obtaining it can be omitted here. Figure 18A and Figure 18B The description of the corresponding steps of the intermediate semiconductor device 30' shown.

[0101] The intermediate semiconductor device 30' may include a first channel stack CS1 and a second channel stack CS2. The first channel stack CS1 is formed on an active pattern 301A of the substrate 301, and an STI structure 303 is located on the side of the active pattern 301A. The second channel stack CS2 is formed above the first channel stack CS1. The first channel stack CS1 may include a first sacrificial layer 311 and a first channel layer 312, and the second channel stack CS2 may include a second sacrificial layer 321 and a second channel layer 322. The intermediate semiconductor device 30' may also include a dummy gate structure 350' and a patterned intermediate isolation layer 315 including residues RE1 and RE2.

[0102] Furthermore, in the intermediate semiconductor device 30' of this step, a space S2 obtained by removing the second channel stack CS2 and the upper portion of the intermediate isolation layer 315 can be formed. Additionally, in the intermediate semiconductor device 30' of this step, the right side portion of the first channel stack CS1 and the lower portion of the intermediate isolation layer 315 thereon can be removed to expose the top surface T3 of the active pattern 301A and the top surface T4 of the patterned intermediate isolation layer 315. Furthermore, the protective layer 316 can be formed on the intermediate semiconductor device 30' in the same manner as the protective layer 216 on the intermediate semiconductor device 20', and as... Figures 11A to 11B and Figures 12A to 12B The pattern shown is illustrated.

[0103] refer to Figure 19A and Figure 19BA thin barrier layer 301B can be formed on the top surface T3 of the active pattern 301A, which is patterned in the second channel stack CS2 to form a space S2 (see...). Figures 4A to 4B and Figures 5A to 5B During the exposure, the second source / drain region in space S2 will be exposed in subsequent steps ( Figure 23A and Figure 23B Formed in ).

[0104] For example, the barrier layer 301B may have a smaller thickness than each of the first sacrificial layers 311, but is not limited thereto. The barrier layer 301B may be epitaxially grown from the active pattern 301A and in-situ doped with impurities, which may have the same characteristics as those in a later step ( Figure 22A and Figure 22B The first source / drain region formed on the first channel layer 312 has the same polarity type as the first source / drain region.

[0105] However, the in-situ doping in this step can be controlled to result in a lower concentration of impurities in the barrier layer 301B. For example, in subsequent steps ( Figure 23A and 23B When the first source / drain region formed above the barrier layer 301B is n-type doped with impurities such as phosphorus (P), arsenic (As), and antimony (Sb), the barrier layer 301B can be doped with the same n-type impurities at a lower concentration than in the first source / drain region to suppress carrier migration from the first source / drain region to the active pattern 301A of the substrate 301, thereby improving the prevention or reduction of current leakage from the first source / drain region to the substrate 301.

[0106] refer to Figure 20A and Figure 20B The dummy channel stack 301C can be grown from the barrier layer 301B, such that the top surface T5 of the dummy channel stack 301C is at or above the top surface T4 of the patterned intermediate isolation layer 315.

[0107] The dummy channel stack 301C can be an epitaxial structure grown from an active pattern 301A having a barrier layer 301B on the lateral side of the first channel stack CS1. The dummy channel stack 301C can be formed to prevent the active pattern 301A from being patterned in the next step when the first channel stack CS1, the lower portion of the intermediate isolation layer 315, and the protective layer 316 thereon are patterned to form a space S1 for the first source / drain region. When the dummy channel stack 301C is formed on the active pattern 301A, the dummy channel stack 301C, instead of the active pattern 301A, can be patterned together with the first channel stack CS1, the lower portion of the patterned intermediate isolation layer 315, and the protective layer 316 thereon. Therefore, the active pattern 301A and the barrier layer 301B below the dummy channel stack 301C can be left unetched to form recesses (such as...) Figure 6A and Figure 6B The depression R1 shown in the figure.

[0108] To achieve this objective, the dummy channel stack 301C can be grown from an active pattern 301A having a barrier layer 301B thereon by controlling the amount of epitaxial elements and / or the duration of epitaxy, to have a height similar to or corresponding to that of the first channel stack CS1 having a patterned intermediate isolation layer 315 and a protective layer 316 thereon. For example, the dummy channel stack 301C can be grown such that its top surface T5 is at or above the level of the top surface T4 of the intermediate isolation layer 315, but is not limited thereto. Furthermore, the dummy channel stack 301C can be grown from a material such as Si, SiGe, or a combination thereof, which is the same as or similar to the material forming the first channel stack CS1 including the first channel layer 312 and the first sacrificial layer 311. The dummy channel stack 301C may be undoped.

[0109] However, the extension in this step can be further controlled so that the top surface T5 of the dummy channel stack 301C is in a position where Figure 13A and Figure 13B The dummy channel stack 201B of the intermediate semiconductor device 20' shown is at or above the level of the top surface T5 of the dummy channel stack 201B, which is above or below the thickness of the barrier layer 301B along the D3 direction. With this additional control over the height of the dummy channel stack 301C, the barrier layer 301B can remain on the top surface T3 of the active pattern 301A after the dummy channel stack 301C is patterned together with the first channel stack CS1 and the patterned intermediate isolation layer 315 and the protective layer 316 thereon.

[0110] refer to Figure 21A and Figure 21BThe first channel stack CS1 and the lower portion of the intermediate isolation layer 315 and the protective layer 316 thereon can be patterned to provide space S1, in which a first source / drain region as the lower source / drain region will be formed in space S1 in the next step.

[0111] It should be understood that in this step, the first channel stack CS1 and the lower portion of the intermediate isolation layer 315 and the protective layer 316 thereon can be removed only along the D1 direction between and on the sides of the dummy gate structures 350', as shown below. Figure 6A As shown, the first channel stack CS1 and the second channel stack CS2, surrounded by or below the dummy gate structure 350', can therefore not be patterned. Thus, the portions of the first channel stack CS1 and the second channel stack CS2 surrounded by or below the dummy gate structure 350' can form a first channel structure CH1 surrounding or below each of the dummy gate structures 350' and a second channel structure CH2 above them. These two channel structures CH1 and CH2 can be... Figure 21B It is shown in the middle with a dashed line. Figure 21B It shows along Figure 21A A sectional view of line I-I'.

[0112] Similar to Figure 14A and Figure 14B The patterning operation performed on the intermediate semiconductor device 20' shown can be performed in this step such that the first channel layer 312 is fully exposed in space S1 along the D1 direction to facilitate the epitaxial growth of the first source / drain region from the first channel layer 312 in the next step. Furthermore, the patterning operation in this step can be performed without removing a portion of the substrate 301 (e.g., the right-hand portion of the active pattern 301A) to form a recess in the active pattern 301A (such as recess R1 in active pattern 101A, e.g.). Figure 6B (As shown). This is because the dummy channel stack 301C and barrier layer 301B formed on the top surface T3 of the active pattern 301A in the previous step can prevent the formation of such a depression in the active pattern 301A.

[0113] Furthermore, the dummy channel stack 301C can be patterned at substantially the same etch rate as the first channel stack CS1, the lower portion of the intermediate isolation layer 315, and the protective layer 316 thereon. Therefore, when the first channel stack CS1 is removed to expose the top surface T3 of the active pattern 301A, the dummy channel stack 301C can also be removed to expose the barrier layer 301B beneath the top surface T3 of the active pattern 301A. This is consistent with... Figure 14A and Figure 14BUnlike the intermediate semiconductor device 20' shown, in the intermediate semiconductor device 20', the top surface T3 of the active pattern 201A is exposed when the dummy channel stack 201B above it is removed.

[0114] At this point, when the first channel stack CS1 is removed, the residues RE1 and RE2 of the intermediate isolation layer 315 can also be removed. However, the intermediate isolation layer 315 remaining on the left side surface of the first channel stack CS1 may not be fully patterned; instead, due to differences in etch selectivity or etch rate between the first channel stack CS1 and the intermediate isolation layer 315, as well as height differences between portions of the intermediate isolation layer 315, its lower portion may remain as residue RE3, such as... Figure 21B As shown. In addition, after the first channel stack CS1 is patterned, a portion of the protective layer 316 may also be retained on the left side surface of the residue RE3 of the intermediate isolation layer 315.

[0115] refer to Figure 22A and Figure 22B The first source / drain region 313 can be in the previous step ( Figure 21A and Figure 21B The space S1 obtained by patterning the first channel stack CS1 is formed by the first channel structure CH1 including the first channel layer 312.

[0116] The first source / drain region 313 can be epitaxially grown primarily along the D1 direction from the first channel layer 312 of the first channel structure CH1 surrounded by or below the dummy gate structure 350', while the first sacrificial layer 311 of the first channel structure CH1 is covered by inner spacers formed on its side surface. When the epitaxial growth of the first source / drain region 313 is performed, the epitaxial structure forming the first source / drain region 313 can be in situ doped with n-type impurities such as phosphorus (P), arsenic (As), antimony (Sb), or p-type impurities such as boron (B), gallium (Ga), or indium (In).

[0117] As in Figure 15A and Figure 15B As in the intermediate semiconductor device 20' shown, no portion of the first source / drain region 313 is formed inside the substrate 301 (e.g., active pattern 301A) because of the previous steps ( Figures 19A to 19B and Figures 20A to 20BThe barrier layer 301B and the dummy channel stack 301C formed in the intermediate semiconductor device 10' do not form a depression in the substrate 301 like the depression R1 formed in the substrate 101 of the intermediate semiconductor device 10'. Therefore, current leakage similar to that that can be generated from a portion 113S of the first source / drain region 113 formed inside the substrate 101 can be prevented or reduced in the stacked semiconductor device made of the intermediate semiconductor device 30'.

[0118] Furthermore, since the barrier layer 301B is formed on the top surface T3 of the active pattern 301A, which is the right-hand portion of the top surface of the active pattern 301A, it can further prevent or reduce possible current leakage from the first source / drain region 313. This is because, regardless of whether the first source / drain region 313 is n-type or p-type, the barrier layer 301B, having a low concentration of impurities (the impurities being of the same type as those in the first source / drain region 313), can suppress carrier migration from the first source / drain region 313 to the substrate 301, as shown in the reference. Figure 19A and Figure 19B As stated above.

[0119] refer to Figure 23A and Figure 23B The second source / drain region 323 can be in the previous step ( Figure 10A and Figure 10B The space S2 obtained by patterning the second channel stack CS2 is formed by the second channel structure CH2 including the second channel layer 322.

[0120] The formation of the second source / drain region 323 can be applied to, for example, Figure 16A and Figure 16B The formation of the second source / drain region 223 of the intermediate semiconductor device 20' shown is performed in the same or similar manner, therefore, its repeated description can be omitted herein. An isolation structure 360 ​​may be formed around the first source / drain region 313 and the second source / drain region 323 to isolate the first source / drain region 313 and the second source / drain region 323 from each other or from other circuit elements.

[0121] refer to Figure 24A and Figure 24B The dummy gate structure 350' and the first sacrificial layer 311 and the second sacrificial layer 321 included in the first channel structure CH1 and the second channel structure CH2, respectively, can be replaced by the gate structure 350 to form a stacked semiconductor device 30.

[0122] The formation of the gate structure 350 can be used in applications such as Figure 17A and Figure 17BThe gate structure 250 of the intermediate semiconductor device 20' shown is formed in the same or similar manner, therefore, its repeated description can be omitted herein.

[0123] However, return to reference Figures 19A to 19B arrive Figures 22A to 22B Because of the barrier layer 301B and the dummy channel stack 301C grown on the substrate 301, the substrate 301 does not need to be patterned when the first channel stack CS1 is removed. Therefore, any portion of the first source / drain region 313 can be left unformed within the substrate 301, thereby preventing or reducing current leakage from the first source / drain region 313 to the substrate 301. Furthermore, the barrier layer 301B can further suppress carrier migration into the substrate 301 to further improve the device performance of the stacked semiconductor device 30.

[0124] Figure 25A and Figure 25B A flowchart illustrating the fabrication of a stacked semiconductor device using dummy channel stacks and barrier layers according to one or more embodiments is shown.

[0125] To pass Figure 25A and Figure 25B The flowchart illustrates how stacked semiconductor devices can be fabricated with reference... Figures 10A to 10B arrive Figures 24A to 24B At least one of the stacked semiconductor devices 20 and 30 is identical or similar.

[0126] In step S10, an initial semiconductor device comprising a first channel stack on a substrate and a second channel stack perpendicularly above the first channel stack can be provided. Figure 1A and Figure 1B Each of the first and second channel stacks may include multiple channel layers, which are nanosheet layers.

[0127] In step S20, the second channel stack can be patterned such that the second channel stack vertically overlaps with the first portion of the first portion and the second portion of the first channel stack. Figure 2A and Figure 2B As a result of patterning the second channel stack in this step, the first channel stack may have a larger channel width and fewer channel layers than the second channel stack.

[0128] In step S30, a dummy gate structure can be formed to stack around the first channel and the second channel. Figures 3A to 3B and Figures 4A to 4B ).

[0129] In step S40, the second portion of the second channel stack and the second portion of the first channel stack can be patterned based on the dummy gate structure to form a first space vertically above the first portion of the first channel stack, and expose the second portion of the first portion and the second portion of the top surface of the substrate, wherein the second portion of the first channel stack is removed from the second portion of the substrate. Figure 5A and 5B A first space is provided to form a second source / drain region in a subsequent step, and a second portion of the top surface of the substrate is exposed to grow a dummy channel stack therefrom in a next step.

[0130] In step S50, a dummy channel stack can be formed on a second portion of the top surface of the substrate exposed in the previous step. Figures 13A to 13B as well as Figures 18A to 18B arrive Figures 20A to 20B The dummy channel stack can be epitaxially grown from a second portion of the top surface of the substrate, such that the top surface of the dummy channel stack can be at or above the level of the top surface of the first channel stack.

[0131] Before forming the dummy channel stack, a barrier layer can be formed on a second portion of the top surface of the substrate, thus allowing the dummy channel stack to be formed on the barrier layer. The barrier layer can be formed of silicon and / or silicon-germanium with a lower concentration of impurities than those to be doped in the first source / drain regions in subsequent steps. The impurities doped in the barrier layer can be of the same type as those to be doped in the first source / drain regions.

[0132] In step S60, the first channel stack and the dummy channel stack can be patterned to form a second space and expose a first portion and a second portion of the top surface of the substrate. Figure 13A and Figure 13B as well as Figure 21A and Figure 21B ).

[0133] Due to the dummy channel stack, the first and second portions of the top surface of the substrate exposed by the patterning operation in this step can be substantially coplanar or aligned in the horizontal direction (i.e., the D1 or D2 direction). Furthermore, due to the dummy channel stack, the second portion of the top surface of the substrate can avoid being patterned when the first channel stack is patterned (this could form a recess in the substrate). If such a recess is formed in the substrate, a first source / drain region to be formed in the next step can also be formed therein to generate or increase current leakage from the first source / drain region into the substrate.

[0134] When a barrier layer is formed on a second portion of the top surface of the substrate prior to the formation of the dummy channel stack in a previous step, the barrier layer can be retained after the dummy channel stack is patterned together with the first channel stack. The barrier layer can be used to further reduce or better prevent current leakage from the first source / drain region to the substrate by suppressing carrier migration from the first source / drain region.

[0135] In step S70, a first source / drain region can be formed in the second space, and a second source / drain region can be formed in the first space. Then, a gate structure replacing the dummy gate structure is formed to complete the formation of the stacked semiconductor device. Figures 15A to 15B arrive Figures 17A to 17B Figures 22A to 22B arrive Figures 24A to 24B ).

[0136] In the above embodiments, the FETs formed at the first and second levels are described as nanosheet transistors comprising a nanosheet layer as a channel layer. However, this disclosure is not limited thereto. According to one or more other embodiments, each of the FETs may be a nanosheet transistor, a FinFET, a forked transistor, or any other type of transistor.

[0137] Figure 26 This illustrates a combination of one or more embodiments. Figures 17A to 17B and Figures 24A to 24B A schematic block diagram of an electronic device comprising one or more stacked semiconductor devices.

[0138] refer to Figure 26 The SoC 1000 can be an integrated circuit in which components of a computing system or other electronic system are integrated. As an example of the SoC 1000, an application processor (AP) may include at least one processor and components for various functions. The SoC 1000 may include a core 1011 (e.g., a processor), a digital signal processor (DSP) 1012, a graphics processing unit (GPU) 1013, embedded memory 1014, a communication interface 1015, and a memory interface 1016. Components of the SoC 1000 can communicate with each other via a bus 1007.

[0139] Core 1011 can process instructions and control operations for components included in SoC 1000. For example, core 1011 can process a series of instructions to run an operating system and execute applications on that operating system. DSP 1012 can generate useful data by processing digital signals (e.g., digital signals provided from communication interface 1015). GPU 1013 can generate data for an image output by a display device based on image data provided from embedded memory 1014 or memory interface 1016, or it can encode image data.

[0140] Embedded memory 1014 can store data necessary for the operation of core 1011, DSP 1012, and GPU 1013. Communication interface 1015 can provide an interface for communication networks or one-to-one communication. Memory interface 1016 can provide an interface for external memory of SoC 1000, such as dynamic random access memory (DRAM), flash memory, etc.

[0141] At least one of core 1011, DSP 1012, GPU 1013, and / or embedded memory 1014 may include components according to one or more embodiments. Figures 17A to 17B and Figures 24A to 24B One or more of the stacked semiconductor devices shown.

[0142] The foregoing is a description of exemplary embodiments and should not be construed as limiting this disclosure. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications to the above embodiments are possible without substantially departing from this disclosure.

[0143] This application is based on and claims priority to U.S. Provisional Application No. 63 / 693,557, filed September 11, 2024, with the United States Patent and Trademark Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A stacked semiconductor device, comprising: Substrate; The first source / drain region on the substrate; as well as A second source / drain region is located vertically above the first source / drain region, and the second source / drain region vertically overlaps with the first portion of the first source / drain region. The first portion of the top surface of the substrate that is vertically below the first portion of the first source / drain region is coplanar or aligned with the second portion of the top surface of the substrate that is vertically below the second portion of the first source / drain region.

2. The stacked semiconductor device of claim 1, wherein the first side surface of the first source / drain region and the first side surface of the second source / drain region are perpendicularly coplanar or aligned. The second side surfaces of the first source / drain region and the second side surfaces of the second source / drain region are not perpendicular, but coplanar or aligned. The second side surface is opposite to the first side surface.

3. The stacked semiconductor device according to claim 2, further comprising: The first channel structure on the first source / drain region; The second channel structure on the second source / drain region; as well as An intermediate isolation layer is located between the first channel structure and the second channel structure. A residual structure having the same material composition as the intermediate isolation layer is formed at the lower portion of the first side surface of the first source / drain region.

4. The stacked semiconductor device of claim 3 further includes a protective layer on the side surface of the residual structure.

5. The stacked semiconductor device according to claim 1, further comprising: A first channel structure on the first source / drain region, the first channel structure comprising a plurality of first nanosheets; as well as A second channel structure on the second source / drain region, the second channel structure comprising multiple second nanosheets. The number of the plurality of second nanosheets is greater than the number of the plurality of first nanosheets.

6. The stacked semiconductor device of claim 1, further comprising a barrier layer on the second portion of the top surface of the substrate.

7. The stacked semiconductor device of claim 6, wherein the barrier layer comprises a dopant of the same type as the dopant in the first source / drain region, and The concentration of the dopant is lower in the barrier layer than in the first source / drain region.

8. The stacked semiconductor device of claim 1, further comprising a barrier layer on the bottom surface of the second portion of the first source / drain region.

9. The stacked semiconductor device of claim 8, wherein the barrier layer comprises a dopant of the same type as the dopant in the first source / drain region, and The concentration of the dopant is lower in the barrier layer than in the first source / drain region.

10. A stacked semiconductor device, comprising: Substrate; The first source / drain region on the substrate; A second source / drain region is vertically above the first source / drain region, and the second source / drain region vertically overlaps with the first portion of the first source / drain region and the first portion of the second portion. as well as A barrier layer is provided on the second portion of a first portion and a second portion of the top surface of the substrate, wherein the second portion of the top surface of the substrate is perpendicularly below the second portion of the first source / drain region.

11. The stacked semiconductor device of claim 10, wherein the barrier layer comprises a dopant of the same type as the dopant in the first source / drain region, and The concentration of the dopant is lower in the barrier layer than in the first source / drain region.

12. The stacked semiconductor device of claim 11, wherein the barrier layer comprises silicon.

13. The stacked semiconductor device of claim 10, wherein the first side surface of the first source / drain region and the first side surface of the second source / drain region are perpendicularly coplanar or aligned. The second side surfaces of the first source / drain region and the second side surfaces of the second source / drain region are not perpendicular, but coplanar or aligned. The second side surface is opposite to the first side surface.

14. The stacked semiconductor device of claim 13, further comprising: The first channel structure on the first source / drain region; The second channel structure on the second source / drain region; as well as An intermediate isolation layer is located between the first channel structure and the second channel structure. A residual structure having the same material composition as the intermediate isolation layer is formed at the lower portion of the first side surface of the first source / drain region.

15. The stacked semiconductor device of claim 10, further comprising: A first channel structure on the first source / drain region, the first channel structure comprising a plurality of first nanosheets; as well as A second channel structure on the second source / drain region, the second channel structure comprising multiple second nanosheets. The number of the plurality of second nanosheets is greater than the number of the plurality of first nanosheets.

16. A method for manufacturing a stacked semiconductor device, the method comprising: A first source / drain region is formed on the substrate; as well as A second source / drain region is formed vertically above the first source / drain region. The process involves forming the first source / drain region and the second source / drain region, such that: The second source / drain region overlaps perpendicularly with the first portion of the first and second portions of the first source / drain region; as well as The first portion of the top surface of the substrate that is vertically below the first portion of the first source / drain region is coplanar or aligned with the second portion of the top surface of the substrate that is vertically below the second portion of the first source / drain region.

17. The method of claim 16, wherein forming the first source / drain region and the second source / drain region comprises: A first channel stack and a second channel stack are formed above the first channel stack, such that the second channel stack overlaps perpendicularly with the first portion of the first and second portions of the first channel stack; The second channel stack and the second portion of the first channel stack are patterned to form a first space vertically above the first portion of the first channel stack and expose the second portion of the top surface of the substrate; A dummy channel stack is formed on the second portion of the top surface of the substrate; as well as The first channel stack and the dummy channel stack are patterned to form a second space and expose the first and second portions of the top surface of the substrate. The first source / drain region is formed in the second space, and the second source / drain region is formed in the first space.

18. The method of claim 17, wherein the dummy channel stack is configured such that the top surface of the dummy channel stack is at a higher level than the top surface of the first channel stack.

19. The method of claim 18, wherein the dummy channel stack is formed by epitaxial growth of at least one of silicon and silicon-germanium on the substrate.

20. The method of claim 17, further comprising: Before forming the first source / drain region, a barrier layer is formed on the second portion of the top surface of the substrate.

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