Semiconductor device

Abstract

A semiconductor device includes: active patterns spaced apart in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source / drain pattern on the active pattern and alternately arranged in the second direction; an upper channel pattern on the lower channel pattern; an upper source / drain pattern on the lower source / drain pattern; a gate pattern extending in the first direction and on the lower channel pattern and the upper channel pattern; a separation pattern between the lower source / drain pattern and another lower source / drain pattern and between the upper source / drain pattern and another upper source / drain pattern in the second direction; and a gate cutting pattern extending through the gate pattern in the second direction to separate the gate pattern.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0125727, filed on September 13, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present invention relates to semiconductor devices. Background Technology

[0003] The development of the electronics industry requires specific characteristics of semiconductor devices (such as high reliability, high speed, and / or versatility). To achieve these characteristics, the structures within semiconductor devices are becoming increasingly complex and integrated. Summary of the Invention

[0004] Some aspects of this disclosure provide a semiconductor device including a discrete pattern that allows sufficient removal of the substrate during a back-side wiring process until the dummy source / drain pattern is exposed, smoothly forming through-vias within a gate dicing pattern, and reducing the distribution of through-vias to allow smoother contact between the through-vias and the underlying source / drain contacts.

[0005] A semiconductor device according to some embodiments of the present disclosure includes: an active pattern spaced apart in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source / drain pattern located on the active pattern and alternately arranged in the second direction; an upper channel pattern on the lower channel pattern and an upper source / drain pattern on the lower source / drain pattern; a gate pattern extending in the first direction and located on the lower channel pattern and the upper channel pattern; a separation pattern located in the second direction between one of the lower source / drain pattern and the upper source / drain pattern and the other of the lower source / drain pattern and the upper source / drain pattern; and a gate dicing pattern extending through the gate pattern in the second direction to separate the gate pattern, wherein, in a third direction different from the first and second directions, the lower end of the separation pattern is higher than the lower end of the gate dicing pattern.

[0006] A semiconductor device according to some embodiments of the present disclosure includes: an active pattern spaced apart in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source / drain pattern located on the active pattern and alternately arranged in the second direction; an upper channel pattern on the lower channel pattern and an upper source / drain pattern on the lower source / drain pattern; a gate pattern extending in the first direction and located on the lower channel pattern and the upper channel pattern; a gate dicing pattern extending through the gate pattern in the second direction to separate the gate pattern; and a through-via located on the gate dicing pattern. Inside, and extending upward in a second direction and a third direction along the gate dicing pattern; wherein, the through via has a first through via portion and a second through via portion and a third through via portion, the first through via portion extending in the second direction and extending from the lower end to the upper end of the through via in the third direction, the second through via portion and the third through via portion being located on one side of the first through via portion in the first direction and arranged alternately in the second direction, and the lower end of the third through via portion being higher in the third direction than the lower part of the first through via portion and the lower part of the second through via portion.

[0007] A semiconductor device according to some embodiments of the present disclosure includes: an active pattern spaced apart in a first direction and extending in a second direction different from the first direction; a lower channel pattern and a lower source / drain pattern located on the active pattern and alternately arranged in the second direction; an upper channel pattern on the lower channel pattern and an upper source / drain pattern on the lower source / drain pattern; a gate pattern extending in the first direction and located on the lower channel pattern and the upper channel pattern; a separation pattern located in the second direction between one of the lower source / drain pattern and the upper source / drain pattern and the other of the lower source / drain pattern and the upper source / drain pattern; and a gate dicing pattern extending through the gate pattern in the second direction to separate the gate pattern; wherein a portion of the separation pattern extends in the first direction and is inserted into the gate dicing pattern.

[0008] Some embodiments of the semiconductor device described herein have a structure that is compatible with or provides sufficient removal of the substrate during back-side wiring processes until the dummy source / drain pattern is exposed, while including the smooth formation of through-vias within the separation pattern and gate dicing pattern, and a reduction in the distribution of through-vias to more smoothly contact the through-vias and lower source / drain contacts. Attached Figure Description

[0009] Figure 1 This is a plan view showing an example of a semiconductor device.

[0010] Figure 2 It is along Figure 1A sectional view taken from lines A-A' and D-D'.

[0011] Figure 3 It is along Figure 1 The sectional view taken by line B-B'.

[0012] Figure 4 It is along Figure 1 A sectional view taken by line C-C'.

[0013] Figure 5 This is a plan view showing an example of a semiconductor device.

[0014] Figure 6 It is along Figure 5 A sectional view taken by line C-C'.

[0015] Figure 7 This is a plan view showing an example of a semiconductor device.

[0016] Figure 8 It is along Figure 7 A sectional view taken by line C-C'.

[0017] Figure 9 This is a plan view showing an example of a semiconductor device.

[0018] Figure 10 It is along Figure 9 A sectional view taken by line C-C'.

[0019] Figure 11 This is a plan view showing an example of a semiconductor device.

[0020] Figure 12 It is along Figure 11 A sectional view taken from lines A-A' and D-D'.

[0021] Figure 13 It is along Figure 11 A sectional view taken by line C-C'.

[0022] Figures 14 to 48 This is a cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Detailed Implementation

[0023] The present disclosure will be described more fully below with reference to the accompanying drawings, in which examples of the present disclosure are illustrated. As those skilled in the art will recognize, the described examples may be modified in various different ways, all without departing from the spirit or scope of the present disclosure.

[0024] Throughout the specification, the same reference numerals designate the same elements.

[0025] In the accompanying drawings, for clarity, the thickness and dimensions of layers, regions, etc., may be exaggerated or modified.

[0026] It will be understood that when an element such as a layer, membrane, region, or substrate is referred to as being "on" another element, the element may be directly on that other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "directly on" another element or "adjacent to" another element, there are no intermediate elements present. The terms "on" or "above" mean placed on or below a portion of an object, and do not necessarily mean placed on the upper side of the object based on the direction of gravity.

[0027] Additionally, in this specification, the phrase "in a plane" means viewing the target portion from the top, and the phrase "in a cross-section" means viewing the cross-section formed by vertically cutting the target portion from the side.

[0028] Furthermore, throughout the specification, two directions parallel to and intersecting the upper end (e.g., surface) of the substrate are defined as a first direction D1 and a second direction D2, respectively, and a direction perpendicular to the upper end of the substrate is described as a third direction D3. For example, the first direction D1 and the second direction D2 may be orthogonal to each other. The first direction D1 and the second direction D2 may be in the same plane (e.g., the same transverse plane corresponding to the surface of the substrate included in or on / from which the device is manufactured).

[0029] Figure 1 This is a plan view showing a semiconductor device. Figure 2 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 3 It is along Figure 1 The sectional view taken by line B-B'. Figure 4 It is along Figure 1 A sectional view taken by line C-C'.

[0030] For clarity and simplicity, Figure 1 The main features shown are the first active region AR1, the second active region AR2, the gate pattern GE, the upper source / drain pattern USD1, the upper source / drain contact aCA, the gate cut pattern 600, the separation pattern 520, and the separation structure 510.

[0031] For example, the semiconductor device can be a three-dimensional semiconductor device (e.g., stacked transistors). In other words, transistors can be stacked on a third direction D3 in a cell region (e.g., in an active region). For example, a single height cell (SHC) can be located between a first power wiring and a second power wiring, and the single height cell can include a first active region AR1 as a bottom tier, and a second active region AR2 can be stacked on top of the first active region AR1 as a top tier.

[0032] For example, the NMOSFET in the first active region AR1 may be located on the active pattern AP, and the PMOSFET in the second active region AR2 may be stacked on the NMOSFET. The first active region AR1 and the second active region AR2 may be spaced apart from each other on the third-direction D3.

[0033] In other words, a three-dimensional semiconductor device may have a first active region AR1 and a second active region AR2 stacked along a third direction D3. Therefore, Figure 1 Semiconductor devices can provide increased integration by reducing the area of ​​logic cells.

[0034] In some implementations, a peripheral region where transistors constituting the processor core or I / O terminals are arranged may be located around the cell region. For example, the peripheral region may be a core / peripheral region. As an example, the peripheral region may include long-gate transistors (or long-channel transistors) having a relatively long gate length (i.e., channel length). Transistors in the peripheral region may operate at higher power than transistors in the cell region. For example, transistors in the cell region may be single-gate (SG) devices, and transistors in the peripheral region may be additional-gate (EG) devices.

[0035] ( Figure 2 and Figure 4 The active pattern AP (marked in the middle) may be defined by a groove TR in the cell region. For example, the active pattern AP may be a portion that protrudes vertically in a third direction D3. In a plane (e.g., in a planar view), the active pattern AP may have a strip shape (e.g., having portions spaced apart in a first direction D1 and extending in a second direction D2). The first active region and the second active region (AR1, AR2) may be sequentially stacked on the active pattern AP.

[0036] For example, the active pattern AP may include a semiconductor material (such as silicon, germanium, or silicon-germanium), and may include, for example, silicon. In some embodiments, as described below, the active pattern AP is formed by replacing the substrate 100 with silicon oxide. Figures 2 to 3 The source / drain contact bCA (marked in the middle) and therefore the active pattern AP may include silicon oxide.

[0037] The device isolation layer ST may fill the trenches between active patterns AP. For example, the device isolation layer ST may include silicon oxide. The upper end of the device isolation layer ST may be coplanar with the upper end of the active pattern AP, or the height of the upper end of the device isolation layer ST may be lower than the height of the upper end of the active pattern AP. In one example, the height may indicate the height on a third direction D3. The device isolation layer ST may not cover the lower channel pattern LCH1 described later.

[0038] A first active region AR1, including a lower channel pattern LCH1 and a lower source / drain pattern LSD1, may be located on an active pattern AP. The lower channel pattern LCH1 may be interposed between a lower source / drain pattern LSD1 and another lower source / drain pattern LSD1 spaced apart from it in a second direction D2. The lower channel pattern LCH1 may connect a pair of lower source / drain patterns LSD1 to each other. For example, the lower channel pattern LCH1 and the lower source / drain pattern LSD1 may be arranged alternately in the second direction D2.

[0039] The lower channel pattern LCH1 may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked on a third-direction D3 and spaced apart from each other. However, this disclosure is not limited thereto, and the lower channel pattern LCH1 may include three or more semiconductor patterns. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include crystalline silicon.

[0040] The lower source / drain pattern LSD1 can be located at the top end or on the top surface of the active pattern AP. The lower source / drain pattern LSD1 can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the top end of the lower source / drain pattern LSD1 can be higher than the top end of the second semiconductor pattern SP2 of the lower channel pattern LCH1.

[0041] The lower source / drain pattern LSD1 may be doped with impurities to have a first conductivity type. The first conductivity type may be N-type or P-type. As an example, the first conductivity type may be N-type. The lower source / drain pattern LSD1 may include silicon (Si) or silicon germanium (SiGe).

[0042] The dummy source / drain pattern 155 may be located below the lower source / drain pattern LSD1. The dummy source / drain pattern 155 may penetrate at least a portion of the active pattern AP. For example, the dummy source / drain pattern 155 may be embedded within the active pattern AP. The dummy source / drain pattern 155 may be located below at least one of a plurality of lower source / drain patterns LSD1.

[0043] For example, the dummy source / drain pattern 155 may include the same material as the lower source / drain pattern LSD1. For example, the dummy source / drain pattern 155 may include silicon (Si) or silicon germanium (SiGe), and may also include carbon (C), silicon (Si), germanium (Ge), or tin (Sn).

[0044] As described below, when the substrate 100 is removed to form the lower source / drain contact bCA, as the substrate 100 is removed until the dummy source / drain pattern 155 is exposed, the lower end of the dummy source / drain pattern 155 may have a flat shape and may contact the lower wiring structure M1b.

[0045] The first interlayer stop film ESL1 may be located on the lower source / drain pattern LSD1. For example, the first interlayer stop film ESL1 may cover the lower source / drain pattern LSD1.

[0046] The first interlayer insulating layer 110 may be located on the first interlayer stop film ESL1. The first interlayer insulating layer 110 may cover the lower source / drain pattern LSD1.

[0047] For example, the first interlayer insulating layer 110 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a low-k material.

[0048] The first interlayer stop film ESL1 may include a material that is etch-selective relative to the first interlayer insulating layer 110. The first interlayer stop film ESL1 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon oxycarbide (SiOC).

[0049] The second active region AR2 may be located above the first active region AR1. The second active region AR2 may include an upper channel pattern UCH1 and an upper source / drain pattern USD1.

[0050] The upper channel pattern UCH1 can be located on the lower channel pattern LCH1. The upper source / drain pattern USD1 can be located on the lower source / drain pattern LSD1. For example, the upper channel pattern UCH1 can be superimposed on the lower channel pattern LCH1 along the third direction D3. The upper source / drain pattern USD1 can be superimposed on the lower source / drain pattern LSD1 along the third direction D3. The upper channel pattern UCH1 can be inserted between an upper source / drain pattern USD1 and another upper source / drain pattern USD1 spaced apart from the upper source / drain pattern USD1 along the second direction D2. The upper channel pattern UCH1 can connect a pair of upper source / drain patterns USD1 to each other. For example, the upper channel pattern UCH1 and the upper source / drain pattern USD1 can be arranged alternately along the second direction D2.

[0051] The upper channel pattern UCH1 may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked on and spaced apart from each other on a third-direction D3. However, this disclosure is not limited thereto, and the upper channel pattern UCH1 may include three or more semiconductor patterns. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH1 may include the same semiconductor material as the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH1 described above.

[0052] At least one intermediate insulating structure DSP can be inserted between the lower channel pattern LCH1 and the upper channel pattern UCH1 on the lower channel pattern LCH1, and at least one dummy channel pattern SDL can be inserted between the first semiconductor pattern to the fourth semiconductor pattern SP1, SP2, SP3 and SP4.

[0053] For example, the intermediate insulating structure DSP can be located between the lower channel pattern LCH1 and the upper channel pattern UCH1, and the dummy channel pattern SDL can be inserted between the intermediate insulating structure DSP and the third semiconductor pattern SP3 of the upper channel pattern UCH1.

[0054] For example, the second semiconductor pattern SP2 of the lower channel pattern LCH1, the third sub-gate portion PO3 of the lower gate pattern LGE1, the intermediate insulating structure DSP, the dummy channel pattern SDL, the fourth sub-gate portion PO4 of the upper gate pattern UGE1, and the third semiconductor pattern SP3 of the upper channel pattern UCH1 can be stacked sequentially on the third-direction D3.

[0055] The intermediate insulating structure DSP may include semiconductor materials (such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe)) or silicon-based insulating materials (such as silicon oxide or silicon nitride). For example, the intermediate insulating structure DSP may include silicon-based insulating materials.

[0056] The dummy channel pattern (SDL) may include semiconductor materials (such as silicon (Si), germanium (Ge), or silicon-germanium (SiGe)) or silicon-based insulating materials (such as silicon oxide or silicon nitride).

[0057] The upper source / drain pattern USD1 may be located on the upper surface of the first interlayer insulating layer 110. The upper source / drain pattern USD1 may be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the upper end of the upper source / drain pattern USD1 may be higher than the upper end of the fourth semiconductor pattern SP4 of the upper channel pattern UCH1.

[0058] The upper source / drain pattern USD1 may be doped with impurities to have a second conductivity type. This second conductivity type may differ from the first conductivity type of the lower source / drain pattern LSD1. For example, the second conductivity type may be P-type. The upper source / drain pattern USD1 may comprise silicon germanium (SiGe) or silicon (Si).

[0059] The second interlayer stop film ESL2 can be located on the upper source / drain pattern USD1. For example, the second interlayer stop film ESL2 can cover the upper source / drain pattern USD1.

[0060] The second interlayer stop film ESL2 may cover the two side surfaces of the upper source / drain pattern USD1 in the first direction D1. The second interlayer stop film ESL2 may not be located between the upper source / drain pattern USD1 and the upper source / drain contact aCA. For example, the upper source / drain pattern USD1 and the upper source / drain contact aCA may be in direct contact.

[0061] The second interlayer insulating layer 120 may be located on the second interlayer stop film ESL2. The second interlayer insulating layer 120 may cover the upper source / drain pattern USD1.

[0062] For example, the second interlayer insulating layer 120 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a low-k material.

[0063] The second interlayer stop film ESL2 may include a material that has etch selectivity relative to the second interlayer insulating layer 120. The second interlayer stop film ESL2 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon oxycarbide (SiOC).

[0064] The gate pattern GE can be located on the lower channel pattern LCH1 and the upper channel pattern UCH1. In a planar configuration, or in a planar diagram (e.g., as shown below) Figure 1As shown in the diagram, the gate pattern GE may have a strip shape (e.g., a rectangular shape) extending in the first direction D1. A portion of the gate pattern GE may be stacked on the third direction D3 with the stacked lower channel pattern LCH1 and upper channel pattern UCH1.

[0065] The gate pattern GE may extend on the third direction D3 from the top of the device isolation layer ST or the top of the active pattern AP to the gate cap pattern GP, ​​which will be described later. The gate pattern GE may extend on the third direction D3 from the lower channel pattern LCH1 of the first active region AR1 to the upper channel pattern UCH1 of the second active region AR2. For example, the gate pattern GE may extend on the third direction D3 from the bottom first semiconductor pattern SP1 to the top fourth semiconductor pattern SP4.

[0066] The gate pattern GE may be located on the top end, bottom surface, and two side surfaces of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4. For example, a logic cell may include a three-dimensional field-effect transistor (e.g., an MBCFET or a GAAFET) in which the gate pattern GE three-dimensionally surrounds the channel.

[0067] The gate pattern GE may have a lower gate pattern LGE1 located within a first active region AR1 and an upper gate pattern UGE1 located within a second active region AR2. The lower gate pattern LGE1 and the upper gate pattern UGE1 may be stacked on a third-party direction D3. The lower gate pattern LGE1 and the upper gate pattern UGE1 may be connected to each other. For example, the gate pattern GE may be a common gate electrode in which the lower gate pattern LGE1 on the lower channel pattern LCH1 and the upper gate pattern UGE1 on the upper channel pattern UCH1 are connected to each other.

[0068] The lower gate pattern LGE1 may have a first sub-gate portion PO1 inserted between the active pattern AP and the first semiconductor pattern SP1, a second sub-gate portion PO2 inserted between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third sub-gate portion PO3 inserted between the second semiconductor pattern SP2 and the intermediate insulating structure DSP.

[0069] The upper gate pattern UGE1 may have a fourth sub-gate portion PO4 inserted between the dummy channel pattern SDL and the third semiconductor pattern SP3, a fifth sub-gate portion PO5 inserted between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and a sixth sub-gate portion PO6 located on the fourth semiconductor pattern SP4.

[0070] For example, the lower gate pattern LGE1 may include a first work function metal pattern located on the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The upper gate pattern UGE1 may include a second work function metal pattern located on the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4. Each of the first and second work function metal patterns may include a metal (including titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), or combinations thereof) and nitrogen (N). The first and second work function metal patterns may have different work functions. The gate pattern GE may include, for example, a low-resistivity metal (including tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof) located on the first and second work function metal patterns.

[0071] A gate insulating layer (or gate insulating film) GI may be interposed between the gate pattern GE and the first semiconductor patterns SP1 to the fourth semiconductor patterns SP4. The gate insulating layer may include a silicon oxide film, a silicon oxynitride film, a high-k dielectric film, or a combination thereof. As an example, the gate insulating film GI may include a silicon oxide film directly covering the surfaces of the first semiconductor patterns SP1 to the fourth semiconductor patterns SP4 and a high-k dielectric film located on the silicon oxide film. In other words, the gate insulating layer GI may include multiple layers of silicon oxide layers and high-k dielectric layers.

[0072] High-dielectric films may include materials with high dielectric constants, which have a higher dielectric constant than silicon oxide films. As examples, high-dielectric-constant materials may include hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

[0073] In some embodiments, the gate spacer is located between the gate pattern GE and the lower source / drain pattern LSD1 and the upper source / drain pattern USD1. For example, the gate spacer may be located between the first sub-gate portion PO1 to the third sub-gate portion PO3 of the lower gate pattern LGE1 and the lower source / drain pattern LSD1, and may be located between the fourth sub-gate portion PO4 and the fifth sub-gate portion PO5 of the upper gate pattern LGE1 and the upper source / drain pattern USD1.

[0074] For example, when viewed in cross-section, the gate spacer may be located on each side of the first sub-gate portion PO1 to the fifth sub-gate portion PO5 in the second direction D2.

[0075] For example, the gate spacer may include a low-k material. The low-k material may include silicon oxide, or a material having a lower dielectric constant than silicon oxide. For example, the low-k material may include silicon oxide, fluorine- or carbon-doped silicon oxide, porous silicon oxide, or an organic polymer dielectric.

[0076] ( Figure 2 A pair of gate spacers GS (marked in the middle) may be arranged on two side surfaces of the sixth sub-gate portion PO6 of the gate pattern GE in the second direction D2. The gate spacers GS may extend along the gate pattern GE in the first direction D1.

[0077] The upper end of the gate spacer GS may be higher than the upper end of the gate pattern GE. The upper end of the gate spacer GS may be coplanar with the upper end of the second interlayer insulating layer 120.

[0078] The gate spacer GS may include SiCN, SiOCN, SiN, or combinations thereof. For example, the gate spacer GS may include multiple layers, each comprising SiCN, SiOCN, SiN, or combinations thereof.

[0079] The gate cover pattern GP may be located on the upper end of the gate pattern GE. The gate cover pattern GP may extend along the gate pattern GE in a first direction D1. For example, the gate cover pattern GP may include SiON, SiCN, SiOCN, SiN, or combinations thereof.

[0080] The gate diced pattern 600 may be located between an active pattern AP and another active pattern AP spaced apart from the active pattern AP in the first direction D1. For example, the gate diced pattern 600 may be alternately arranged with the active pattern AP in the first direction D1. The gate diced pattern 600 may be spaced apart from the active pattern AP in the first direction D1, and the device isolation layer ST may be located between the gate diced pattern 600 and the active pattern AP.

[0081] The gate dicing pattern 600 may extend in the second direction D2. For example, in a planar or planar diagram (e.g., Figure 1 In the gate cutting pattern 600, the gate cutting pattern 600 may have a strip shape (e.g., a rectangular shape), the strip shape (e.g., a rectangular shape) having portions spaced apart from each other in a first direction D1 and extending in a second direction D2.

[0082] The gate cleaving pattern 600 may extend in the third direction D3. For example, the gate cleaving pattern 600 may extend in the third direction D3 from a height lower than the lower end of the gate pattern GE to a height higher than the upper end of the gate pattern GE. For example, the lower end of the gate cleaving pattern 600 may be closer to the lower end of the active pattern AP in the third direction D3 than the lower end of the gate pattern GE.

[0083] For example, the height (or vertical height) of the lower end of the gate dicing pattern 600 may be lower than the height of the upper end of the active pattern AP, lower than the height of the lower end of the discrete pattern 520 described later, lower than the height of the lower end of the through-via 650 described later, and higher than or substantially equal to the height of the lower end of the dummy source / drain pattern 155. The lower end of the gate dicing pattern 600 may contact the upper end of the lower wiring structure M1b.

[0084] The gate dicing pattern 600 may be located between a lower gate pattern LGE1 and another lower gate pattern LGE1 spaced apart from the lower gate pattern LGE1 in the first direction D1. Alternatively, the gate dicing pattern 600 may be located between an upper gate pattern UGE1 and another upper gate pattern UGE1 spaced apart from the upper gate pattern UGE1 in the first direction D1.

[0085] Therefore, a gate pattern GE can be separated from another gate pattern GE that is spaced apart from the first gate pattern GE in the first direction D1 by the gate cut pattern 600. For example, the gate cut pattern 600 can extend through the gate pattern GE in the second direction D2, and the gate cut pattern 600 can penetrate the lower gate pattern LGE1 and the upper gate pattern UGE1 of the gate pattern GE. Therefore, the connection of the gate patterns GE can be cut by the gate cut pattern 600.

[0086] The gate cleaving pattern 600 may be located between a lower source / drain pattern LSD1 and another lower source / drain pattern LSD1 spaced apart from the lower source / drain pattern LSD1 in the first direction D1. The gate cleaving pattern 600 may be located between an upper source / drain pattern USD1 and an upper source / drain pattern USD1 (e.g., another upper source / drain pattern USD1 spaced apart from the upper source / drain pattern USD1 in the first direction D1).

[0087] Additionally, the gate dicing pattern 600 may be located between the lower source / drain contact bCA and another lower source / drain contact bCA spaced apart from the lower source / drain contact bCA in the first direction D1. The gate dicing pattern 600 may be located between the lower gate contact bCB and another lower gate contact bCB spaced apart from the lower gate contact bCB in the first direction D1.

[0088] Meanwhile, as described later, since the separation pattern 520 is formed at the location where the gate pattern GE, lower channel pattern LCH1, and upper channel pattern UCH1 are removed by the gate dicing pattern 600, the gate dicing pattern 600 can be located between the gate pattern GE and the separation pattern 520 in the first direction D1. For example, the separation pattern 520 can be located between one gate dicing pattern 600 and another gate dicing pattern 600 spaced apart from the one gate dicing pattern 600 in the first direction D1.

[0089] As an example, such as Figure 4 As shown, the gate dicing pattern 600 may include a gap-filling insulating layer 620 and an insulating liner 610, with the insulating liner 610 located on both sides of the gap-filling insulating layer 620 in the first direction D1.

[0090] The gap-filling insulating layer 620 can be positioned to fill the internal space of the gate dicing pattern 600. The gap-filling insulating layer 620 can be located approximately at the center of the gate dicing pattern 600 in the first direction D1.

[0091] A portion of the insulating liner 610 may be separated from each other on both sides of the gap-filling insulating layer 620 in the first direction D1. For example, in the first direction D1, the insulating liner 610 may be located between the gate pattern GE and the gap-filling insulating layer 620, and may also be located between the separation pattern 520 and the gap-filling insulating layer 620.

[0092] The gate dicing pattern 600 may include an insulating material. For example, the gate dicing pattern 600 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0093] For example, the gap-filling insulating layer 620 and the insulating liner 610 constituting the gate dicing pattern 600 may comprise different materials. For example, the gap-filling insulating layer 620 may comprise silicon oxide, and the insulating liner 610 may comprise silicon nitride. However, this is only an example, and the materials of the gap-filling insulating layer 620 and the insulating liner 610 may be varied in various ways.

[0094] The through-hole 650 may be located within the gate cut pattern 600.

[0095] The through-via 650 may extend in the third direction D3 to penetrate all or at least a portion of the gate dicing pattern 600. The upper portion of the through-via 650 may connect to the upper source / drain contact aCA, and the lower portion of the through-via 650 may connect to the lower source / drain contact bCA. Therefore, the through-via 650 may connect between the upper source / drain contact aCA and the lower source / drain contact bCA. Additionally, the through-via 650 may connect to the lower wiring structure M1b.

[0096] For example, the through-via 650 may extend on the third direction D3 from a height higher than the lower end of the gate diced pattern 600 to a height lower than or substantially the same as the upper end of the gate diced pattern 600. For example, the lower end of the through-via 650 may be located on the third direction D3 further away from the lower end of the active pattern AP than the lower end of the gate diced pattern 600.

[0097] Additionally, the height of the lower end of the through-via 650 may be lower than the height of the upper end of the active pattern AP, higher than the height of the lower end of the gate diced pattern 600, higher than the height of the lower end of the discrete pattern 520, and higher than the height of the lower end of the dummy source / drain pattern 155. The lower end of the through-via 650 may not contact the upper end of the lower wiring structure M1b. The connection portion CM, described later, may be located between the through-via 650 and the lower wiring structure M1b.

[0098] The through-via 650 may extend along the gate cut pattern 600 in the second direction D2. For example, in a plane, or in a planar view (e.g., as shown in the diagram). Figure 1 As shown in the diagram, the through-via 650 may have a strip shape, the strip shape being spaced apart in a first direction D1 and extending in a second direction D2. Multiple through-vias may be spaced apart from each other in the first direction D1. Therefore, the through-via 650 may extend through the gate pattern GE in the second direction D2, and the through-via 650 may penetrate the lower gate pattern LGE1 and the upper gate pattern UGE1 of the gate pattern GE.

[0099] The through-via 650 may be located approximately at the center of the gate diced pattern 600 in the first direction D1. The insulating liner 610 of the gate diced pattern 600 may be separated from each other on both sides of the through-via 650 in the first direction D1. The gap-filling insulating layer 620 of the gate diced pattern 600 may be positioned to fill the internal space between the through-via 650 and the insulating liner 610.

[0100] In some embodiments, the through-via 650 includes a conductive pattern and a blocking pattern surrounding the conductive pattern. For example, the conductive pattern may include a metal (including aluminum, copper, tungsten, molybdenum, or combinations thereof). The blocking pattern may cover the sidewalls and bottom surface of the conductive pattern. The blocking pattern may include a metal film or a metal nitride film. The metal film may include titanium, tantalum, tungsten, nickel, cobalt, platinum, or combinations thereof. The metal nitride film may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or combinations thereof.

[0101] For example, the through-hole 650 may have a first through-hole portion to a third through-hole portion 651, 652 and 653.

[0102] The first via portion 651 may extend in the second direction D2 and may extend in the third direction D3 from the lower end to the upper end of the through via 650. For example, the first via portion 651 may extend in the third direction D3 from a height higher than the lower end of the gate diced pattern 600 to a height lower than or substantially the same as the upper end of the gate diced pattern 600.

[0103] The first via portion 651 may extend along the gate dicing pattern 600 in the second direction D2. For example, in a plane (e.g., Figure 1 In the first via portion 651, the first via portion may have a strip shape extending in the second direction D2.

[0104] The second via portion 652 and the third via portion 653 may be located on one side of the first via portion 651 in the first direction D1. For example, the second via portion 652 and the third via portion 653 may be located on the surface of the first via portion 651 facing the separation pattern 520.

[0105] The second via portion 652 and the third via portion 653 may be alternately arranged in the second direction D2. When the first via portion 651 extends in the second direction D2, the first via portion 651 passes through the separation pattern 520 and the upper source / drain pattern USD1 alternately arranged in the second direction D2. At this time, the second via portion 652 may be located between the first via portion 651 and the upper source / drain pattern USD1, and the third via portion 653 may be located between the first via portion 651 and the separation pattern 520. The third via portion 653 may contact the separation pattern 520, and for example, may contact the protrusion 522 of the separation pattern 520 described below.

[0106] The second via portion 652 may extend from the lower end to the upper end of the through via 650 in the third direction D3, and the third via portion 653 may extend from the middle to the upper end of the through via 650 in the third direction D3. For example, the height of the lower end of the third via portion 653 may be higher than the height of the lower end of the first via portion 651 and the lower end of the second via portion 652. The height of the upper end of the third via portion 653 may be substantially the same as the height of the upper end of the first via portion 651 and the upper end of the second via portion 652. Accordingly, the length of the third via portion 653 in the third direction D3 may be shorter than the length of the first via portion 651 and the second via portion 652 (e.g., the length in the third direction D3).

[0107] Meanwhile, since the through-hole 650 is located within the gate dicing pattern 600 and the gate dicing pattern 600 is filled with a gap-filling insulating layer 620, the through-hole 650 can be surrounded by the gap-filling insulating layer 620.

[0108] For example, the gap-filling insulating layer 620 may be located on one side of the first via portion 651 in the first direction D1, and may be located between the first via portion 651 and the insulating liner 610 on one side. The gap-filling insulating layer 620 may be located on the other side of the second via portion 652 and the third via portion 653 in the first direction D1, and may be located between the second via portion 652 and the third via portion 653 and the insulating liner 610 on the other side. The gap-filling insulating layer 620 may be located below the first via portion 651 and the second via portion 652 in the third direction D3, and may be located between the first via portion 651 and the second via portion 652 and the lower wiring structure M1b.

[0109] Additionally, the gap-filling insulating layer 620 may have an insertion portion 620a located below the third via portion 653 in the third direction D3. As described above, since the length of the third via portion 653 in the third direction D3 is shorter than the length of the second via portion 652 (e.g., the length in the third direction D3), a portion of the through-hole 650 is not located below the third via portion 653 and may be filled with the insertion portion 620a of the gap-filling insulating layer 620. Furthermore, when the second via portion 652 and the third via portion 653 are alternately arranged in the second direction D2, the insertion portion 620a of the gap-filling insulating layer 620 may also be alternately arranged with the second via portion 652 in the second direction D2.

[0110] For example, when the gate dicing pattern 600 includes an oxide-containing gap-filling insulating layer 620 and a nitride-containing insulating liner 610, as described below, etching for forming a through-via 650 within the gate dicing pattern 600 can be performed smoothly.

[0111] At this time, due to the difference in etching rate between the gap-filling insulating layer 620 and the insulating liner 610, a portion of the separation pattern 520 (e.g., the protruding portion 522 of the separation pattern 520) may be formed within the gate dicing pattern 600.

[0112] Therefore, when the gate cut pattern 600 is etched to form the through via 650, relatively more (e.g., deeper) etching is performed at the location of the protrusion 522 where the separator pattern 520 is not inserted, so that a second via portion 652 with a relatively deep depth on the third direction D3 is formed, and at the location of the protrusion 522 where the separator pattern 520 is inserted, since the separator pattern 520 is etched together with the gate cut pattern, relatively less (e.g., shallower) etching is performed, so that a third via portion 653 with a relatively shallow depth on the third direction D3 can be formed.

[0113] Additionally, when the separation pattern 520 is spaced apart in the second direction D2, the second through-hole portion 652 and the third through-hole portion 653 of the through-hole 650 are also alternately positioned in the second direction D2, and when in the cross-section (e.g., Figure 2 When observed in the image, the boundary between the through-hole 650 and the gap-filling insulation layer 620 may have an uneven wavy shape in the third direction D3 while following the second direction D2.

[0114] Additionally, a portion of the separation pattern 520 inserted into the gate dicing pattern 600 (e.g., the protruding portion 522 of the separation pattern 520) may contact the through via 650 (e.g., the third via portion 653 of the through via 650).

[0115] The separation pattern 520 may be located between a lower source / drain pattern LSD1 and another lower source / drain pattern LSD1 spaced apart from the lower source / drain pattern LSD1 in the second direction D2. Alternatively, the separation pattern 520 may be located between an upper source / drain pattern USD1 and another upper source / drain pattern USD1 spaced apart from the upper source / drain pattern USD1 in the second direction D2.

[0116] For example, the separation pattern 520 can be alternated with the lower source / drain pattern LSD1 on the second direction D2. Alternatively, the separation pattern 520 can be alternated with the upper source / drain pattern USD1 on the second direction D2.

[0117] The separation pattern 520 may be located between the upper source / drain contact aCA and another upper source / drain contact aCA spaced apart from the upper source / drain contact aCA in the second direction D2. Alternatively, the separation pattern 520 may be located between the lower source / drain contact bCA and another lower source / drain contact bCA spaced apart from the lower source / drain contact bCA in the second direction D2.

[0118] The separation pattern 520 may be located between the gate patterns GE separated by the gate dicing pattern 600 in the first direction D1. For example, the gate dicing pattern 600 may be located between the gate pattern GE and the separation pattern 520 in the first direction D1.

[0119] After removing at least a portion of the gate pattern GE, lower gate pattern LGE1, and upper gate pattern UGE1 cut by the gate dicing pattern 600, a separation pattern 520 may be formed at the location where at least a portion of the gate pattern GE, lower gate pattern LGE1, and upper gate pattern UGE1 were removed. For example, the separation pattern 520 may be located between one gate dicing pattern 600 and another gate dicing pattern 600 spaced apart in the first direction D1. The separation pattern 520 may extend in the first direction D1 from one gate dicing pattern 600 to "another gate dicing pattern 600 spaced apart in the first direction D1 from the one gate dicing pattern 600".

[0120] Additionally, the separation pattern 520 may be located on the same line as the gate pattern GE. In other words, the separation pattern 520 and the gate pattern GE may be stacked on the first direction D1, and the width of the separation pattern 520 on the second direction D2 may be similar to or substantially the same as the width of the gate pattern GE on the second direction D2.

[0121] The separation pattern 520 may extend in a first direction D1 parallel to the gate pattern GE. For example, in a plane (e.g., Figure 1 In the process, the separation pattern 520 may have a strip shape and may include portions that are spaced apart from each other in the second direction D2 and extend in the first direction D1.

[0122] The separate pattern 520 can be located on the active pattern AP.

[0123] However, the height of the upper end of the active pattern AP located below the split pattern 520 can be lower than the height of the upper end of the active pattern AP located below the gate pattern GE. Therefore, the height of the lower end of the split pattern 520 can be lower than the height of the lower end of the gate pattern GE.

[0124] The separation pattern 520 may extend along the third direction D3. For example, the separation pattern 520 may extend along the third direction D3 from a height lower than the lower end of the lower source / drain pattern LSD1 to a height higher than the upper end of the upper source / drain pattern USD1. For example, the lower end of the separation pattern 520 may be located along the third direction D3 closer to the lower end of the active pattern AP than the lower end of the lower source / drain pattern LSD1.

[0125] For example, the height of the lower end of the split pattern 520 may be lower than the height of the upper end of the active pattern AP, lower than the height of the lower source / drain pattern LSD1, higher than the height of the lower end of the dummy source / drain pattern 155, higher than the height of the lower end of the gate cut pattern 600, and lower than the height of the lower end of the through via 650.

[0126] The separation pattern 520 may be spaced apart from the lower wiring structure M1b on the third-direction D3. In other words, the lower end of the separation pattern 520 may not contact the upper end of the lower wiring structure M1b. The active pattern AP may be located between the separation pattern 520 and the lower wiring structure M1b.

[0127] Therefore, as described below, when removing the substrate 100 to form the lower source / drain contact bCA, the substrate 100 can be prevented from being insufficiently removed due to being blocked by the separation pattern 520, and the substrate 100 can be fully removed until the virtual source / drain pattern 155 is exposed.

[0128] For example, the separation pattern 520 may include an insulating material. For example, the separation pattern 520 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof, and may include silicon nitride.

[0129] A portion of the separation pattern 520 may extend in the first direction D1 and be inserted into the gate cut pattern 600.

[0130] For example, the separation pattern 520 may have a main body portion 521 and a protruding portion 522, and the protruding portion 522 of the separation pattern 520 may be inserted into the gate dicing pattern 600.

[0131] The main body portion 521 may be located adjacent to the gate diced pattern 600 in the first direction D1. The main body portion 521 may be located between one gate diced pattern 600 and another gate diced pattern 600 spaced apart from the one gate diced pattern 600 in the first direction D1. The main body portion 521 may extend in the first direction D1 from one gate diced pattern 600 to the other gate diced pattern 600 spaced apart in the first direction D1. The main body portion 521 may contact the sidewall of the gate diced pattern 600 in the first direction D1.

[0132] The main body portion 521 may extend in the third direction D3. For example, the main body portion 521 may extend in the third direction D3 from a height lower than the lower end of the lower source / drain pattern LSD1 to a height higher than the upper end of the upper source / drain pattern USD1.

[0133] The protruding portion 522 may protrude from the main body portion 521 in the first direction D1.

[0134] The protruding portion 522 may protrude from the upper end of the main body portion 521 in the first direction D1. In the third direction D3, the height of the upper end of the protruding portion 522 may be substantially the same as the height of the upper end of the main body portion 521, and the height of the lower end of the protruding portion 522 may be higher than the height of the lower end of the main body portion 521. Therefore, when in cross-section (e.g., Figure 4 When observed in the image, the separated pattern 520 may have a "T" shape.

[0135] When the main body portion 521 contacts the sidewall of the gate diced pattern 600 in the first direction D1, the protrusion 522 can be inserted into the gate diced pattern 600. For example, the protrusion 522 can be superimposed on a portion of the gate diced pattern 600 along the third direction D3. For example, the protrusion 522 can be located on the gap-filling insulating layer 620 of the gate diced pattern 600 through the insulating liner 610.

[0136] Additionally, the protruding portion 522 may contact the through-hole 650. For example, the protruding portion 522 may contact the third through-hole portion 653 of the through-hole 650. Furthermore, the lower end of the protruding portion 522 may be higher than the lower end of the third through-hole portion 653.

[0137] The separation structure 510 may be located on one side of the lower source / drain pattern LSD1 in the second direction D2. Alternatively, the separation structure 510 may be located on one side of the upper source / drain pattern USD1 in the second direction D2. The separation structure 510 may be arranged spaced apart from the separation pattern 520 in the second direction D2.

[0138] In some embodiments, the separation structure 510 is arranged alternately with the lower source / drain pattern LSD1 in the second direction D2. Alternatively, the separation structure 510 may be arranged alternately with the upper source / drain pattern USD1 in the second direction D2.

[0139] The separation structure 510 may be located on one side of the gate pattern GE in the second direction D2. The separation structure 510 may be formed at this location after the gate pattern GE, the lower gate pattern LGE1, and the upper gate pattern UGE1 have been removed.

[0140] The separation structure 510 may extend in a first direction D1 parallel to the gate pattern GE. Therefore, the separation structure 510 may pass adjacent to a plurality of active patterns AP spaced apart from each other in the first direction D1. For example, in a plane or in a planar view (e.g., Figure 1 In the first direction D1, the separation structure 510 may have a strip shape with the longest extension direction.

[0141] The separation structure 510 may be located on the active pattern AP and may extend in the third direction D3. For example, the separation structure 510 may extend in the third direction D3 from a height lower than the lower end of the lower source / drain pattern LSD1 to a height higher than the upper end of the upper source / drain pattern USD1.

[0142] For example, the separation structure 510 may include an insulating material. For example, the separation structure 510 may include silicon oxide, silicon nitride, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof.

[0143] The upper source / drain contact aCA can be electrically connected to the upper source / drain pattern USD1 through the second interlayer insulating layer 120. Alternatively, in some embodiments, the upper gate contact is electrically connected to the gate pattern GE through the second interlayer insulating layer 120 and the gate cap pattern GP.

[0144] The upper source / drain contact aCA may extend in the first direction D1 and connect to the through-via 650. A portion of the upper source / drain contact aCA may be inserted into the gate dicing pattern 600. For example, a portion of the upper source / drain contact aCA may be stacked with a portion of the gate dicing pattern 600 along the third direction D3. For example, a portion of the upper source / drain contact aCA may be located on the gap-filling insulating layer 620 through the insulating liner 610 of the gate dicing pattern 600. For example, the upper source / drain contact aCA may contact the second via portion 652 of the through-via 650. Therefore, the upper source / drain contact aCA may be connected to the lower source / drain contact bCA through the through-via 650.

[0145] In some embodiments, the upper source / drain contact aCA includes a conductive pattern and a blocking pattern surrounding the conductive pattern. For example, the conductive pattern may include aluminum, copper, tungsten, molybdenum, or combinations thereof. The blocking pattern may cover the side and bottom surfaces of the conductive pattern. The blocking pattern may include a metal film or a metal nitride film. The metal film may include titanium, tantalum, tungsten, nickel, cobalt, platinum, or combinations thereof. The metal nitride film may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or combinations thereof.

[0146] In some embodiments, the upper interlayer insulation layer is located on the upper source / drain contact aCA and covers the upper source / drain contact aCA.

[0147] The lower source / drain contact bCA may be located below the lower source / drain pattern LSD1 and may be electrically connected to the lower source / drain pattern LSD1. For example, the lower source / drain contact bCA may be electrically connected to the lower source / drain pattern LSD1 by penetrating the active pattern AP.

[0148] The connecting portion CM may be located below the lower source / drain contact bCA and the through-hole 650. The connecting portion CM may extend in the first direction D1 to connect the lower source / drain contact bCA and the through-hole 650. Therefore, the lower source / drain contact bCA can be connected to the upper source / drain contact aCA through the connecting portion CM and the through-hole 650.

[0149] The connection portion CM may be located on the third direction D3 between the lower wiring structure M1b, the lower source / drain contact bCA, and the through via 650. A portion of the connection portion CM may be inserted into the gate dicing pattern 600. For example, a portion of the connection portion CM may be stacked along the third direction D3 with a portion of the gate dicing pattern 600. For example, a portion of the connection portion CM may be located beneath the gap-filling insulating layer 620 via the insulating liner 610 of the gate dicing pattern 600.

[0150] For example, the connecting portion CM may contact the first via portion 651, the second via portion 652, or both of the through via 650.

[0151] Additionally, the lower gate contact bCB may be located below the lower gate pattern LGE1 and may be electrically connected to the lower gate pattern LGE1. For example, the lower gate contact bCB may be electrically connected to the lower gate pattern LGE1 by penetrating the active pattern AP or the device isolation layer ST.

[0152] In some embodiments, each of the lower source / drain contact bCA and the lower gate contact bCB includes a conductive pattern and a blocking pattern surrounding the conductive pattern. For example, the conductive pattern may include a metal (including aluminum, copper, tungsten, molybdenum, or combinations thereof). The blocking pattern may cover the side and bottom surfaces of the conductive pattern. The blocking pattern may include a metal film or a metal nitride film. The metal film may include titanium, tantalum, tungsten, nickel, cobalt, platinum, or combinations thereof. The metal nitride film may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or combinations thereof.

[0153] The lower wiring structure M1b can be located below the lower source / drain contact bCA and the lower gate contact bCB.

[0154] The lower wiring structure M1b may include a lower interlayer insulation layer 410 and a lower metal layer 420 within the lower interlayer insulation layer 410.

[0155] The lower interlayer insulating layer 410 may be located below the lower source / drain contact bCA and the lower gate contact bCB, and may cover the lower end of the active pattern AP, the device isolation layer ST, the lower source / drain contact bCA, the lower gate contact bCB, the dummy source / drain pattern 155, the connection portion CM and the separation pattern 520.

[0156] The lower interlayer insulation layer 410 may include an insulating material (e.g., silicon oxide, silicon nitride, silicon oxynitride, low-k material, or a combination thereof).

[0157] The lower metal layer 420 may be placed within the lower interlayer insulating layer 410. The lower metal layer 420 may include a lower power supply wiring, a lower wiring, and a lower via. The lower via may be located on the lower power supply wiring and the lower wiring. The lower via may be inserted between the lower source / drain contact bCA, the lower gate contact bCB, and the connection portion CM and the lower power interconnect and the lower interconnect, respectively.

[0158] The lower power wiring and lower wiring of the lower metal layer 420 may include the same or different conductive materials. For example, the lower power wiring and lower wiring may include aluminum, copper, tungsten, molybdenum, cobalt, or combinations thereof.

[0159] Figure 5 This is a plan view showing a semiconductor device. Figure 6 It is along Figure 5 A sectional view taken by line C-C'.

[0160] Figure 5 and Figure 6 The examples shown in the text are similar to Figures 1 to 4 The examples shown are essentially the same, and therefore, except where the context otherwise indicates or suggests otherwise, Figures 1 to 4 The description also applies to Figure 5 and Figure 6 Additionally, the same reference numerals are used for the same components.

[0161] Reference Figure 5 and Figure 6 A portion of the separation pattern 520 may not be inserted into the gate dicing pattern 600. For example, the separation pattern 520 may not have a protrusion 522. The separation pattern 520 may not overlap with the gate dicing pattern 600 along the third direction D3. In addition, the separation pattern 520 may be spaced apart from the through via 650 in the first direction D1 and may not contact the through via 650.

[0162] Furthermore, the second via portion 652 and the third via portion 653 of the through via 650 may have the same length in the third direction D3. For example, the second via portion 652 and the third via portion 653 may extend from the lower end to the upper end of the through via 650 in the third direction D3. For example, the height of the lower end of the third via portion 653 may be substantially the same as the height of the lower end of the first via portion 651 and the lower end of the second via portion 652. The height of the upper end of the third via portion 653 may be substantially the same as the height of the upper end of the first via portion 651 and the upper end of the second via portion 652.

[0163] Therefore, when the substrate 100 is removed to form the lower source / drain contact bCA, the substrate 100 can be sufficiently removed until the dummy source / drain pattern 155 is exposed, while the through-via 650 is formed such that the boundary between the through-via 650 and the gap-filling insulating layer 620, when viewed in cross-section, does not have an uneven wavy shape in the third direction D3 while traveling along the second direction D2. In this case, the dispersion of the through-via 650 can be reduced to achieve a smoother contact between the through-via 650 and the lower source / drain contact bCA during the back-side wiring process.

[0164] Figure 7 This is a plan view showing a semiconductor device. Figure 8 It is along Figure 7 A sectional view taken by line C-C'. Figure 7 and Figure 8 The examples shown in the text are similar to Figures 1 to 4 The examples shown are essentially the same, so unless otherwise indicated or suggested by the context, Figures 1 to 4 The description also applies to Figure 7 and Figure 8 Additionally, the same reference numerals are used for the same components.

[0165] Reference Figure 7 and Figure 8 The separation pattern 520 may have a main body portion 521 and a protruding portion 522. The main body portion 521 is located next to the gate dicing pattern 600 in the first direction D1, and the protruding portion 522 protrudes from the main body portion 521 and is inserted into the gate dicing pattern 600 in the first direction D1.

[0166] At this time, the protruding portion 522 of the separation pattern 520 can be inserted into one side of the gate dicing pattern 600 in the first direction D1 and extend to the other side of the gate dicing pattern 600. Additionally, the through-hole 650 can extend in the second direction D2 to separate the protruding portion 522 on one side of the gate dicing pattern 600 from the protruding portion 522 on the other side of the gate dicing pattern 600. For example, the through-hole 650 can penetrate the protruding portion 522 of the separation pattern 520 in the second direction D2.

[0167] Meanwhile, the second via portion 652 and the third via portion 653 of the through via 650 can have the same length in the third direction D3. For example, the second via portion 652 and the third via portion 653 can extend from the lower end to the upper end of the through via 650 in the third direction D3. In other words, the height of the lower end of the third via portion 653 can be substantially the same as the height of the lower end of the first via portion 651 and the lower end of the second via portion 652. The height of the upper end of the third via portion 653 can be substantially the same as the height of the upper end of the first via portion 651 and the upper end of the second via portion 652.

[0168] Therefore, when removing the substrate 100 to form the lower source / drain contact bCA, the substrate 100 can be sufficiently removed until the dummy source / drain pattern 155 is exposed, while the through-via 650 is formed such that, when viewed in cross-section, the boundary between the through-via 650 and the gap-filling insulating layer 620 does not have an uneven wavy shape in the third direction D3 while traveling along the second direction D2. In this case, the distribution of the through-via 650 can be reduced to achieve a smoother contact between the through-via 650 and the lower source / drain contact bCA during the back-side wiring process.

[0169] Figure 9 This is a plan view showing a semiconductor device. Figure 10 It is along Figure 9 A sectional view taken by line C-C'. Figure 9 and Figure 10 The examples shown in the text are similar to Figures 1 to 4 The examples shown are essentially the same, so unless otherwise indicated or suggested by the context, Figures 1 to 4 The description also applies to Figure 9 and Figure 10 Additionally, the same reference numerals are used for the same components.

[0170] Reference Figure 9 and Figure 10 The through-hole 650 can contact the insulating liner 610 in the first direction D1, and the gap-filling insulating layer 620 can be located below the through-hole 650 in the third direction D3.

[0171] For example, the gap-filling insulating layer 620 is not located on either side of the through-via 650 in the first direction D1, and the through-via 650 may fill the interior of the gate diced pattern 600 in the first direction D1, excluding the insulating liner 610. In other words, the insulating liner 610 may be located between the through-via 650 and the separation pattern 520, and the gap-filling insulating layer 620 may not be located between the through-via 650 and the separation pattern 520. Additionally, the insulating liner 610 may be located between the through-via 650 and the gate pattern GE, and the gap-filling insulating layer 620 may not be located between the through-via 650 and the gate pattern GE.

[0172] The protruding portion 522 of the separation pattern 520 can be inserted into the gate cut pattern 600 and can be superimposed on a portion of the gate cut pattern 600 on the third direction D3, but the protruding portion 522 can pass through the insulating liner 610 of the gate cut pattern 600 and be located on the through via 650, and can not contact the gap filling insulating layer 620.

[0173] Meanwhile, the second via portion 652 and the third via portion 653 of the through via 650 can have the same length in the third direction D3. For example, the second via portion 652 and the third via portion 653 can extend from the lower end to the upper end of the through via 650 in the third direction D3. In other words, the height of the lower end of the third via portion 653 can be substantially the same as the height of the lower end of the first via portion 651 and the lower end of the second via portion 652. The height of the upper end of the third via portion 653 can be substantially the same as the height of the upper end of the first via portion 651 and the upper end of the second via portion 652.

[0174] Therefore, when removing the substrate 100 to form the lower source / drain contact bCA, the substrate 100 can be sufficiently removed until the dummy source / drain pattern 155 is exposed, while the through-via 650 is formed such that, when viewed in cross-section, the boundary between the through-via 650 and the gap-filling insulating layer 620 does not have an uneven wavy shape in the third direction D3 while traveling along the second direction D2. In this case, the distribution of the through-via 650 can be reduced to achieve a smoother contact between the through-via 650 and the lower source / drain contact bCA during the back-side wiring process.

[0175] Figure 11 This is a plan view showing an example of a semiconductor device. Figure 12 It is along Figure 11 A sectional view taken from lines A-A' and D-D'. Figure 13 It is along Figure 11 A sectional view taken by line C-C'. Figures 11 to 13 The examples shown in the text are similar to Figures 1 to 4The examples shown are essentially the same, so except where the context otherwise indicates or suggests otherwise. Figures 1 to 4 The description also applies to Figures 11 to 13 Additionally, the same reference numerals are used for the same components.

[0176] Reference Figures 11 to 13 The gate dicing pattern 600 includes a gap-filling insulating layer 620 containing silicon oxide and an insulating liner 610 containing silicon nitride, and the separation pattern 520 may include silicon oxide.

[0177] In this case, when the gate cut pattern 600 is etched to form the through via 650, even though the protrusions 522 of the separation pattern 520 are etched together, the etching is performed uniformly because the etching rates of the gap-filling insulating layer 620 of the gate cut pattern 600 and the separation pattern 520 are similar, and thus the through via 650 can be formed, such that when in the cross-section (e.g., Figure 12 When observed in the diagram, the boundary between the through-via 650 and the gap-filling insulating layer 620 does not have an uneven wavy shape in the third direction D3 while traveling along the second direction D2. In this case, the distribution of the through-via 650 can be reduced to achieve a smoother contact between the through-via 650 and the lower source / drain contact bCA during the back-side wiring process.

[0178] A portion of the separation pattern 520 may extend in the first direction D1 and be inserted into the gate dicing pattern 600. For example, the separation pattern 520 may have a main body portion 521 and a protruding portion 522, and the protruding portion 522 of the separation pattern 520 may be inserted into the gate dicing pattern 600.

[0179] The second via portion 652 and the third via portion 653 of the through via 650 may have the same length in the third direction D3. For example, the second via portion 652 and the third via portion 653 may extend from the lower end to the upper end of the through via 650 in the third direction D3. In other words, the height of the lower end of the third via portion 653 may be substantially the same as the height of the lower end of the first via portion 651 and the lower end of the second via portion 652. The height of the upper end of the third via portion 653 may be substantially the same as the height of the upper end of the first via portion 651 and the upper end of the second via portion 652.

[0180] Next, we will refer to Figures 14 to 48 A method for manufacturing a semiconductor device is described. Additionally, the above description... Figures 1 to 4 For reference.

[0181] Figure 14 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 15It is along Figure 1 The sectional view taken along line C-C'. At this point, along... Figure 1 The cross-sectional view taken by the B-B' line can be compared with Figure 15 The same, and therefore it is omitted.

[0182] Reference Figure 14 and Figure 15 The first sacrificial layer SAL1 and the second sacrificial layer SAL2, as well as the first active layer ACL1 and the second active layer ACL2, can be alternately stacked on the substrate 100.

[0183] For example, a first sacrificial layer SAL1, a first active layer ACL1, a first sacrificial layer SAL1, a first active layer ACL1, and a first sacrificial layer SAL1 can be sequentially stacked on substrate 100. An intermediate insulating structure DSP and a dummy channel pattern SDL can be stacked on the first sacrificial layer SAL1. A second sacrificial layer SAL2, a second active layer ACL2, a second sacrificial layer SAL2, and a second active layer ACL2 can be sequentially stacked on the dummy channel pattern SDL.

[0184] The substrate 100 may be a semiconductor substrate, including silicon, germanium, silicon-germanium, etc., or a compound semiconductor substrate. As an example, the substrate 100 may be a silicon substrate.

[0185] The first sacrificial layer SAL1 and the second sacrificial layer SAL2 may comprise one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe). For example, the first active layer ACL1 and the second active layer ACL2 may comprise silicon (Si).

[0186] The stacked first sacrificial layer SAL1 and second sacrificial layer SAL2, first active layer ACL1 and second active layer ACL2, intermediate insulating structure DSP and dummy channel pattern SDL can be patterned to form a stacked pattern STP.

[0187] For example, a stacked pattern STP can be formed by forming a hard mask pattern on the top second active layer ACL2 and using the hard mask pattern as an etch mask to etch the stacked layers on the substrate 100. While the stacked pattern STP is being formed, the upper end of the substrate 100 can be patterned to form a trench TR defining the active pattern AP. The stacked pattern STP may have a strip shape extending in the second direction D2.

[0188] The stacked pattern STP may include: a lower stacked pattern STP1 above the active pattern AP and an upper stacked pattern STP2 on the lower stacked pattern STP1. The lower stacked pattern STP1 may include an alternately stacked first sacrificial layer SAL1 and a first active layer ACL1. The upper stacked pattern STP2 may include an alternately stacked second sacrificial layer SAL2 and a second active layer ACL2.

[0189] On substrate 100, a device isolation layer ST that fills trenches can be formed. For example, an insulating layer covering the active pattern AP and the stacked pattern STP can be formed over the entire surface of substrate 100. The insulating layer can be recessed until the stacked pattern STP is exposed, thereby forming the device isolation layer ST.

[0190] Figure 16 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 17 It is along Figure 1 The sectional view taken along line C-C'. At this point, along... Figure 1 The cross-sectional view taken by the B-B' line can be compared with Figure 17 The same, and therefore it is omitted.

[0191] Reference Figure 16 and Figure 17 Multiple sacrificial pattern PPs can be formed through a stacked pattern STP. Each sacrificial pattern PP can be formed in a linear shape extending in a first direction D1. For example, the sacrificial pattern PPs can be formed by forming a sacrificial film on the stacked pattern STP, forming a hard mask pattern on the sacrificial film, and patterning the sacrificial film using the hard mask pattern as an etch mask. The sacrificial film may include amorphous silicon or polycrystalline silicon.

[0192] Additionally, a pair of gate spacers GS can be formed on the two side surfaces of the sacrificial pattern PP in the second direction D2, and a preliminary capping layer MP can be formed on the sacrificial pattern PP.

[0193] Figure 18 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 19 It is along Figure 1 The sectional view taken by line B-B'. Figure 20 It is along Figure 1 A sectional view taken by line C-C'.

[0194] Reference Figures 18 to 20 Using a sacrificial pattern PP, a preliminary capping layer MP, and a gate spacer GS as an etching mask, at least a portion of the stacked pattern STP and the active pattern AP are etched to form a recess, and a dummy source / drain pattern 155, a lower source / drain pattern LSD1, a first interlayer stop film ESL1, a first interlayer insulating layer 110, an upper source / drain pattern USD1, a second interlayer stop film ESL2, and a second interlayer insulating layer 120 are sequentially formed within the recess.

[0195] Figure 21 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 22 It is along Figure 1 The sectional view taken by line B-B'. Figure 23 It is along Figure 1 A sectional view taken by line C-C'.

[0196] Reference Figures 21 to 23 The initial capping layer MP can be removed to expose the sacrificial pattern PP, and the first recess RS1 can be formed by removing the exposed sacrificial pattern PP.

[0197] For example, to remove the sacrificial pattern PP, wet etching can be used with an etchant that selectively etches polysilicon. By removing the sacrificial pattern PP, the first sacrificial layer SAL1 and the second sacrificial layer SAL2 can be exposed.

[0198] Next, an etching process is performed to selectively etch the exposed first sacrificial layer SAL1 and second sacrificial layer SAL2, such that only the first sacrificial layer SAL1 and the second sacrificial layer SAL2 can be removed while keeping the first semiconductor pattern SP1 and the second semiconductor pattern SP2 intact.

[0199] For example, the etching process of the first sacrificial layer SAL1 and the second sacrificial layer SAL2 can achieve a high etching rate for silicon-germanium. For example, the etching process can achieve a high etching rate for silicon-germanium with a germanium concentration greater than 10 at% (atomic percentage).

[0200] Figure 24 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 25 It is along Figure 1 The sectional view taken by line B-B'. Figure 26 It is along Figure 1 A sectional view taken by line C-C'.

[0201] Reference Figures 24 to 26 The gate pattern GE can be formed in the region where the sacrificial pattern PP, the first sacrificial layer SAL1, and the second sacrificial layer SAL2 are removed.

[0202] First, a gate insulating film GI can be conformally formed in the region where the sacrificial pattern PP, the first sacrificial layer SAL1, and the second sacrificial layer SAL2 are removed.

[0203] Next, a gate pattern GE can be formed on the gate insulating film GI. The gate pattern GE can be formed by forming a lower gate pattern LGE1, including a first sub-gate portion PO1 to a third sub-gate portion PO3, between the first semiconductor patterns SP1, and an upper gate pattern UGE1, including a fourth sub-gate portion PO4 to a sixth sub-gate portion PO6, between the second semiconductor patterns SP2.

[0204] The gate pattern GE can be recessed, reducing its height. A gate cap pattern GP can be formed on the recessed gate pattern GE. A planarization process can be performed on the gate cap pattern GP so that the upper surface of the gate cap pattern GP is coplanar with the upper surface of the second interlayer insulating layer 120.

[0205] Figure 27 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 28 It is along Figure 1 The sectional view taken by line B-B'. Figure 29 It is along Figure 1 A sectional view taken by line C-C'.

[0206] Reference Figures 27 to 29 A gate cutting pattern 600 can be formed, which extends through the gate pattern GE in the second direction D2 to cut the connection of the gate pattern GE.

[0207] For example, the gate cut pattern 600 can be formed by forming a hard mask pattern on the gate cover pattern GP, ​​using the hard mask pattern as an etching mask to etch the gate pattern GE, conformally applying an insulating liner 610 to the area where the gate pattern GE has been removed, and then filling the space between the insulating liner 610 with a gap-filling insulating layer 620.

[0208] Figure 30 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 31 It is along Figure 1 The sectional view taken by line B-B'. Figure 32 and Figure 33 It is along Figure 1 A sectional view taken by line C-C'.

[0209] Reference Figures 30 to 33 A fourth recess RS4 is formed at the location where the separation structure 510 will be formed, and a fifth recess RS5 is formed at the location where the separation pattern 520 will be formed.

[0210] For example, a hard mask pattern HM is formed on the gate cover pattern GP, ​​and the gate cover pattern GP is etched using the hard mask pattern HM as an etch mask to form a second recess RS2 to expose the gate pattern GE. At this time, spacers SPC can be formed on the two sidewalls of the second recess RS2 in the first direction D1.

[0211] Next, the gate pattern GE exposed by the second recess RS2 is removed, and the upper channel pattern UCH1 and lower channel pattern LCH1 exposed along with the gate pattern GE are also removed. In this process, other gate patterns GE located below the hard mask pattern HM can be removed without the spacer SPC, the gap-filling insulating layer 620 of the gate cut pattern 600 located below the spacer SPC can be partially etched to form the third recess RS3, and a portion of the active pattern AP and the device isolation layer ST located below the lower channel pattern LCH1 can be removed to form the fifth recess RS5.

[0212] However, at this point, the active pattern AP and device isolation layer ST within the fifth recess RS5 are not completely removed, and at least a portion of the active pattern AP and device isolation layer ST is retained. Therefore, the height of the lower end of the separation pattern 520 subsequently formed in the fifth recess RS5 can be higher than the height of the lower end of the dummy source / drain pattern 155, and when the substrate 100 is removed to form the lower source / drain contact bCA, the substrate 100 is prevented from being insufficiently removed due to being blocked by the separation pattern 520, and the substrate 100 can be sufficiently removed until the dummy source / drain pattern 155 is exposed.

[0213] Figure 34 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 35 It is along Figure 1 The sectional view taken by line B-B'. Figure 36 It is along Figure 1 A sectional view taken by line C-C'.

[0214] Reference Figures 34 to 36 A separation structure 510 is formed in the fourth recess RS4, and a separation pattern 520 is formed in the third recess RS3 and the fifth recess RS5.

[0215] For example, the separation structure 510 and the separation pattern 520 can be formed by filling each of the third recess RS3 to the fifth recess RS5 with insulating material and planarizing the insulating material until the hard mask pattern HM is exposed. The planarization of the insulating material can be performed using an etch-back process or a chemical mechanical polishing (CMP) process.

[0216] At this point, the main body portion 521 of the separation pattern 520 can be formed within the fifth recess RS5, and the protruding portion 522 of the separation pattern 520 can be formed within the third recess RS3. The protruding portion 522 of the separation pattern 520 can be located on the gap-filling insulating layer 620. If the separation pattern 520 and the spacer SPC are made of the same material, the boundary between the separation pattern 520 and the spacer SPC may not be identifiable. Subsequently, the spacer SPC and the hard mask pattern HM can be removed.

[0217] Figure 37 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 38 It is along Figure 1 The sectional view taken by line B-B'. Figure 39 It is along Figure 1 A sectional view taken by line C-C'.

[0218] Reference Figures 37 to 39 An insulating layer 620 is etched at the location where the through-hole 650 will be formed to fill the gaps of the gate cut pattern 600, thereby forming the sixth recess RS6 and the seventh recess RS7.

[0219] For example, a hard mask pattern is formed on the gate cover pattern GP, ​​and the hard mask pattern is used as an etching mask to etch the gap-filling insulating layer 620 of the gate cut pattern 600.

[0220] At this time, when the etch gap fills the insulating layer 620, at the location where the protrusion 522 of the separation pattern 520 is not inserted, relatively more etching is performed, resulting in the formation of a seventh recess RS7 with a relatively deep depth in the third direction D3. At the location where the protrusion 522 of the separation pattern 520 is inserted, since a portion of the protrusion 522 must be etched together with the gap fill insulating layer 620, relatively less etching is performed, resulting in the formation of a sixth recess RS6 with a relatively shallow depth in the third direction D3. An insertion portion 620a can be formed in the gap fill insulating layer 620 below the sixth recess RS6.

[0221] Figure 40 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 41 It is along Figure 1 The sectional view taken by line B-B'. Figure 42 It is along Figure 1 A sectional view taken by line C-C'.

[0222] Reference Figures 40 to 42 Through-holes 650 are formed in the sixth recess RS6 and the seventh recess RS7.

[0223] For example, a through-hole 650 can be formed by filling each of the sixth recess RS6 and the seventh recess RS7 with metal. At this time, a first through-hole portion 651 and a second through-hole portion 652 of the through-hole 650 are formed in the seventh recess RS7, and a third through-hole portion 653 is formed in the sixth recess RS6.

[0224] Figure 43 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 44 It is along Figure 1 The sectional view taken by line B-B'. Figure 45 It is along Figure 1 A sectional view taken by line C-C'.

[0225] Reference Figures 43 to 45 This forms the upper source / drain contact aCA to connect to the upper source / drain pattern USD1.

[0226] For example, a hard mask pattern is formed on the second interlayer insulating layer 120, and the hard mask pattern is used as an etching mask to pattern the second interlayer insulating layer 120, such that the second interlayer insulating layer 120 penetrates in the third direction D3 to form a contact hole at the upper end of the upper source / drain pattern USD1. For example, the patterning can be performed using dry etching.

[0227] By filling the contact holes with metal, an upper source / drain contact aCA can be formed that is connected to the upper source / drain pattern USD1.

[0228] Figure 46 It is along Figure 1 A sectional view taken from lines A-A' and D-D'. Figure 47 It is along Figure 1 The sectional view taken by line B-B'. Figure 48 It is along Figure 1 A sectional view taken by line C-C'.

[0229] Reference Figures 46 to 48 First, remove the substrate 100.

[0230] For example, the substrate 100 can be removed by performing an etching process. The etching process can be performed by, for example, a wet etching method, but is not limited thereto.

[0231] At this time, since the height of the lower end of the separation pattern 520 is higher than the height of the lower end of the dummy source / drain pattern 155, the substrate 100 is prevented from being insufficiently removed by being blocked by the separation pattern 520, and the substrate 100 can be sufficiently removed until the dummy source / drain pattern 155 is exposed.

[0232] In some implementations, when the active pattern AP includes a semiconductor material (such as silicon), the silicon can be removed and replaced with silicon oxide.

[0233] Next, a lower source / drain contact bCA connected to the lower source / drain pattern LSD1 is formed, and a lower gate contact bCB connected to the lower gate pattern LGE1 connected to the gate pattern GE is formed.

[0234] For example, a portion of the dummy source / drain pattern 155 can be removed to form a contact hole, through which the lower source / drain pattern LSD1 is exposed. Next, the lower source / drain contact bCA is formed by filling the contact hole and electrically connecting it to the lower source / drain pattern LSD1.

[0235] Next, a patterning process can be performed to remove a portion of the device isolation layer ST or the active pattern AP, thereby forming a contact hole through which the lower gate pattern LGE1 of the gate pattern GE is exposed. At this point, the contact hole can penetrate the active pattern AP or the device isolation layer ST. Next, a lower gate contact bCB is formed to fill the contact hole and electrically connect to the lower gate pattern LGE1 of the gate pattern GE.

[0236] Next, a connection portion CM can be formed extending from below the lower source / drain contact bCA to below the through-hole 650. After the patterning process, the connection portion CM can be filled with metal to form the connection portion CM connecting the lower source / drain contact bCA and the through-hole 650.

[0237] The lower source / drain contact bCA, lower gate contact bCB, and connection portion CM have been described above using separate processes. However, this disclosure is not limited to this, and the lower source / drain contact bCA, lower gate contact bCB, and connection portion CM can be formed simultaneously, or the lower gate contact bCB can be formed first, followed by the lower source / drain contact bCA and connection portion CM.

[0238] Refer again Figures 1 to 4 A lower wiring structure M1b can be formed, including a lower metal layer 420 and a lower interlayer insulating layer 410 covering the lower metal layer 420. The lower metal layer 420 is electrically connected to the lower source / drain contact bCA, the lower gate contact bCB and the connection portion CM at the lower end of the active pattern AP and the device isolation layer ST.

[0239] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims. Specific features described in the context of individual embodiments (e.g., the presence / configuration of floating patterns) may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a specific combination, in some cases one or more features from the combination may be removed from the combination, and a combination may refer to a sub-combination or a variation of a sub-combination.

[0240] Although this disclosure has been described with reference to various examples, it should be understood that the disclosure is not limited to those examples, but rather is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the disclosure.

Claims

1. A semiconductor device, comprising: An active pattern extends in a second direction different from the first direction, wherein the first and second directions are in a common transverse plane; The lower channel pattern and the lower source / drain pattern are arranged on the active pattern and are arranged alternately in the second direction; The upper groove pattern is above the lower groove pattern; The upper source / drain pattern is on the lower source / drain pattern; A gate pattern extends in a first direction and is disposed on a lower channel pattern and an upper channel pattern; A separate pattern is arranged in a second direction between a lower source / drain pattern and another lower source / drain pattern, and between an upper source / drain pattern and another upper source / drain pattern; and A gate dicing pattern extends in a second direction through the gate pattern to separate portions of the gate pattern. In a third direction perpendicular to the first and second directions, the lower end of the separation pattern is higher than the lower end of the gate dicing pattern.

2. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: a dummy source / drain pattern, wherein the lower source / drain pattern is on the dummy source / drain pattern. The lower end of the separated pattern is higher than the lower end of the dummy source / drain pattern, and The lower end of the gate dicing pattern is either higher than or equal to the lower end of the dummy source / drain pattern.

3. The semiconductor device according to claim 2, wherein, The semiconductor device further includes a lower wiring structure, wherein the active pattern is on the lower wiring structure. The separation pattern is located on the active pattern, and the lower part of the separation pattern is spaced apart from the lower wiring structure. In this configuration, the lower end of the gate dicing pattern contacts the lower wiring structure, and In this configuration, the lower end of the dummy source / drain pattern contacts the lower wiring structure.

4. The semiconductor device according to claim 1, in, The gate dicing pattern is arranged between the gate pattern and the separation pattern in a first direction, and The separation pattern extends from the gate dicing pattern in a first direction to another gate dicing pattern spaced apart from the gate dicing pattern in the first direction.

5. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: a discrete structure having a longest dimension in a first direction, wherein the discrete structure extends over a plurality of portions of the active pattern spaced apart from each other in the first direction, and The separation structure is arranged adjacent to the lower source / drain pattern and the upper source / drain pattern on the lateral side in the second direction.

6. The semiconductor device according to claim 1, wherein, Separated patterns include: The main body portion is adjacent to the gate dicing pattern in the first direction; and The protruding portion extends from the main body portion into the gate dicing pattern in a first direction.

7. The semiconductor device according to claim 1, wherein, The semiconductor device further includes a through-via extending in the gate dicing pattern.

8. The semiconductor device according to claim 7, wherein, Through-holes include: The first via portion extends, in a third direction, from the lowest height of the through-hole to the highest height of the through-hole; and The second and third via portions are arranged adjacent to the first via portion on its lateral side in the first direction, and alternately arranged in the second direction. The third via portion is arranged in the first direction between the first via portion and the separation pattern. The second via portion extends from the lowest height of the through via to the highest height of the through via in a third direction, and The third via portion has a lower end that is between the lowest and highest heights of the via in the third direction, and extends to the highest height of the via in the third direction.

9. The semiconductor device according to claim 8, wherein, The upper height of the third via portion is the same as the upper height of the first via portion and the upper height of the second via portion, and The length of the third via portion in the third direction is shorter than the length of the first via portion and the second via portion in the third direction.

10. The semiconductor device according to claim 8, wherein, Gate dicing patterns include: The gap is filled with an insulating layer; and An insulating liner is provided on the opposite transverse side of the gap-filling insulating layer in the first direction.

11. The semiconductor device according to claim 10, in, The through-hole is adjacent to the insulating liner in the first direction, and The through-hole is located in the gap-filling insulating layer.

12. The semiconductor device according to claim 10, wherein, The gap-filling insulating layer includes silicon oxide. The insulating liner comprises silicon nitride, and The separation pattern includes silicon nitride.

13. The semiconductor device according to claim 10, wherein, The gap-filling insulation layer includes an insertion portion, wherein a third via portion is on the insertion portion, and wherein the insertion portion is arranged alternately with the second via portion in a second direction.

14. The semiconductor device according to claim 7, wherein, A portion of the separation pattern extends into the gate cut pattern and contacts the through-via.

15. The semiconductor device according to claim 7, wherein, Separated patterns include: The main body portion is adjacent to the gate dicing pattern in the first direction, and The protruding portion extends from the main body into the gate dicing pattern in the first direction. The protruding portion of the separation pattern protrudes into the first lateral side of the gate dicing pattern in a first direction and extends to the second lateral side of the gate dicing pattern opposite to the first lateral side. The through-hole extends in the second direction between the protrusion on the first lateral side of the gate dicing pattern and the protrusion on the second lateral side of the gate dicing pattern.

16. The semiconductor device according to claim 7, wherein, The semiconductor device further includes: Upper source / drain contacts are on the upper source / drain pattern and are electrically connected to the upper source / drain pattern; and Lower source / drain contacts, wherein the lower source / drain pattern is on the lower source / drain contacts and is electrically connected to the lower source / drain contacts. The upper source / drain contact and the lower source / drain contact are electrically connected to the through-hole.

17. The semiconductor device according to claim 16, wherein, The semiconductor device further includes: The connection portion includes a lower source / drain contact and a through-hole on the connection portion, which extends in a first direction to electrically connect the lower source / drain contact to the through-hole.

18. The semiconductor device according to claim 1, wherein, Gate dicing patterns include: The gap is filled with an insulating layer; and An insulating liner, on the opposite transverse side of the gap-filling insulating layer in the first direction, The gap-filling insulating layer includes silicon oxide. The insulating liner includes silicon nitride. The separation pattern includes silicon oxide, and The semiconductor device further includes: a through-via extending in a gate dicing pattern, wherein the through-via includes: a first via portion extending in a third direction from the lowest height of the through-via to the highest height of the through-via; and a second via portion and a third via portion arranged adjacent to the first via portion on a lateral side in a first direction and alternately arranged in a second direction. The third via portion is arranged in the first direction between the first via portion and the separation pattern, and The lower end of the third via is at the same height as the lower end of the second via.

19. A semiconductor device, comprising: An active pattern extends in a second direction different from the first direction, wherein the first and second directions are in a common transverse plane; The lower channel pattern and the lower source / drain pattern are arranged on the active pattern and are arranged alternately in the second direction; The upper groove pattern is above the lower groove pattern; The upper source / drain pattern is on the lower source / drain pattern; A gate pattern extends in a first direction and is disposed on a lower channel pattern and an upper channel pattern; A gate dicing pattern, extending in a second direction through the gate pattern to separate portions of the gate pattern; and A through-via is disposed in a gate dicing pattern, wherein the through-via includes: a first via portion extending from the lower end of the through-via to the upper end of the through-via in a third direction perpendicular to the first and second directions; and a second via portion and a third via portion disposed adjacent to the first via portion on the lateral side in the first direction and alternately disposed in the second direction. The lower end of the third via portion is higher in the third direction than the lower ends of the first via portion and the second via portion.

20. A semiconductor device, comprising: An active pattern extends in a second direction different from the first direction, wherein the first and second directions are in a common transverse plane; The lower channel pattern and the lower source / drain pattern are arranged on the active pattern and are arranged alternately in the second direction; The upper groove pattern is above the lower groove pattern; The upper source / drain pattern is on the lower source / drain pattern; A gate pattern extends in a first direction and is disposed on a lower channel pattern and an upper channel pattern; A separate pattern is arranged in a second direction between a lower source / drain pattern and another lower source / drain pattern, and between an upper source / drain pattern and another upper source / drain pattern; and A gate dicing pattern extends in a second direction through the gate pattern to separate portions of the gate pattern. In this case, a portion of the separation pattern protrudes into the gate dicing pattern in the first direction.

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