Electronic substrate and method for manufacturing same

Abstract

The invention discloses an electronic substrate and a manufacturing method thereof. The electronic substrate comprises a substrate, a transistor, a data line and a conductive element. The transistor is arranged on the substrate and comprises an active layer, a source electrode, a drain electrode and a gate electrode arranged on the active layer, the active layer is arranged between the source electrode and the drain electrode and overlaps with the gate electrode, and the active layer, the source electrode and the drain electrode are formed by the same semiconductor material layer. The data line is disposed on the substrate and electrically connected to the transistor. The conductive element is arranged on the data line and the semiconductor material layer and is electrically connected with the data line and the source electrode.

Description

Technical Field

[0001] This invention relates to an electronic substrate and a method for manufacturing the same, and more particularly to an electronic substrate containing transistors and a method for manufacturing the same. Background Technology

[0002] With technological advancements, displays have become ubiquitous electronic devices. A common driving method involves using active phase array circuits to drive corresponding pixels to display images. However, current methods for manufacturing array circuits require multiple photolithographic processes and corresponding photomasks, for example, more than nine photomasks. Furthermore, each photomask is expensive, thus limiting the manufacturing cost of displays. In addition, as display resolution increases, the number of signal lines in the array circuit needs to be increased; however, to maintain aperture ratio, the linewidth of the signal lines must be reduced, leading to a higher risk of signal line breakage. Summary of the Invention

[0003] The purpose of this invention is to provide an electronic substrate and a method for manufacturing the same, so as to reduce the number of photomasks and / or reduce the occurrence of broken data lines.

[0004] Some embodiments of the present invention provide an electronic substrate, which includes a substrate, a transistor, a data line, and conductive elements. The transistor is disposed on the substrate and includes an active layer, a source, a drain, and a gate disposed on the active layer. The active layer is disposed between the source and drain and overlaps with the gate, and the active layer, source, and drain are formed of the same semiconductor material layer. The data line is disposed on the substrate and electrically connected to the transistor. The conductive elements are disposed on the data line and the semiconductor material layer and electrically connected to the data line and the source.

[0005] Some embodiments of the present invention provide a method for manufacturing an electronic substrate. First, a substrate is provided, and a first metal layer is formed on the substrate, wherein the first metal layer includes data lines. Then, a first insulating layer is formed on the first metal layer, and a semiconductor material layer is formed on the first insulating layer. Subsequently, a second insulating layer is formed on the semiconductor material layer, and a second metal layer is formed on the second insulating layer, wherein the second metal layer includes scan lines, and the scan lines include gates. Then, a source and a drain are formed in the semiconductor material layer, wherein the semiconductor material layer includes an active layer, and the active layer is disposed between the source and the drain. In the cross-sectional direction of the electronic substrate, the gate overlaps the active layer, and the scan lines are disposed on the data lines.

[0006] In the electronic substrate and manufacturing method of the present invention, since the active layer, source and drain can be formed from the same semiconductor material layer, it is not necessary to form the source and drain through an additional metal layer, thereby helping to reduce the number of photomasks or manufacturing costs. Attached Figure Description

[0007] Figure 1 The diagram shown is a top view of the electronic substrate according to the first embodiment of the present invention.

[0008] Figure 2 The image shows along Figure 1 A cross-sectional view of section line A-A'.

[0009] Figure 3 The diagram shown is a top view of the electronic substrate according to the second embodiment of the present invention.

[0010] Figure 4 The image shows along Figure 3 A schematic cross-sectional view along section line B-B'.

[0011] Figure 5 The diagram shown is a top view of the electronic substrate according to the third embodiment of the present invention.

[0012] Figure 6 The image shows along Figure 5 A cross-sectional view along section line C-C'.

[0013] Figure 7 The diagram shown is a top view of the electronic substrate according to the fourth embodiment of the present invention.

[0014] Figure 8 The image shows along Figure 7 A schematic cross-sectional view of section line D-D'.

[0015] Figure 9 The diagram shown is a top view of an electronic substrate according to a variation of the fourth embodiment of the present invention.

[0016] Figure 10 The diagram shown is a top view of the electronic substrate according to the fifth embodiment of the present invention.

[0017] Figure 11 The diagram shown is a top view of the electronic substrate according to the sixth embodiment of the present invention.

[0018] Figure 12 The diagram shown is a cross-sectional view of the electronic substrate according to the seventh embodiment of the present invention.

[0019] Explanation of reference numerals in the attached figures: 1,2,3,4,4a,5,6,7 - Electronic substrate; 14,16,18 - Conductive element; AL - Active layer; CE - Common electrode; CL - Common line; D1 - First direction; D2 - Second direction; DE - Drain; DL - Data line; E1,E2 - Electrode; GE - Gate; IN1,IN11,IN12,IN2,IN21,IN22,IN3,IN4 - Insulating layer; M1 - First metal layer; M2 - Second metal layer; PE - Pixel electrode; S - Slit; SE - Source; SEM - Semiconductor material layer; SGL - Signal line; SL - Scan line; SLa - Strip; SP - Light-shielding pattern; Sub - Substrate; T - Transistor; TD - Top view; TH1,TH2,TH3,TH4,TH5,TH6,TH7,TH8,TH9,TH10,TH11,TH12 - Through hole; TL1,TL2 - Transparent conductive layer. Detailed Implementation

[0020] The present invention will be described in detail below with reference to specific embodiments and accompanying drawings. To make the invention clearer and easier to understand, the accompanying drawings are simplified schematic diagrams, and the elements therein may not be drawn to scale. Furthermore, the number and dimensions of the elements in the drawings are merely illustrative and are not intended to limit the scope of the invention.

[0021] Throughout this specification and the appended claims, certain terms are used to refer to specific elements. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same elements, and this invention is not intended to distinguish between elements that have the same function but different names.

[0022] In the specification and claims of this invention, the words "containing" and "including" are open-ended terms and should therefore be interpreted as "containing but not limited to...".

[0023] The use of ordinal numbers, such as "first" and "second," in the specification and claims of this invention to modify the elements of the claims does not imply or represent any prior ordinal number of the claimed element, nor does it represent the order of one claimed element with another, or the order of manufacturing methods. The use of such ordinal numbers is only to enable a claim element with a certain name to be clearly distinguished from another claim element with the same name.

[0024] The directional terms used in the following embodiments, such as up, down, left, right, front, or back, are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the invention.

[0025] Furthermore, when an element or membrane is referred to as being "on" or "above" another element or membrane, or as being "connected" to another element or membrane, it should be understood that the element or membrane is directly located on or directly connected to the other element or membrane, or that there may be other elements or membranes between them (in a non-direct case). Conversely, when an element or membrane is referred to as being "directly" "on" or "directly connected" to another element or membrane, it should be understood that there are no inserted elements or membranes between them.

[0026] The term "electrical connection" encompasses any direct or indirect means of electrical connection. An electrical connection between two components can be achieved through direct contact for transmitting electrical signals, with no other components between them. Alternatively, two components can be electrically connected by bridging between them via an intermediate component to transmit electrical signals. In this invention, "coupling" can also be referred to as "electrical connection."

[0027] In this invention, the terms “about,” “substantially,” or “approximately” generally represent falling within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

[0028] It should be understood that the following embodiments can be modified by replacing, recombining, or mixing features from multiple different embodiments to complete other embodiments without departing from the spirit of the invention. Features from different embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the invention or conflict with it.

[0029] In this invention, the length, thickness, width, height, distance and area can be measured by optical microscope (OM), electron microscope (e.g., scanning electron microscope (SEM)) or other methods, but are not limited thereto.

[0030] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It is understood that these terms, for example, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant art and this invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this invention.

[0031] The electronic substrate of this invention is applicable to any electronic device. The electronic device may include, for example, a display device, a light-emitting device, a sensing device, an antenna device, a touch device, a splicing device, or other suitable electronic devices, but is not limited thereto. The display device of this invention may include light-emitting diodes, color conversion layers, or other suitable materials, or combinations thereof, but is not limited thereto. The electronic device may be, for example, a bendable, stretchable, foldable, rollable, and / or flexible electronic device, but is not limited thereto. The display device may be applied, for example, to laptops, public displays, splicing displays, automotive displays, touch displays, televisions, monitors, smartphones, tablets, light source modules, lighting equipment, military equipment, or, for example, to electronic devices applied to the aforementioned products, but is not limited thereto. The display device may include, for example, liquid crystal molecules, light-emitting diodes, color conversion layers, other suitable display media, or combinations thereof, but is not limited thereto. The light-emitting diode (LED) may include, for example, organic light-emitting diodes (OLEDs), miniLEDs, microLEDs, or quantum dot LEDs (including QLEDs and QDLEDs), but is not limited thereto. The color conversion layer may include wavelength conversion materials and / or filter materials, and may include, for example, fluorescent materials, phosphorescent materials, quantum dot (QD) materials, other suitable materials, or combinations thereof, but is not limited thereto. The display device may include liquid crystal displays, electrophoretic displays, or other suitable devices, but is not limited thereto. The sensing device may be, for example, a sensing device for detecting changes in capacitance, light, heat, or ultrasound, but is not limited thereto. The sensing device may include, for example, biosensors, touch sensors, fingerprint sensors, other suitable sensors, or combinations of sensors of the above types. The antenna device may be, for example, a liquid crystal antenna or other types of antennas, but is not limited thereto. The splicing device may include, for example, a splicing display device or a splicing antenna device, but is not limited thereto. Furthermore, the shape of the electronic device can be, for example, rectangular, circular, polygonal, with curved edges, curved, or other suitable shapes. The electronic device may have peripheral systems such as drive systems, control systems, light source systems, and shelving systems. The electronic device may include electronic units, which can include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, and sensors.It should be noted that the electronic device of the present invention can be any combination of the above-described devices, but is not limited thereto. The electronic substrate described below uses an array substrate of a liquid crystal display panel as an example, but the present invention is not limited thereto. In some embodiments, the electronic substrate can also be used as an array substrate of a sensing panel or other devices.

[0032] Figure 1 The diagram shown is a top view of the electronic substrate according to the first embodiment of the present invention. Figure 2 The image shows along Figure 1 A sectional view along section line A-A'. (See diagram.) Figure 1 and Figure 2 As shown, the electronic substrate 1 includes a substrate Sub, a transistor T, a data line DL, and a conductive element 14, wherein the transistor T and the data line DL are disposed on the substrate Sub. The transistor T includes an active layer AL, a source SE, a drain DE, and a gate GE disposed on the active layer AL, wherein the active layer AL is disposed between the source SE and the drain DE and overlaps with the gate GE, and the active layer AL, the source SE, and the drain DE are formed from the same semiconductor material layer SEM. The data line DL is disposed on the substrate Sub and electrically connected to the transistor T. The conductive element 14 is disposed on the data line DL and the semiconductor material layer SEM and connects the data line DL and the source SE. Since the active layer AL, the source SE, and the drain DE can be formed from the same semiconductor material layer SEM, it is not necessary to form the source SE and the drain DE through an additional metal layer, thereby helping to reduce the number of photomasks or manufacturing costs.

[0033] Specifically, in this embodiment, the electronic substrate 1 may include a first metal layer M1, an insulating layer IN1, a semiconductor material layer SEM, an insulating layer IN2, a second metal layer M2, an insulating layer IN3, and a transparent conductive layer TL1, sequentially disposed on the substrate Sub. The substrate Sub may, for example, include a flexible substrate or a non-flexible substrate. The substrate Sub may, for example, include glass, ceramic, quartz, sapphire, acrylic, polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polyethersulfone (PES), polybutylene terephthalate (PBT), polyethylene naphthalate (PEN), or polyarylate (PAR), other suitable materials, or combinations thereof, but is not limited thereto.

[0034] exist Figure 1 and Figure 2In some embodiments, the first metal layer M1 may include a signal line extending along a first direction D1, but is not limited thereto. The signal line may be, for example, a data line DL; in other words, the data line DL may be formed by the first metal layer M1. In other embodiments, the data line DL may also be formed by other metal layers. The first metal layer M1 may, for example, be in direct contact with the upper surface of the substrate Sub. Since the substrate Sub may have a flat upper surface, forming the signal line directly on the upper surface of the substrate Sub helps to reduce or avoid uneven etching caused by topographic irregularities. This reduces line breakage and improves product yield even with a reduced signal line width.

[0035] The first metal layer M1 may further include a light-shielding pattern SP, disposed between the substrate Sub and the active layer AL and overlapping the active layer AL, to reduce the influence of light on the active layer AL, allowing the transistor T to operate normally. For example, the area of ​​the light-shielding pattern SP may be larger than the area of ​​the active layer AL or the overlapping area of ​​the semiconductor material layer SEM and the gate GE. The first metal layer M1 may be a single-layer or multi-layer structure. The first metal layer M1 may include, for example, molybdenum nitride, copper, other suitable materials, or combinations thereof. Since the data line DL and the light-shielding pattern SP can be formed from the same first metal layer M1, compared to the case where the data line DL and the light-shielding pattern SP are formed from different metal layers, this embodiment can save a photomask and a photolithographic process, thereby reducing manufacturing costs.

[0036] In some embodiments, the gate GE may be electrically connected to the light-shielding pattern SP, such that the light-shielding pattern SP can serve as another gate of the transistor T. In this case, the transistor T may be a double-gate type transistor, but is not limited thereto. In other embodiments, the light-shielding pattern SP may also provide a voltage different from the gate voltage for bias adjustment.

[0037] An insulating layer IN1 may be disposed on the first metal layer M1, which can be used to reduce the influence of moisture or gases (such as oxygen) on the SEM of the semiconductor material layer. For example, the insulating layer IN1 may include silicon oxide, silicon nitride, other suitable materials, or combinations thereof. Figure 2 In this structure, insulating layer IN1 may be a multilayer structure, such as a sequential stack of insulating layers IN11 and IN12. Insulating layers IN11 and IN12 may be made of the same or different materials. In some embodiments, the thickness of insulating layer IN11 may be, for example, less than the thickness of insulating layer IN12, wherein insulating layer IN11 may comprise silicon nitride and insulating layer IN12 may comprise silicon oxide, but is not limited thereto. The thickness of insulating layer IN11 may be approximately 300 to 800 angstroms. For example, 400 angstroms, 500 angstroms, 600 angstroms, or 700 angstroms, and the thickness of the IN12 insulating layer can be approximately 2000 to 3500 angstroms, for example, 2500 angstroms, 2700 angstroms, 3000 angstroms, or 3200 angstroms.

[0038] The electronic substrate 1 may also include a pixel electrode PE, electrically connected to a transistor T. Figure 1 In some embodiments, the pixel electrode PE may be formed of a semiconductor material layer SEM and connected to the drain electrode DE. In other words, the pixel electrode PE and the drain electrode DE may be different parts of the semiconductor material layer SEM that are connected to each other, but are not limited thereto. The semiconductor material layer SEM may include metal oxides or other suitable materials. The metal oxides herein may include indium gallium zinc oxide (IGZO) or other suitable metal oxide semiconductors. In some embodiments, the thickness of the semiconductor material layer SEM may be approximately 200–500 angstroms, for example, 250 angstroms, 300 angstroms, 350 angstroms, 400 angstroms, or 450 angstroms.

[0039] It should be noted that the pixel electrode PE, drain electrode DE, and source electrode SE may include dopants, thus possessing a certain conductivity and conductive properties. The active layer AL, however, does not contain dopants and possesses semiconductor properties, therefore it can serve as the channel layer for the transistor T. In other words, the conductivity of the pixel electrode PE, drain electrode DE, and source electrode SE can be greater than that of the active layer AL. Dopants may be, for example, substances generated during the formation of the insulating layer IN3, wherein the dopants may be, for example, hydrogen or other suitable conductive ions, but are not limited thereto. In some embodiments, the dopants may also be other charged ions, for example, implanted into the semiconductor material layer SEM via an ion implantation process, but are not limited thereto. Since the pixel electrode PE and the active layer AL can be formed from the same semiconductor material layer SEM, the photomask for separately forming the pixel electrode PE can be saved, thereby reducing manufacturing costs. Furthermore, when the semiconductor material layer SEM is formed of metal oxide, the semiconductor material layer SEM has a certain transmittance, allowing a portion of the semiconductor material layer SEM to serve as the pixel electrode PE, thus reducing the impact on the utilization rate of light generated by the backlight module. For example, the transmittance of the pixel electrode PE is greater than 80%, for example, 85%, 90%, 95%, 99%, or 99.9%. In this case, the electronic substrate 1 can serve as the array substrate of the liquid crystal display panel.

[0040] The insulating layer IN2 can be disposed on the semiconductor material layer SEM and can serve as the gate insulating layer of transistor T. Figure 2In the embodiments described, the insulating layer IN2 may be a multilayer structure, but is not limited thereto. The insulating layer IN2 may, for example, include an insulating layer IN21 and an insulating layer IN22, sequentially disposed on a semiconductor material layer SEM. The density of the insulating layer IN21 may be greater than the density of the insulating layer IN22. By forming the insulating layers IN21 and IN22 separately, the start-up voltage of the transistor T can be adjusted. The insulating layers IN21 and IN22 may, for example, include silicon oxide or other suitable insulating materials. The total thickness of the insulating layers IN21 and IN22 may be approximately 1000–2000 angstroms, for example, 1100 angstroms, 1300 angstroms, 1500 angstroms, 1700 angstroms, or 1900 angstroms.

[0041] A second metal layer M2 may be disposed on the insulating layer IN2, and the second metal layer M2 may include a gate GE. In a cross-sectional view of the electronic substrate 1, the gate GE overlaps the active layer AL. Figure 2 In this embodiment, the gate GE may be formed by a second metal layer M2. The second metal layer M2 may also include a scan line SL, and a portion of the scan line SL may serve as the gate GE. In other words, the scan line SL may include the gate GE. Furthermore, the scan line SL may include a strip-shaped portion SLa extending along a second direction D2 different from the first direction D1 and connected to the gate GE. The second direction D2 may be, for example, perpendicular to or not perpendicular to the first direction D1. The strip-shaped portion SLa of the scan line SL may span the data line DL and be disposed on the data line DL, but is not limited thereto.

[0042] exist Figure 2 In some embodiments, the second metal layer M2 may further include a conductive element 14 electrically connecting the data line DL and the source SE. For example, the insulating layer IN2 may have a via TH1, and the insulating layers IN2 and IN1 may have another via TH2, wherein the via TH1 overlaps the source SE, and the via TH2 overlaps the data line DL. Furthermore, the conductive element 14 may extend into the vias TH1 and TH2 to connect to the data line DL and the source SE. The second metal layer M2 may, for example, comprise a single-layer or multi-layer structure. A multi-layer structure may, for example, comprise titanium nitride, copper, copper alloys, other suitable materials, or combinations thereof. Copper alloys may, for example, comprise molybdenum, titanium, copper, magnesium, aluminum, chromium, other suitable materials, or combinations thereof. In some embodiments, the conductive element 14 may be formed from the second metal layer M2, while other conductive layers may be formed.

[0043] An insulating layer IN3 may be disposed on the second metal layer M2. In one embodiment, the insulating layer IN3 may, for example, have a flat upper surface to facilitate the formation of a transparent conductive layer TL1 thereon. The insulating layer IN3 may, for example, comprise an inorganic material, an organic material, or a combination thereof. The inorganic material may, for example, comprise silicon nitride or other suitable materials. The thickness of the insulating layer IN3 may be approximately 2000 to 3000 angstroms, for example, 2300 angstroms, 2500 angstroms, or 2700 angstroms.

[0044] exist Figure 2 In this embodiment, the transparent conductive layer TL1 may include a common electrode CE disposed on the insulating layer IN3, and the common electrode CE overlaps with the pixel electrode PE in the top view direction TD of the electronic substrate 1. The common electrode CE may have a plurality of slits S arranged sequentially along a direction. The slits S may be arranged, for example, along a second direction D2, but are not limited thereto. Through the structure of the slits S, the electric field between the pixel electrode PE and the common electrode CE can drive the liquid crystal molecules located on the electronic substrate 1 to rotate, thereby presenting the desired grayscale value.

[0045] In some embodiments, the first metal layer M1, the second metal layer M2, or the transparent conductive layer TL1 may further include a common line electrically connected to a common electrode CE for transmitting a common voltage signal, but are not limited thereto. For example, when the first metal layer M1 includes a common line, the structure of the common line can be referred to... Figure 9 or Figure 10 When the second metal layer M2 includes a common line, the structure of the common line can be referenced. Figure 5 or Figure 7 However, it is not limited to this.

[0046] Although Figure 1 , Figure 2 The accompanying figures below show the structure corresponding to a single pixel or subpixel, that is, a data line DL, a scan line SL, a transistor T, and a pixel electrode PE. However, the electronic substrate of the present invention is not limited thereto and may also include multiple data lines DL, multiple scan lines SL, multiple transistors T, and multiple pixel electrodes PE.

[0047] The present invention will further describe in detail the method for manufacturing the electronic substrate 1 in this embodiment. For example... Figure 1 and Figure 2 As shown, a method for manufacturing an electronic substrate 1 may include providing a substrate Sub; forming a first metal layer M1 on the substrate Sub; forming an insulating layer IN1 on the first metal layer M1; forming a semiconductor material layer SEM on the insulating layer IN1; forming an insulating layer IN2 on the semiconductor material layer SEM; forming a second metal layer M2 on the insulating layer IN2; and forming a source electrode SE and a drain electrode DE in the semiconductor material layer SEM.

[0048] Specifically, the formation of the first metal layer M1 may include forming a metal material over the entire substrate Sub, and then performing a first photolithography process with a first photomask to pattern the metal material into the first metal layer M1. The formation of the metal material may include, for example, a deposition process or other suitable processes. In this embodiment, the first metal layer M1 may be formed directly on the upper surface of the substrate Sub. This method helps to reduce line breaks and improve product yield when the linewidth of the signal lines (e.g., data lines DL) in the first metal layer M1 is reduced.

[0049] After the first metal layer M1 is formed, an insulating layer IN1 can be formed on the substrate Sub and the first metal layer M1. The formation of the insulating layer IN1 may include, for example, performing one or more deposition processes or other suitable processes. Deposition processes may include, for example, chemical vapor deposition, physical vapor deposition, other suitable deposition processes, or combinations thereof. Figure 2 In some embodiments, the step of forming insulating layer IN1 may include sequentially forming insulating layer IN11 and insulating layer IN12, but is not limited thereto.

[0050] Then, a semiconductor material layer SEM is formed on the insulating layer IN1. The method for forming the semiconductor material layer SEM may include forming a semiconductor material over the entire insulating layer IN1, and then performing a second photolithography process using a second photomask to pattern the semiconductor material into a semiconductor material layer SEM. At this point, the semiconductor material layer SEM exhibits semiconductor properties but not conductor properties.

[0051] After forming the semiconductor material layer SEM, an insulating layer IN2 can be formed on the semiconductor material layer SEM and the insulating layer IN1. Figure 2 In this embodiment, the step of forming insulating layer IN2 may include sequentially forming insulating layer IN21 and insulating layer IN22. It should be noted that the step of forming insulating layer IN21 may be slower than the step of forming insulating layer IN22, so that the step of forming insulating layer IN21 can be used to form the portion of insulating layer IN2 with a higher dielectric constant, while the step of forming insulating layer IN22 can be used to shorten the time of forming insulating layer IN2, thereby forming an insulating layer IN2 with a certain thickness. The steps of forming insulating layer IN21 and forming insulating layer IN22 may include performing a deposition process or other suitable processes.

[0052] It should be noted that hydrogen is generated during the formation of insulating layers IN21 and IN22, thus the semiconductor material layer SEM is doped with hydrogen ions during this process, giving it conductive properties. To maintain the semiconductor properties of the semiconductor material layer SEM before the formation of the source (SE) and drain (DE), the steps for forming insulating layers IN21 and IN22 may each include an annealing process or other thermal processes after the deposition process to remove hydrogen ions from the semiconductor material layer SEM.

[0053] Between the step of forming the insulating layer IN2 and the step of forming the second metal layer M2, a third photomask can be used to perform a third photolithography process to form a through hole TH1 in the insulating layer IN2 and a through hole TH2 in the insulating layers IN2 and IN1.

[0054] Next, the formation of the second metal layer M2 may involve forming a metal material over the insulating layer IN2, followed by a fourth photolithography process using a fourth photomask to pattern the metal material into the second metal layer M2. Since vias TH1 and TH2 are formed before the formation of the second metal layer M2, the conductive elements 14 of the second metal layer M2 can be formed simultaneously in both vias TH1 and TH2, thereby achieving an electrical connection between the data line DL and the source SE of the transistor T. Because the method of forming the second metal layer M2 is similar to or the same as the method of forming the first metal layer M1, it will not be described in detail here.

[0055] After forming the second metal layer M2, the source (SE) and drain (DE) can be formed in the semiconductor material layer SEM. Figure 2 In some embodiments, the steps of forming the source (SE) and drain (DE) may include forming an insulating layer (IN3) on the second metal layer (M2) and the insulating layer (IN2). The insulating layer (IN3) may be formed using a deposition process or other suitable process. Since the step of forming the insulating layer (IN3) generates dopants, in this step, dopants may be simultaneously introduced into the portion of the semiconductor material layer (SEM) that does not overlap with the scan line (SL) to give it conductive properties, thereby forming the source (SE), drain (DE), and pixel electrode (PE) in the semiconductor material layer (SEM), but this invention is not limited thereto.

[0056] The dopant can be a substance used or generated in the step of forming the insulating layer IN3, or ions implanted through an ion implantation process. For example, when the insulating layer IN3 comprises silicon nitride, the precursors for forming the insulating layer IN3 may include silane and ammonia. Therefore, hydrogen is generated in the step of forming the insulating layer IN3 as a dopant, which enters the semiconductor material layer SEM to form the source SE, drain DE, and pixel electrode PE.

[0057] In addition, although the conductive element 14 overlaps with the semiconductor material layer SEM in the top view TD, making it difficult to directly introduce dopants, the metal atoms in the conductive element 14 will diffuse into the part where the semiconductor material layer SEM and the conductive element 14 overlap, or the dopants doped into the part adjacent to the semiconductor material layer SEM and the conductive element 14 will diffuse into the part where the semiconductor material layer SEM and the conductive element 14 overlap, thus exhibiting conductive properties.

[0058] After forming the insulating layer IN3, a fifth photolithography process can be performed using a fifth photomask to form vias in the insulating layer IN3, facilitating the electrical connection between the subsequently formed common electrode CE and the common line. The vias formed in the fifth photolithography process can penetrate the insulating layer depending on the film layer where the common line is formed. For example, when the first metal layer M1 includes the common line, the vias can penetrate the insulating layers IN1, IN2, and IN3. When the second metal layer M2 includes the common line, the vias can penetrate the insulating layer IN3.

[0059] Then, a transparent conductive layer TL1 is formed on the insulating layer IN3. The step of forming the transparent conductive layer TL1 may include forming a transparent conductive material over the insulating layer IN3, and then performing a sixth photolithography process using a sixth photomask to pattern the transparent conductive material into the transparent conductive layer TL1. The transparent conductive material of the transparent conductive layer TL1 may include indium tin oxide (ITO), indium zinc oxide (IZO), or other suitable materials.

[0060] As can be seen from the above, the method for manufacturing the electronic substrate 1 in this embodiment requires a total of 6 photomasks. Therefore, compared with the 9 photomasks in the prior art, the architecture of the electronic substrate 1 in this embodiment can significantly simplify the manufacturing steps and reduce the number of photomasks used, thereby reducing the manufacturing cost.

[0061] The electronic substrate and its manufacturing method of the present invention are not limited to the above embodiments and may have other embodiments. For the sake of simplicity, the same reference numerals will be used to label the same elements in other embodiments of the present invention as in the above embodiments. To clearly illustrate other embodiments, the differences between other embodiments and the above embodiments will be highlighted below, and repeated parts will not be described again.

[0062] Figure 3 The figure shown is a top view of the electronic substrate according to the second embodiment of the present invention. Figure 4 The image shows along Figure 3 A sectional view along section line B-B'. (See diagram.) Figure 3 and Figure 4 As shown, the electronic substrate 2 in this embodiment and Figure 1 and Figure 2The difference between the electronic substrate 1 and the electronic substrate 2 is that the electronic substrate 2 may further include an insulating layer IN4 and a transparent conductive layer TL2, and the pixel electrode PE and the conductive element 14 may be formed by the transparent conductive layer TL2. The common electrode CE may still be formed by the transparent conductive layer TL1, and the transparent conductive layer TL1 is disposed on the transparent conductive layer TL2. Specifically, the insulating layer IN4 is disposed between the second metal layer M2 and the insulating layer IN3, and the transparent conductive layer TL2 is disposed between the insulating layer IN4 and the insulating layer IN3. Furthermore, the insulating layers IN2 and IN4 may have a through-hole TH1 overlapping the source electrode SE and a through-hole TH3 overlapping the drain electrode DE, and the insulating layers IN1, IN2, and IN4 may have a through-hole TH2 overlapping the data line DL. The conductive element 14 may extend into the through-holes TH1 and TH2, thus electrically connecting the source electrode SE and the data line DL. The pixel electrode PE may extend into the through-hole TH3, thereby electrically connecting to the drain electrode. The transparent conductive layer TL2 may include the same or similar transparent conductive material as the transparent conductive layer TL1, such as indium tin oxide (ITO), indium zinc oxide (IZO) or other suitable materials.

[0063] exist Figure 3 In some embodiments, at least a portion of the data line DL may not extend along the first direction D1, but may form an angle of less than 90 degrees with the first direction D1, but is not limited thereto. In some embodiments, the data line DL may also extend along the first direction D1. In some embodiments, Figure 3 The extension direction of the data line DL can also be applied to any of the embodiments described above or below.

[0064] In the method for manufacturing the electronic substrate 2 in this embodiment, the step of forming the insulating layer IN4 can be performed after forming the second metal layer M2, and the method of forming the insulating layer IN4 can include a deposition process or other suitable processes. The insulating layer IN4 may, for example, include silicon oxide or other suitable materials. It should be noted that in this embodiment, the steps of forming the source SE and drain DE in the semiconductor material layer SEM can be performed simultaneously with the step of forming the insulating layer IN4, but are not limited thereto. Furthermore, the methods of forming the source SE and drain DE are the same as or similar to those in the above embodiments, and therefore will not be described in detail here. Figure 3 and Figure 4 In some embodiments, the steps of forming the source electrode SE and the drain electrode DE may not involve forming pixel electrodes, but are not limited to this.

[0065] After forming the insulating layer IN4, a third photolithography process can be performed using a third photomask to form vias TH1 and TH3 in the insulating layers IN4 and IN2, and via TH2 in the insulating layers IN4, IN2, and IN1. In this embodiment, via TH1 exposes the source electrode SE, via TH2 exposes the data line DL, and via TH3 exposes the drain electrode DE.

[0066] After forming vias TH1, TH2, and TH3, a transparent conductive layer TL2 can be formed on the insulating layer IN4. The transparent conductive layer TL2 can be formed by comprehensively forming a transparent conductive material layer on the insulating layer IN4, followed by a seventh photomask and a seventh photolithography process to pattern the transparent conductive material layer into pixel electrodes PE and conductive elements 14 that are separated from each other. The pixel electrodes PE can be electrically connected to the drain electrode DE through vias TH3, while the conductive elements 14 can be electrically connected to the source electrode SE and the data line DL through vias TH1 and TH2. Other parts of the electronic substrate 2 and other steps of the manufacturing method can be the same as described above. Figure 1 and Figure 2 The embodiments are as described above, so they will not be elaborated upon here.

[0067] Figure 5 The figure shown is a top view of the electronic substrate according to the third embodiment of the present invention. Figure 6 The image shows along Figure 5 A cross-sectional view along section line C-C'. (See diagram.) Figure 5 and Figure 6 As shown, the electronic substrate 3 in this embodiment and Figure 1 and Figure 2 The difference between the electronic substrate 1 and the common electrode 3 is that the common electrode CE of the electronic substrate 3 can be formed by a semiconductor material layer SEM, while the pixel electrode PE is not formed by a semiconductor material layer SEM. The common electrode CE can be separated from the drain electrode DE, the source electrode SE, and the active layer AL, thereby electrically isolating it from the drain electrode DE. Furthermore, the transparent conductive layer TL1 can include the pixel electrode PE, electrically connected to the drain electrode DE. For example, insulating layers IN2 and IN3 can have a through-hole TH3, and the pixel electrode PE can extend into the through-hole TH3, electrically connected to the drain electrode DE. In this embodiment, the pixel electrode PE can have multiple slits S, arranged sequentially along one direction, for example, along a second direction D2, but is not limited thereto. Through the structure of the slits S, the electric field between the common electrode CE and the pixel electrode PE can drive the liquid crystal molecules located on the electronic substrate 3 to rotate.

[0068] In this embodiment, the second metal layer M2 may further include a common line CL extending along the second direction D2. The insulating layer IN2 may have a through-hole TH4 overlapping the common electrode CE and the common line CL, such that the common line CL can extend into the through-hole TH4 and be electrically connected to the common electrode CE.

[0069] In the method for manufacturing the electronic substrate 3 in this embodiment, the step of forming the source electrode SE and the drain electrode DE may include forming a common electrode CE separated from the drain electrode DE in the semiconductor material layer SEM. Since the method of forming the common electrode CE is similar to or the same as... Figure 2 The method for forming the pixel electrode PE will not be elaborated here. Other parts of the electronic substrate 3 and other steps of the manufacturing process are the same as described above. Figure 1 and Figure 2 Implementation examples or Figure 3 and Figure 4 The embodiments are as described above, so they will not be elaborated upon here.

[0070] Figure 7 The figure shown is a top view of the electronic substrate according to the fourth embodiment of the present invention. Figure 8 The image shows along Figure 7 A cross-sectional view along section line D-D'. (See diagram.) Figure 7 and Figure 8 As shown, the electronic substrate 4 in this embodiment and Figure 5 and Figure 6 The difference between the electronic substrate 1 and the electronic substrate 4 is that the conductive elements of the electronic substrate 4 can all be formed by a transparent conductive layer TL1. Specifically, insulating layers IN2 and IN3 can have a via TH1 overlapping the source electrode SE, a via TH3 overlapping the drain electrode DE, and a via TH4 overlapping the common electrode CE. Insulating layers IN1, IN2, and IN3 can also have a via TH2 overlapping the data line DL. The transparent conductive layer TL1 can include conductive elements 14 and 16, wherein conductive element 14 can extend into vias TH1 and TH2 to electrically connect the source electrode SE to the data line DL, and conductive element 16 can extend into via TH4 to electrically connect to the common electrode CE.

[0071] exist Figure 7 In this embodiment, the common line CL can be formed by a second metal layer M2, and a through-hole TH5 can be provided thereon, so that the conductive element 16 can extend into the through-hole TH5 and be electrically connected to the common line CL, so that the common electrode CE can be electrically connected to the common line CL through the conductive element 16. For example, Figure 8 The insulating layer IN3 shown may have a through-hole TH5, but is not limited thereto. In some embodiments, the common line CL may also be formed of a first metal layer M1 or a transparent conductive layer TL1.

[0072] In the method for manufacturing the electronic substrate 4 in this embodiment, since conductive elements 14 and 16 can be formed by the transparent conductive layer TL1, through-holes TH1, TH2, TH3, TH4, and TH5 can be formed by a fifth photolithography process. In other words, a third photolithography process is unnecessary, thus reducing the number of manufacturing steps and the number of photomasks used can be reduced to five, thereby lowering manufacturing costs. Other parts of the electronic substrate 4 and other steps of the manufacturing method can be the same as described above. Figure 1 and Figure 2 Implementation examples Figure 3 and Figure 4 Implementation examples or Figure 5 and Figure 6 Examples of these embodiments are therefore not described in detail here. In some embodiments, Figure 7 and Figure 8 The conductive element formed by the transparent conductive layer TL1 can also be used Figure 1 and Figure 2 The conductive element 14 or Figure 3 and Figure 4 Conductive element 14.

[0073] Figure 9 The diagram shown is a top view of an electronic substrate according to a variation of the fourth embodiment of the present invention. Figure 9 As shown, the electronic substrate 4a of this modified embodiment and Figure 7 The difference in the electronic substrate 4 is that the common line CL in this variant embodiment can be formed by the first metal layer M1. Figure 9 In this case, the common line CL may extend, for example, along the first direction D1. The insulating layer between the first metal layer M1 and the transparent conductive layer TL1 (e.g., Figure 8 The insulating layers IN3, IN2, and IN1 shown may have through-holes TH5. Other portions of the electronic substrate 4a and other steps of the manufacturing method may be the same as those described above. Figure 7 and Figure 8 Examples of these embodiments are therefore not described in detail here. In some embodiments, Figure 9 The common line CL formed by the first metal layer M1 can also be applied to Figure 1 , Figure 3 or Figure 5 In the electronic substrate.

[0074] Figure 10 The diagram shown is a top view of the electronic substrate according to the fifth embodiment of the present invention. Figure 10 As shown, the electronic substrate 5 in this embodiment and Figure 5The difference in the electronic substrate 3 is that, in this embodiment, the scan line SL and the data line DL can be formed by the first metal layer M1 and the second metal layer M2, respectively. In this embodiment, the gate GE can be formed by the second metal layer M2 and is electrically connected to the data line DL through the via TH6. The common line CL and the light-shielding pattern SP can also be formed by the first metal layer M1. The insulating layer between the first metal layer M1 and the second metal layer M2 (e.g., Figure 6 The insulating layers IN1 and IN2 shown may have through-holes TH6. In one embodiment, the light-shielding pattern SP may be directly connected to the scan line SL, for example, so that the light-shielding pattern SP can serve as another gate of the transistor T, but is not limited thereto. In other embodiments, the light-shielding pattern SP may also be separated from the scan line SL.

[0075] exist Figure 10 In some embodiments, the electronic substrate 5 may not include the conductive element 14 and the via TH2, and the data line DL may be electrically connected to the source SE through the via TH1, but is not limited thereto. In some embodiments, the data line DL may also be electrically connected to the source SE through the conductive element. Other parts of the electronic substrate 5 and other steps of the manufacturing method may be the same as those described above. Figure 5 and Figure 6 Examples of these embodiments are therefore not described in detail here. In some embodiments, Figure 10 The structure of the scan line SL and data line DL can also be applied. Figure 1 or Figure 3 The scan line SL and the data line DL.

[0076] Figure 11 The diagram shown is a top view of the electronic substrate according to the sixth embodiment of the present invention. Figure 11 As shown, the electronic substrate 6 in this embodiment and Figure 10 The difference between the electronic substrate 5 and the electronic substrate 6 is that the conductive elements of the electronic substrate 6 can all be formed by a transparent conductive layer TL1. Specifically, the transparent conductive layer TL1 may include conductive elements 14, 16 and 18, wherein conductive element 14 can extend into vias TH1 and TH2 to electrically connect the source electrode SE to the data line DL, conductive element 16 can extend into vias TH4 and TH5 to electrically connect the common electrode CE to the common line CL, and conductive element 18 can extend into vias TH6 and TH7 to electrically connect the gate electrode GE to the scan line SL.

[0077] exist Figure 11 In the embodiments, the insulating layer between the semiconductor material layer and the transparent conductive layer TL1 (e.g., Figure 8 The insulating layers IN2 and IN3 shown may have through holes TH1, TH3 and TH4, and the insulating layer between the second metal layer M2 and the transparent conductive layer TL1 (e.g., Figure 8The insulating layer IN3 shown may have through holes TH2 and TH7, and the insulating layer between the first metal layer M1 and the transparent conductive layer TL1 (e.g., Figure 8 The insulating layers IN1, IN2 and IN3 shown may have through holes TH5 and TH6, but are not limited thereto.

[0078] In the method for manufacturing the electronic substrate 6 in this embodiment, since conductive elements 14, 16, and 18 can be formed from the transparent conductive layer TL1, through-holes TH1, TH2, TH3, TH4, TH5, TH6, and TH7 can be formed through a fifth photolithography process. In other words, a third photolithography process is unnecessary, thus reducing the number of manufacturing steps and saving the number of photomasks. Other parts of the electronic substrate 6 and other steps of the manufacturing method can be the same as... Figure 1 and Figure 2 Implementation examples Figure 3 and Figure 4 Implementation examples or Figure 5 and Figure 6 The embodiments are as described above, so they will not be elaborated upon here.

[0079] Figure 12 The diagram shown is a cross-sectional view of the electronic substrate according to the seventh embodiment of the present invention. Figure 12 As shown, the electronic substrate 7 in this embodiment and Figure 2 The difference in the electronic substrate 1 is that the first metal layer M1 may further include a signal line SGL, which is electrically insulated from the data line DL, so that the signal line SGL can be used to transmit a signal different from the data signal in the data line DL. For example, the signal line SGL may be a common line, a bias signal line, a sensing signal line, or other suitable signal line. For example, the signal line SGL may be a sensing signal line that transmits a light sensing signal or a touch sensing signal.

[0080] exist Figure 12 In this embodiment, the transparent conductive layer TL1 may further include an electrode E1 electrically connected to the signal line SGL. For example, the insulating layer IN1 may have a through-hole TH8, such that a portion of the insulating layer IN2 can be disposed within the through-hole TH8. The insulating layer IN2 may also have a through-hole TH9, exposing the signal line SGL, and the insulating layer IN3 may also have a through-hole TH10, overlapping the through-hole TH8, such that the electrode E1 can be disposed within the through-hole TH10 and the through-hole TH9, and in contact with the signal line SGL. In this embodiment, the aperture of the through-hole TH10 may be larger than the aperture of the through-hole TH9, and the through-hole TH9 may be located within the through-hole TH8, but is not limited thereto.

[0081] In some embodiments, the electronic substrate 7 may not include conductive elements 14, through holes TH1 and TH2, and the insulating layer IN1 may have through hole TH11, overlapping the data line DL, so that the source SE can be electrically connected to the data line DL through through hole TH11.

[0082] In some embodiments, the second metal layer M2 may further include an electrode E2, separated from the gate GE, and the electrode E2 may overlap with the pixel electrode PE. The insulating layer IN3 may also have a through-hole TH12, overlapping the electrode E2, and the common electrode CE may be electrically connected to the electrode E2 through the through-hole TH12, so that the electrode E2 and the pixel electrode PE may be coupled to form a storage capacitor.

[0083] In the method for manufacturing the electronic substrate 7 in this embodiment, since the signal line SGL is contained in the first metal layer M1, it can be formed by a first photomask and a first lithography process. Figure 2 The difference in this embodiment is that the step of forming the insulating layer IN1 may include performing an eighth lithography process with an eighth photomask to form vias TH8 and TH11 in the insulating layer IN1, and the step of forming the insulating layer IN2 may include performing a ninth lithography process with a ninth photomask to form via TH9 in the insulating layer IN2. Furthermore, since the electronic substrate 7 does not contain conductive elements, vias TH1 and TH2, the method of this embodiment can omit the third photomask and third lithography process described in the previous embodiment.

[0084] Furthermore, electrode E2 is contained within the second metal layer M2, and therefore can be formed using a fourth photomask and a fourth lithography process. Additionally, the vias TH10 and TH12 in the insulating layer IN3 can be formed using a fifth photomask and a fifth lithography process. Other parts of the electronic substrate 7 and other steps of the manufacturing method can be the same as described above. Figure 1 and Figure 2 The embodiments are as described above, so they will not be elaborated upon here.

[0085] In summary, in the electronic substrate of the present invention, since the signal lines can be formed by the first metal layer and directly disposed on the upper surface of the substrate, it helps to reduce or avoid uneven etching caused by uneven terrain. This reduces line breakage and improves product yield even with a reduced signal line width. Furthermore, in the method for manufacturing the electronic substrate of the present invention, since the data lines, light-shielding patterns, pixel electrodes, source electrodes, drain electrodes, scan lines, gate electrodes, common electrodes, and conductive elements can be formed by at least the first metal layer, a semiconductor material layer, a second metal layer, and a transparent conductive layer, the manufacturing steps are significantly simplified, and the number of photomasks used is reduced, thereby lowering manufacturing costs.

[0086] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An electronic substrate, characterized in that, include: One substrate; A transistor is disposed on the substrate, and the transistor includes an active layer, a source, a drain and a gate disposed on the active layer, wherein the active layer is disposed between the source and the drain and overlaps with the gate, and the active layer, the source and the drain are formed of the same semiconductor material layer. A data line is disposed on the substrate and electrically connected to the transistor; as well as A conductive element is disposed on the data line and the semiconductor material layer and electrically connected to the data line and the source electrode.

2. The electronic substrate as described in claim 1, characterized in that, The conductivity of the source and the drain is greater than that of the active layer.

3. The electronic substrate as described in claim 1, characterized in that, The semiconductor material layer includes metal oxides.

4. The electronic substrate as described in claim 1, characterized in that, The data line is formed of a first metal layer, the gate and the conductive element are formed of a second metal layer, and the second metal layer is disposed on the first metal layer.

5. The electronic substrate as described in claim 1, characterized in that, It also includes a scan line disposed on the substrate and electrically connected to the gate of the transistor, wherein the scan line is formed by a first metal layer, the data line and the gate are formed by a second metal layer, and the second metal layer is disposed on the first metal layer.

6. A method for manufacturing an electronic substrate, characterized in that, include: Provide a substrate; A first metal layer is formed on the substrate, wherein the first metal layer includes a data line; A first insulating layer is formed on the first metal layer; A semiconductor material layer is formed on the first insulating layer; A second insulating layer is formed on the semiconductor material layer; A second metal layer is formed on the second insulating layer, wherein the second metal layer includes a scan line, and the scan line includes a gate; and A source and a drain are formed in the semiconductor material layer, wherein the semiconductor material layer includes an active layer and the active layer is disposed between the source and the drain; In the cross-sectional view of the electronic substrate, the gate overlaps the active layer, and the scan line is positioned on the data line.

7. The method for manufacturing an electronic substrate as described in claim 6, characterized in that, The conductivity of the source and the drain is greater than that of the active layer.

8. The method for manufacturing an electronic substrate as described in claim 6, characterized in that, The semiconductor material layer includes metal oxides.

9. The method for manufacturing an electronic substrate as described in claim 6, characterized in that, The second metal layer also includes a conductive element that electrically connects the data line and the source electrode.

10. The method for manufacturing an electronic substrate as described in claim 6, characterized in that, It also includes forming a third insulating layer on the second metal layer and forming a transparent conductive layer on the third insulating layer, wherein the transparent conductive layer includes a common electrode.

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