Circuit structure for eliminating antenna effect and semiconductor structure

Abstract

The invention relates to a circuit structure and a semiconductor structure for eliminating an antenna effect, the circuit structure for eliminating the antenna effect comprises at least one diode and a buffer, one end of the diode and the input end of the buffer are connected with the input end of the circuit structure, and the output end of the buffer is the output end of the circuit structure. The other end of the diode is grounded. In the embodiment of the invention, through the above circuit structure, charges accumulated in the circuit can be exported through the diode, that is to say, when the charges are accumulated too much, reverse breakdown can be preferentially carried out on a grid tube of the diode, so that charge leakage is realized, damage to a grid electrode in a semiconductor device needing to eliminate an antenna effect can be avoided, and the antenna effect can be eliminated. And the antenna effect in the circuit is effectively eliminated.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a circuit structure and semiconductor structure for eliminating antenna effects. Background Technology

[0002] As integrated circuits move into deep submicron designs, device sizes continue to shrink, circuit scales expand, and gate delays become increasingly smaller. Interconnect delays have become one of the main factors limiting circuit performance improvements. In deep submicron integrated circuit fabrication processes, a plasma-based ion etching process is commonly used. This technology can meet the requirements of continuously increasing mask etching resolution as device sizes shrink. However, free charges are generated during the etching process. When etching semiconductors (metals or polysilicon), the exposed conductor surface collects free charges, and the amount of accumulated charge is proportional to the area of ​​the conductor exposed to the plasma beam. When the charged conductor is directly connected to the device gate, a tunneling current forms in the thin oxide layer under the polysilicon gate, thus discharging the charge.

[0003] During chip manufacturing, exposed metal wires or conductors such as polysilicon collect electrical charges (e.g., charged particles generated by plasma etching), causing an increase in potential. The longer the wire, the more charge is collected, and the higher the voltage. When the accumulated charge exceeds a certain amount, this current can damage the oxide layer, thereby reducing the reliability and lifespan of the device and even the entire chip. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a circuit structure and a semiconductor structure for eliminating antenna effects.

[0005] On the one hand, embodiments of this application disclose a circuit structure for eliminating antenna effects, including at least one diode and a buffer;

[0006] One end of the diode and the input terminal of the buffer are both connected to the input terminal of the circuit structure;

[0007] The output of the buffer is the output of the circuit structure;

[0008] The other end of the diode is grounded.

[0009] In some possible embodiments, one end of the diode is the positive terminal of at least one of the diodes.

[0010] In some possible embodiments, at least one diode comprises a plurality of diodes connected in parallel;

[0011] The positive terminal of each diode is connected to the input terminal of the circuit structure;

[0012] The negative terminal of each diode is grounded.

[0013] In some possible embodiments,

[0014] The buffer includes at least two cascaded inverters;

[0015] Inverters include PMOS transistors and NMOS transistors.

[0016] In some possible embodiments, the input terminal and the gate of the circuit structure are connected.

[0017] In some possible embodiments, an equivalent capacitance is also included;

[0018] One end of the equivalent capacitor is connected to the input terminal; the other end of the equivalent capacitor is connected to the power supply.

[0019] On the other hand, embodiments of this application disclose a semiconductor structure for eliminating antenna effects, comprising:

[0020] The substrate includes a first region and a second region; the first region includes a third region and a fourth region; the third region includes a first NMOS region and a first PMOS region; the first NMOS region includes a first doped region, a first source region, and a first drain region; the first PMOS region includes a first well region; the first well region includes a second drain region, a second source region, and a second doped region; the fourth region includes a second NMOS region and a second PMOS region; the second NMOS region includes a third doped region, a third source region, and a third drain region; the second PMOS region includes a second well region; the second well region includes a fourth drain region, a fourth source region, and a fourth doped region; the second region includes a first terminal structure and a second terminal structure; the first terminal structure and the second terminal structure are the two-terminal structures of a diode;

[0021] A first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are located on a substrate; a first source region and a first drain region are located on both sides of the first gate structure, a second source region and a second drain region are located on both sides of the second gate structure, a third source region and a third drain region are located on both sides of the third gate structure, and a fourth source region and a fourth drain region are located on both sides of the fourth gate structure.

[0022] Both the first and third doped regions are implanted with first doped ions; both the second and fourth doped regions are implanted with second doped ions.

[0023] In some possible embodiments, the second region further includes a third PMOS region;

[0024] The third PMOS region includes the third well region; the third well region includes the sixth drain region, the sixth source region, and the sixth doped region;

[0025] The substrate also includes a sixth gate structure; the sixth drain region and the sixth source region are located on both sides of the sixth gate structure;

[0026] The sixth doped region was implanted with second doped ions.

[0027] In some possible embodiments, the semiconductor structure includes a plurality of second regions and a gate structure corresponding to each second region.

[0028] In some possible embodiments, the semiconductor structure includes a plurality of first regions and a gate structure corresponding to each first region.

[0029] In some possible embodiments,

[0030] Both the first gate structure and the first terminal structure of the second gate structure are used to connect signal input lines;

[0031] The third gate structure, the fourth gate structure, the first drain region, and the second drain region are all used to connect signal connection lines;

[0032] The second source region, the second doped region, the fourth source region, and the fourth doped region are all used to connect to the power supply;

[0033] The second terminal structure, the first doped region, the first source region, the third doped region, and the third source region are all used for grounding;

[0034] Both the third and fourth drain regions are used to connect signal output lines.

[0035] In some possible embodiments,

[0036] The sixth gate structure is used to connect the signal input line;

[0037] The sixth drain region, the sixth source region, and the sixth doped region are all used to connect to the power supply.

[0038] On the other hand, embodiments of this application disclose an electronic device, which includes a semiconductor structure for eliminating antenna effects as described above.

[0039] The technical solution provided in this application has the following technical effects:

[0040] The circuit structure for eliminating the antenna effect includes at least one diode and a buffer. One end of the diode and the input terminal of the buffer are both connected to the input terminal of the circuit structure. The output terminal of the buffer is the output terminal of the circuit structure, and the other end of the diode is grounded. In this embodiment, the above circuit structure allows the diode to discharge accumulated charge in the circuit. Excessive charge accumulation will preferentially cause reverse breakdown from the diode, thus achieving charge leakage. This avoids damage to the gate of the semiconductor device whose antenna effect needs to be eliminated, effectively eliminating the antenna effect in the circuit. Attached Figure Description

[0041] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic diagram of a circuit structure for eliminating antenna effects provided in an embodiment of this application. Figure 1 ;

[0043] Figure 2 This is a schematic diagram of a circuit structure for eliminating antenna effects provided in an embodiment of this application. Figure 2 ;

[0044] Figure 3 This is a schematic diagram of a circuit structure for eliminating antenna effects provided in an embodiment of this application. Figure 3 ;

[0045] Figure 4 This is a schematic diagram of a circuit structure for eliminating antenna effects provided in an embodiment of this application. Figure 4 ;

[0046] Figure 5 This is a schematic diagram of a semiconductor structure for eliminating antenna effects provided in an embodiment of this application. Figure 1 ;

[0047] Figure 6 This is a schematic diagram of a semiconductor structure for eliminating antenna effects provided in an embodiment of this application;

[0048] Figure 7 This is a schematic flowchart of a signal processing method based on a memory computing module provided in an embodiment of this application;

[0049] 10 - Diode; 20 - Buffer; 30 - Equivalent capacitance;

[0050] 40 - Substrate; 60 - First region; 70 - Second region; 601 - Third region; 602 - Fourth region;

[0051] 603 - First NMOS region; 604 - First PMOS region; 605 - Second NMOS region; 606 - Second PMOS region; 608 - Third PMOS region;

[0052] 611 - First well region; 612 - Second well region; 613 - Third well region;

[0053] 101 - First source region; 102 - First drain region; 103 - First doped region; 104 - First gate structure;

[0054] 201 - Second source region; 202 - Second drain region; 203 - Second doped region; 204 - Second gate structure;

[0055] 301 - Third source region; 302 - Third drain region; 303 - Third doped region; 304 - Third gate structure;

[0056] 401 - Fourth source region; 402 - Fourth drain region; 403 - Fourth doped region; 404 - Fourth gate structure;

[0057] 501 - First end structure; 502 - Second end structure;

[0058] 601 - Sixth source region; 602 - Sixth drain region; 603 - Sixth doped region; 604 - Sixth gate structure;

[0059] 1-Signal input line; 2-Signal connection line; 3-Power supply; 4-Ground; 5-Signal output line. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0061] It should be noted that the term "an embodiment" or "embodiment" in the specification of the embodiments of this application refers to a specific feature, structure, or characteristic that can be included in at least one implementation of this application. It should be understood that in the specification, claims, and accompanying drawings of the embodiments of this application, the terms "upper," "lower," "top," "bottom," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature. Moreover, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, in the description of this embodiment, unless otherwise stated, "a plurality of" means two or more. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, or product that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0062] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0063] To make the objectives, technical solutions, and advantages disclosed in the embodiments of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the embodiments of this application and are not intended to limit the embodiments of this application.

[0064] Currently, in digital back-end design with layout and routing, methods to correct antenna effects are mainly based on reducing the total area of ​​the metal wires connected to the grid or adding auxiliary charge discharge circuits. Examples include layer skipping, adding diodes, or inserting buffers.

[0065] However, the layer-skipping method can disconnect the metal layer exhibiting antenna effects, connecting it to other layers (skipping upwards or downwards) via vias, and finally returning to the current layer. This method addresses the antenna effect by changing the layers of the metal wiring, but it also increases the number of vias. Since vias have high resistance, they directly affect chip timing and crosstalk issues.

[0066] Adding diodes can be done by directly connecting them to the metal layer connected to the gate transistor and exhibiting an antenna effect, thus creating a charge discharge path. However, in cases with long metal lines, multiple diodes need to be added, resulting in excessive fan-out and directly impacting the chip's timing.

[0067] Inserting a buffer can increase the number of gate transistors and achieve the purpose of skipping layers, but it cannot leak too much accumulated charge, thus fundamentally solving the problem of antenna effect.

[0068] In view of this, embodiments of this application provide a schematic diagram of a circuit structure for eliminating antenna effects. Figure 1 ,like Figure 1 As shown, the circuit structure for eliminating antenna effects includes at least one diode 10 and a buffer 20.

[0069] Optionally, one end of diode 10 and the input terminal of buffer 20 are both connected to the input terminal In of the circuit structure, and the output terminal of the buffer is the output terminal Out of the circuit structure. The other end of diode 10 is grounded.

[0070] In this embodiment, one end of diode 10 is the anode of at least one diode 10, and the other end is the cathode. That is, the anode of at least one diode 10 and the input terminal of buffer 20 are both connected to the input terminal In of the circuit structure, and the output terminal of the buffer is the output terminal Out of the circuit structure. The cathode of at least one diode is grounded.

[0071] In this embodiment, the input terminal and gate of the circuit structure for eliminating antenna effects are connected. That is, the positive terminal of diode 10 in at least one diode and the input terminal of buffer 20 can be connected to the gate via a signal input line, wherein the gate is the gate of the semiconductor device in which the antenna effect needs to be eliminated.

[0072] In this embodiment, the circuit structure described above allows the diode to discharge the accumulated charge in the circuit. If too much charge accumulates, it will preferentially break down from the diode in reverse, thus achieving charge leakage. This avoids damage to the gate of the semiconductor device that needs to eliminate the antenna effect and effectively eliminates the antenna effect in the circuit.

[0073] This application provides a schematic diagram of a circuit structure for eliminating antenna effects. Figure 2 ,like Figure 2 As shown, in this circuit structure for eliminating antenna effects, at least one diode includes multiple diodes 10 connected in parallel. The positive terminal of each diode 10 is connected to the input terminal In of the circuit structure, and the negative terminal of each diode is grounded.

[0074] In other words, the positive terminal of each diode in at least one diode and the input terminal of the buffer 20 can be connected to the gate via a signal input line, wherein the gate is the gate in the semiconductor device for which the antenna effect needs to be eliminated.

[0075] This application provides a schematic diagram of a circuit structure for eliminating antenna effects. Figure 3 ,like Figure 3 As shown, the circuit structure for eliminating the antenna effect may include a diode 10 and a buffer 20. The anode of diode 10 and the input terminal of buffer 20 are both connected to the input terminal In of the circuit structure, that is, connected to the gate of the semiconductor device whose antenna effect needs to be eliminated via a signal input line. The output terminal of buffer 20 is the output terminal Out of the circuit structure, and the cathode of diode 10 is grounded.

[0076] like Figure 3 As shown, in one alternative embodiment, the buffer may include at least two cascaded inverters, each inverter consisting of a PMOS transistor and an NMOS transistor.

[0077] In some possible embodiments, the buffer contains at least two inverters, and the number is even, such as four, eight, or sixteen inverters. A buffer with four inverters requires four drivers, and a buffer with eight inverters requires eight drivers.

[0078] For example Figure 3The buffer shown is used as an example for explanation. The two inverters are the first inverter and the second inverter. The first inverter includes a first PMOS transistor and a first NMOS transistor, and the second inverter includes a second PMOS transistor and a second NMOS transistor.

[0079] In this circuit, the gates of both the first PMOS transistor and the first NMOS transistor are connected to the input terminal In. The sources of both the first and second PMOS transistors are connected to the power supply. The sources of both the first and second NMOS transistors are grounded. The drains of both the second PMOS transistor and the second NMOS transistor are connected to the output terminal Out. The signal connection lines between the drains of the first PMOS transistor, the gates of the second PMOS transistor, the drains of the first NMOS transistor, the gates of the second NMOS transistor, and the two inverters are connected.

[0080] In the embodiments of this application, such as Figure 3 As shown, the first terminal of the diode is connected to the input terminal In of the circuit structure, and the second terminal is grounded.

[0081] In this embodiment, the circuit structure for eliminating antenna effects described above not only enables signal line skipping and breaks longer signal lines, but also increases the number of diodes, reducing charge accumulation in the circuit. Furthermore, this standard digital unit can reduce the fan-out number in diode-adding methods and enhance drive performance, reducing the impact of timing and crosstalk. More importantly, combining one or more parallel diodes with a multi-drive buffer to form a standard digital unit can save area and wiring resources during fabrication.

[0082] This application provides a schematic diagram of a circuit structure for eliminating antenna effects. Figure 4 ,like Figure 4 As shown, the circuit structure for eliminating the antenna effect may include a diode 10, a buffer 20, and an equivalent capacitor 30. The anode of diode 10, the input terminal of buffer 20, and one end of the equivalent capacitor 30 are all connected to the input terminal In of the circuit structure, that is, connected to the gate of the semiconductor device whose antenna effect needs to be eliminated via a signal input line. The output terminal of buffer 20 is the output terminal Out of the circuit structure, the cathode of diode 10 is grounded, and the other end of the equivalent capacitor 30 is connected to the power supply.

[0083] For example Figure 4 The buffer shown is used as an example for explanation. The two inverters are the first inverter and the second inverter. The first inverter includes a first PMOS transistor and a first NMOS transistor, and the second inverter includes a second PMOS transistor and a second NMOS transistor.

[0084] In this circuit, the gates of both the first PMOS transistor and the first NMOS transistor are connected to the input terminal In. The sources of both the first and second PMOS transistors are connected to the power supply. The sources of both the first and second NMOS transistors are grounded. The drains of both the second PMOS transistor and the second NMOS transistor are connected to the output terminal Out. The signal connection lines between the drains of the first PMOS transistor, the gates of the second PMOS transistor, the drains of the first NMOS transistor, the gates of the second NMOS transistor, and the two inverters are connected.

[0085] In the embodiments of this application, such as Figure 4 As shown, the first terminal of the diode is connected to the input terminal In of the circuit structure, and the second terminal is grounded.

[0086] In this embodiment, the gate of the equivalent capacitor is connected to the input terminal In of the circuit structure, and the source and drain of the equivalent capacitor are both connected to the power supply.

[0087] In some possible embodiments, the equivalent capacitance described above is for fabricational symmetry. Optionally, the equivalent capacitance does not participate in charge leakage.

[0088] This application provides a schematic diagram of a semiconductor structure for eliminating antenna effects. Figure 1 ,like Figure 5 As shown, the semiconductor structure corresponds to the circuit structure described above. The semiconductor structure includes a substrate 40, a plurality of gate structures located on the substrate 40, and a simplified schematic diode structure.

[0089] Optionally, the substrate 40 includes a first region 60 and a second region 70. The first region 60 includes a third region 601 and a fourth region 602. The third region 601 includes a first NMOS region 603 and a first PMOS region 604. The first NMOS region 603 sequentially includes a first doped region 103, a first source region 101 and a first drain region 102. The first PMOS region 604 includes a first well region 611. The first well region 611 sequentially includes a second drain region 202, a second source region 201 and a second doped region 203. The fourth region 602 includes a second NMOS region 605 and a second PMOS region 606. The second NMOS region 605 sequentially includes a third doped region 303, a third source region 301, and a third drain region 302. The second PMOS region 606 includes a second well region 612, which sequentially includes a fourth drain region 402, a fourth source region 401, and a fourth doped region 403. The second region 70 includes a first terminal structure 501 and a second terminal structure 502. The first terminal structure 501 and the second terminal structure 502 are the two-terminal structures of a diode.

[0090] Optionally, the plurality of gate structures located on the substrate 40 include a first gate structure 104, a second gate structure 204, a third gate structure 304, and a fourth gate structure 404. Specifically, a first source region 101 and a first drain region 102 are located on opposite sides of the first gate structure 104, a second source region 201 and a second drain region 202 are located on opposite sides of the second gate structure 204, a third source region 301 and a third drain region 302 are located on opposite sides of the third gate structure 304, and a fourth source region 401 and a fourth drain region 402 are located on opposite sides of the fourth gate structure 404.

[0091] In some possible embodiments, the first doped region 103 and the third doped region 303 are implanted with first doped ions, and the second doped region 203 and the fourth doped region 403 are both implanted with second doped ions.

[0092] In some possible embodiments, the second source region 201, the second drain region 202, the fourth source region 401 and the fourth drain region 402 are all implanted with first doped ions, and the first source region 101, the first drain region 102, the third source region 301 and the third drain region 302 are all implanted with second doped ions.

[0093] This application provides a schematic diagram of a semiconductor structure for eliminating antenna effects. Figure 2 ,like Figure 6 As shown, the semiconductor structure corresponds to the circuit structure described above. The semiconductor structure includes a substrate 40 and a plurality of gate structures located on the substrate 40.

[0094] Apart from Figure 5 In this embodiment, the second region 70 further includes a third PMOS region 608. Optionally, the third PMOS region 608 includes a third well region 613, which sequentially includes a sixth drain region 602, a sixth source region 601, and a sixth doped region 603. Optionally, the substrate 40 also includes a sixth gate structure 604, with the sixth drain region 602 and the sixth source region 601 located on either side of the sixth gate structure 604.

[0095] The sixth drain region 602 and the sixth source region 601 are implanted with first doped ions, and the sixth doped region 603 is implanted with second doped ions.

[0096] Optionally, the substrate can be a P-type substrate, the first dopant ion can be a P-type impurity, and the second dopant ion can be an N-type impurity.

[0097] This application provides a schematic diagram of a semiconductor structure for eliminating antenna effects, as shown in the following embodiments. Figure 7As shown in the embodiment of this application, the first gate structure 104, the second gate structure 204, and the first terminal structure 501 are all used to connect to the signal input line 1; the third gate structure 304, the fourth gate structure 404, the first drain region 102, and the second drain region 202 are all used to connect to the signal connection line 2; the second source region 201, the second doped region 203, the fourth source region 401, and the fourth doped region 403 are all used to connect to the power supply 3; the second terminal structure 502, the first doped region 103, the first source region 101, the third doped region 303, and the third source region 301 are all used to ground 4; and the third drain region 302 and the fourth drain region 402 are all used to connect to the signal output line 5.

[0098] Optionally, the sixth gate structure 604 is used to connect the signal input line 1, and the sixth drain region 602, the sixth source region 601 and the sixth doped region 603 are all used to connect the power supply 3.

[0099] In some possible embodiments, the semiconductor structure may include a plurality of first regions 60 and a gate structure corresponding to each first region 60, that is, multiple pairs of inverters described in the above circuit structure, and the multiple pairs of inverters form a buffer.

[0100] In some possible embodiments, the semiconductor structure may include a plurality of second regions 70 and a gate structure corresponding to each second region 70, namely a plurality of parallel diodes as described in the circuit structure above.

[0101] In one alternative embodiment, a circuit structure consisting of multiple diodes and more inverters can significantly reduce charge accumulation compared to a circuit structure formed by a buffer consisting of a single diode and two inverters. Optionally, the circuit structure may include three diodes in parallel and four driven buffers. Alternatively, the circuit structure may include six diodes in parallel and eight driven buffers.

[0102] In the embodiments of this application, the number of diodes and drivers included in the circuit structure can be determined according to the actual situation.

[0103] In summary, the following effects can be achieved through the embodiments of this application:

[0104] First, it is easy to implement, with a standard digital unit architecture and simple structure and function;

[0105] Secondly, it can eliminate the antenna effect. The diodes in the standard unit discharge the accumulated charge, and the multi-drive buffer can reduce the line length, increase the gate area, and reduce the charge accumulation in the circuit.

[0106] Third, the structure is flexible, and the number of diodes in parallel in the standard unit and the driving capability of the multi-drive buffer can be adjusted according to the amount of charge accumulation due to the antenna effect in the actual circuit.

[0107] Fourth, it reduces the impact of timing and crosstalk. This standard digital unit can reduce the number of diodes on the signal lines and enhance the drive, thereby reducing timing and crosstalk.

[0108] Fifth, it saves area and winding resources. This standard digital unit combines diodes and buffers to reduce area and winding resources while eliminating antenna effects.

[0109] Sixth, it has strong applicability and can be implemented in different process nodes.

[0110] Accordingly, embodiments of this application also provide an electronic device that includes a semiconductor structure for eliminating antenna effects.

[0111] The electronic device described in the embodiments of this application can be any electronic product or device such as a smartphone, desktop computer, tablet computer, laptop computer, digital assistant, augmented reality (AR) / virtual reality (VR) device, smart voice interaction device, smart home appliance, smart wearable device, vehicle terminal device, etc., or any intermediate product including the above-mentioned storage device.

[0112] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, specific embodiments have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0113] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0114] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0115] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A circuit structure for eliminating antenna effects, characterized in that, Includes at least one diode and a buffer; One end of the diode and the input terminal of the buffer are both connected to the input terminal of the circuit structure; The output terminal of the buffer is the output terminal of the circuit structure; The other end of the diode is grounded.

2. The circuit structure for eliminating antenna effects according to claim 1, characterized in that, One end of the diode is the positive terminal of each of the at least one diode.

3. The circuit structure for eliminating antenna effects according to claim 1, characterized in that, The at least one diode includes a plurality of diodes connected in parallel; The positive terminal of each diode is connected to the input terminal of the circuit structure; The negative terminal of each diode is grounded.

4. The circuit structure for eliminating antenna effects according to claim 1, characterized in that, The buffer includes at least two cascaded inverters; The inverter includes a PMOS transistor and an NMOS transistor.

5. The circuit structure for eliminating antenna effects according to claim 1, characterized in that, The input terminal and the gate of the circuit structure are connected.

6. The circuit structure for eliminating antenna effects according to claim 1, characterized in that, It also includes the equivalent capacitance; One end of the equivalent capacitor is connected to the input terminal; the other end of the equivalent capacitor is connected to the power supply.

7. A semiconductor structure for eliminating antenna effects, characterized in that, include: A substrate; the substrate includes a first region and a second region; the first region includes a third region and a fourth region; the third region includes a first NMOS region and a first PMOS region; the first NMOS region includes a first doped region, a first source region, and a first drain region; the first PMOS region includes a first well region; the first well region includes a second drain region, a second source region, and a second doped region; the fourth region includes a second NMOS region and a second PMOS region; the second NMOS region includes a third doped region, a third source region, and a third drain region; the second PMOS region includes a second well region; the second well region includes a fourth drain region, a fourth source region, and a fourth doped region; the second region includes a first end structure and a second end structure; the first end structure and the second end structure are the two-end structures of a diode; A first gate structure, a second gate structure, a third gate structure, and a fourth gate structure are located on the substrate; the first source region and the first drain region are located on both sides of the first gate structure, the second source region and the second drain region are located on both sides of the second gate structure, the third source region and the third drain region are located on both sides of the third gate structure, and the fourth source region and the fourth drain region are located on both sides of the fourth gate structure. Both the first doped region and the third doped region are implanted with first doped ions; both the second doped region and the fourth doped region are implanted with second doped ions.

8. The semiconductor structure for eliminating antenna effects according to claim 7, characterized in that, The second region also includes a third PMOS region; The third PMOS region includes a third well region; the third well region includes a sixth drain region, a sixth source region, and a sixth doped region; The substrate further includes a sixth gate structure; the sixth drain region and the sixth source region are located on both sides of the sixth gate structure; The sixth doped region is implanted with the second doped ions.

9. The semiconductor structure for eliminating antenna effects according to claim 7 or 8, characterized in that, The semiconductor structure includes multiple second regions and a gate structure corresponding to each second region.

10. The semiconductor structure for eliminating antenna effects according to claim 7 or 8, characterized in that, The semiconductor structure includes multiple first regions and a gate structure corresponding to each first region.

11. The semiconductor structure for eliminating antenna effects according to claim 8, characterized in that, The first gate structure, the second gate structure, and the first terminal structure are all used to connect signal input lines; The third gate structure, the fourth gate structure, the first drain region, and the second drain region are all used to connect signal connection lines; The second source region, the second doped region, the fourth source region, and the fourth doped region are all used to connect to the power supply; The second end structure, the first doped region, the first source region, the third doped region, and the third source region are all used for grounding; Both the third and fourth drain regions are used to connect signal output lines.

12. The semiconductor structure for eliminating antenna effects according to claim 11, characterized in that, The sixth gate structure is used to connect the signal input line; The sixth drain region, the sixth source region, and the sixth doped region are all used to connect to the power supply.

13. An electronic device, characterized in that, The electronic device includes a semiconductor structure for eliminating antenna effects as described in any one of claims 7-12.

Images