High-hydrolysis-resistance LED epitaxial wafer and preparation method thereof

Abstract

The invention discloses a high-hydrolysis-resistance LED epitaxial wafer and a preparation method thereof. The high-hydrolysis-resistance LED epitaxial wafer comprises a substrate, a buffer layer, a 3D GaN layer, a U-type GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well layer, an electron blocking layer and a P-type GaN layer, wherein the U-shaped GaN layer comprises a first U-shaped GaN layer, a low-temperature InGaN insertion layer, a U-shaped GaN transition layer and a second U-shaped GaN layer which are stacked in sequence. By implementing the method, the hydrolysis resistance of the LED can be effectively improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a highly hydrolysis-resistant LED epitaxial wafer and its preparation method. Background Technology

[0002] In the traditional LED epitaxial wafer growth process, due to the significant difference in lattice constants and thermal expansion coefficients between the substrate and GaN material, a U-type GaN layer is typically grown between the substrate and the N-type GaN layer for transition. However, the U-type GaN layer has poor crystal quality, containing numerous dislocations and voids, resulting in a high number of epitaxial defects in the subsequently grown N-type GaN layer. These defects provide channels for rapid diffusion of water molecules and air, leading to a decrease in epitaxial wafer quality. Furthermore, the chip typically requires the formation of MESA steps to expose the N-type GaN layer. This structure is highly susceptible to hydrolysis at high temperatures, causing the chip to dim or even detach from its electrode. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a highly hydrolysis-resistant LED epitaxial wafer and its preparation method, which can effectively improve the hydrolysis resistance of LEDs.

[0004] To address the aforementioned problems, this invention discloses a highly hydrolysis-resistant LED epitaxial wafer, comprising a substrate and a buffer layer, a 3D GaN layer, a U-type GaN layer, an N-type GaN layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate; wherein, the U-type GaN layer comprises a first U-type GaN layer, a low-temperature InGaN insertion layer, a U-type GaN transition layer, and a second U-type GaN layer sequentially stacked.

[0005] As an improvement to the above technical solution, the growth temperature of the low-temperature InGaN insertion layer is 800℃~950℃, and the thickness is 20Å~100Å.

[0006] As an improvement to the above technical solution, the thickness of the U-shaped GaN transition layer is 0.2μm~0.5μm.

[0007] As an improvement to the above technical solution, the thickness of the first U-shaped GaN layer is 1μm~2μm, and the thickness of the second U-shaped GaN layer is 1μm~2μm.

[0008] As an improvement to the above technical solution, the thickness of the N-type GaN layer is 1.4 μm to 1.6 μm, and the N-type GaN layer includes a first GaN layer and a second GaN layer that are periodically alternately stacked, with the number of alternating stacking periods being 40 to 60. The second GaN layer is a Si-doped GaN layer with a Si doping concentration of 1 × 10⁻⁶. 19 atoms / cm 3 ~2×10 19atoms / cm 3 .

[0009] As an improvement to the above technical solution, the stress relief layer comprises periodically alternating GaN stress relief layers and InGaN stress relief layers, with the number of alternating stacking periods being 3 to 6. The GaN stress relief layer is a Si-doped GaN layer with a Si doping concentration of 4 × 10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3 The InGaN stress relief layer has a thickness of 200 Å to 300 Å, and the In composition ratio is 0.1 to 0.2, with a thickness of 30 Å to 50 Å.

[0010] Accordingly, the present invention also discloses a method for preparing a highly hydrolysis-resistant LED epitaxial wafer, which includes the following steps: A substrate is provided on which a buffer layer, a 3D GaN layer, a U-type GaN layer, an N-type GaN layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially grown; wherein the U-type GaN layer comprises a first U-type GaN layer, a low-temperature InGaN insertion layer, a U-type GaN transition layer, and a second U-type GaN layer stacked sequentially.

[0011] As an improvement to the above technical solution, the U-shaped GaN layer is prepared using the following steps: The growth pressure was controlled at 100 torr to 200 torr, the growth temperature at 1100℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, the carrier gas was H2, and the N source and Ga source were introduced to grow the first U-shaped GaN layer. The growth pressure was controlled at 100 torr to 200 torr, the growth temperature at 800℃ to 950℃, and the rotation speed at 400 r / min to 600 r / min. N source, In source and Ga source were introduced to grow a low-temperature InGaN insertion layer. The growth pressure was controlled at 100 torr to 200 torr, the growth temperature at 1100℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, and the carrier gas was H2. N source and Ga source were introduced to grow U-shaped GaN transition layer. The growth pressure was controlled at 100 torr to 200 torr, the growth temperature at 1100℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, and the carrier gas was H2. N source and Ga source were introduced to grow the second U-shaped GaN layer.

[0012] As an improvement to the above technical solution, after growing the low-temperature InGaN insertion layer, the temperature is increased to 1050℃~1100℃, and the heating time is 30s~150s.

[0013] As an improvement to the above technical solution, the N-type GaN layer is prepared using the following steps: The growth pressure was controlled at 200 torr to 400 torr, the growth temperature at 1080℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, and N source and Ga source were introduced. The growth time was 5s to 8s to grow the first GaN layer. The growth pressure was controlled at 200 torr to 400 torr, the growth temperature at 1080℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, and N source, Ga source and Si source were introduced. The growth time was 5s to 8s to grow the second GaN layer. The first and second GaN layers are grown periodically by repeated stacking.

[0014] Implementing this invention has the following beneficial effects: The high hydrolysis-resistant LED epitaxial wafer provided by this invention includes a U-shaped GaN layer comprising a first U-shaped GaN layer, a low-temperature InGaN insertion layer, a U-shaped GaN transition layer, and a second U-shaped GaN layer stacked sequentially. The low-temperature InGaN insertion layer amplifies line defects extending from the first U-shaped GaN layer. After annealing, InN is fully decomposed to form a V-shaped notch. The U-shaped GaN transition layer forms 3D growth at the V-shaped notch. After repeatedly filling the defects, the second 2D U-shaped GaN layer is grown, reducing epitaxial defects caused by the U-shaped GaN layer. The number of N-type GaN layer line dislocations grown on the U-shaped GaN layer is reduced, and the growth quality is effectively improved, ultimately enhancing the hydrolysis resistance of the chip. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a high hydrolysis-resistant LED epitaxial wafer provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a high hydrolysis-resistant LED epitaxial wafer provided in an embodiment of the present invention; Figure 3 This is a flowchart of a method for preparing a highly hydrolysis-resistant LED epitaxial wafer according to an embodiment of the present invention. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below.

[0017] like Figure 1As shown, the present invention discloses a high hydrolysis resistant LED epitaxial wafer, comprising a substrate 1 and a buffer layer 2, a 3D GaN layer 3, a U-type GaN layer 4, an N-type GaN layer 5, a stress relief layer 6, a multiple quantum well layer 7, an electron blocking layer 8, and a P-type GaN layer 9 sequentially stacked on the substrate 1; wherein, the U-type GaN layer 4 comprises a first U-type GaN layer 41, a low-temperature InGaN insertion layer 42, a U-type GaN transition layer 43, and a second U-type GaN layer 44 sequentially stacked.

[0018] The high hydrolysis-resistant LED epitaxial wafer provided by this invention includes a U-shaped GaN layer 4 comprising a first U-shaped GaN layer 41, a low-temperature InGaN insertion layer 42, a U-shaped GaN transition layer 43, and a second U-shaped GaN layer 44 stacked sequentially. The low-temperature InGaN insertion layer 42 amplifies the line defects extending from the first U-shaped GaN layer 41. After annealing, the InN is fully decomposed to form a V-shaped notch. The U-shaped GaN transition layer 43 forms 3D growth at the V-shaped notch. After repeatedly filling the defects, the second U-shaped GaN layer 44 is grown in 2D, which reduces the epitaxial defects caused by the U-shaped GaN layer 4. The line dislocations of the N-shaped GaN layer 5 grown on the U-shaped GaN layer 4 are reduced, the growth quality is effectively improved, and the hydrolysis resistance of the chip is ultimately improved.

[0019] In one embodiment, the growth temperature of the low-temperature InGaN insertion layer 42 is 800℃~950℃, and the thickness is 20Å~100Å, exemplarily 40Å, 50Å, 60Å, 80Å or 90Å, but not limited thereto. If the thickness of the low-temperature InGaN insertion layer 42 is less than 20Å, it is difficult to form a sufficiently large V-shaped pit, which will cause a large number of dislocations to extend directly to the N-type GaN layer 5; if the thickness of the low-temperature InGaN insertion layer 42 is greater than 100Å, the crystal quality of the low-temperature grown InGaN layer itself is poor, and the excessive thickness will introduce a large number of point defects and stress, inducing new dislocations and stacking faults. In addition, low-temperature growth itself is not conducive to the incorporation and migration of In, and excessive thickness will also aggravate the inhomogeneity of In composition.

[0020] In one embodiment, the thickness of the U-shaped GaN transition layer 43 is 0.2 μm to 0.5 μm, exemplarily 0.25 μm, 0.3 μm, 0.35 μm, 0.4 μm, or 0.45 μm, but not limited thereto. If the thickness of the U-shaped GaN transition layer 43 is less than 0.2 μm, it is difficult to effectively fill the defects of the low-temperature InGaN insertion layer 42; if the thickness of the U-shaped GaN transition layer 43 is greater than 0.5 μm, it will cause a decrease in crystal quality.

[0021] It is understood that by inserting a low-temperature InGaN insertion layer 42 and a U-shaped GaN transition layer 43 into the U-shaped GaN layer 4, a first U-shaped GaN layer 41, a low-temperature InGaN insertion layer 42, a U-shaped GaN transition layer 43, and a second U-shaped GaN layer 44 are formed by sequentially stacking these layers. That is, the first U-shaped GaN layer 41 and the second U-shaped GaN layer 44 have the same structure, but their thicknesses can be the same or different. In one embodiment, the thickness of the first U-shaped GaN layer 41 is 1 μm to 2 μm, exemplarily 1.2 μm, 1.4 μm, 1.5 μm, 1.6 μm, or 1.8 μm, but not limited thereto. The thickness of the second U-shaped GaN layer 44 is 1 μm to 2 μm, exemplarily 1.2 μm, 1.4 μm, 1.5 μm, 1.6 μm, or 1.8 μm, but not limited thereto. Preferably, the first U-shaped GaN layer 41 and the second U-shaped GaN layer 44 have the same thickness.

[0022] In one embodiment, the thickness of the N-type GaN layer 5 is 1.4 μm to 1.6 μm, exemplary values ​​are 1.42 μm, 1.45 μm, 1.5 μm, 1.52 μm, or 1.58 μm, but it is not limited thereto. Preferably, such as Figure 2 As shown, the N-type GaN layer 5 includes a first GaN layer 51 and a second GaN layer 52 that are periodically stacked alternately, with a period number of 40 to 60. The second GaN layer 52 is a Si-doped GaN layer with a Si doping concentration of 1 × 10⁻⁶. 19 atoms / cm 3 ~2×10 19 atoms / cm 3 The GaN epitaxial layer grown by MOCVD has a Ga surface. Although it does not react with water at room temperature, after high Si doping, the epitaxial layer exhibits enhanced N polarity, making it highly susceptible to hydrolysis at high temperatures. Therefore, improving the growth quality of the N-type GaN layer 5 is crucial for enhancing its hydrolysis resistance. In the embodiments of the present invention, the periodically alternating first GaN layer 51 and second GaN layer 52 form a superlattice structure. The numerous heterointerfaces in the superlattice structure can effectively bend and block upward-extending through dislocations, reducing the dislocation density reaching the multi-quantum well layer 7, thereby obtaining a higher quality multi-quantum well layer 7.

[0023] In one embodiment, the stress relief layer 6 comprises periodically alternating GaN stress relief layers and InGaN stress relief layers, with the number of alternating stacking periods being 3 to 6. The GaN stress relief layer is a Si-doped GaN layer with a Si doping concentration of 4 × 10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3The InGaN stress relief layer has a thickness of 200 Å to 300 Å, and the In composition ratio is 0.1 to 0.2, with a thickness of 30 Å to 50 Å.

[0024] In addition to the structure described above, the other layered structures of the present invention have the following characteristics: The substrate 1 can be a sapphire substrate, a silicon substrate, or a SiC substrate, but is not limited thereto. Preferably, it is a patterned sapphire substrate.

[0025] The buffer layer 2 can be an AlN buffer layer and / or an AlGaN buffer layer, but is not limited thereto. Preferably, it is an AlN buffer layer.

[0026] The thickness of the 3D GaN layer 3 is 1μm to 2μm. The 3D GaN layer 3 can cover the pattern of the substrate 1, reduce dislocation defects at the bottom of the epitaxial structure, release the bottom stress of the epitaxial structure, and thus improve the crystal quality of the subsequently grown epitaxial structure.

[0027] The multi-quantum-well layer 7 comprises periodically alternating InGaN quantum well layers and GaN quantum barrier layers, with an alternating stacking period of 8 to 20. The InGaN quantum well layers are Si-doped InGaN quantum well layers with a Si doping concentration of 1 × 10⁻⁶. 18 atoms / cm 3 ~2×10 18 atoms / cm 3 The thickness is 20 Å to 30 Å, the InGaN quantum well layer has an In composition ratio of 0.3 to 0.4%, and the GaN quantum barrier layer is a Si-doped GaN quantum barrier layer with a Si doping concentration of 1 × 10⁻⁶. 18 atoms / cm 3 ~2×10 18 atoms / cm 3 The thickness is 100Å~120Å.

[0028] The electron blocking layer 8 can be an AlGaN electron blocking layer with an Al composition ratio of 0.2~0.3 and a thickness of 20nm~130nm.

[0029] The p-type GaN layer 9 can be a Mg-doped GaN layer with a Mg doping concentration of 2 × 10⁻⁶. 19 atoms / cm 3 ~3×10 19 atoms / cm 3 The thickness is 10nm~150nm.

[0030] Correspondingly, such as Figure 3As shown, this invention also discloses a method for preparing a highly hydrolysis-resistant LED epitaxial wafer, which includes the following steps: S1, Provide a substrate 1.

[0031] S2. A buffer layer 2, a 3D GaN layer 3, a U-type GaN layer 4, an N-type GaN layer 5, a stress-relieving layer 6, a multiple quantum well layer 7, an electron-blocking layer 8, and a P-type GaN layer 9 are sequentially grown on substrate 1. The epitaxial structure can be grown using MOCVD, MBE, PVD, or VPE, but is not limited to these methods. Specifically, S2 includes the following steps: S21. Grow a buffer layer 2 on substrate 1.

[0032] Specifically, in one embodiment, the buffer layer 2 is an AlN buffer layer, and the growth of the buffer layer 2 includes the following steps: The AlN buffer layer was grown by PVD at a temperature of 600℃~700℃ and a power of 2500W~5000W. During growth, Ar was used as the sputtering gas, N2 as the precursor, and Al as the sputtering target. The ratio of Ar to N2 was (4~6):1.

[0033] S22. Grow a 3D GaN layer 3 on the buffer layer 2.

[0034] Specifically, in one embodiment, a 3D GaN layer 3 is grown by MOCVD, with the growth pressure controlled at 100 torr to 200 torr, the growth temperature at 900℃ to 1100℃, the rotation speed of the graphite disk at 700 r / min to 900 r / min, the carrier gas being H2, and NH3 being introduced as the N source and TMGa as the Ga source.

[0035] S23. Grow a U-shaped GaN layer 4 on the 3D GaN layer 3.

[0036] Specifically, in one embodiment, the U-shaped GaN layer 4 includes a first U-shaped GaN layer 41, a low-temperature InGaN insertion layer 42, a U-shaped GaN transition layer 43, and a second U-shaped GaN layer 44, stacked sequentially. The growth of the U-shaped GaN layer 4 includes the following steps: S231, control the growth pressure to 100 torr~200 torr, the growth temperature to 1100℃~1250℃, the rotation speed of the graphite disk to 1000r / min~1200r / min, the carrier gas to be H2, introduce NH3 as N source, TMGa as Ga source, and grow the first U-shaped GaN layer 41.

[0037] S232, control the growth pressure to 100 torr~200 torr, the growth temperature to 800℃~950℃, the rotation speed of the graphite disk to 400r / min~600r / min, introduce NH3 as N source, TMGa as Ga source, TMIn as In source, and grow a low-temperature InGaN insertion layer 42.

[0038] In a preferred embodiment, after growing the low-temperature InGaN insertion layer 42, the temperature is raised to 1050℃~1100℃ for 30s~150s, and after annealing, the InN is fully decomposed to form a V-shaped notch.

[0039] S233, control the growth pressure to 100 torr~200 torr, the growth temperature to 1100℃~1250℃, the rotation speed of the graphite disk to 1000r / min~1200r / min, the carrier gas to be H2, introduce NH3 as N source, TMGa as Ga source, and grow U-shaped GaN transition layer 43.

[0040] S234, control the growth pressure to 100 torr~200 torr, the growth temperature to 1100℃~1250℃, the rotation speed of the graphite disk to 1000r / min~1200r / min, the carrier gas to be H2, introduce NH3 as N source, TMGa as Ga source, and grow the second U-shaped GaN layer 44.

[0041] S24. Grow an N-type GaN layer 5 on the U-type GaN layer 4.

[0042] Specifically, in one embodiment, the N-type GaN layer 5 includes a first GaN layer 51 and a second GaN layer 52 that are periodically and alternately stacked. The growth of the N-type GaN layer 5 includes the following steps: S241, control the growth pressure to 200 torr~400 torr, the growth temperature to 1080℃~1250℃, the rotation speed of the graphite disk to 1000r / min~1200r / min, introduce NH3 as N source, TMGa as Ga source, and the growth time to 5s~8s to grow the first GaN layer 51.

[0043] S242, control the growth pressure to 200 torr~400 torr, the growth temperature to 1080℃~1250℃, the rotation speed of the graphite disk to 1000r / min~1200r / min, introduce NH3 as N source, TMGa as Ga source, SiH4 as Si source, and the growth time to 5s~8s to grow the second GaN layer 52.

[0044] S243, Repeatedly stack and periodically grow the first GaN layer 51 and the second GaN layer 52.

[0045] S25. A stress-relieving layer 6 is grown on the N-type GaN layer 5.

[0046] Specifically, in one embodiment, the stress relief layer 6 comprises periodically alternating GaN stress relief layers and InGaN stress relief layers. The growth of the stress relief layer 6 includes the following steps: S251, control the growth pressure to 100 torr~200 torr, the growth temperature to 800℃~950℃, the rotation speed of the graphite disk to 400r / min~600r / min, introduce NH3 as N source, TMIn as In source, TEGa as Ga source, and grow InGaN stress relief layer.

[0047] S252, control the growth pressure to 100 torr~200 torr, the growth temperature to 800℃~950℃, the rotation speed of the graphite disk to 400r / min~600r / min, introduce NH3 as N source, TEGa as Ga source, SiH4 as Si source, and grow GaN stress relief layer.

[0048] S253, GaN stress-relieving layers and InGaN stress-relieving layers are periodically grown by repeated stacking.

[0049] S26. A multi-quantum well layer 7 is grown on the stress relief layer 6.

[0050] Specifically, in one embodiment, the multi-quantum-well layer 7 comprises periodically alternating layers of InGaN quantum wells and GaN quantum barrier layers. The growth of the multi-quantum-well layer 7 includes the following steps: S261. Control the growth pressure to 100 torr~200 torr, the growth temperature to 750℃~850℃, the rotation speed of the graphite disk to 400r / min~600r / min, introduce NH3 as N source, TMIn as In source, TEGa as Ga source, SiH4 as Si source, and grow InGaN quantum well layer.

[0051] S262, control the growth pressure to 100 torr~200 torr, the growth temperature to 750℃~850℃, the rotation speed of the graphite disk to 400r / min~600r / min, introduce NH3 as N source, TEGa as Ga source, SiH4 as Si source, and grow GaN quantum barrier layer.

[0052] S263, InGaN quantum well layers and GaN quantum barrier layers are repeatedly stacked and periodically grown.

[0053] S27. An electron blocking layer 8 is grown on the multi-quantum well layer 7.

[0054] Specifically, in one embodiment, an AlGaN electron blocking layer is grown by MOCVD, with the growth pressure controlled at 100 torr to 200 torr, the growth temperature at 950°C to 1050°C, the rotation speed of the graphite disk at 1000 r / min to 1200 r / min, and NH3 as the N source, TMGa as the Ga source, and TMAl as the Al source.

[0055] S28. A P-type GaN layer 9 is grown on the electron blocking layer 8.

[0056] Specifically, in one embodiment, a P-type GaN layer 9 is grown by MOCVD, with the growth pressure controlled at 100 torr to 200 torr, the growth temperature at 850°C to 1050°C, the rotation speed of the graphite disk at 500 r / min to 1200 r / min, and NH3 as the N source, TMGa as the Ga source, and CP2Mg as the Mg source.

[0057] The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides a highly hydrolysis-resistant LED epitaxial wafer, including a substrate and a buffer layer, a 3D GaN layer, a U-type GaN layer, an N-type GaN layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate.

[0058] The substrate is a sapphire substrate, and the buffer layer is an AlN buffer layer with a thickness of 17 nm. The thickness of the 3D GaN layer is 1.5 μm.

[0059] The U-shaped GaN layer comprises a first U-shaped GaN layer, a low-temperature InGaN insertion layer, a U-shaped GaN transition layer, and a second U-shaped GaN layer, stacked sequentially. The first U-shaped GaN layer has a thickness of 1.5 μm, the low-temperature InGaN insertion layer is grown at 900 °C and has a thickness of 50 Å, the U-shaped GaN transition layer has a thickness of 0.3 μm, and the second U-shaped GaN layer has a thickness of 1.5 μm.

[0060] The N-GaN layer has a thickness of 1.5 μm and a Si doping concentration of 1.5 × 10⁻⁶. 19 atoms / cm 3 .

[0061] The stress relief layer has a periodic structure with 5 periods. Each period consists of sequentially stacked GaN and InGaN stress relief layers. The Si doping concentration of the GaN stress relief layer is 4.5 × 10⁻⁶. 18 atoms / cm 3 The thickness is 250 Å, and the thickness of the InGaN stress relief layer is 40 Å.

[0062] The multi-quantum-well layer has a periodic structure with 15 periods, and each period consists of sequentially stacked In... 0.35 Ga 0.65 N quantum well layer and GaN quantum barrier layer, In 0.35 Ga 0.65 The thickness of the N quantum well layer is 25 Å, the thickness of the GaN quantum barrier layer is 115 Å, and the Si doping concentration is 1.5 × 10⁻⁶. 18 atoms / cm 3 .

[0063] The electron blocking layer is an AlGaN electron blocking layer with an Al content of 0.25% and a thickness of 35nm.

[0064] The thickness of the p-type GaN layer is 20 nm, and the Mg doping concentration is 2.5 × 10⁻⁶. 19 atoms / cm 3 .

[0065] The preparation method of the high hydrolysis resistant LED epitaxial wafer in this embodiment is as follows: S1. Provide a substrate.

[0066] S2. Sequentially grow a buffer layer, a 3D GaN layer, a U-type GaN layer, an N-type GaN layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate. Specifically, S2 includes the following steps: S21. Grow a buffer layer on the substrate.

[0067] Specifically, the buffer layer is an AlN buffer layer, and the growth of the buffer layer includes the following steps: An AlN buffer layer was grown by PVD at a temperature of 650℃ and a power of 3000W. During growth, Ar was used as the sputtering gas, N2 as the precursor, and Al as the sputtering target. The ratio of Ar to N2 was 5:1.

[0068] S22. Grow a 3D GaN layer on the buffer layer.

[0069] Specifically, 3D GaN layers were grown by MOCVD, with the growth pressure controlled at 150 torr, the growth temperature at 1000℃, the rotation speed of the graphite disk at 800 r / min, the carrier gas being H2, and NH3 being introduced as the N source and TMGa as the Ga source.

[0070] S23. Grow a U-shaped GaN layer on a 3D GaN layer.

[0071] Specifically, the U-shaped GaN layer comprises a first U-shaped GaN layer, a low-temperature InGaN insertion layer, a U-shaped GaN transition layer, and a second U-shaped GaN layer stacked sequentially. The growth of the U-shaped GaN layer includes the following steps: S231, control the growth pressure to 150 torr, the growth temperature to 1200℃, the rotation speed of the graphite disk to 1200r / min, the carrier gas to be H2, introduce NH3 as N source and TMGa as Ga source, and grow the first U-shaped GaN layer.

[0072] S232, control the growth pressure to 160 torr, the growth temperature to 900℃, the rotation speed of the graphite disk to 500r / min, introduce NH3 as N source, TMGa as Ga source, TMIn as In source, and grow a low-temperature InGaN insertion layer.

[0073] After growing the low-temperature InGaN insertion layer, the temperature was increased to 1080℃, and the heating time was 100s.

[0074] S233, control the growth pressure to 120 torr, the growth temperature to 1200℃, the rotation speed of the graphite disk to 1200r / min, the carrier gas to be H2, introduce NH3 as N source and TMGa as Ga source, and grow a U-shaped GaN transition layer.

[0075] S234. The growth pressure is controlled at 150 torr, the growth temperature at 1200℃, the rotation speed of the graphite disk is 1200r / min, the carrier gas is H2, NH3 is introduced as the N source, TMGa is introduced as the Ga source, and the second U-shaped GaN layer is grown.

[0076] S24. Grow an N-type GaN layer on a U-type GaN layer.

[0077] Specifically, an N-type GaN layer was grown by MOCVD, with the growth pressure controlled at 300 torr, the growth temperature at 1100℃, the rotation speed of the graphite disk at 1000 r / min, the carrier gas being H2, and NH3 as the N source, TMGa as the Ga source, and SiH4 as the Si source.

[0078] S25. A stress-relieving layer is grown on an N-type GaN layer.

[0079] Specifically, the stress-relieving layer comprises periodically alternating layers of GaN and InGaN stress-relieving layers. The growth of the stress-relieving layer includes the following steps: S251, control the growth pressure to 150 torr, the growth temperature to 850℃, the rotation speed of the graphite disk to 500r / min, introduce NH3 as N source, TMIn as In source, TEGa as Ga source, and grow InGaN stress relief layer.

[0080] S252, control the growth pressure at 150 torr, the growth temperature at 880℃, the rotation speed of the graphite disk at 500 r / min, introduce NH3 as the N source, TEGa as the Ga source, and SiH4 as the Si source to grow the GaN stress relief layer.

[0081] S253, GaN stress-relieving layers and InGaN stress-relieving layers are periodically grown by repeated stacking.

[0082] S26. Grow a multi-quantum-well layer on the stress-relieving layer.

[0083] Specifically, the multi-quantum-well layer comprises periodically alternating layers of InGaN quantum wells and GaN quantum barriers. The growth of the multi-quantum-well layer includes the following steps: S261. The growth pressure is controlled at 180 torr, the growth temperature at 800℃, the rotation speed of the graphite disk is 600 r / min, and NH3 is introduced as the N source, TMIn as the In source, TEGa as the Ga source, and SiH4 as the Si source to grow the InGaN quantum well layer.

[0084] S262, control the growth pressure to 150 torr, the growth temperature to 820℃, the rotation speed of the graphite disk to 500 r / min, introduce NH3 as N source, TEGa as Ga source, SiH4 as Si source, and grow GaN quantum barrier layer.

[0085] S263, InGaN quantum well layers and GaN quantum barrier layers are repeatedly stacked and periodically grown.

[0086] S27. An electron blocking layer is grown on a multi-quantum-well layer.

[0087] Specifically, an AlGaN electron blocking layer was grown by MOCVD, with the growth pressure controlled at 150 torr, the growth temperature at 1000℃, the rotation speed of the graphite disk at 1200 r / min, and NH3 as the N source, TMGa as the Ga source, and TMAl as the Al source.

[0088] S28. Grow a P-type GaN layer on the electron blocking layer.

[0089] Specifically, a P-type GaN layer was grown by MOCVD, with the growth pressure controlled at 120 torr, the growth temperature at 1000℃, the rotation speed of the graphite disk at 800 r / min, and NH3 as the N source, TMGa as the Ga source, and CP2Mg as the Mg source.

[0090] Example 2 This embodiment provides a highly hydrolysis-resistant LED epitaxial wafer, which differs from Embodiment 1 in that the N-type GaN layer includes a periodically alternating first GaN layer and a second GaN layer, with 50 alternating periods. The second GaN layer is a Si-doped GaN layer with a Si doping concentration of 1.5 × 10⁻⁶. 19 atoms / cm 3 .

[0091] Accordingly, the growth of the N-type GaN layer includes the following steps: S241, control the growth pressure to 300 torr, the growth temperature to 1100℃, the rotation speed of the graphite disk to 1100r / min, introduce NH3 as the N source and TMGa as the Ga source, and grow for 6s to grow the first GaN layer.

[0092] S242, control the growth pressure to 300 torr, the growth temperature to 1200℃, the rotation speed of the graphite disk to 1200r / min, introduce NH3 as N source, TMGa as Ga source, SiH4 as Si source, and the growth time to 6s to grow the second GaN layer.

[0093] S243, Repeatedly stack and periodically grow the first GaN layer and the second GaN layer.

[0094] Everything else is the same as in Example 1.

[0095] Comparative Example 1 This comparative example provides a highly hydrolysis-resistant LED epitaxial wafer, which differs from Example 1 in that a low-temperature InGaN insertion layer and a U-shaped GaN transition layer are not inserted into the U-shaped GaN layer. Correspondingly, the fabrication method does not include the preparation of the low-temperature InGaN insertion layer and the U-shaped GaN transition layer. All other aspects are the same as in Example 1.

[0096] The LED epitaxial wafers obtained in Examples 1, 2 and Comparative Example 1 were fabricated into 55mil×55mil chips and subjected to lighting tests under the conditions of 85℃ temperature, 85%RH humidity and -10V reverse voltage. The lighting time was 336h, and performance was tested.

[0097] (1) Light decay rate = (initial luminous flux - luminous flux after lighting test) / initial luminous flux × 100%.

[0098] (2) Failure rate = Number of LEDs that failed after lighting test / Total number of LEDs × 100%.

[0099] (3) Hydrolysis resistance: Observe the surface condition of the chip after the lighting test. If there is no altered layer in the epitaxial structure and no corrosion on the chip surface, it indicates high hydrolysis resistance; if there is an obvious altered layer, dicing corrosion, etc. in the epitaxial structure, it indicates low hydrolysis resistance.

[0100] The specific results are shown in the table below:

[0101] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A highly hydrolysis-resistant LED epitaxial wafer, characterized in that, It includes a substrate and a buffer layer, a 3D GaN layer, a U-type GaN layer, an N-type GaN layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer sequentially stacked on the substrate; wherein, the U-type GaN layer includes a first U-type GaN layer, a low-temperature InGaN insertion layer, a U-type GaN transition layer, and a second U-type GaN layer sequentially stacked.

2. The high hydrolysis-resistant LED epitaxial wafer as described in claim 1, characterized in that, The growth temperature of the low-temperature InGaN insertion layer is 800℃~950℃, and the thickness is 20Å~100Å.

3. The high hydrolysis-resistant LED epitaxial wafer as described in claim 1, characterized in that, The thickness of the U-shaped GaN transition layer is 0.2 μm to 0.5 μm.

4. The high hydrolysis-resistant LED epitaxial wafer as described in claim 1, characterized in that, The thickness of the first U-shaped GaN layer is 1μm~2μm, and the thickness of the second U-shaped GaN layer is 1μm~2μm.

5. The high hydrolysis-resistant LED epitaxial wafer as described in claim 1, characterized in that, The thickness of the N-type GaN layer is 1.4 μm to 1.6 μm. The N-type GaN layer comprises a first GaN layer and a second GaN layer that are periodically stacked alternately, with 40 to 60 alternating periods. The second GaN layer is a Si-doped GaN layer with a Si doping concentration of 1 × 10⁻⁶. 19 atoms / cm 3 ~2×10 19 atoms / cm 3 .

6. The high hydrolysis-resistant LED epitaxial wafer as described in claim 1, characterized in that, The stress relief layer comprises periodically alternating GaN stress relief layers and InGaN stress relief layers, with 3 to 6 alternating periods. The GaN stress relief layer is a Si-doped GaN layer with a Si doping concentration of 4 × 10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3 The InGaN stress relief layer has a thickness of 200 Å to 300 Å, and the In composition ratio is 0.1 to 0.2, with a thickness of 30 Å to 50 Å.

7. A method for preparing a highly hydrolysis-resistant LED epitaxial wafer, used to prepare the highly hydrolysis-resistant LED epitaxial wafer as described in any one of claims 1 to 6, characterized in that, Includes the following steps: A substrate is provided on which a buffer layer, a 3D GaN layer, a U-type GaN layer, an N-type GaN layer, a stress relief layer, a multiple quantum well layer, an electron blocking layer, and a P-type GaN layer are sequentially grown; wherein the U-type GaN layer comprises a first U-type GaN layer, a low-temperature InGaN insertion layer, a U-type GaN transition layer, and a second U-type GaN layer stacked sequentially.

8. The method for preparing a highly hydrolysis-resistant LED epitaxial wafer as described in claim 7, characterized in that, The U-shaped GaN layer is prepared using the following steps: The growth pressure was controlled at 100 torr to 200 torr, the growth temperature at 1100℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, the carrier gas was H2, and the N source and Ga source were introduced to grow the first U-shaped GaN layer. The growth pressure was controlled at 100 torr to 200 torr, the growth temperature at 800℃ to 950℃, and the rotation speed at 400 r / min to 600 r / min. N source, In source and Ga source were introduced to grow a low-temperature InGaN insertion layer. The growth pressure was controlled at 100 torr to 200 torr, the growth temperature at 1100℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, and the carrier gas was H2. N source and Ga source were introduced to grow U-shaped GaN transition layer. The growth pressure was controlled at 100 torr to 200 torr, the growth temperature at 1100℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, and the carrier gas was H2. N source and Ga source were introduced to grow the second U-shaped GaN layer.

9. The method for preparing a highly hydrolysis-resistant LED epitaxial wafer as described in claim 8, characterized in that, After growing the low-temperature InGaN insertion layer, the temperature is increased to 1050℃~1100℃, and the heating time is 30s~150s.

10. The method for preparing a high hydrolysis-resistant LED epitaxial wafer as described in claim 7, characterized in that, The N-type GaN layer is prepared using the following steps: The growth pressure was controlled at 200 torr to 400 torr, the growth temperature at 1080℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, and N source and Ga source were introduced. The growth time was 5s to 8s to grow the first GaN layer. The growth pressure was controlled at 200 torr to 400 torr, the growth temperature at 1080℃ to 1250℃, the rotation speed at 1000 r / min to 1200 r / min, and N source, Ga source and Si source were introduced. The growth time was 5s to 8s to grow the second GaN layer. The first and second GaN layers are grown periodically by repeated stacking.

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