Semiconductor chip
By setting bumps of different sizes on semiconductor chips, the high production cost problem caused by fixed bump size in the prior art is solved, and the test effect is maintained while the cost is reduced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-11
- Publication Date
- 2026-03-13
AI Technical Summary
In existing technologies, the size of the bumps on semiconductor chips is fixed during chip probe testing, resulting in high production costs.
On a semiconductor chip, the size of the first bump used for chip probe testing remains unchanged, while the size of the second bump not used for chip probe testing is reduced, thereby reducing production costs by using gold bump material.
By reducing the size of bumps not used for chip probe testing, production costs are reduced, while the size of bumps used for testing remains unchanged to ensure testing effectiveness.
Smart Images
Figure CN121666028A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a semiconductor chip. Background Technology
[0002] Chip probe (CP) testing is a critical step in semiconductor manufacturing, situated between wafer fabrication and chip packaging. CP testing verifies the electrical characteristics and functionality of each semiconductor chip at the wafer level. During CP testing, automated test equipment (ATE) uses probe cards connected to the bumps of each semiconductor chip, applying predetermined test signals to test whether the semiconductor chip meets default performance standards, such as operating voltage, current consumption, signal timing, and whether specific functions are executed correctly. Summary of the Invention
[0003] This invention provides a semiconductor chip in which the size of bumps used for chip probe testing remains constant, while the size of bumps not used for chip probe testing is reduced. Since the bumps are typically made of gold, reducing the size of the bumps can reduce production costs.
[0004] The semiconductor chip of an embodiment of the present invention includes a plurality of first bonding pads, a plurality of second bonding pads, a plurality of first bumps, and a plurality of second bumps. The first bonding pads and second bonding pads are arranged along the long side direction of the active surface of the semiconductor chip. The first bumps are disposed on the first bonding pads and are used for chip probe testing. The second bumps are disposed on the second bonding pads and are not used for chip probe testing. The size of the first bumps is larger than the size of the second bumps. Attached Figure Description
[0005] Figure 1A and Figure 1B This is a top view schematic diagram of the semiconductor chip shown in an embodiment of the present invention;
[0006] Figure 2A yes Figure 1B A three-dimensional schematic diagram of the semiconductor chip in the embodiment;
[0007] Figure 2B yes Figure 1B A three-dimensional schematic diagram of the first and second protrusions in the embodiment;
[0008] Figure 3 This is a top view schematic diagram of a semiconductor chip shown in another embodiment of the present invention;
[0009] Figure 4 This is a top view schematic diagram of a semiconductor chip shown in another embodiment of the present invention;
[0010] Figure 5 This is a schematic diagram of an integrated circuit shown in an embodiment of the present invention. Detailed Implementation
[0011] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.
[0012] Figure 1A and Figure 1B This is a top view schematic diagram of the semiconductor chip 100 according to an embodiment of the present invention. Please refer to... Figure 1A and Figure 1B The semiconductor chip 100 includes a plurality of first bonding pads PD1, a plurality of second bonding pads PD2, a plurality of first bumps BP1, and a plurality of second bumps BP2. The first bonding pads PD1 and the second bonding pads PD2 are arranged along the long side SL direction X of the active surface S1 of the semiconductor chip 100. The active surface S1 is the surface of the semiconductor chip 100 on which the first bonding pads PD1 and the second bonding pads PD2 are arranged.
[0013] Semiconductor chip 100 can be disposed on thin-film substrate 110 to form a thin-film flip package. Taking a display driver IC as an example, the display driver IC is typically bonded to a flexible substrate using gold bumps. The gold bumps are grown on the chip pads during the wafer (wafer) bump fabrication process, and in chip probe testing, probes on a probe card contact the bumps to perform electrical tests.
[0014] exist Figure 1A In this embodiment, the size of the first pad PD1 is larger than the size of the second pad PD2. For example, the length L3 of the first pad PD1 is greater than the length L4 of the second pad PD2, wherein the length L3 of the first pad PD1 and the length L4 of the second pad PD2 extend in the Y direction of the short side SS of the active surface S1. However, the present invention is not limited thereto.
[0015] Figure 1B The bump configuration is further illustrated. For chip probe testing, the configuration of the first bump BP1 and the second bump BP2 corresponds to the probe configuration of the probe card. Specifically, the first bump BP1, used for chip probe testing, is configured on the first pad PD1, and the second bump BP2, not used for chip probe testing, is configured on the second pad PD2. The size of the first bump BP1 is larger than the size of the second bump BP2.
[0016] Figure 2A Show Figure 1B A three-dimensional schematic diagram of the semiconductor chip in the embodiment. Figure 2B Show Figure 1B A three-dimensional schematic diagram of the first protrusion BP1 and the second protrusion BP2 in the embodiment. Please refer to... Figure 2A and Figure 2BIn this embodiment, the second length L2 of the second bump BP2 is less than the first length L1 of the first bump BP1, wherein the first length L1 of the first bump BP1 and the second length of the second bump BP2 extend in the short side SS direction Y of the active surface S1.
[0017] Furthermore, the first height H1 of the first bump BP1 is equal to the second height H2 of the second bump BP2. The first width W1 of the first bump BP1 is also equal to the second width W2 of the second bump BP2, wherein the first width W1 of the first bump BP1 and the second width W2 of the second bump BP2 extend along the long side SL direction X of the active surface S1. In another embodiment, the first bump BP1 and the second bump BP2 may have different widths and / or heights, but have the same length along the short side SS direction Y.
[0018] Figure 3 This is a top view schematic diagram of a semiconductor chip according to another embodiment of the present invention. Please refer to... Figure 3 An equal number of second bumps BP2 are disposed between two first bumps BP1. For example, seven second bumps BP2 are disposed between first bumps 301 and 309, and seven second bumps BP2 are disposed between first bumps 309 and 317, and so on. The number of second bumps BP2 is for illustrative purposes only and is not intended to limit the invention.
[0019] Figure 4 This is a top view schematic diagram of a semiconductor chip 400 according to another embodiment of the present invention. Please refer to... Figure 4 Different numbers of second bumps BP2 are periodically arranged between two first bumps BP1. For example, four second bumps BP2 are arranged between first bumps 401 and 406, and ten second bumps BP2 are arranged between first bumps 417 and 422. That is, in this example, four and ten second bumps BP2 are periodically arranged between two first bumps BP1. The number of second bumps BP2 is for illustrative purposes only and is not intended to limit the invention.
[0020] Figure 5 This is a schematic diagram of an integrated circuit according to an embodiment of the present invention. Please refer to... Figure 1B and Figure 5 ,like Figure 5 As shown, the semiconductor chip 100 includes a display driver integrated circuit 500. The integrated circuit 500 includes multiple display driver channels 510. The display driver channels 510 output data voltages to a display panel (not shown). A first pad PD1 and a second pad PD2 are connected to the output terminals of their respective display driver channels 510.
[0021] In this embodiment, the chip probe test is a multi-point chip probe test. During the chip probe test, hundreds or thousands of display driver channels 510 are grouped and tested sequentially via a switching circuit 512 within the integrated circuit. The switching circuit 512 is used for CP testing. For example, every 16 display driver channels 510 are grouped for chip probe testing, where two output bumps (labeled 16N+1 and 16N+6) are selected for probing. Other output bumps (labeled 16N+2 to 16N+5 and 16N+7 to 16N+16) are not selected for probing. During the CP test, the outputs of the 16 display driver channels 510 are connected one by one to one of the two probing output bumps (labeled 16N+1 and 16N+6) via the switching circuit 512. Therefore, the number of bumps required for chip probe testing is relatively small.
[0022] On the other hand, in this embodiment, the semiconductor chip 100 may be a display driver integrated circuit for driving a display panel. The first bump BP1 and the second bump BP2 are used to connect to the data lines of the display panel via inner and outer pins disposed on the thin-film substrate. In another embodiment, the semiconductor chip 100 may be a touch driver integrated circuit for driving a touch panel or a touch display driver integrated circuit for driving a touch display panel. In this example, the semiconductor chip 100 may include a plurality of third bumps and a plurality of fourth bumps connected to the touch sensing lines of the touch panel or the touch display panel, and its implementation is similar to that of the first bump BP1 and the second bump BP2 described in the foregoing embodiments.
[0023] In summary, in the embodiments of the present invention, in the wafer bump fabrication process of the display driver integrated circuit, the size of the bumps used for chip probe testing remains unchanged, while the size of the bumps not used for chip probe testing is reduced. Since the material of the bumps is typically gold, reducing the size of the bumps can reduce production costs.
[0024] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A semiconductor chip, comprising: Multiple first bonding pads and multiple second bonding pads are arranged along the long side of the active surface of the semiconductor chip; Multiple first bumps are disposed on the first solder pad and are used for chip probe testing; Multiple second bumps are disposed on the second pad and are not used for the chip probe test, wherein the size of the first bump is larger than the size of the second bump.
2. The semiconductor chip of claim 1, wherein the first bump includes a first length, the second bump includes a second length less than the first length, and the first length of the first bump and the second length of the second bump extend in the short side direction of the active surface.
3. The semiconductor chip of claim 2, wherein the first bump includes a first width, the second bump includes a second width equal to the first width, and the first width of the first bump and the second width of the second bump extend in the long side direction of the active surface.
4. The semiconductor chip according to claim 3, wherein the first bump includes a first height, the second bump includes a second height, and the first height is equal to the second height.
5. The semiconductor chip according to claim 1, wherein the first bonding pad and the second bonding pad have the same size.
6. The semiconductor chip according to claim 1, wherein the size of the first bonding pad is larger than the size of the second bonding pad.
7. The semiconductor chip of claim 1, further comprising an integrated circuit, wherein the integrated circuit comprises: Multiple display drive channels are provided for outputting data voltages to a display panel, wherein the first pad and the second pad are connected to the output terminals of their respective display drive channels.
8. The semiconductor chip of claim 7, wherein the semiconductor chip is disposed on a thin-film substrate to form a thin-film flip package, and the first bump and the second bump are configured to be connected to data lines of the display panel via inner and outer pins disposed on the thin-film substrate.
9. The semiconductor chip of claim 1, wherein the first bump and the second bump are connected to the touch sensing line of the touch panel or the touch display panel.
10. The semiconductor chip of claim 1, wherein the configuration of the first bump and the second bump corresponds to the probe configuration of the probe card.
11. The semiconductor chip of claim 1, wherein the same number of second bumps are disposed between two of the first bumps.
12. The semiconductor chip of claim 1, wherein a different number of the second bumps are periodically disposed between two of the first bumps.