Fuse structure and manufacturing method thereof

Abstract

The invention provides a fuse structure and a manufacturing method thereof, and the method comprises the steps: carrying out the ion implantation of an upper surface layer of a polysilicon patterned layer after the polysilicon patterned layer is formed, so as to obtain a pre-amorphization layer with a preset thickness, and forming a metal seed layer on the pre-amorphization layer, and performing heat treatment to diffuse part of metal in the metal seed layer to the pre-amorphization layer, and then removing the metal seed layer. Because the metal is easier to diffuse in the non-crystallized silicon, the metal silicide layer with more stable thickness can be formed. According to the fuse structure, the thickness fluctuation of the metal silicide layer is small, so that the resistance consistency of the fuse is higher, and the melting point current and time are more stable.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a fuse structure and its fabrication method. Background Technology

[0002] With the advancement of integrated circuit design, chip design processes are becoming increasingly complex, inevitably introducing more defects and reducing chip yield. To improve chip yield, redundancy technology is constantly evolving. Electronic fuse (E-fuse) technology has been widely used in redundancy circuits to mitigate chip failure issues. The programming principle of E-fuse utilizes the theory of electromigration. The anode is connected to the programming voltage, and the cathode is grounded. Even with a voltage difference between the two electrodes, their potentials differ, and a stable, relatively large current flows through the fuse. Due to the significant difference in resistivity between silicide alloys and polycrystalline silicon, the current primarily concentrates in the polycrystalline silicon alloy layer. Electromigration first occurs in this layer of the device, leading to a large number of atomic movements and the formation of voids. This causes the fuse to exhibit a high resistance, which can be considered as an open circuit, and this open circuit is permanent. Therefore, the E-fuse circuit uses the difference in resistance before and after programming to store the circuit value. Currently, E-fuse technology is under continuous research, with the goal of achieving smaller area occupancy, lower programming current, and lower compilation voltage. This poses greater challenges to the development of E-fuse structure and performance, especially in terms of fuse linkwidth, fusing current, and fusing time.

[0003] In E-fuse development, extensive layout and design of experiments (DOE) are conducted, such as adjusting polysilicon, silicide, contact (CT), and implantation, to confirm the E-fuse structure and process conditions. One drawback of this method is that silicide thickness can fluctuate, leading to inconsistent E-fuse resistance and affecting melting point current and melting time.

[0004] Therefore, how to improve the silicide thickness stability of the fuse structure has become an important technical problem that needs to be solved by those skilled in the art.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a fuse structure and its manufacturing method, which solves the problems of easy fluctuation in silicide thickness and low testing efficiency in the prior art fuse structure.

[0007] To achieve the above and other related objectives, the present invention provides a method for manufacturing a fuse, comprising the following steps:

[0008] A gate structure is provided, the gate structure comprising: two sidewalls and a polysilicon patterning layer between the two sidewalls;

[0009] Ion implantation is performed on the upper surface of the polycrystalline silicon patterned layer to obtain a pre-amorphous layer of a predetermined thickness;

[0010] A metal seed layer is formed on the pre-amorphized layer;

[0011] Heat treatment is performed to allow the metal elements in the metal seed layer to diffuse into the pre-amorphized layer;

[0012] The metal seed layer is removed to obtain the fuse.

[0013] Optionally, the thickness of the pre-amorphized layer is less than or equal to half the thickness of the polycrystalline silicon patterned layer before ion implantation.

[0014] Optionally, the dose range of the ion implantation is 1×10⁻⁶. 14 cm -2 ~1×10 15 cm -2 The energy range is 45 keV to 65 keV.

[0015] Optionally, at the end of the ion implantation, the ion implantation depth is one-third of the thickness of the polysilicon patterned layer before ion implantation.

[0016] Optionally, the method further includes: providing a substrate, wherein the gate structure is formed above the substrate, a shallow trench isolation structure is provided in the substrate, the shallow trench isolation structure surrounds an active region in the substrate, and the fuse structure is located on the shallow trench isolation structure.

[0017] Optionally, before performing heat treatment to allow the metal elements in the metal seed layer to diffuse into the pre-amorphized layer, the method further includes forming a barrier layer on the metal seed layer.

[0018] Optionally, removing the metal seed layer includes removing both the barrier layer and the metal seed layer.

[0019] Optionally, the metal seed layer may include a NiPt alloy layer.

[0020] Optionally, the ion is Ge or Si.

[0021] On the other hand, the present invention provides a fuse structure, comprising:

[0022] Anode section;

[0023] Cathode section;

[0024] A fuse section is connected between the anode section and the cathode section;

[0025] The fuse structure is formed using the fuse manufacturing method described above.

[0026] As described above, the fuse fabrication method of the present invention involves, after forming a polycrystalline silicon patterned layer, first performing ion implantation on the upper surface of the polycrystalline silicon patterned layer to obtain a pre-amorphous layer of a predetermined thickness, then forming a metal seed layer on the pre-amorphous layer, followed by heat treatment to allow some of the metal in the metal seed layer to diffuse into the pre-amorphous layer, and finally removing the metal seed layer. Because metal diffuses more easily in amorphous silicon, a more stable metal silicide layer can be formed, resulting in higher fuse resistance consistency and more stable melting point current and time. Attached Figure Description

[0027] Figure 1 The image shown is a top view of a fuse structure.

[0028] Figure 2 Displayed as Figure 1 The cross-sectional view of the fuse structure shown.

[0029] Figure 3 The diagram shown is a process flow diagram of the method for manufacturing the fuse of the present invention.

[0030] Figure 4 The diagram shown illustrates the structure obtained after forming a polycrystalline silicon patterned layer and sidewalls using the fuse fabrication method of the present invention.

[0031] Figure 5 The diagram shown illustrates the structure obtained after ion implantation of the upper surface layer of a polycrystalline silicon patterned layer to obtain a pre-amorphous layer of a predetermined thickness, as described in the fuse fabrication method of the present invention.

[0032] Figure 6 The diagram shown illustrates the structure obtained after forming a metal seed layer on a pre-amorphized layer using the fuse fabrication method of the present invention.

[0033] Figure 7 The diagram shown illustrates the structure obtained after forming a barrier layer on a metal seed layer using the fuse manufacturing method of the present invention.

[0034] Figure 8The diagram shows the structure obtained after heat treatment to obtain a metal silicide layer, which is a method for manufacturing the fuse of the present invention.

[0035] Figure 9 The diagram shown illustrates the structure obtained after removing the barrier layer and the metal seed layer in the method for manufacturing the fuse according to the present invention.

[0036] Figure 10 The image shown is a top view of the fuse structure of the present invention.

[0037] Component designation explanation

[0038] 101 Anode section

[0039] 102 Fuse Section

[0040] 103 Cathode section

[0041] 104 Shallow trench isolation structure

[0042] 105 polycrystalline silicon layer

[0043] 106 Metal silicide layer

[0044] Steps S1 to S5

[0045] 201 Polysilicon Patterning Layer

[0046] 202 Side Wall

[0047] 203 Shallow trench isolation structure

[0048] 204 pre-amorphous layer

[0049] 205 Metal Seed Layer

[0050] 206 Barrier Layer

[0051] 207 Metal silicide layer

[0052] 301 Anode Section

[0053] 302 Cathode Section

[0054] 303 Fuse Section

[0055] 304 metal silicide layer Detailed Implementation

[0056] Please see Figure 1 The image shows a top view of a fuse structure, including an anode section 101, a fuse section 102, and a cathode section 103 connected in sequence. Please refer to [link / reference]. Figure 2 Displayed as Figure 1The cross-sectional view of the fuse structure shown is shown, wherein the fuse structure is fabricated on a shallow trench isolation structure 104. The fuse structure includes a polysilicon layer 105 and a metal silicide layer 106 located on the upper surface of the polysilicon layer 105. The polysilicon layer 105 has sidewalls 202 on both sides. Figure 1 and Figure 2 In the fuse structure shown, the thickness of the metal silicide layer 106 is prone to fluctuation, resulting in inconsistent fuse resistance and affecting the melting point current and time.

[0057] This invention improves the manufacturing method of the fuse, making the thickness of the metal silicide layer more stable. In the fuse structure of this invention, due to the small fluctuation in the thickness of the metal silicide layer, the fuse resistance is more consistent, and the melting point current and time are more stable.

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] Please see Figures 3 to 10 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] Example 1

[0061] This embodiment provides a method for fabricating a fuse structure. Please refer to [link / reference]. Figure 3 The diagram shows the process flow of this method, which includes the following steps:

[0062] S1: A gate structure is provided, the gate structure comprising: two sidewalls and a polysilicon patterning layer between the two sidewalls;

[0063] S2: Ion implantation is performed on the upper surface of the polycrystalline silicon patterned layer to obtain a pre-amorphous layer of a predetermined thickness;

[0064] S3: Form a metal seed layer on the pre-amorphized layer;

[0065] S4: Perform heat treatment to allow some of the metal in the metal seed layer to diffuse into the pre-amorphized layer;

[0066] S5: Remove the metal seed layer to obtain a fuse structure composed of the polysilicon patterning layer and the metal silicide layer.

[0067] The steps described above are explained in detail below with reference to the accompanying diagram.

[0068] Please refer to the following first. Figure 4 Step S1 is performed: a gate structure is provided, the gate structure including: two side walls 202 and a polysilicon patterning layer 201 between the two side walls 202.

[0069] Specifically, step S1 may include the following process: providing a substrate having a fuse structure forming region, the fuse structure forming region including an anode region, a fuse region and a cathode region connected in sequence; forming a polysilicon layer on the substrate; etching the polysilicon layer to obtain a polysilicon patterned layer 201 located in the fuse structure forming region; forming sidewalls 202 on both sides of the polysilicon patterned layer 201.

[0070] As an example, the substrate may be a silicon substrate or other suitable semiconductor substrate, wherein a shallow trench isolation structure 203 is provided in the substrate, the shallow trench isolation structure 203 surrounds an active region in the substrate, and the fuse structure forming region is located on the shallow trench isolation structure.

[0071] Specifically, the polysilicon patterned layer 201 can be obtained by first depositing a polysilicon layer and then patterning the polysilicon layer using semiconductor processes such as photolithography and etching. The sidewall 202 can be a silicon nitride sidewall, used to protect the side of the polysilicon patterned layer 201.

[0072] Please see again Figure 5 Step S2 is performed: Ion implantation is performed on the upper surface of the polycrystalline silicon patterned layer 201 to obtain a pre-amorphous layer 204 of a preset thickness.

[0073] As an example, the thickness of the pre-amorphous layer 204 is less than or equal to half the thickness of the polysilicon patterned layer 201 before ion implantation. For example, in one embodiment, the thickness of the pre-amorphous layer 204 is one-quarter of the thickness of the polysilicon patterned layer 201. The thickness of the pre-amorphous layer 204 should not be too thin or too thick. If it is too thin, the resistance of the fuse structure will be too high, while if it is too thick, the cost will increase significantly without significantly improving the performance.

[0074] Specifically, the depth of ion implantation can be controlled by adjusting the energy of ion implantation, thereby obtaining the required pre-amorphized layer thickness.

[0075] As an example, the ion implantation depth is less than the thickness of the final metal silicide layer. For instance, in one embodiment, the thickness of the final metal silicide layer to be formed is half the thickness of the polysilicon patterned layer 201 before ion implantation. Therefore, at the end of ion implantation, the ion implantation depth is controlled to be only about one-third of the thickness of the polysilicon patterned layer before ion implantation. After ion implantation ends, the ions can still penetrate down to a certain thickness, for example, to half the thickness of the polysilicon patterned layer 201 before ion implantation, thereby making the manufacturing process more standardized and the corresponding fuse resistance value more stable.

[0076] It should be noted that the term "approximately" in this invention means that the positive or negative deviation from the specified thickness or depth does not exceed 10%.

[0077] As an example, the dose range of the ion implantation is 1 × 10⁻⁶. 14 cm -2 ~1×10 15 cm -2 The energy range is 45 keV to 65 keV.

[0078] As an example, the ion can be Ge or Si.

[0079] Please see again Figure 6 Then, perform step S3: form a metal seed layer 205 on the pre-amorphous layer 204 using sputtering or other suitable methods.

[0080] As an example, the metal seed layer 205 includes a NiPt alloy layer so that a nickel silicide layer can be subsequently obtained.

[0081] As an example, the step of forming a barrier layer on the metal seed layer 205 is also included; please refer to [link to relevant documentation]. Figure 7 The diagram shows the structure obtained after the barrier layer 206 is formed on the metal seed layer 205 by sputtering or other suitable methods.

[0082] Specifically, the barrier layer 206 is used to prevent the metal in the metal seed layer 205 from diffusing upwards. In some embodiments, the barrier layer 206 includes a TiN layer.

[0083] Please see again Figure 8 Step S4 is performed: heat treatment is carried out to allow the metal elements in the metal seed layer 205 to diffuse into the pre-amorphous layer 204.

[0084] Specifically, the metal elements in the metal seed layer 205 diffuse into the pre-amorphized layer 204 to obtain the metal silicide layer 207.

[0085] As an example, the heat treatment includes rapid thermal annealing (RTA).

[0086] Specifically, during the heat treatment process, some of the metal in the metal seed layer 205, such as some of the Ni in the NiPt alloy layer, diffuses downward into the pre-amorphous layer 204. Compared to the polycrystalline silicon layer without ion implantation, NiPt diffuses more easily in the pre-amorphous layer 204, which is beneficial for obtaining NiSi metal silicide with a more stable thickness.

[0087] Please see again Figure 9 Then, perform step S5: remove the metal seed layer 205 to obtain the fuse.

[0088] Specifically, the fuse is composed of the polysilicon patterning layer 201 and the metal silicide layer 207.

[0089] Thus, a fuse is produced. In the fuse production method of the present invention, before the metal silicide is formed, a pre-amorphous layer of a certain thickness is first formed on the upper surface of the polycrystalline silicon patterned layer by ion implantation. In subsequent steps, the metal diffuses more easily in the amorphous silicon, that is, the diffusion speed is faster, which helps to form a metal silicide layer with a more uniform and stable thickness.

[0090] Example 2

[0091] This embodiment provides a fuse structure, which is formed using the fuse structure manufacturing method described in Embodiment 1.

[0092] Please see Figure 10 The diagram shows a top view of the fuse structure, which includes an anode portion 301, a cathode portion 302, and a fuse portion 303, wherein the fuse portion 303 is connected between the anode portion 301 and the cathode portion 302.

[0093] Specifically, the fuse structure includes a polysilicon patterned layer and a metal silicide layer located on the upper surface of the polysilicon patterned layer.

[0094] Specifically, the thickness of the metal silicide layer can be set according to actual needs. For example, in one embodiment, the thickness of the metal silicide layer is half the thickness of the polysilicon patterning layer before ion implantation.

[0095] Specifically, the width of the fuse portion 303 is smaller than the width of the anode portion 301 and smaller than the width of the cathode portion 302.

[0096] Specifically, the dimensions of the anode portion 301, the cathode portion 302, and the fuse portion 303, such as length, width, and thickness, can be adjusted according to actual needs, and no specific limitations are imposed in this invention.

[0097] In this embodiment of the fuse structure, the thickness of the metal silicide layer is more stable, resulting in higher consistency in fuse resistance and more stable melting point current and time. This fuse structure can be applied to redundant circuits to improve chip failure issues, exhibiting more stable performance. It can also be used as a component of test structures during the development of fuse structure and performance.

[0098] In summary, the fuse fabrication method of the present invention, after forming a polycrystalline silicon patterned layer, first performs ion implantation on the upper surface of the polycrystalline silicon patterned layer to obtain a pre-amorphous layer of a predetermined thickness, then forms a metal seed layer on the pre-amorphous layer, and then performs heat treatment to allow some of the metal in the metal seed layer to diffuse into the pre-amorphous layer, after which the metal seed layer is removed. Because metal diffuses more easily in amorphous silicon, a more stable metal silicide layer can be formed, resulting in higher fuse resistance consistency and more stable melting point current and time. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0099] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a fuse, characterized in that, Includes the following steps: A gate structure is provided, the gate structure comprising: two sidewalls and a polysilicon patterning layer between the two sidewalls; Ion implantation is performed on the upper surface of the polycrystalline silicon patterned layer to obtain a pre-amorphous layer of a predetermined thickness; A metal seed layer is formed on the pre-amorphized layer; Heat treatment is performed to allow the metal elements in the metal seed layer to diffuse into the pre-amorphized layer; The metal seed layer is removed to obtain the fuse.

2. The method for manufacturing a fuse according to claim 1, characterized in that: The thickness of the pre-amorphized layer is less than or equal to half the thickness of the polycrystalline silicon patterned layer before ion implantation.

3. The method for manufacturing a fuse according to claim 1, characterized in that: The dose range of the ion implantation is 1×10⁻⁶. 14 cm -2 ~1×10 15 cm -2 The energy range is 45 keV to 65 keV.

4. The method for manufacturing a fuse according to claim 1, characterized in that: At the end of the ion implantation, the ion implantation depth is one-third of the thickness of the polysilicon patterned layer before ion implantation.

5. The method for manufacturing a fuse according to claim 1, characterized in that: The method further includes: providing a substrate, wherein the gate structure is formed above the substrate, a shallow trench isolation structure is provided in the substrate, the shallow trench isolation structure surrounds an active region in the substrate, and the fuse structure is located on the shallow trench isolation structure.

6. The method for manufacturing a fuse according to claim 1, characterized in that: Before performing heat treatment to allow the metal elements in the metal seed layer to diffuse into the pre-amorphized layer, the method further includes forming a barrier layer on the metal seed layer.

7. The method for manufacturing a fuse according to claim 6, characterized in that: The removal of the metal seed layer includes: Remove the barrier layer and the metal seed layer.

8. The method for manufacturing a fuse according to claim 1, characterized in that: The metal seed layer includes a NiPt alloy layer.

9. The method for manufacturing a fuse according to claim 1, characterized in that: The ions are Ge or Si.

10. A fuse structure, characterized in that, include: Anode section; Cathode section; A fuse section is connected between the anode section and the cathode section; The fuse structure is formed using the fuse manufacturing method as described in any one of claims 1-9.

Images