Mother substrate for display device and display device

Abstract

The invention provides a mother substrate for a display device and the display device. According to one embodiment, a mother substrate for a display device includes a plurality of panel portions, a display element disposed in a display region, a rib layer having a pixel opening overlapping the display element, and an inspection pad disposed in a peripheral region. The inspection pad has a first metal layer and a second metal layer overlapping the first metal layer. The rib layer is disposed between the first metal layer and the second metal layer and has a first opening for the second metal layer and the first metal layer to come into contact with each other, and the first metal layer has a first layer formed of a first metal material, a second layer formed of a second metal material and overlapping the first layer, and a third layer formed of the first metal material and overlapping the second layer. The third layer has a region that exposes the second layer in the first opening. The second metal layer has a first contact portion that is in contact with the second layer in the region and a second contact portion that is in contact with the third layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2024-157569, filed on September 11, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a mother substrate for a display device and a display device. Background Technology

[0004] In recent years, display devices using organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In such display devices, technologies are needed to suppress reliability degradation. Summary of the Invention

[0005] Generally, according to the embodiments, the mother substrate for the display device includes: a plurality of panel portions having a display area and a peripheral area surrounding the display area; a display element disposed in the display area; a rib layer disposed in the display area and the peripheral area, and having pixel openings overlapping with the display element; and an inspection pad disposed in the peripheral area. The inspection pad has a first metal layer and a second metal layer overlapping the first metal layer. The rib layer is disposed between the first metal layer and the second metal layer, and further has a first opening for contact between the second metal layer and the first metal layer. The first metal layer has a first layer formed of a first metal material, a second layer formed of a second metal material and overlapping the first layer, and a third layer formed of the first metal material and overlapping the second layer. The third layer has a region in the first opening that exposes the second layer. The second metal layer has a first contact portion that contacts the second layer in the region and a second contact portion that contacts the third layer.

[0006] According to other embodiments, a mother substrate for a display device includes: a plurality of panel portions having a display area and a peripheral area surrounding the display area; a display element disposed in the display area; a rib layer disposed in the display area and the peripheral area, and having pixel openings overlapping the display element; and an inspection pad disposed in the peripheral area. The inspection pad has a first metal layer and a second metal layer overlapping the first metal layer. The rib layer is disposed between the first metal layer and the second metal layer, and has a first opening for contact between the second metal layer and the first metal layer. The first metal layer has a first layer formed of a first metal material, a second layer formed of a second metal material and overlapping the first layer, and a third layer formed of the first metal material and overlapping the second layer. The second metal layer has a fourth layer formed of the first metal material, a fifth layer formed of the second metal material and overlapping the fourth layer, and a sixth layer formed of the first metal material and overlapping the fifth layer. The inspection pad has a first part and a second part, the first part being stacked with the first layer, the second layer, the fourth layer, the fifth layer and the sixth layer, and the second part being stacked with the first layer, the second layer, the third layer, the fourth layer, the fifth layer and the sixth layer.

[0007] According to another embodiment, a display device includes: a display area; a peripheral area surrounding the display area; a display element disposed in the display area; a rib layer disposed in the display area and the peripheral area, and having pixel openings overlapping the display element; and an inspection pad disposed in the peripheral area. The inspection pad has a first metal layer and a second metal layer overlapping the first metal layer. The rib layer is disposed between the first metal layer and the second metal layer, and has a first opening for contact between the second metal layer and the first metal layer. The first metal layer has a first layer formed of a first metal material, a second layer formed of a second metal material and overlapping the first layer, and a third layer formed of the first metal material and overlapping the second layer. The third layer has a region in the first opening exposing the second layer. The second metal layer has a first contact portion contacting the second layer in the region, and a second contact portion contacting the third layer.

[0008] Based on this structure, it is possible to provide a motherboard for a display device and a display device that can suppress reliability degradation. Attached Figure Description

[0009] Figure 1 This is a top view showing a schematic structural example of the display device according to the first embodiment.

[0010] Figure 2This is a schematic top view of an example of the layout of subpixels.

[0011] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device along line III-III.

[0012] Figure 4 This is a schematic top view of the mother substrate of the first embodiment.

[0013] Figure 5 This is a schematic top view of a portion of the mother substrate.

[0014] Figure 6 It is along Figure 5 A schematic cross-sectional view of the display device with the VI-VI line.

[0015] Figure 7 It means Figure 6 A magnified view of part VII in the image.

[0016] Figure 8 It means Figure 6 A magnified view of part VIII in the image.

[0017] Figure 9 This is a flowchart illustrating an example of a method for manufacturing a display device.

[0018] Figure 10A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0019] Figure 10B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0020] Figure 11A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0021] Figure 11B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0022] Figure 12A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0023] Figure 12B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0024] Figure 13A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0025] Figure 13B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0026] Figure 14AIt is a schematic cross-sectional view showing the manufacturing process of the display device.

[0027] Figure 14B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0028] Figure 15A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0029] Figure 15B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0030] Figure 16A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0031] Figure 16B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0032] Figure 17A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0033] Figure 17B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0034] Figure 18A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0035] Figure 18B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0036] Figure 19A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0037] Figure 19B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0038] Figure 20A It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0039] Figure 20B It is a schematic cross-sectional view showing the manufacturing process of the display device.

[0040] Figure 21 It is a schematic cross-sectional view showing the process of forming the display element.

[0041] Figure 22 It is a schematic cross-sectional view showing the process of forming the display element.

[0042] Figure 23 It is a schematic cross-sectional view showing the process of forming the display element.

[0043] Figure 24It is a schematic cross-sectional view showing the process of forming the display element.

[0044] Figure 25 This is a diagram used to illustrate and inspect the openings where pads overlap.

[0045] Figure 26 This is a schematic cross-sectional view showing the manufacturing process of the comparative example display device.

[0046] Figure 27 This is a schematic cross-sectional view showing the manufacturing process of the comparative example display device.

[0047] Figure 28 This is a schematic cross-sectional view showing the manufacturing process of the comparative example display device.

[0048] Figure 29 This is a schematic cross-sectional view showing the manufacturing process of the comparative example display device.

[0049] Figure 30 This is a schematic cross-sectional view showing the manufacturing process of the comparative example display device.

[0050] Figure 31 This is a schematic top view showing the mother substrate of the second embodiment. Detailed Implementation

[0051] Hereinafter, various embodiments will be described with reference to the accompanying drawings. It should be noted that the disclosed content is merely an example, and appropriate modifications that remain consistent with the spirit of the invention and are readily conceived by those skilled in the art are of course included within the scope of this invention. Furthermore, regarding the accompanying drawings, to make the description clearer, the width, thickness, shape, etc., of each part are sometimes schematically shown compared to the actual form; however, this is merely an example and does not limit the interpretation of the invention. Additionally, in this specification and the various drawings, the same reference numerals are used for constituent elements that perform the same or similar functions as those described with respect to previously presented figures, and sometimes repeated detailed descriptions are appropriately omitted.

[0052] It should be noted that, in the accompanying drawings, mutually orthogonal X-axis, Y-axis, and Z-axis are shown as needed and for ease of understanding. The direction along the X-axis is referred to as the first direction X, the direction along the Y-axis as the second direction Y, and the direction along the Z-axis as the third direction Z. The view of various elements parallel to the third direction Z is called a top view.

[0053] In the following description, "overlap" includes not only the case where other elements overlap with the object element from the third direction Z, but also the case where they overlap from the opposite direction of the third direction Z. Furthermore, "overlap" includes not only the case where object elements are in contact with each other, but also the case where object elements are spaced apart from each other, and the case where other elements are located between object elements.

[0054] The display devices in each embodiment are organic electroluminescent display devices that use organic light-emitting diodes (OLEDs) as display elements, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle devices, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0055] [First Implementation]

[0056] Figure 1 This is a top view showing a schematic structural example of the display device DSP according to this embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10 and a plurality of conductive pads PD. The substrate 10 has a circular main body portion 10a and an extension portion 10b extending from the main body portion 10a in a second direction Y. The extension portion 10b is formed as a trapezoid with a width that decreases as it moves away from the main body portion 10a in the first direction X. The extension portion 10b has a substrate end 10c extending along the first direction X.

[0057] However, the shape of the substrate 10 when viewed from above can also be other shapes such as rectangle, square, or ellipse. The substrate 10 is formed of insulating materials such as glass or plastic.

[0058] The display panel PNL also includes a display area DA for displaying images and a peripheral area SA surrounding the display area DA. The display area DA overlaps with the main body 10a when viewed from above. In this embodiment, the shape of the display area DA when viewed from above is circular. However, the shape of the display area DA when viewed from above can also be other shapes such as rectangle, square, or ellipse.

[0059] The surrounding area SA has a mounting area MA. The mounting area MA corresponds to the area overlapping with extension 10b when viewed from above. Multiple pads PD are located within the mounting area MA. Figure 1 In the example shown, multiple pads (PDs) are arranged at equal intervals in the first direction X. The flexible substrate (FPC) is connected to the multiple pads (PDs) by adhesive. Alternatively, in addition to the flexible substrate (FPC), IC chips, etc., may also be mounted in the mounting area MA.

[0060] The display area DA has multiple pixels PX arranged in a matrix along the first direction X and the second direction Y. Each pixel PX has multiple sub-pixels SP. In one example, pixel PX has a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. It should be noted that, in addition to the above three colors of sub-pixels, pixel PX may also have four or more sub-pixels with additional sub-pixels of other colors such as white.

[0061] The sub-pixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a driving transistor 3, and a capacitor 4. The pixel switch 2 and the driving transistor 3 are, for example, switching elements composed of thin-film transistors.

[0062] In pixel switch 2, the gate is connected to scan line GL. One of the source and drain of pixel switch 2 is connected to signal line SL, and the other is connected to the gate of driving transistor 3 and capacitor 4. Figure 1 In the example shown, the scan line GL extends along the first direction X, and the signal line SL extends along the second direction Y. The signal line SL connects the pixel circuit 1 to the pad PD. In the driving transistor 3, one of the source and drain is connected to the power supply line PL and the capacitor 4, and the other is connected to the anode of the display element DE. It should be noted that the structure of the pixel circuit 1 is not limited to the example shown.

[0063] Figure 2 This is a schematic top view showing an example of the layout of subpixels SP1, SP2, and SP3. Figure 2 In the example shown, subpixels SP2 and SP3 are arranged with subpixel SP1 in the first direction X. Moreover, subpixels SP2 and SP3 are arranged in the second direction Y.

[0064] With subpixels SP1, SP2, and SP3 arranged in this layout, the display area DA contains columns of subpixels SP2 and SP3 alternately arranged in the second direction Y, and multiple columns of subpixels SP1 repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. It should be noted that the layout of subpixels SP1, SP2, and SP3 is not limited to... Figure 2 The example shown.

[0065] A rib layer 5 is configured in the display area DA. Rib layer 5 has pixel openings AP1, AP2, and AP3 in sub-pixels SP1, SP2, and SP3, respectively. Figure 2 In the example shown, pixel aperture AP1 is larger than pixel aperture AP2, and pixel aperture AP2 is larger than pixel aperture AP3.

[0066] That is, among sub-pixels SP1, SP2, and SP3, sub-pixel SP1 has the largest aperture ratio, and sub-pixel SP3 has the smallest aperture ratio. It should be noted that the sizes of pixel apertures AP1, AP2, and AP3 are not limited to this example. For instance, at least two of pixel apertures AP1, AP2, and AP3 can also have the same size.

[0067] Sub-pixel SP1 has a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap with pixel opening AP1. Sub-pixel SP2 has a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap with pixel opening AP2. Sub-pixel SP3 has a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap with pixel opening AP3.

[0068] Display elements DE1, DE2, and DE3 are disposed in the display area DA. The portion of the lower electrode LE1, the upper electrode UE1, and the portion of the organic layer OR1 that overlaps with the pixel opening AP1 constitutes the display element DE1 of sub-pixel SP1. The portion of the lower electrode LE2, the upper electrode UE2, and the portion of the organic layer OR2 that overlaps with the pixel opening AP2 constitutes the display element DE2 of sub-pixel SP2. The portion of the lower electrode LE3, the upper electrode UE3, and the portion of the organic layer OR3 that overlaps with the pixel opening AP3 constitutes the display element DE3 of sub-pixel SP3. Display elements DE1, DE2, and DE3 may also include a capping layer described later. Rib layers 5 surround these display elements DE1, DE2, and DE3 respectively.

[0069] A partition wall 6 is configured in the display area DA. The partition wall 6 is located above the rib layer 5 and overlaps with the rib layer 5 in general. Figure 2 In the example shown, the partition wall 6 has the same planar shape as the rib layer 5. That is, the partition wall 6 has openings in sub-pixels SP1, SP2, and SP3, respectively.

[0070] From another perspective, the rib layer 5 and the partition wall 6 appear as a grid when viewed from above, respectively surrounding display elements DE1, DE2, and DE3. The partition wall 6 surrounds pixel openings AP1, AP2, and AP3. The partition wall 6 serves as wiring to supply a common voltage to the upward electrodes UE1, UE2, and UE3.

[0071] In this embodiment, inorganic insulating layers IL1, IL2, and IL3 are respectively disposed below the lower electrodes LE1, LE2, and LE3. Figure 2 In the example shown, the inorganic insulating layers IL1, IL2, and IL3 are separated from each other.

[0072] The inorganic insulating layers IL1, IL2, and IL3 have a shape that is slightly larger than that of the lower electrodes LE1, LE2, and LE3, respectively. That is, the end E1x of the inorganic insulating layer IL1 protrudes from the end E1 of the lower electrode LE1 over the entire circumference.

[0073] Additionally, the end E2x of the inorganic insulating layer IL2 protrudes from the end E2 of the lower electrode LE2 throughout the entire circumference. The end E3x of the inorganic insulating layer IL3 protrudes from the end E3 of the lower electrode LE3 throughout the entire circumference.

[0074] It should be noted that the shapes of the inorganic insulating layers IL1, IL2, and IL3 are not limited to... Figure 2 The example shown. For instance, a portion of the inorganic insulating layers IL1, IL2, and IL3 can also be connected. Additionally, a portion of each of the ends E1x, E2x, and E3x can overlap with the lower electrodes LE1, LE2, and LE3.

[0075] The lower electrodes LE1, LE2, and LE3 are respectively connected to the pixel circuit 1 (more specifically, the pixel circuit 1 of the sub-pixels SP1, SP2, and SP3) through contact holes (not shown). Figure 1 The drain of the driving transistor 3 shown is connected. Contact holes (not shown) overlap with the rib layer 5 and the partition wall 6.

[0076] Figure 3 It is along Figure 2 A schematic cross-sectional view of the display device DSP with line III-III. A circuit layer 11 is disposed on the substrate 10. The circuit layer 11 includes... Figure 1 The diagram shows various circuits and wiring, including pixel circuit 1, scan line GL, signal line SL, and power line PL. Circuit layer 11 is covered by organic insulating layer 12. Organic insulating layer 12 functions as a planarization film to flatten the unevenness caused by circuit layer 11.

[0077] Inorganic insulating layers IL1, IL2, and IL3 are disposed on top of organic insulating layer 12. Lower electrodes LE1, LE2, and LE3 are disposed on top of inorganic insulating layers IL1, IL2, and IL3, respectively. That is, inorganic insulating layers IL1, IL2, and IL3 are disposed between organic insulating layer 12 and lower electrodes LE1, LE2, and LE3 in display area DA.

[0078] Rib layer 5 is disposed above organic insulating layer 12 and lower electrodes LE1, LE2, and LE3. The ends of lower electrodes LE1, LE2, and LE3 ( Figure 2 The ends E1, E2, E3 and the ends of the inorganic insulating layers IL1, IL2, IL3 shown are shown. Figure 2 The ends E1x, E2x, and E3x shown are all covered by rib layer 5.

[0079] The partition wall 6 includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a wider width than the lower portion 61. As a result, the two ends of the upper portion 62 protrude compared to the sides of the lower portion 61. That is, the partition wall 6 is an overhanging shape in which the two ends of the upper portion 62 protrude compared to the sides of the lower portion 61.

[0080] exist Figure 3 In the example shown, the lower part 61 has a bottom layer 63 and a axial layer 64. The bottom layer 63 is located between the axial layer 64 and the rib layer 5. Furthermore, in Figure 3 In the example shown, the upper part 62 has a first top layer 65 and a second top layer 66. The first top layer 65 is disposed above the axis layer 64. The second top layer 66 is disposed above the first top layer 65.

[0081] Organic layer OR1 covers lower electrode LE1 through pixel opening AP1. Upper electrode UE1 covers organic layer OR1 and is opposite to lower electrode LE1. Organic layer OR2 covers lower electrode LE2 through pixel opening AP2. Upper electrode UE2 covers organic layer OR2 and is opposite to lower electrode LE2. Organic layer OR3 covers lower electrode LE3 through pixel opening AP3. Upper electrode UE3 covers organic layer OR3 and is opposite to lower electrode LE3. Upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of partition wall 6.

[0082] Display element DE1 includes a capping layer CP1 covering the upper electrode UE1. Display element DE2 includes a capping layer CP2 covering the upper electrode UE2. Display element DE3 includes a capping layer CP3 covering the upper electrode UE3. Capping layers CP1, CP2, and CP3 respectively serve as optical adjustment layers to improve the light extraction efficiency emitted by organic layers OR1, OR2, and OR3.

[0083] In the following description, the multilayer comprising organic layer OR1, upper electrode UE1 and capping layer CP1 is referred to as laminated film FL1, the multilayer comprising organic layer OR2, upper electrode UE2 and capping layer CP2 is referred to as laminated film FL2, and the multilayer comprising organic layer OR3, upper electrode UE3 and capping layer CP3 is referred to as laminated film FL3.

[0084] Subpixels SP1, SP2, and SP3 are respectively provided with sealing layers SE11, SE12, and SE13 covering the laminated films FL1, FL2, and FL3. Specifically, sealing layer SE11 continuously covers the capping layer CP1 and the partition wall 6 around subpixel SP1. Sealing layer SE12 continuously covers the capping layer CP2 and the partition wall 6 around subpixel SP2. Sealing layer SE13 continuously covers the capping layer CP3 and the partition wall 6 around subpixel SP3.

[0085] exist Figure 3 In the example shown, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6. Additionally, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 can also be in contact above the partition wall 6.

[0086] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. Laminated membranes FL1, FL2, FL3 may also be disposed in at least a portion of these gaps.

[0087] Sealing layers SE11, SE12, and SE13 are covered by resin layer RS1. Resin layer RS1 is covered by sealing layer SE2. Sealing layer SE2 is covered by resin layer RS2. Resin layers RS1, RS2, and sealing layer SE2 are continuously disposed throughout the entire display area DA, and a portion of them also extends to the peripheral area SA.

[0088] Alternatively, a polarizer, protective film, or glass cover can be disposed above the resin layer RS2. Such a cover can be bonded to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive). Furthermore, color filters corresponding to the colors of sub-pixels SP1, SP2, and SP3 can be disposed above the display elements DE1, DE2, and DE3, respectively.

[0089] The organic insulating layer 12 is formed of organic insulating materials such as polyimide. The inorganic insulating layers IL1, IL2, IL3, rib layer 5, and sealing layers SE11, SE12, SE13, and SE2 are formed of inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon nitride oxide (SiON).

[0090] Inorganic insulating layers IL1, IL2, and IL3 are formed, for example, of an inorganic insulating material different from that of rib layer 5. In one example, inorganic insulating layers IL1, IL2, and IL3 are formed of silicon nitride, rib layer 5 is formed of silicon oxide, and sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. Resin layers RS1 and RS2 are formed, for example, of resin materials (organic insulating materials) such as epoxy resin and acrylic resin.

[0091] The lower electrodes LE1, LE2, and LE3 are, for example, multilayer bodies comprising a transparent electrode formed of an oxide conductive material such as ITO and a metal electrode formed of a metallic material such as silver. The upper electrodes UE1, UE2, and UE3 are, for example, formed of a metallic material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0092] Organic layers OR1, OR2, and OR3 are composed of multiple thin films, including a light-emitting layer. In one example, organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, a light-emitting layer, a hole blocking layer, an electron transport layer, and an electron injection layer are sequentially stacked in the third direction Z. However, organic layers OR1, OR2, and OR3 may also have other structures, such as a so-called tandem structure including multiple light-emitting layers.

[0093] The capping layers CP1, CP2, and CP3, for example, have a stacked structure composed of multiple overlapping transparent layers. These transparent layers can include layers formed of inorganic materials and layers formed of organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers differ from the refractive indices of the upper electrodes UE1, UE2, and UE3, and the refractive indices of the sealing layers SE11, SE12, and SE13. It should be noted that at least one of the capping layers CP1, CP2, and CP3 may be omitted.

[0094] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. Pixel currents corresponding to the image signals of signal line SL are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of sub-pixels SP1, SP2, and SP3, respectively.

[0095] Organic layers OR1, OR2, and OR3 emit light according to the flowing current. Specifically, when a current is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a current is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a current is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0096] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 can also emit light of the same color (e.g., white). In this case, the display device DSP can also include a color filter that converts the light emitted by the light-emitting layers into light of the colors corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP can also include a layer containing quantum dots, which are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the sub-pixels SP1, SP2, and SP3.

[0097] The bottom layer 63 and the axial layer 64 are formed of metallic materials, for example. For example, molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb) can be used as the metallic material for the bottom layer 63. For example, aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi) can be used as the metallic material for the axial layer 64. It should be noted that at least one of the bottom layer 63 and the axial layer 64 may also have a multi-layered structure. Furthermore, the axial layer 64 may also include a layer formed of an insulating material. Moreover, the bottom portion 61 may also have a single-layer structure formed of a conductive material.

[0098] For example, the first top layer 65 is formed of a metallic material, and the second top layer 66 is formed of a transparent conductive oxide. For example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloys, or molybdenum-niobium alloys can be used as the metallic material for the first top layer 65. For example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide) can be used as the conductive oxide for the second top layer 66. It should be noted that the upper part 62 may also have a single-layer structure formed of a specific material. Furthermore, the upper part 62 may also include a layer formed of an insulating material.

[0099] When manufacturing a display device DSP, a large mother substrate is made having multiple regions (panel sections) each corresponding to a display panel PNL. The structure applicable to this mother substrate will be described below.

[0100] Figure 4 This is a schematic top view of the mother substrate MB (mother substrate for display device) in this embodiment. The mother substrate MB is rectangular, as shown in the figure, but it can also be other shapes such as circles.

[0101] The mother substrate MB has multiple panel portions PP arranged in a matrix and blank areas BA surrounding these panel portions PP. Figure 4 In the example shown, multiple panel portions PP are arranged with gaps BA in the first direction X and the second direction Y. However, the arrangement of multiple panel portions PP on the mother substrate MB is not limited to this example.

[0102] Figure 5 This is a schematic top view of a portion of the mother substrate MB. The focus of this view is on a panel portion PP. The shape of the panel portion PP corresponds to the cutting line CL1 used to cut the panel portion PP from the mother substrate MB.

[0103] The panel portion PP has the aforementioned display area DA and peripheral area SA. Furthermore, the peripheral area SA includes an inspection area TA. Multiple inspection pads TD for inspecting the operation of the display panel PNL are arranged in the inspection area TA. The inspection pads TD are, for example, rectangular in shape. The inspection pads TD are arranged at intervals in the first direction X.

[0104] A cutting line CL2 is formed on the panel portion PP. The cutting line CL2 is equivalent to... Figure 1 The diagram shows the outline of the display panel PNL. The panel portion PP is divided by a cutting line CL2 into a portion including the display area DA and a portion including the inspection area TA.

[0105] The inspection pad TD is positioned between the display area DA and the cut line CL1. Alternatively, the cut line CL2 is positioned between the display area DA and the inspection pad TD.

[0106] Although not illustrated, multiple inspection pads are also provided in the blank area BA. These inspection pads can include inspection pads for inspecting the operation of the display panel PNL and inspection pads for measuring the thickness of specific layers formed on the mother substrate MB. Furthermore, multiple alignment marks can also be provided in the blank area BA.

[0107] Figure 6 It is along Figure 5 A schematic cross-sectional view of the DSP display device with VI-VI lines. Figure 6 The image shows a portion of the inspection area TA in the panel portion PP, which includes the inspection pad TD.

[0108] As described above, the display device DSP includes a circuit layer 11. The circuit layer 11 is disposed above the substrate 10, covering the display area DA and the peripheral area SA. The circuit layer 11 includes inorganic insulating layers 111, 112, and 113, an organic insulating layer 114, and wiring TW (inspection wiring). The wiring TW connects the inspection pad TD to the inspection object. The wiring TW includes wiring TW1 and TW2.

[0109] An inorganic insulating layer 111 is disposed on the substrate 10. A wiring TW1 is disposed on the inorganic insulating layer 111. The wiring TW1 is formed on the same layer as, for example, the scan line GL. An inorganic insulating layer 112 is disposed on the inorganic insulating layer 111 and the wiring TW1.

[0110] Wiring TW2 is disposed on inorganic insulating layer 112. Wiring TW2 is formed on the same layer as signal line SL, for example. Wiring TW2 is electrically connected to wiring TW1 via contact holes (not shown). Inorganic insulating layer 113 is disposed on inorganic insulating layer 112 and wiring TW2. Organic insulating layer 114 is disposed on inorganic insulating layer 113.

[0111] The display device DSP also includes a metal layer M3 (first metal layer). The metal layer M3 is disposed on the organic insulating layer 114. In addition, at least a portion of the metal layer M3 is located directly above the wiring TW2.

[0112] The metal layer M3 is electrically connected to the wiring TW2. Specifically, the metal layer M3 contacts the wiring TW2 through the openings of the inorganic insulating layer 113 and the organic insulating layer 114.

[0113] An organic insulating layer 12 is disposed over the display area DA and the surrounding area SA. The organic insulating layer 12 is disposed on top of the organic insulating layer 114 and the metal layer M3. The organic insulating layer 12 has an opening 121 (second opening).

[0114] The display device DSP also includes an inorganic insulating layer IL. The inorganic insulating layer IL is formed, for example, from the same material and using the same manufacturing process as the inorganic insulating layers IL1, IL2, and IL3 in the display area DA. The inorganic insulating layer IL is disposed in the inspection area TA between the organic insulating layer 12 and the rib layer 5. The inorganic insulating layer IL has an opening ILA (the third opening).

[0115] Rib layer 5 is configured to cover the display area DA and the surrounding area SA. Rib layer 5 is disposed on top of organic insulating layer 12 and inorganic insulating layer IL. From another viewpoint, organic insulating layer 12 is disposed between metal layer M3 and rib layer 5. Rib layer 5 has, for example, a greater thickness than inorganic insulating layer IL. Rib layer 5 has an opening 51 (first opening).

[0116] A sealing layer SE2 is configured to cover the display area DA and the surrounding area SA. The sealing layer SE2 is disposed on the rib layer 5. The sealing layer SE2 has an opening SEA (the fourth opening).

[0117] The opening 121 of the organic insulating layer 12, the opening ILA of the inorganic insulating layer IL, the opening 51 of the rib layer 5, and the opening SEA of the sealing layer SE2 overlap with each other. These openings 121, ILA, 51, and SEA overlap with the metal layer M3. In other words, the metal layer M3 is exposed from the openings 121, ILA, 51, and SEA.

[0118] The display device DSP also includes a metal layer M4 (the second metal layer). The pad TD is formed by metal layers M3 and M4. Metal layer M4 is located directly above and electrically connected to metal layer M3. In other words, metal layer M4 contacts metal layer M3 at openings 121, ILA, 51, and SEA. Looking at rib 5, rib 5 is positioned between metal layers M3 and M4.

[0119] Here, the structure of metal layers M3 and M4 will be described. Metal layers M3 and M4 are multilayer bodies comprising multiple layers formed of different metallic materials.

[0120] The metal layer M3 has a first layer M31 overlapping the organic insulating layer 114, a second layer M32 overlapping the first layer M31, and a third layer M33 overlapping the second layer M32. The first layer M31 and the third layer M33 are formed of a first metal material, and the second layer M32 is formed of a second metal material.

[0121] Layer 1 M31 is in contact with wiring TW2. Layer 3 M33 has an area A3 that exposes layer 2 M32 of metal layer M3. Area A3 is located directly above wiring TW2.

[0122] Metal layer M4 has a fourth layer M41 overlapping metal layer M3, a fifth layer M42 overlapping metal layer M41, and a sixth layer M43 overlapping metal layer M42. The fourth layer M41 and the sixth layer M43 are formed of a first metallic material, and the fifth layer M42 is formed of a second metallic material. Here, as an example, the first metallic material is a titanium-based material, and the second metallic material is an aluminum-based material; however, the first metallic material and the second metallic material are not limited to this example.

[0123] Additionally, the fourth layer M41 of the metal layer M4 has a first contact portion C1 that contacts the second layer M32 and a second contact portion C2 that contacts the third layer M33. The first contact portion C1 and the second contact portion C2 are located inside the opening 121 of the organic insulating layer 12.

[0124] The first contact portion C1 overlaps with region A3. The second contact portion C2 does not overlap with region A3. The first contact portion C1 is located above the routing TW, and the second contact portion C2 is not located above the routing TW. If we focus on the inspection pad TD, a first portion P1 including the first contact portion C1 and a second portion P2 including the second contact portion C2 are formed on the inspection pad TD.

[0125] Figure 7 It means Figure 6 A magnified view of part VII in the image. Figure 8 It means Figure 6 A magnified view of part VIII. Figure 7 The image shows the first part, P1, of inspecting pad TD. Figure 8 Part P2 of the inspection of pad TD is shown in the figure.

[0126] like Figure 7 As shown, part P1 is stacked with layer 1 M31, layer 2 M32, layer 4 M41, layer 5 M42, and layer 6 M43. (As...) Figure 8As shown, the second part P2 is stacked with the first layer M31, the second layer M32, the third layer M33, the fourth layer M41, the fifth layer M42 and the sixth layer M43.

[0127] The thickness T21 of part P2 is greater than the thickness T11 of part P1. The spacing between the second layer M32 and the fifth layer M42 in part P2 is greater than the spacing between the second layer M32 and the fifth layer M42 in part P1.

[0128] In other words, the thickness T22 of the layer formed by the second metal material between the second layer M32 and the fifth layer M42 in part 2 P2 is greater than the thickness T12 of the layer formed by the second metal material between the second layer M32 and the fifth layer M42 in part 1 P1.

[0129] Inorganic insulating layers 111, 112, and 113 are formed from any one of silicon oxide, silicon nitride, and silicon nitride. Wiring TW2 is formed, for example, from multiple layers. Wiring TW2 is formed, for example, in the same manner as metal layers M3 and M4.

[0130] It should be noted that at least one of the wiring TW2, metal layers M3, and M4 can also be formed by distributing aluminum layers between layers formed of molybdenum-based materials. The organic insulating layer 114 is formed of an organic insulating material such as polyimide.

[0131] Next, an example of a manufacturing method for a display device DSP will be described.

[0132] Figure 9 This is a flowchart illustrating an example of a manufacturing method for a display device DSP. Figures 10A to 20B These are schematic cross-sectional views showing the manufacturing process of the display device DSP.

[0133] Figure 10A , 11A Models 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A primarily focus on inspecting pad TD (Technical Design). Figure 10B , 11B 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B primarily focus on pad PD.

[0134] When forming the panel portion PP, firstly, a circuit layer 11 and a metal layer M3 are formed on the substrate 10 of the mother substrate MB. Figure 9 Process PR1). Process PR1 includes preparing a substrate 10 having a panel portion PP.

[0135] The circuit layer 11 includes inorganic insulating layers 111, 112, and 113, an organic insulating layer 114, and wiring TW. The circuit layer 11 is formed on the entire mother substrate MB, which includes not only the display area DA but also the peripheral area SA.

[0136] like Figure 10A and Figure 10B As shown, a metal layer M3 is formed in the peripheral region SA, including the inspection region TA. The process of forming the metal layer M3 includes forming a first layer M31 from a first metal material, forming a second layer M32 from a second metal material, forming a third layer M33 from the first metal material, and patterning the first layer M31, the second layer M32, and the third layer M33. The first layer M31, the second layer M32, and the third layer M33 are formed, for example, by sputtering.

[0137] Next, an organic insulating layer 12 is formed above the circuit layer 11 and the metal layer M3. Figure 9 Process PR2). An organic insulating layer 12 is formed on the entire mother substrate MB, including not only the display area DA but also the peripheral area SA. Process PR2 includes patterning the organic insulating layer 12. An opening 121 is formed in the organic insulating layer 12. Figure 6 (As shown).

[0138] Next, as Figure 10A , 10B As shown, an inorganic insulating layer IL and a rib layer 5 are formed above the organic insulating layer 12 and the metal layer M3. Figure 9 (Process PR3). Rib layer 5 is formed on the entire mother substrate MB. Rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0139] After process PR3, a process for forming inspection opening AP10 is performed. Figure 9 Process PR4). In process PR4, resist R1 is applied over rib 5. For example... Figure 11A As shown, the resist R1 has a layer difference portion 12a above the wiring TW and the organic insulating layer 12. Figure 12A The shape of the opening at the top (as shown). In contrast, as... Figure 11B As shown, the resist R1 has no opening above the pad PD.

[0140] Subsequently, dry etching was performed on the rib layer 5 and the inorganic insulating layer IL using resist R1 as a mask. This removed the portions of the rib layer 5 and the inorganic insulating layer IL that were exposed from the resist R1.

[0141] After process PR4, such as Figure 12AAs shown, an inspection opening AP10 is formed in the rib layer 5 and the inorganic insulating layer IL, overlapping with the metal layer M3. The inspection opening AP10 is formed in the area overlapping with the metal layer M3 and the area overlapping with the wiring TW.

[0142] Furthermore, the rib layer 5 and the inorganic insulating layer IL are also removed in the region overlapping with the lamination portion 12a of the organic insulating layer 12. As a result, the sealing layer SE2, described later, adheres tightly to the lamination portion 12a of the organic insulating layer 12 and is difficult to peel off.

[0143] Additionally, the rib layer 5 and the inorganic insulating layer IL, which overlap with the pad PD, were not removed. After the aforementioned dry etching, as... Figure 13A , 13B The resist R1 is removed (stripped) as shown.

[0144] After process PR4, such as Figure 13A As shown, a portion of the metal layer M3 of pad TD is exposed, but as... Figure 13B As shown, the metal layer M3 of the pad PD is not exposed. By covering the metal layer M3 of the pad PD with the inorganic insulating layer IL and the rib layer 5, the metal layer M3 is protected in the next process (the process of forming display elements DE1, DE2, and DE3).

[0145] After process PR4, processes for forming display elements DE1, DE2, and DE3 are performed. Figure 9 Processes PR5 to PR7). After forming display elements DE1, DE2, and DE3, a lighting inspection of display elements DE1, DE2, and DE3 is performed using the metal layer M3 exposed from the inspection opening AP10 of the inspection pad TD. Figure 9 Process PR8).

[0146] After process PR8, such as Figure 14A , 14B As shown, a sealing layer SE2 is formed covering the rib layer 5. Figure 9 The sealing layer SE2 is formed, for example, by CVD on the entire mother substrate MB. Figure 14A As shown, the sealing layer SE2 covers the inspection opening AP10. In other words, the sealing layer SE2 contacts the metal layer M3 at the inspection opening AP10.

[0147] After process PR9, a process is performed to form an opening that exposes metal layer M3. Figure 9 The process PR10). In other words, the process is performed to remove the pad PD and inspect the sealing layer SE2, rib layer 5 and inorganic insulating layer IL at the pad TD.

[0148] In process PR10, resist R2 is applied over the sealing layer SE2. For example... Figure 15A, 15B As shown, the resist R2 has an opening above the pad PD and the inspection pad TD.

[0149] Subsequently, dry etching was performed on the sealing layer SE2, the rib layer 5, and the inorganic insulating layer IL using resist R2 as a mask. This removed the portions of the sealing layer SE2, the rib layer 5, and the inorganic insulating layer IL that were exposed from the resist R2.

[0150] After process PR10, such as Figure 16A , 16B As shown, openings overlapping with the metal layer M3 are formed in rib layer 5, inorganic insulating layer IL, and sealing layer SE2. If focusing on inspecting pad TD, opening 51 is formed in rib layer 5, opening ILA in inorganic insulating layer IL, and opening SEA in sealing layer SE2. If focusing on pad PD, the metal layer M3 is exposed. After the above etching, as... Figure 17A , 17B The resist R2 is removed as shown.

[0151] In process PR10, the region of the third layer M33 of metal layer M3 that overlaps with the inspection opening AP10 is subjected to at least two dry etching processes. As a result, the third layer M33 overlapping with the inspection opening AP10 is removed, forming region A3. As described above, the second layer M32 of metal layer M3 is exposed from region A3. Region A3, for example, has an area equal to that of the inspection opening AP10.

[0152] Next, after process PR10, the metal layer M3 of the inspection pad TD is used to perform a lighting check on display components DE1, DE2, and DE3. Figure 9 Process PR11).

[0153] After process PR11, a process is performed to remove the sealant layer SE2 at the pad PD. Figure 9 In process PR12, a photoresist R3 is applied over the sealing layer SE2. The photoresist R3 covers the opening 121 of the organic insulating layer 12, the opening 51 of the rib layer 5, the opening ILA of the inorganic insulating layer IL, and the opening SEA of the sealing layer SE2. Figure 18B As shown, resist R3 is not positioned above pad PD.

[0154] like Figure 18A As shown, the resist R3 has an opening above the inspection pad TD. Specifically, the resist R3 has an opening AP20. In this embodiment, the opening AP20 is an example of a cleaning opening.

[0155] The third layer M33 of metal layer M3 is exposed from opening AP20. If focusing on inspection opening AP10, the location of opening AP20 does not overlap with the location of inspection opening AP10. Subsequently, dry etching is performed on sealing layer SE2 using resist R3 as a mask.

[0156] In process PR12, the sealing layer SE2 is removed in the area including pads PD (e.g., between adjacent pads PD). Conversely, the oxide film on the surface of the third layer M33, exposed from the opening AP20, is removed in the inspection pad TD. In other words, the surface of the third layer M33 is cleaned by dry etching. Process PR12 corresponds to the process used to clean the metal layer M3.

[0157] Furthermore, etching in process PR12 is performed with an intensity sufficient to prevent the third layer M33 exposed from opening AP20 from disappearing. Following the aforementioned dry etching, as... Figure 19A , 19B The resist R3 is removed as shown.

[0158] After process PR12, a process for forming metal layer M4 is performed. Figure 9 Process PR13 includes forming a fourth layer M41 from a first metal material, forming a fifth layer M42 from a second metal material, forming a sixth layer M43 from the first metal material, and patterning the fourth layer M41, the fifth layer M42, and the sixth layer M43. The fourth layer M41, the fifth layer M42, and the sixth layer M43 are formed, for example, by sputtering.

[0159] From another perspective, in process PR13, during the inspection of pad TD formation in part 1, P1 ( Figure 6 (as shown) and Part 2 P2 ( Figure 6 (As shown). Additionally, the second contact portion C2 ( Figure 6 (As shown) For example, it corresponds to the portion that overlaps with the region where the opening AP20 is formed (the region after the oxide film is removed from the surface of the 3rd layer M33).

[0160] exist Figure 20A In the example shown, the second contact portion C2 is offset from the first contact portion C1 in the opposite direction of the second direction Y. It should be noted that the second contact portion C2 may also be offset from the first contact portion C1 in any of the following directions: the first direction X, the opposite direction of the first direction X, or the second direction Y.

[0161] After process PR13, such as Figure 20A , 20B As shown, inspection pads TD and PD, including metal layer M4, are formed. Then, a process is performed to form resin layer RS2. Figure 9Process PR14, etc., involves cutting each panel portion PP from the mother substrate MB along the cutting line CL1. Figure 9 The process PR15). Then, along the cutting line CL2, cut away the inspection area TA (inspection pad TD) from the peripheral area SA. Figure 9 The process PR16 is then completed. Thus, the display panel PNL is finished.

[0162] Figures 21 to 24 These are schematic cross-sectional views showing the processes involved in forming display elements DE1, DE2, and DE3, respectively. Figures 21 to 24 In this study, the focus is primarily on sub-pixels SP1, SP2, and SP3. It should be noted that... Figures 21 to 24 In the text, elements below the organic insulating layer 12 are omitted. At the point when process PR4 is completed, such as... Figure 21 As shown, a partition wall 6 is formed on the rib layer 5 in the display area DA.

[0163] Then, the process for forming the display element DE1 is carried out. Figure 9 Process PR5). During the formation of display element DE1, such as... Figure 21 As shown, a laminated film FL1 and a sealing layer SE11 are formed. Figure 3 As shown, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through a pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a capping layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the capping layer CP1 can be formed, for example, by vapor deposition. In addition, the sealing layer SE11 can be formed, for example, by CVD.

[0164] The laminated film FL1 and the sealing layer SE11 are formed on the entire mother substrate MB, which includes not only the display area DA of each panel portion PP, but also the peripheral area SA and the blank area BA. The laminated film FL1 is divided into multiple parts by a cantilevered partition wall 6. The sealing layer SE11 continuously covers each of the partitioned parts of the laminated film FL1 and the partition wall 6.

[0165] Next, the laminated film FL1 and the sealing layer SE11 are patterned. In this patterning, as... Figure 21 As shown, resist R5 is disposed on top of the sealing layer SE11. Resist R5 covers a portion of the sub-pixel SP1 and the surrounding partition wall 6.

[0166] Next, an etching process using resist R5 as a mask is performed. Thus, as... Figure 22As shown, the portions of the laminated film FL1 and the sealing layer SE11 exposed from the resist R5 are removed. In other words, the portions of the laminated film FL1 and the sealing layer SE11 that overlap with the lower electrode LE1 are left, and the rest are removed. Thus, the display element DE1 is formed in the sub-pixel SP1. For example, in the peripheral region SA and the blank region BA, the laminated film FL1 and the sealing layer SE11 are removed by this etching process. This etching process can include wet etching and dry etching sequentially performed on the sealing layer SE11, the capping layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, the resist R5 is removed.

[0167] After process PR5, a process for forming display element DE2 is performed. Figure 9 The process PR6). Display element DE2 can be formed using the same steps as display element DE1. That is, when forming display element DE2, the laminated film FL2 and the sealing layer SE12 are formed on the entire mother substrate MB. Figure 3 As shown, the laminated film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through a pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a capping layer CP2 covering the upper electrode UE2.

[0168] The organic layer OR2, the upper electrode UE2, and the capping layer CP2 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE12 can be formed, for example, by CVD. The laminated film FL2 is divided into multiple portions by cantilevered partition walls 6. The sealing layer SE12 continuously covers each of the separated portions of the laminated film FL2 and the partition walls 6. This is achieved by patterning the laminated film FL2 and the sealing layer SE12, as follows: Figure 23 As shown, display element DE2 is formed in sub-pixel SP2. For example, in the peripheral area SA and the blank area BA, the laminated film FL2 and the sealing layer SE12 are removed by etching during patterning.

[0169] After process PR6, a process for forming display element DE3 is performed. Figure 9 The process PR7). Display element DE3 can be formed using the same steps as display elements DE1 and DE2. That is, when forming display element DE3, the laminated film FL3 and the sealing layer SE13 are formed on the entire mother substrate MB. Figure 3 As shown, the laminated film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through a pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a capping layer CP3 covering the upper electrode UE3.

[0170] The organic layer OR3, the upper electrode UE3, and the capping layer CP3 can be formed, for example, by vapor deposition. Additionally, the sealing layer SE13 can be formed, for example, by CVD. The laminated film FL3 is divided into multiple portions by cantilevered partition walls 6. The sealing layer SE13 continuously covers each of the separated portions of the laminated film FL3 and the partition walls 6. This is achieved by patterning the laminated film FL3 and the sealing layer SE13, as follows: Figure 24 As shown, display element DE3 is formed in sub-pixel SP3. For example, in the peripheral area SA and the blank area BA, the laminated film FL3 and the sealing layer SE13 are removed by etching during patterning.

[0171] It should be noted that this scenario assumes that display elements DE1, DE2, and DE3 are formed in sequence, but they can also be formed in other orders.

[0172] Figure 25 This diagram illustrates the openings 121, ILA, 51, and SEA that overlap with the pad TD during inspection. Figure 25 In the original text, some elements, such as the metal layer M4, were omitted.

[0173] The area of ​​opening 121 in organic insulating layer 12 is smaller than the area of ​​opening 51 in rib layer 5 when viewed from above. The area of ​​opening ILA in inorganic insulating layer IL is, for example, equal to the area of ​​opening 51 when viewed from above. In other words, the edge of opening ILA is aligned with the edge of opening 51. The area of ​​opening SEA in sealing layer SE2 is smaller than the areas of openings 51 and ILA, but larger than the area of ​​opening 121 when viewed from above.

[0174] In addition, such as Figure 25 As shown, the area to be dry etched in process PR4 is defined as region AE1, the area to be dry etched in process PR10 is defined as region AE2, and the area to be dry etched in process PR12 is defined as region AE3.

[0175] exist Figure 25 In the image, dotted shadows were added to region AE1, diagonal shadows were added to region AE2, and intersecting shadows were added to region AE3.

[0176] The shape of region AE1 corresponds to the edge of opening 51, ILA. The inner region of region AE1 overlaps with the inspection opening AP10 (region A3 of metal layer M3). The shape of region AE2 corresponds to the edge of opening SEA of sealing layer SE2. Region AE3 overlaps with opening AP20 of resist R3. As described above, the location forming opening AP20 does not overlap with the location forming inspection opening AP10.

[0177] Figures 26 to 30This is a schematic cross-sectional view showing the manufacturing process of the comparative example display device DSP10. Figures 26 to 30 The main focus is on inspecting the pad TD.

[0178] First, such as Figure 26 As shown, a circuit layer 11, a metal layer M3, an organic insulating layer 12, an inorganic insulating layer 11, and a rib layer 5 are formed on the substrate 10 of the mother substrate MB.

[0179] Next, a process for forming openings AP100 in the inorganic insulating layer IL and the rib layer 5 is performed. In this process, a photoresist with an opening shape above the inspection pad TD is applied on the rib layer 5. Then, dry etching is performed on the rib layer 5 and the inorganic insulating layer IL using the photoresist as a mask.

[0180] This removes the portions of the rib layer 5 and the inorganic insulating layer IL that are exposed from the resist. After this process, as... Figure 27 As shown, an opening AP100 is formed in the rib layer 5 and the inorganic insulating layer IL. The metal layer M3 is exposed through the opening AP100.

[0181] Next, after processes for forming display elements DE1, DE2, and DE3, and a lighting inspection process, a sealing layer SE2 covering the rib layer 5 is formed. The sealing layer SE2 covers the opening AP100.

[0182] Next, a process is performed to remove the sealing layer SE2 at the inspection pad TD. In this process, a resist with an opening above the inspection pad TD is applied on the sealing layer SE2.

[0183] Next, a photoresist is used as a mask to perform dry etching on the sealing layer SE2. This removes the portion of the sealing layer SE2 exposed from the photoresist. After this process, as... Figure 28 As shown, an opening AP200 is formed in the sealing layer SE2.

[0184] The third layer M33, which overlaps with the opening AP200, is subjected to dry etching at least twice. As a result, in the region overlapping with the opening AP200, the third layer M33 is removed, and the second layer M32 of the metal layer M3 is exposed from the opening AP200.

[0185] Next, a process is performed to remove the sealant layer SE2 at the pad PD. If the focus is on inspecting the pad TD, then... Figure 29 As shown, a resist R3 with an opening above the inspection pad TD is disposed on the sealing layer SE2. In other words, the resist R3 has an opening AP300.

[0186] The location where opening AP300 is formed overlaps with the aforementioned openings AP100 and AP200. The second layer M32 of metal layer M3 is exposed through opening AP300. In this process, the second layer M32, formed of aluminum-based material, may be dissolved by the resist developer, or the exposed surface of the second layer M32 may oxidize. Afterwards, as... Figure 30 As shown, the process for forming metal layer M4 is carried out.

[0187] In the comparative example display device DSP10, such as Figure 30 As shown, the fourth layer M41 of metal layer M4 is in contact with the second layer M32 of metal layer M3. The second layer M32 that the fourth layer M41 contacts is, for example, oxidized.

[0188] Because the second layer M32 has high resistance after oxidation, the connection resistance between metal layers M3 and M4 becomes high. This poses a potential risk of poor electrical contact between metal layers M3 and M4. Using such inspection pads (TD) to inspect display areas (DA, etc.) may reduce the reliability of the mother substrate and display device.

[0189] In this embodiment, the metal layer M4 has a second contact portion C2 that contacts the third layer M33 of the metal layer M3. Since the second contact portion C2 contacts the third layer M33 instead of the oxidized second layer M32 of the metal layer M3, the connection resistance with the metal layer M3 can be reduced.

[0190] Therefore, inspection pads TD can be formed on the mother substrate MB, where metal layers M3 and M4 are stably connected. By using such inspection pads TD, the display area DA (e.g., display elements DE1, DE2, DE3, etc.) can be reliably inspected. As a result, the reliability degradation of the mother substrate MB and the display device DSP can be suppressed.

[0191] Furthermore, in the manufacturing method of this embodiment, an opening AP20 is formed ( Figure 18A The position shown is not in the same position as the inspection opening AP10 (as shown). Figure 13A The positions shown overlap.

[0192] Therefore, the third layer M33 of metal layer M3 is exposed through opening AP20. Consequently, in process PR12, the oxide film on the surface of the third layer M33 exposed through opening AP20 can be removed (cleaned). As a result, poor electrical contact between metal layer M3 and metal layer M4 is less likely to occur. In other words, in this embodiment, a contact portion where poor electrical contact between metal layer M3 and metal layer M4 is less likely to occur can be formed.

[0193] Additionally, the second layer M32 is not exposed from the opening AP20. Therefore, compared with the use of Figure 29Compared to the manufacturing method of the comparative example display device DSP10, the dissolution of the second layer M32 of the metal layer M3 can be suppressed.

[0194] If the mother substrate MB, display device DSP, and display device DSP are manufactured as described above, reliability degradation can be suppressed. Furthermore, various other suitable effects can be obtained from this embodiment.

[0195] [Second Implementation]

[0196] The second embodiment will be described. The same configuration as the first embodiment can be applied to the configuration of the display device DSP, the mother substrate MB, and the manufacturing method of the display device DSP, which are not mentioned in this embodiment.

[0197] Figure 31 This is a schematic top view of the mother substrate MB in this embodiment. In this embodiment, the display area DA is a rectangle that is longer in the second direction Y. Additionally, the inspection pad TD is positioned near the pad PD (peripheral area SA). Specifically, the inspection pad TD is positioned between the cut line CL2 and the display area DA. It should be noted that the configuration of the inspection pad TD is not limited to this. Figure 31 The example shown. For instance, the inspection pad TD can also be configured between adjacent pads PD.

[0198] By cutting with cleaving line CL2, a display panel for a display device DSP equipped with inspection pads TD can be formed. Even if the panel portion PP has this structure, the same effect as in the first embodiment can be obtained by applying the structure disclosed in the first embodiment.

[0199] It should be noted that the structure of the panel portion (PP) can be adapted to various other configurations. For example, the display area (DA) of each panel portion (PP) can be a rectangle that is longer in the first direction (X), or it can be a square. Furthermore, the display area (DA) can also be a shape comprising multiple straight or curved sections.

[0200] Based on the display device, mother substrate, and manufacturing method described above as embodiments of the present invention, all display devices, mother substrates, and manufacturing methods that can be implemented by those skilled in the art with appropriate design modifications, as long as they contain the essence of the present invention, also fall within the scope of the present invention.

[0201] Within the scope of the present invention, various modifications will be conceived by those skilled in the art, and these modifications are also understood to fall within the scope of the present invention. For example, solutions obtained by appropriately adding, deleting, or designing the constituent elements of the above embodiments, or solutions obtained by adding, omitting, or changing the conditions of processes, are naturally included within the scope of the present invention as long as they possess the essence of the present invention.

[0202] Furthermore, regarding other effects brought about by the solutions described in the above embodiments, effects known from the description in this specification or effects that can be appropriately conceived by those skilled in the art are of course also understood to be brought about by the present invention.

Claims

1. A mother substrate for a display device, characterized in that, have: Multiple panel sections, each having a display area and a peripheral area surrounding the display area; A display element is disposed in the display area; A rib layer, disposed in the display area and the peripheral area, has pixel openings that overlap with the display element; and Inspect the pads, which are positioned in the surrounding area. The inspection pads have: First metal layer; and The second metal layer overlapping the first metal layer, The rib layer is disposed between the first metal layer and the second metal layer, and also has a first opening for contact between the second metal layer and the first metal layer. The first metal layer has: The first layer is formed of a first metallic material; A second layer formed of a second metallic material and overlapping the first layer; and A third layer formed of the first metallic material and overlapping the second layer. The third layer has an area in the first opening that exposes the second layer. The second metal layer has: The first contact portion that contacts the second layer in the region; and The second contact portion that contacts the third layer.

2. The mother substrate for a display device according to claim 1, characterized in that, It also includes inspection wiring that overlaps with the first metal layer. The first contact portion is located above the inspection wiring. The second contact portion is not located above the inspection wiring.

3. The mother substrate for a display device according to claim 1, characterized in that, It also includes an organic insulating layer disposed between the first metal layer and the rib layer. The organic insulating layer has a second opening that overlaps with the first opening. The area of ​​the second opening is smaller than the area of ​​the first opening when viewed from above. The first contact portion and the second contact portion are located inside the second opening.

4. The mother substrate for a display device according to claim 3, characterized in that, It also includes an inorganic insulating layer disposed between the organic insulating layer and the rib layer. The inorganic insulating layer has a third opening that overlaps with the first opening and the second opening.

5. The mother substrate for a display device according to claim 1, characterized in that, The display area also includes partition walls surrounding the pixel openings. The partition wall includes a lower portion disposed above the rib layer and an upper portion having an end portion protruding from the side of the lower portion.

6. The mother substrate for a display device according to any one of claims 1 to 5, characterized in that, The display area and the surrounding area also include a sealing layer, which is disposed above the rib layer and is formed of an inorganic material. The sealing layer has a fourth opening that overlaps with the first opening. The area of ​​the fourth opening is smaller than the area of ​​the first opening when viewed from above.

7. A mother substrate for a display device, characterized in that, have: Multiple panel sections, each having a display area and a peripheral area surrounding the display area; A display element is disposed in the display area; A rib layer, disposed in the display area and the peripheral area, has pixel openings that overlap with the display element; and Inspect the pads, which are positioned in the surrounding area. The inspection pads have: First metal layer; and The second metal layer overlapping the first metal layer, The rib layer is disposed between the first metal layer and the second metal layer, and has a first opening for the second metal layer to contact the first metal layer. The first metal layer has: The first layer is formed of a first metallic material; A second layer formed of a second metallic material and overlapping the first layer; and A third layer formed of the first metallic material and overlapping the second layer. The second metal layer has: The fourth layer is formed from the first metallic material; A fifth layer formed of the second metallic material and overlapping the fourth layer; and A sixth layer formed of the first metallic material and overlapping the fifth layer. The inspection pads are formed with a first part and a second part. The first part comprises a first layer, a second layer, a fourth layer, a fifth layer, and a sixth layer. The second part is composed of the first layer, the second layer, the third layer, the fourth layer, the fifth layer, and the sixth layer.

8. The mother substrate for a display device according to claim 7, characterized in that, The thickness of the second part is greater than the thickness of the first part.

9. The mother substrate for a display device according to claim 7, characterized in that, The spacing between the second layer and the fifth layer in the second part is larger than the spacing between the second layer and the fifth layer in the first part.

10. A display device, characterized in that, have: Display area; The surrounding area, which encloses the display area; A display element is disposed in the display area; A rib layer is disposed in the display area and the peripheral area, and has pixel openings that overlap with the display element; and Inspect the pads, which are positioned in the surrounding area. The inspection pads have: First metal layer; and The second metal layer overlapping the first metal layer, The rib layer is disposed between the first metal layer and the second metal layer, and has a first opening for the second metal layer to contact the first metal layer. The first metal layer has: The first layer is formed of a first metallic material; A second layer formed of a second metallic material and overlapping the first layer; and A third layer formed of the first metallic material and overlapping the second layer, the third layer having an area in the first opening exposing the second layer, the second metallic layer having: The first contact portion that contacts the second layer in the region; and The second contact portion that contacts the third layer.

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