SiC power module interconnection structure with low warpage deformation, SiC power module and preparation method thereof

Abstract

The application discloses a SiC power module interconnection structure with low warping deformation, a SiC power module and a preparation method thereof, and relates to the field of semiconductor preparation. The preparation method of the SiC power module with low warping deformation comprises the steps of pretreatment and assembly of a substrate and a buffer layer, chip mounting and sintering of an interconnection layer, electrode connection and stress isolation, and packaging integration and stabilization treatment. The preparation method of the SiC power module with low warping deformation constructs a whole-process stress control system including pretreatment, sintering, welding and packaging, a titanium-copper composite buffer layer and a invar buffer sheet form a double stress buffer barrier, four-stage sintering and gradient cooling precisely release thermal stress, stress matching design of the electrode connection and packaging process, effectively inhibits thermal stress accumulation at each link, significantly reduces the warping deformation of the substrate, guarantees the metallurgical bonding reliability of the SiC power chip and the copper-clad ceramic substrate, and greatly improves the module heat dissipation efficiency and long-term working stability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor fabrication, and in particular to a SiC power module interconnect structure with low warpage, a SiC power module, and a method for fabricating the same. Background Technology

[0002] During the fabrication and operation of SiC power modules, the inherent differences in the thermal expansion coefficients of core components such as the SiC power chip, copper-clad ceramic substrate, and interconnect materials, coupled with the lack of coordinated control strategies for thermal stress at each stage of traditional fabrication processes, lead to the gradual accumulation of thermal stress throughout the entire fabrication process. This ultimately causes warping and deformation of the copper-clad ceramic substrate. This warping creates micro-gaps between the SiC power chip and the heat dissipation interface, significantly increasing contact thermal resistance and reducing heat dissipation efficiency. It can also lead to peeling defects at critical interfaces such as the nano-silver interconnect layer and the copper plating layer, severely impacting the module's conductivity and long-term reliability. This issue becomes a core bottleneck restricting the performance improvement of SiC power modules, especially in large-size modules or operating scenarios with a wide temperature range of -55℃ to 200℃. Summary of the Invention

[0003] The purpose of this invention is to provide a SiC power module interconnect structure with low warpage deformation, a SiC power module and a method for fabricating the same, so as to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a method for fabricating a SiC power module with low warpage deformation, comprising the following steps:

[0005] S1. Pretreatment and assembly of substrate and buffer layer: The aluminum silicon carbide base plate, titanium-copper composite buffer layer and copper-clad ceramic substrate are cleaned, activated and vacuum annealed in sequence; the titanium-copper composite buffer layer is attached between the copper-clad ceramic substrate and the aluminum silicon carbide base plate to form a low-stress load-bearing component; and nano silver solder paste that has been degassed by vacuum is applied to the preset position of the copper layer of the copper-clad ceramic substrate.

[0006] S2. Chip mounting and interconnect layer sintering: Multiple SiC power chips are mounted on nano-silver solder paste in a centrally symmetrical array and pre-pressed and cured. The solder paste is then sintered in four stages to form a nano-silver interconnect layer. Finally, the temperature is cooled to room temperature through gradient cooling.

[0007] S3. Electrode connection and stress isolation: An Invar buffer sheet is attached to the lower surface of the electrode connection area of ​​the copper-clad ceramic substrate. The main electrode, driving electrode and copper layer are fixed by ultrasonic welding to form a gate star connection and an independent source circuit. Low temperature tempering is performed after welding.

[0008] S4. Packaging, integration and stabilization: Assemble the above structure with a special engineering plastic shell, fill the gaps with high-temperature silicone gel for sealing, and vacuum low-temperature annealing after packaging.

[0009] Preferably, in step S1: the nano-silver solder paste coating thickness is 50-100μm, and the uniformity error does not exceed 2%; the copper-clad ceramic substrate is annealed at 150℃ for 2 hours, and the aluminum silicon carbide substrate is annealed in stages from 120℃ for 1 hour to 180℃ for 2 hours; the edges of the copper-clad layer are rounded with a radius of 0.5-1mm; after pretreatment, the initial warpage of the substrate is controlled within 0.03%, laying the foundation for stress control in subsequent processes.

[0010] Preferably, the four-stage heating and sintering process in step S2 specifically includes:

[0011] Low-temperature dehumidification stage: The room temperature is increased to 120℃ at 2℃ / min and held for 10min to slowly remove the residual moisture in the nano-silver solder paste, avoiding rapid heating to generate bubbles that could lead to interconnect layer defects and thus cause local stress concentration.

[0012] Pre-sintering stage: Heat to 180℃ at 3℃ / min and hold for 8min to allow the solder paste to shrink and form initially, establish the initial connection between the SiC power chip and the copper-clad layer, and control the shrinkage rate to match the thermal expansion characteristics of the substrate.

[0013] Densification sintering stage: maintain a temperature increase of 3℃ / min to 220℃ and hold for 15min to allow the nano-silver particles to fully diffuse and fuse, forming a nano-silver interconnect layer with a density of ≥95%, ensuring thermal and electrical conductivity while reducing residual stress inside the interconnect layer;

[0014] Transitional cooling stage: Cooling down to 180℃ at 1℃ / min to achieve a smooth transition between sintering and subsequent gradient cooling, avoiding new thermal stress caused by sudden temperature changes;

[0015] The thermal conductivity of the nano-silver interconnect layer formed by this process is no less than 200 W / m. K, and the thermal expansion matching error with the substrate is ≤5%.

[0016] Preferably, in step S2, the gradient cooling process and the four-stage heating sintering process work together to achieve precise release of sintering stress, specifically including:

[0017] Differentiated cooling in different zones: The cooling rate of the central area of ​​the copper-clad ceramic substrate is 2℃ / min, the edge area is 1℃ / min, and the four corner areas are 0.8℃ / min, which matches the difference in thermal stress distribution in different areas of the copper-clad ceramic substrate, with the stress at the edge / corner being higher than that at the center.

[0018] Inert atmosphere assistance: Nitrogen gas with a purity of ≥99.99% is introduced into the furnace and directionally blown on the upper and lower surfaces of the copper-clad ceramic substrate to ensure that the temperature difference between the upper and lower surfaces of the substrate does not exceed 5°C, thus avoiding bending stress caused by temperature difference.

[0019] Two-stage stress relief pulse: Cooling is paused when the temperature reaches 150°C, and the temperature is raised to 160°C and held for 3 minutes to release the residual stress generated during the densification sintering stage. Cooling is paused again when the temperature reaches 80°C, and the temperature is raised to 90°C and held for 2 minutes to release the accumulated stress during the transition cooling and initial cooling stages. After the gradient cooling is completed, the substrate warpage is controlled within 0.06%.

[0020] Preferably, in step S3, the ultrasonic welding parameters are designed to be adapted to the electrode type, and work in conjunction with the gradient cooling strategy to ensure that no new stress is added during subsequent processing. Specifically, this includes:

[0021] Differentiated welding parameter adaptation: The main electrode uses 300W power, 50N pressure and 500ms time to ensure welding strength while reducing the heat-affected zone through high power and short time. The drive electrode uses 250W power, 40N pressure and 400ms time to avoid electrode damage or local deformation of the substrate caused by high power.

[0022] Synergistic isolation of welding stress: The Invar buffer sheet attached before welding works synergistically with the low-stress copper-clad ceramic substrate after gradient cooling to absorb the impact stress and local thermal stress generated by ultrasonic welding, so that the local warpage increment of the non-welded area of ​​the copper-clad ceramic substrate does not exceed 0.01%;

[0023] Post-weld stabilization treatment: The low-temperature tempering process parameters are 100℃ for 5 minutes, which is connected with the stress release logic of gradient cooling to further release residual welding stress. After welding, the connection resistance of each electrode is less than 1mΩ, and there are no peeling defects at the connection interface between the electrode and the substrate.

[0024] Preferably, in step S4, the vacuum low-temperature annealing parameters are 120°C and 3 hours of holding time. This, together with the four-stage heating sintering, gradient cooling, and ultrasonic welding processes, achieves final stress stabilization throughout the entire process, further releasing the assembly stress generated during the packaging and integration process, and ultimately stabilizing the substrate warpage to within 0.08%.

[0025] The low-warpage SiC power module interconnect structure is fabricated using a low-warpage SiC power module fabrication method. It is formed step by step by the collaborative process of the fabrication method steps S1-S3, including: multiple SiC power chips distributed in a centrally symmetrical array, a nano-silver interconnect layer, a copper-clad ceramic substrate, an aluminum silicon carbide substrate, an electrode system, a titanium-copper composite buffer layer, and an Invar buffer sheet. The warpage of the entire interconnect structure substrate does not exceed 0.1%, which is ensured by the above collaborative process.

[0026] Preferably, the copper-clad ceramic substrate is formed by a co-firing process of a copper-clad layer and an aluminum nitride ceramic layer, with the copper-clad layer located on the upper surface of the aluminum nitride ceramic layer; the nano-silver interconnect layer is solidified by a four-stage heating sintering process, completely filling the space between the bottom surface of the SiC power chip and the copper-clad layer, achieving a metallurgical bond between the two; the titanium-copper composite buffer layer is located between the lower surface of the aluminum nitride ceramic layer and the upper surface of the aluminum silicon carbide substrate, and is fixed by a bonding process; the electrode system includes a main electrode and a driving electrode, which are respectively fixedly connected to the corresponding area of ​​the edge of the copper-clad layer by an adaptive ultrasonic welding process, and the driving electrode forms a gate star connection and an independent source circuit; the Invar buffer sheet is attached to the lower surface of the copper-clad ceramic substrate corresponding to the connection area of ​​the main electrode and the driving electrode, on the same side as the titanium-copper composite buffer layer.

[0027] Preferably, the thermal conductivity of the nano-silver interconnect layer is not less than 200 W / m. K; The volume ratio of the copper clad layer to the aluminum nitride ceramic layer in the copper-clad ceramic substrate is 1:1.2 to 1:1.5, and the thermal conductivity of the aluminum nitride ceramic layer is not less than 200 W / m. K; The thickness of the titanium-copper composite buffer layer is 10-20μm, the volume ratio of Ti to Cu is 1:3, the thickness of the Invar buffer sheet is 0.5mm and the coefficient of thermal expansion does not exceed 1.5ppm / ℃.

[0028] The SiC power module includes a low-warpage SiC power module interconnect structure and a special engineering plastic shell. The special engineering plastic shell is fixed to an aluminum silicon carbide base plate and wraps around the interconnect structure. The gap between the special engineering plastic shell and the interconnect structure is filled with high-temperature silicon gel. The main electrode and the drive electrode are led out from the opening in the shell.

[0029] The technical effects and advantages of this invention are as follows:

[0030] 1. The fabrication method of this low-warpage SiC power module constructs a synergistic stress control system for the entire process of pretreatment, sintering, welding and packaging. The titanium-copper composite buffer layer and the Invar buffer sheet form a dual stress buffer barrier. The four-stage sintering and gradient cooling precisely release thermal stress. The stress matching design of electrode connection and packaging process effectively suppresses the accumulation of thermal stress in each stage, significantly reduces substrate warpage, and ensures the reliability of the metallurgical bonding between SiC power chip and copper-clad ceramic substrate, greatly improving the module's heat dissipation efficiency and long-term working stability.

[0031] 2. The fabrication method of this low-warpage SiC power module includes a four-stage heating and sintering process. The low-temperature dehumidification stage avoids defects and localized stress concentration in the nano-silver interconnect layer caused by solder paste bubbles. The pre-sintering stage controls the solder paste shrinkage rate to match the thermal expansion characteristics of the copper-clad ceramic substrate, reducing thermal mismatch stress. The densification sintering stage forms a nano-silver interconnect layer with a density ≥95%, ensuring thermal and electrical conductivity and reducing internal residual stress. The transition cooling stage achieves a smooth connection, avoiding sudden temperature changes that generate new thermal stress, and ensuring that the thermal expansion matching error between the nano-silver interconnect layer and the copper-clad ceramic substrate is ≤5%.

[0032] 3. The fabrication method of this low warpage SiC power module utilizes a gradient cooling process and a four-stage heating sintering process to achieve precise stress release during sintering. Differentiated cooling in different regions matches the thermal stress distribution differences in different areas of the copper-clad ceramic substrate, specifically alleviating high stress at the edges / corners. Inert atmosphere directional purging avoids bending stress caused by temperature differences. Two-stage stress release pulses precisely release residual stress accumulated in each stage of sintering, achieving precise stress release in conjunction with the sintering process, providing a low-stress foundation for subsequent electrode welding.

[0033] 4. The fabrication method of this low-warpage SiC power module utilizes ultrasonic welding parameters adapted to electrode type and a gradient cooling strategy to ensure no additional stress during subsequent processing. Differentiated welding parameters are adapted to the structural and performance requirements of the main electrode and drive electrode, ensuring welding strength while reducing the heat-affected zone. The Invar buffer sheet and the substrate state after gradient cooling work together to effectively absorb welding impact stress and local thermal stress, avoiding additional warpage during welding. The low-temperature tempering process is logically connected with the gradient cooling stress release to further release residual welding stress and ensure the reliability of electrode connections. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the process of the present invention;

[0035] Figure 2 This is a schematic diagram of the overall structure of the SiC power module of the present invention;

[0036] Figure 3 This is a schematic diagram of the internal structure of the SiC power module of the present invention;

[0037] Figure 4 This is a schematic diagram of the electrode system and the special engineering plastic shell of the present invention;

[0038] Figure 5 This is a partial structural schematic diagram of the SiC power module interconnect structure with low warpage deformation and the special engineering plastic shell of the present invention.

[0039] Figure 6 For the present invention Figure 5 Floor plan;

[0040] Figure 7 This is a schematic diagram of the structure of the SiC power chip, the nano-silver interconnect layer, and the copper-clad ceramic substrate of the present invention;

[0041] Figure 8 For the present invention Figure 7 Side view.

[0042] In the figure: 1. SiC power chip; 2. Nano-silver interconnect layer; 3. Copper-clad ceramic substrate; 31. Copper-clad layer; 32. Aluminum nitride ceramic layer; 4. Aluminum silicon carbide substrate; 5. Electrode system; 51. Main electrode; 52. Drive electrode; 6. Titanium-copper composite buffer layer; 7. Invar buffer sheet; 8. Special engineering plastic shell. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] This invention provides, for example Figures 1-8 The method for fabricating a SiC power module with low warpage deformation, as shown, includes the following steps:

[0045] S1. Pretreatment and assembly of substrate and buffer layer: The aluminum silicon carbide base plate 4, titanium-copper composite buffer layer 6 and copper-clad ceramic substrate 3 are cleaned, activated and vacuum annealed in sequence; the titanium-copper composite buffer layer 6 is attached between the copper-clad ceramic substrate 3 and the aluminum silicon carbide base plate 4 to form a low-stress load-bearing component; and nano silver solder paste that has been degassed by vacuum is applied to the preset position of the copper layer 31 of the copper-clad ceramic substrate 3.

[0046] S2. Chip mounting and interconnect layer sintering: Multiple SiC power chips 1 are mounted on nano-silver solder paste in a centrally symmetrical array and pre-pressed and cured. The solder paste is sintered in four stages to form nano-silver interconnect layer 2, and then cooled to room temperature through gradient cooling.

[0047] S3. Electrode connection and stress isolation: An Invar buffer sheet 7 is attached to the lower surface of the electrode connection area of ​​the copper-clad ceramic substrate 3. The main electrode 51, the driving electrode 52 and the copper-clad layer 31 are fixed by ultrasonic welding to form a gate star connection and an independent source circuit. After welding, the electrode is tempered at low temperature.

[0048] S4. Packaging, integration and stabilization: Assemble the above structure with the special engineering plastic shell 8, fill the gaps with high-temperature silicone gel for sealing, and vacuum low-temperature annealing after packaging.

[0049] A collaborative stress control system is constructed for the entire process of pretreatment, sintering, welding and packaging. The titanium-copper composite buffer layer 6 and the Invar buffer sheet 7 form a dual stress buffer barrier. The four-stage sintering and gradient cooling precisely release thermal stress. The stress matching design of electrode connection and packaging process effectively suppresses the accumulation of thermal stress in each stage, significantly reduces substrate warping deformation, and ensures the metallurgical bonding reliability of SiC power chip 1 and copper-clad ceramic substrate 3, greatly improving the module's heat dissipation efficiency and long-term working stability.

[0050] Furthermore, in step S1: the thickness of the nano-silver solder paste coating is 50-100μm, and the uniformity error does not exceed 2%; the copper-clad ceramic substrate 3 is annealed at 150℃ for 2 hours, and the aluminum silicon carbide substrate 4 is annealed in stages from 120℃ for 1 hour to 180℃ for 2 hours; the edges of the copper-clad layer 31 are rounded with a radius of 0.5-1mm; after pretreatment, the initial warpage of the substrate is controlled within 0.03%, laying the foundation for stress control in subsequent processes.

[0051] The high-precision coating of nano-silver solder paste avoids stress distribution imbalance after sintering. The targeted segmented annealing process accurately releases the internal residual stress of the copper-clad ceramic substrate 3 and the aluminum silicon carbide base plate 4. The rounded corner design of the copper-clad layer 31 reduces edge stress concentration. The strict control of the initial warpage lays the foundation for stress control in subsequent processes, reducing the risk of final substrate warpage from the source.

[0052] Furthermore, the four-stage heating and sintering process in step S2 specifically includes:

[0053] Low-temperature dehumidification stage: The room temperature is increased to 120℃ at 2℃ / min and held for 10min to slowly remove the residual moisture in the nano-silver solder paste, avoiding rapid heating to generate bubbles that could lead to interconnect layer defects and thus cause local stress concentration.

[0054] Pre-sintering stage: Heat to 180℃ at 3℃ / min and hold for 8min to allow the solder paste to shrink and form initially, establish the initial connection between SiC power chip 1 and copper layer 31, and control the shrinkage rate to match the thermal expansion characteristics of the substrate.

[0055] Densification sintering stage: maintain a temperature increase of 3℃ / min to 220℃ and hold for 15min to allow the nano-silver particles to fully diffuse and fuse, forming a nano-silver interconnect layer 2 with a density of ≥95%, ensuring thermal and electrical conductivity while reducing residual stress inside the interconnect layer;

[0056] Transitional cooling stage: Cooling down to 180℃ at 1℃ / min to achieve a smooth transition between sintering and subsequent gradient cooling, avoiding new thermal stress caused by sudden temperature changes;

[0057] The thermal conductivity of the nano-silver interconnect layer 2 formed by this process is no less than 200 W / m. K, and the thermal expansion matching error with the copper-clad ceramic substrate 3 is ≤5%.

[0058] During the low-temperature dehumidification stage, solder paste bubbles are avoided to prevent defects and localized stress concentration in the nano-silver interconnect layer 2. During the pre-sintering stage, the solder paste shrinkage rate is controlled to match the thermal expansion characteristics of the copper-clad ceramic substrate 3, reducing thermal mismatch stress. During the densification sintering stage, a nano-silver interconnect layer 2 with a density of ≥95% is formed, ensuring thermal and electrical conductivity and reducing internal residual stress. During the transition cooling stage, a smooth connection is achieved to avoid new thermal stress caused by sudden temperature changes, ensuring that the thermal expansion matching error between the nano-silver interconnect layer 2 and the copper-clad ceramic substrate 3 is ≤5%.

[0059] Furthermore, in step S2, the gradient cooling process and the four-stage heating sintering process work together to achieve precise release of sintering stress, specifically including:

[0060] Differentiated cooling in different zones: The cooling rate of the central region of the copper-clad ceramic substrate 3 is 2℃ / min, the edge region is 1℃ / min, and the four corner regions are 0.8℃ / min, which matches the difference in thermal stress distribution in different regions of the copper-clad ceramic substrate 3, with the stress at the edge / four corners being higher than that at the center.

[0061] Inert atmosphere assistance: Nitrogen gas with a purity of ≥99.99% is introduced into the furnace and directionally blows the upper and lower surfaces of the copper-clad ceramic substrate 3 to ensure that the temperature difference between the upper and lower surfaces of the substrate does not exceed 5°C, thus avoiding bending stress caused by temperature difference.

[0062] Two-stage stress relief pulse: Cooling is paused when the temperature reaches 150°C, and the temperature is raised to 160°C and held for 3 minutes to release the residual stress generated during the densification sintering stage. Cooling is paused again when the temperature reaches 80°C, and the temperature is raised to 90°C and held for 2 minutes to release the accumulated stress during the transition cooling and initial cooling stages. After the gradient cooling is completed, the substrate warpage is controlled within 0.06%.

[0063] Differentiated cooling in different regions of the copper-clad ceramic substrate is used to match the different thermal stress distributions in different areas, which can be used to alleviate high stress at the edges and corners. Inert atmosphere directional purging avoids bending stress caused by temperature difference. Two-stage stress release pulses accurately release the residual stress accumulated in each stage of sintering. In conjunction with the sintering process, it can achieve precise stress release and provide a low-stress foundation for subsequent electrode welding.

[0064] Furthermore, in step S3, the ultrasonic welding parameters are designed to be adapted to the electrode type, and work in conjunction with the gradient cooling strategy to ensure that no new stress is added during subsequent processing. Specifically, this includes:

[0065] Welding parameter differentiation adaptation: The main electrode 51 uses 300W power, 50N pressure and 500ms time to ensure welding strength while reducing the heat-affected zone through high power and short time. The driving electrode 52 uses 250W power, 40N pressure and 400ms time to avoid electrode damage or local deformation of the substrate caused by high power.

[0066] Synergistic isolation of welding stress: The Invar buffer sheet 7 attached before welding works in synergy with the low-stress copper-clad ceramic substrate 3 after gradient cooling to absorb the impact stress and local thermal stress generated by ultrasonic welding, so that the local warpage increment of the non-welded area of ​​the copper-clad ceramic substrate 3 does not exceed 0.01%;

[0067] Post-weld stabilization treatment: The low-temperature tempering process parameters are 100℃ for 5 minutes, which is connected with the stress release logic of gradient cooling to further release residual welding stress. After welding, the connection resistance of each electrode is less than 1mΩ, and there are no peeling defects at the connection interface between the electrode and the substrate.

[0068] Differentiated welding parameters are adapted to the structural and performance requirements of the main electrode 51 and the driving electrode 52, ensuring welding strength while reducing the heat-affected zone. The Invar buffer sheet 7 works in synergy with the state of the substrate after gradient cooling to effectively absorb welding impact stress and local thermal stress, avoiding additional warping during the welding process. The low-temperature tempering process is connected with the gradient cooling stress release logic to further release residual welding stress and ensure the reliability of electrode connection.

[0069] Furthermore, in step S4, the vacuum low-temperature annealing parameters are 120℃ and 3h, which, together with the four-stage heating sintering, gradient cooling and ultrasonic welding process, achieve the final stabilization of stress throughout the process, further releasing the assembly stress generated during the packaging and integration process, so that the substrate warpage is finally stabilized within 0.08%.

[0070] Vacuum low-temperature annealing specifically releases the assembly stress generated during the packaging and integration process, forming a whole-process stress synergistic control with pretreatment, sintering, cooling, welding and other preceding processes, ultimately stabilizing the substrate warpage within 0.08%, ensuring warpage stability during long-term module operation.

[0071] The low-warpage SiC power module interconnect structure is fabricated using a low-warpage SiC power module fabrication method. It is formed step by step by the collaborative process of the fabrication method steps S1-S3, including: multiple SiC power chips 1 distributed in a centrally symmetrical array, a nano-silver interconnect layer 2, a copper-clad ceramic substrate 3, an aluminum silicon carbide substrate 4, an electrode system 5, a titanium-copper composite buffer layer 6, and an Invar buffer sheet 7. The warpage of the entire interconnect structure substrate does not exceed 0.1%, which is ensured by the above collaborative process.

[0072] The interconnect structure components form an organic whole. The elastic deformation capabilities of the titanium-copper composite buffer layer 6, the Invar buffer sheet 7, and the nano-silver interconnect layer 2 work together to effectively absorb thermal stress. The layout of the centrally symmetrical array of SiC power chips 1 ensures uniform stress distribution, ultimately achieving low substrate warpage while improving the thermal conductivity and connection reliability of the interconnect structure.

[0073] Furthermore, the copper-clad ceramic substrate 3 is composited from a copper-clad layer 31 and an aluminum nitride ceramic layer 32 through a co-firing process, with the copper-clad layer 31 located on the upper surface of the aluminum nitride ceramic layer 32; the nano-silver interconnect layer 2 is solidified and formed by a four-stage heating sintering process, completely filling the space between the bottom surface of the SiC power chip 1 and the copper-clad layer 31, achieving a metallurgical bond between the two; the titanium-copper composite buffer layer 6 is located between the lower surface of the aluminum nitride ceramic layer 32 and the upper surface of the aluminum silicon carbide substrate 4, and is fixed by a bonding process; the electrode system 5 includes a main electrode 51 and a driving electrode 52, which are fixedly connected to the corresponding area of ​​the edge of the copper-clad layer 31 by an adaptive ultrasonic welding process, with the driving electrode 52 forming a gate star connection and an independent source circuit; the Invar buffer sheet 7 is attached to the lower surface of the copper-clad ceramic substrate 3 corresponding to the connection area of ​​the main electrode 51 and the driving electrode 52, on the same side as the titanium-copper composite buffer layer 6.

[0074] The co-fired composite structure of copper-clad layer 31 and aluminum nitride ceramic layer 32 ensures the basic performance of the substrate; the metallurgical bonding of nano-silver interconnect layer 2 improves connection reliability and thermal conductivity; the positional layout of titanium-copper composite buffer layer 6 and Invar buffer sheet 7 forms targeted stress buffer; the welding method and connection structure of electrode system 5 reduce circuit coupling and further optimize stress distribution.

[0075] Furthermore, the thermal conductivity of the silver nano-interconnect layer 2 is not less than 200 W / m. K; In the copper-clad ceramic substrate 3, the volume ratio of the copper-clad layer 31 to the aluminum nitride ceramic layer 32 is 1:1.2 to 1:1.5, and the thermal conductivity of the aluminum nitride ceramic layer 32 is not less than 200W / m. K; Titanium-copper composite buffer layer 6 with a thickness of 10-20μm, Ti to Cu volume ratio of 1:3, Invar buffer sheet 7 with a thickness of 0.5mm and a thermal expansion coefficient not exceeding 1.5ppm / ℃.

[0076] The high thermal conductivity of the nano-silver interconnect layer 2 and the aluminum nitride ceramic layer 32 improves heat dissipation efficiency. The optimized volume ratio of the copper cladding layer 31 and the aluminum nitride ceramic layer 32 reduces the thermal mismatch stress of the substrate itself. The material ratio of the titanium-copper composite buffer layer 6 and the low expansion characteristics of the Invar buffer sheet 7 further enhance the stress buffering capacity, and work together to ensure low warpage and high reliability.

[0077] The SiC power module includes a low-warpage SiC power module interconnect structure and a special engineering plastic housing 8. The special engineering plastic housing 8 is fixed to and encloses the interconnect structure with an aluminum silicon carbide base plate 4, and the gap between the special engineering plastic housing 8 and the interconnect structure is filled with high-temperature silicon gel. The main electrode 51 and the drive electrode 52 are led out from the opening in the housing.

[0078] The special engineering plastic housing 8 provides mechanical protection and insulation, while the high-temperature silicone gel filling and sealing enhances the module's sealing performance and mechanical stability, and also buffers assembly stress. The lead-out design of the main electrode 51 and the drive electrode 52 ensures stable electrical transmission. Combined with the low warpage characteristics of the interconnect structure, the module has excellent heat dissipation efficiency, long-term reliability and electromagnetic compatibility.

[0079] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating a SiC power module with low warpage deformation, characterized in that, Includes the following steps: S1. Pretreatment and assembly of substrate and buffer layer: The aluminum silicon carbide base plate (4), titanium-copper composite buffer layer (6) and copper-clad ceramic substrate (3) are cleaned, activated and vacuum annealed in sequence. The titanium-copper composite buffer layer (6) is attached between the copper-clad ceramic substrate (3) and the aluminum silicon carbide base plate (4) to form a low stress bearing component. The copper layer (31) of the copper-clad ceramic substrate (3) is coated with vacuum degassed nano silver solder paste at the preset position. S2, Chip mounting and interconnect layer sintering: Multiple SiC power chips (1) are mounted on nano silver solder paste in a centrally symmetrical array and pre-pressed and cured. The solder paste is then sintered in four stages to form a nano silver interconnect layer (2), and then cooled to room temperature through gradient cooling. S3. Electrode connection and stress isolation: An Invar buffer sheet (7) is attached to the lower surface of the electrode connection area of ​​the copper-clad ceramic substrate (3). The main electrode (51), the driving electrode (52) and the copper-clad layer (31) are fixed by ultrasonic welding to form a gate star connection and an independent source circuit. After welding, the circuit is tempered. S4. Packaging integration and stabilization treatment: The above structure is assembled with a special engineering plastic shell (8), and the gap is sealed by filling with high-temperature silicone gel. After packaging, vacuum annealing is performed. The four-stage heating and sintering process in step S2 specifically includes: Low-temperature dehumidification stage: The room temperature is increased to 120℃ at a rate of 2℃ / min and kept warm for 10min; Pre-sintering stage: Heat to 180℃ at 3℃ / min and hold for 8min to allow the solder paste to shrink and form initially, establish the initial connection between the SiC power chip (1) and the copper-clad layer (31), and control the shrinkage rate to match the thermal expansion characteristics of the substrate. Densification sintering stage: maintain a temperature of 3℃ / min to 220℃, hold for 15min to allow the nano-silver particles to fully diffuse and fuse, forming a nano-silver interconnect layer (2). Transition cooling stage: The temperature is reduced to 180℃ at a rate of 1℃ / min to achieve a smooth transition between sintering and subsequent gradient cooling.

2. The method for fabricating a low-warpage SiC power module according to claim 1, characterized in that, In step S1: the thickness of the nano silver solder paste coating is 50-100μm, the copper-clad ceramic substrate (3) is annealed at 150℃ and held for 2h, the aluminum silicon carbide base plate (4) is annealed in stages from 120℃ for 1h to 180℃ for 2h, and the edges of the copper-clad layer (31) are rounded with a radius of 0.5-1mm.

3. The method for fabricating a low-warpage SiC power module according to claim 1, characterized in that, The gradient cooling process in step S2 specifically includes: Differentiated cooling in different regions: The cooling rate of the central region of the copper-clad ceramic substrate (3) is 2℃ / min, the edge region is 1℃ / min, and the four corner regions are 0.8℃ / min, to match the thermal stress distribution differences in different regions of the copper-clad ceramic substrate (3). Inert atmosphere assistance: Nitrogen gas is introduced into the furnace and the upper and lower surfaces of the copper-clad ceramic substrate (3) are directionally purged; Two-stage stress relief pulse: Cooling is paused when the temperature reaches 150°C, and the temperature is raised to 160°C and held for 3 minutes to release the residual stress generated during the densification sintering stage. Cooling is paused again when the temperature reaches 80°C, and the temperature is raised to 90°C and held for 2 minutes to release the accumulated stress during the transition cooling and initial cooling stages.

4. The method for fabricating a low-warpage SiC power module according to claim 1, characterized in that, In step S3, the ultrasonic welding parameters are designed to be adapted to the electrode type, specifically including: Welding parameter differentiation adaptation: The main electrode (51) adopts 300W power, 50N pressure and 500ms time to ensure welding strength, while reducing the heat-affected zone by high power and short time; the driving electrode (52) adopts 250W power, 40N pressure and 400ms time. Synergistic isolation of welding stress: The Invar buffer sheet (7) attached before welding and the low-stress copper-clad ceramic substrate (3) after gradient cooling work together to absorb the impact stress and local thermal stress generated by ultrasonic welding. Post-weld stabilization treatment: The tempering process parameters are 100℃ and 5min, which is connected with the stress release logic of gradient cooling to release residual welding stress.

5. The method for fabricating a low-warpage SiC power module according to claim 1, characterized in that, In step S4, the vacuum annealing parameters are 120℃ and 3h.

6. A SiC power module interconnect structure with low warpage deformation, characterized in that, The SiC power module with low warpage deformation is prepared by the preparation method of any one of claims 1-5, and is formed step by step by the collaborative process of preparation method steps S1-S3, including: multiple SiC power chips (1) distributed in a centrally symmetrical array, a nano silver interconnect layer (2), a copper-clad ceramic substrate (3), an aluminum silicon carbide base plate (4), an electrode system (5), a titanium-copper composite buffer layer (6), and an Invar buffer sheet (7).

7. The low-warpage SiC power module interconnect structure according to claim 6, characterized in that, The copper-clad ceramic substrate (3) is formed by a co-firing process of a copper-clad layer (31) and an aluminum nitride ceramic layer (32). The copper-clad layer (31) is located on the upper surface of the aluminum nitride ceramic layer (32). The nano-silver interconnect layer (2) is solidified by a four-stage heating sintering process and completely fills the space between the bottom surface of the SiC power chip (1) and the copper-clad layer (31) to achieve metallurgical bonding between the two. The titanium-copper composite buffer layer (6) is located on the lower surface of the aluminum nitride ceramic layer (32) and the aluminum silicon carbide substrate (4). The upper surfaces are fixed together by bonding process. The electrode system (5) includes a main electrode (51) and a driving electrode (52). The two are fixedly connected to the corresponding area of ​​the edge of the copper-clad layer (31) by an adaptive ultrasonic welding process. The driving electrode (52) forms a gate star connection and an independent circuit with the source. The Invar buffer sheet (7) is attached to the lower surface of the copper-clad ceramic substrate (3) corresponding to the connection area of ​​the main electrode (51) and the driving electrode (52), on the same side as the titanium-copper composite buffer layer (6).

8. The low-warpage SiC power module interconnect structure according to claim 7, characterized in that, In the copper-clad ceramic substrate (3), the volume ratio of the copper-clad layer (31) to the aluminum nitride ceramic layer (32) is 1:1.2 to 1:1.5, and the titanium-copper composite buffer layer (6) has a thickness of 10-20 μm.

9. A SiC power module, comprising the low warpage SiC power module interconnect structure and a special engineering plastic housing (8) as described in any one of claims 6-8, characterized in that, The special engineering plastic shell (8) is fixed to the aluminum silicon carbide base plate (4) and wraps the interconnect structure. The gap between the special engineering plastic shell (8) and the interconnect structure is filled with high-temperature silicon gel. The main electrode (51) and the driving electrode (52) are led out from the opening of the shell.

Images