Chip packaging structure, packaging method thereof and electronic equipment

Abstract

The embodiment of the invention provides a chip packaging structure, a packaging method thereof and electronic equipment, relates to the technical field of semiconductors, and is used for reducing the packaging cost of the chip packaging structure. The chip packaging structure comprises a chip structure, a conductive structure, a plastic packaging layer and a supporting layer, wherein the chip structure and the conductive structure are stacked and electrically connected with each other; the plastic packaging layer is arranged on the conductive structure and surrounds the chip structure; and the supporting layer is arranged on the conductive structure and wraps at least part of the side surface of the chip structure. Wherein the plastic packaging layer and the supporting layer are arranged around the chip structure together, and at least part of the plastic packaging layer is attached to the side face of the chip structure. The material of the supporting layer is different from that of the plastic packaging layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a chip packaging structure and packaging method thereof, and electronic equipment. Background Technology

[0002] With the development of electronic technology, the functions of electronic devices are becoming increasingly diverse and comprehensive. This leads to the integration of chips that perform different functions into electronic devices, which in turn increases the demand for chip integration on integrated circuits within electronic devices. Consequently, integrated circuit packaging is evolving from planar packaging to vertically stacked packaging, such as 2.5D or 3D packaging, to improve the integration density of integrated circuits.

[0003] However, existing chip packaging processes are complex and costly in order to achieve high-density, small-size, and low-power chip packaging. Summary of the Invention

[0004] This application provides a chip packaging structure, packaging method, and electronic device to reduce the packaging cost of the chip packaging structure.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] A first aspect of this application provides a chip packaging structure, including a chip structure and a conductive structure stacked and electrically connected to each other, a molding compound layer disposed on the conductive structure and surrounding the chip structure, and a support layer disposed on the conductive structure and encapsulating at least a portion of the sides of the chip structure. The molding compound layer and the support layer together surround the chip structure, and at least a portion of the molding compound layer is attached to the sides of the chip structure. The support layer is made of a different material than the molding compound layer.

[0007] The chip packaging structure provided in this application embodiment has a support layer and a molding compound layer wrapped around at least part of the side surfaces of the chip structure. This strengthens the mechanical strength of the chip packaging structure, protects the chip structure, and improves its reliability. Furthermore, since the support layer is located on the side surface of the chip structure, and the material of the support layer has the same or similar coefficient of thermal expansion as the material of the chip structure, the expansion and contraction of the support layer and the chip structure are similar or similar during high-temperature expansion and low-temperature cooling. This makes the interaction force between the support layer and the chip structure negligible. The support layer provides mechanical protection for the chip structure, alleviates stress concentration problems caused by thermal expansion and contraction, reduces the risk of chip warpage in the chip packaging structure, and reduces the difference in thermal expansion coefficients caused by different materials. Because the support layer replaces part of the molding compound material, the amount of molding compound material used is reduced, which also lowers the packaging cost of the chip packaging structure. For larger chip structures, the material of the support layer has a certain degree of rigidity and can also provide support, preventing the molding compound layer from collapsing.

[0008] In one possible implementation, the molding compound layer surrounds the chip structure, and the support layer surrounds the molding compound layer. In this way, the molding compound layer also fills the gap between the support layer and the chip structure, thereby strengthening the mechanical strength of the chip package structure and protecting the chip structure.

[0009] In one possible implementation, the support layer is made of silicon or silicon dioxide. This provides one implementation of the support layer. When silicon is used as the support layer material, it can be formed by photoforming and etching processes on the wafer, reducing the cost of the chip packaging structure. Furthermore, since the support layer material is the same as the chip structure material, it can reduce the difference in thermal expansion coefficients caused by different materials and alleviate the stress effects caused by thermal expansion and contraction.

[0010] In one possible implementation, the chip structure thickness is greater than or equal to 100 μm, and the molding compound material includes epoxy molding compound. This strengthens the mechanical properties of the chip package structure, protects the chip structure, and improves its reliability. Using epoxy molding compound as the molding compound material avoids incomplete filling of the molding compound due to an excessively thick chip structure.

[0011] In one possible implementation, the chip structure thickness is less than 100 μm, and the molding compound includes a dry film layer or a chip bonding film layer. This reduces the cost of the chip packaging structure.

[0012] In one possible implementation, the chip package structure further includes a connection layer and a carrier plate; the connection layer is located on the side of the chip structure away from the conductive structure, and the carrier plate is located on the side of the connection layer away from the chip structure. In this way, the connection layer or the carrier plate covers the surface of the chip structure, thus protecting the surface of the chip structure.

[0013] In one possible implementation, the connecting layer and the encapsulating layer are integrally molded. This reduces the number of process steps and increases manufacturing efficiency.

[0014] In one possible implementation, the surface of the support layer furthest from the conductive structure is flush with the surface of the chip structure furthest from the conductive structure. This places the support layer on the side of the chip structure, reducing the risk of chip warpage in the chip package and mitigating stress concentration issues.

[0015] In one possible implementation, the conductive structure includes a redistribution layer and bumps; the bumps are located on the side of the redistribution layer away from the chip structure, and the redistribution layer and the bumps are electrically connected. This provides an embodiment of a chip package structure.

[0016] In one possible implementation, the chip package structure further includes a wafer structure; the wafer structure is disposed between the chip structure and the conductive structure; the wafer structure has a plurality of first contacts and a plurality of second contacts, and the chip structure has a plurality of third contacts and a plurality of fourth contacts; the first contacts and second contacts are electrically connected, and the third contacts and fourth contacts are electrically connected. The first contacts of the wafer structure are electrically connected to the third contacts of the chip structure. This provides an embodiment of a 3D IC chip package structure.

[0017] In one possible implementation, the chip package structure further includes an adapter board; the adapter board is disposed between the chip structure and the conductive structure, and is electrically connected to both the chip structure and the conductive structure. This provides an embodiment of a 2.5D IC chip package structure.

[0018] A second aspect of this application provides a chip packaging method, comprising: forming a support layer; the support layer having a through groove; placing a chip structure in the through groove; the support layer being disposed on at least a portion of the side surface of the chip structure; forming a molding compound layer, the molding compound layer filling the through groove and at least covering the side surface of the chip structure; forming a conductive structure, the conductive structure being electrically connected to the chip structure; and cutting the support layer or the molding compound layer so that the cut chip structure, conductive structure, molding compound layer and support layer form a chip packaging structure.

[0019] The chip packaging method provided in this application involves placing the chip structure after creating a through-groove in the support layer and filling it with molding compound material. This allows the support layer and molding compound to wrap around at least a portion of the sides of the chip structure, enhancing the mechanical strength of the chip packaging structure, protecting the chip structure, and improving its reliability. Furthermore, since the support layer is located on the side of the chip structure, and the material of the support layer has the same or similar coefficient of thermal expansion as the material of the chip structure, the expansion and contraction of the support layer and the chip structure are similar or nearly identical during high-temperature expansion and low-temperature cooling. This makes the interaction force between the support layer and the chip structure negligible. The support layer provides mechanical protection for the chip structure, mitigating stress concentration during thermal expansion and contraction, reducing the risk of chip structure warpage, and mitigating the difference in thermal expansion coefficients between different materials. The presence of the support layer reduces the amount of molding compound material used, thus lowering the packaging cost of the chip packaging structure. For larger chip structures, the support layer material has a certain degree of rigidity, providing additional support and preventing the molding compound from collapsing.

[0020] In one possible implementation, before forming the support layer, the method further includes: providing a wafer having a plurality of first contacts and second contacts; the first contacts being distributed on a first surface of the wafer, and the second contacts being distributed within the wafer, the first contacts and the second contacts being electrically connected; forming the support layer, including: forming the support layer on the first surface of the wafer; and exposing the first contacts with through-grooves. This provides a connection method for a chip structure.

[0021] In one possible implementation, placing the chip structure within the through-groove further includes connecting the chip structure to a first contact point on the wafer. This provides a connection method for the chip structure.

[0022] In one possible implementation, forming a conductive structure includes: forming a conductive structure on the side of the wafer away from the chip structure, and electrically connecting the conductive structure to a second contact. This provides a connection method between the wafer and the conductive structure.

[0023] In one possible implementation, a support layer is formed on a first surface of the wafer, comprising: forming a support film on the first surface of the wafer, the support film covering a plurality of first contacts of the wafer; and forming through grooves in the support film to expose at least a portion of the first contacts, thereby forming the support layer. In this way, the support layer is located on the side of the chip structure, which can reduce the risk of chip structure warping in the chip packaging structure and alleviate stress concentration problems.

[0024] In one possible implementation, after forming a support film on the first surface of the wafer and before creating through-grooves in the support film, the method further includes thinning the support film. This allows the thickness of the remaining support film to be close to the thickness of the chip structure to be placed.

[0025] In one possible implementation, the wafer and the support layer are connected using a fused bonding process. This provides a bonding method that enables high-density, small-size packaging structures and reduces the packaging cost of the chip.

[0026] In one possible implementation, the wafer and chip structure are connected using a hybrid bonding process. This provides a bonding method that enables high-density, small-size packaging structures and reduces the packaging cost of the chip package structure.

[0027] In one possible implementation, forming a conductive structure on the side of the wafer away from the chip structure includes: placing a carrier plate on the side of the chip structure away from the wafer; connecting the carrier plate and the chip structure via an interconnect layer; thinning the wafer to expose a second contact; forming a conductive structure on the second contact; and after forming the conductive structure on the second contact, and before cutting the support layer or molding compound, the method further includes: removing the carrier plate. This provides an implementation of the conductive structure.

[0028] In one possible implementation, the carrier board and the chip structure are connected using a lamination bonding process. This provides a bonding method and can reduce the packaging cost of the chip package structure.

[0029] In one possible implementation, forming the molding compound also includes forming the molding compound on a surface of the chip structure away from the wafer. This reduces the number of process steps and simplifies the fabrication process.

[0030] A third aspect of the embodiments of this application provides an electronic device, including a chip package structure and a printed circuit board according to any one of the first aspects, wherein the chip package structure is electrically connected to the printed circuit board.

[0031] The electronic device provided in the third aspect of the embodiments of this application includes the chip packaging structure of any one of the first aspects, and its beneficial effects are the same as those of the chip packaging structure, which will not be repeated here. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0033] Figure 2A This is a schematic diagram of a chip packaging structure carried on a PCB according to an embodiment of this application;

[0034] Figure 2BA schematic diagram illustrating a chip packaging structure;

[0035] Figure 3 This is a schematic diagram of a chip packaging structure provided in an embodiment of this application;

[0036] Figure 4 A schematic flowchart illustrating a chip packaging structure packaging method provided in this application embodiment;

[0037] Figures 5A-5R This is a schematic diagram illustrating a packaging method for a chip packaging structure provided in an embodiment of this application.

[0038] Figure 6A This is a schematic diagram of another chip packaging structure provided in an embodiment of this application;

[0039] Figure 6B This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0040] Figure 6C This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0041] Figure 7A This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0042] Figure 7B This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0043] Figure 8A This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0044] Figure 8B This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0045] Figure 8C This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0046] Figure 8D This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0047] Figure 8E This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0048] Figure 8F This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0049] Figure 9A This is a schematic diagram of another chip packaging structure provided in the embodiments of this application;

[0050] Figure 9B This is a schematic diagram of another chip packaging structure provided in an embodiment of this application.

[0051] Figure Labels

[0052] 1-Electronic device; 2-Display module; 3-Middle frame; 4-Housing; 5-Cover plate; 10-Chip packaging structure; 11-Packaging board; 12-Chip; 100-Wafer; 111-Through groove; 110-Chip structure; 120-Wafer structure; 130-Conductive structure; 131-Rewiring layer; 132-Bump; 140-Adapter board; 101-First contact; 102-Second contact; 103-First contact; 104-Second contact; a1-First surface; a2-Second surface; 210'-Support film; 210-Support layer; 220'-Encapsulation film; 220-Encapsulation layer; 310-Carrier board; 320-Connection layer. Detailed Implementation

[0053] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0054] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0055] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0056] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0057] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0058] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, or a financial terminal product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle DVDs, etc. Financial terminal products include ATMs, self-service terminals, etc. This application does not impose special limitations on the specific form of the above-mentioned electronic device. For ease of explanation, the following embodiments all use mobile phones as an example for illustration.

[0059] Example of the structure of an electronic device, such as Figure 1 As shown, the electronic device 1 mainly includes a display module 2, a middle frame 3, a housing (or battery cover, back cover) 4, and a cover plate 5.

[0060] The display module 2 has a light-emitting side that allows the display image to be seen and a non-light-emitting side that is opposite to the light-emitting side. The back of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.

[0061] The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, a cover glass (CG), which can have a certain degree of toughness.

[0062] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to mount internal components such as batteries, printed circuit boards (PCBs), cameras, and antennas. After the housing 4 is closed with the middle frame 3, the aforementioned internal components are located between the housing 4 and the middle frame 3.

[0063] For example, display module 2 includes a display panel (DP).

[0064] The aforementioned electronic device 1 also includes chip packaging structures disposed on a printed circuit board, such as a processor (CPU) chip, a radio frequency chip, a radio frequency power amplifier (PA) chip, a system on a chip (SOC), a power management integrated circuit (PMIC), a memory chip (e.g., high bandwidth memory (HBM)), an audio processor chip, a touch screen control chip, NAND flash, an image sensor chip, an artificial intelligence (AI) chip, and a game graphics card chip. The PCB is used to carry the aforementioned chip packaging structures and to complete signal interaction with the aforementioned chip packaging structures.

[0065] like Figure 2A As shown, the chip package structure 10 is mounted on a printed circuit board. Typically, the chip 12 with functional circuitry is electrically connected to the package board 11, and then electrically connected to the PCB through the package board 11.

[0066] Among them, the packaging board 11 is the carrier of the chip packaging structure and serves as the connector between the chip 12 and the PCB, thereby realizing the connection between the chip 12 and the PCB.

[0067] External pins (solder balls or pads) are provided on both the first and second surfaces of the package board 11. External pins on one surface of the package board 11 are connected to the chip 12, and external pins on the other surface are connected to the PCB.

[0068] For example, external pins on the first surface of the package board 11 are connected to the chip 12, and external pins on the second surface of the package board 11 are connected to the PCB.

[0069] The chip 12 is electrically connected to the packaging board 11. The chip 12 can be a bare chip or a packaged chip. This application embodiment does not limit this, and can be reasonably set according to the actual situation.

[0070] For example, chip 12 integrates at least one transistor, which may be a field-effect transistor (FET).

[0071] It is clarified here that field-effect transistors can include planar transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or junction field-effect transistors (JFETs), and can also include three-dimensional transistors such as fin field-effect transistors (FinFETs), gate all-around field-effect transistors (GAAFETs), or forksheet field-effect transistors (forksheet FETs or FSFETs). This application does not limit the scope of the field-effect transistors.

[0072] With the development of semiconductor technology, the functions of electronic devices 1 are becoming increasingly diverse and comprehensive. This necessitates the integration of chips 12, which perform different functions, within the electronic device 1, thus increasing the demand for chip packaging structures 10 on the printed circuit boards (PCBs) within the electronic device 1. While improving the performance of IC dies is crucial, the requirements for chip packaging structures 10 are also becoming increasingly stringent. On one hand, chips 12 are gradually becoming miniaturized, with their manufacturing processes shrinking—for example, towards 5nm, 3nm, and even 1nm, approaching physical limits. On the other hand, the increasing demand for heterogeneous integration of chips with different processes, functions, or materials presents new challenges to the development of planar PCBs, driving the development of PCB packaging from planar packaging to vertically stacked packaging, thereby realizing 3D IC packaging technology and 2.5D IC packaging technology. For example, chips with different functions, such as microelectromechanical system (MEMS) chips, radio frequency communication chips, passive device chips, and processor chips, can all be vertically stacked and integrated using the aforementioned packaging technologies, thereby maximizing the utilization of vertical integration space and improving the integration density of the PCB.

[0073] For example, in 2.5D IC packaging technology or 3D IC packaging technology, an interposer (INTP) is used to realize the interconnection between chips 12 and between chips 12 and the packaging board 11. Chip 12 is connected to the PCB through the interposer. As one of the important structures in chip packaging technology, the interposer has significant advantages in design and fabrication.

[0074] However, with the miniaturization of chip 12, its design cost has increased. To meet the miniaturization and multifunctionality requirements of the chip package structure 10, advanced packaging technology has become a development direction for semiconductor technology. Advanced packaging technology generally refers to packaging technology that integrates different systems into the same package to achieve higher system efficiency. In other words, as long as the packaging technology can improve the overall performance of the chip (including transmission speed, computing speed, etc.), it can be considered advanced packaging. Advanced packaging can achieve the requirements of high-density integration, miniaturization, and low cost of chips, and features small size, high performance, and low power consumption. Currently common advanced packaging technologies include fan-out packaging and fan-in packaging.

[0075] Taking chip 12 as an example (a bare IC die), this illustrates a fan-out packaging technology, such as... Figure 2B As shown, multiple IC dies with different functions are placed on an adapter board. Then, the IC dies are connected to the wafer via the adapter board using a chip-on-wafer (COW) packaging process, and finally connected to the packaging board 11. In other words, the chips are first connected to the wafer using COW packaging, and then the COW chips are connected to the packaging board 11, which is a 2.5D chip-on-wafer-on-substrate (CoWoS) structure. The IC dies are also surrounded by a molding compound.

[0076] The aforementioned COW bonding and chip-on-chip (COC) bonding both utilize thermal compression bonding (TCB) with microbumps, such as solder balls, as the bonding layer for connection. Due to the size limitations of solder balls—they are relatively large and spherical—chip packaging structures cannot be made smaller, hindering the development of high-density, small-size chip packaging structures. However, by using hybrid bonding methods with copper pads as the bonding layer, chip packaging sizes can be reduced to the nanometer scale. Therefore, using copper pads for interconnection enables higher-density chip packaging structures.

[0077] However, current chip packaging processes first require a temporary bonding process. This involves using temporary bonding adhesive to bond a support plate to one side of the chip structure, forming conductive structures such as bumps on the other side. Then, the support plate is removed using laser debonding or mechanical debonding processes, and any remaining temporary bonding adhesive on the chip surface is cleaned. Finally, a molding compound is formed, followed by dicing and other packaging processes to complete the packaging. Because the temporary bonding adhesive needs to be heat-resistant and easily removed (e.g., its properties must be altered and removed under laser irradiation), its cost is high, as is its removal. Furthermore, the high costs of the temporary bonding and debonding processes, as well as the relatively high costs of the molding compound and temporary bonding adhesive, contribute to the overall high cost of chip packaging.

[0078] Based on this, in order to reduce the cost of the packaging process, embodiments of this application provide a chip packaging structure, such as... Figure 3 As shown, the chip packaging structure includes a chip structure 110 and a conductive structure 130 stacked and electrically connected to each other, a molding compound 220 disposed on the conductive structure 130 and surrounding the chip structure 110, and a support layer 210 disposed on the conductive structure 130 and covering at least a portion of the sides of the chip structure 110. The molding compound 220 and the support layer 210 together surround the chip structure 110, and at least a portion of the molding compound 220 is attached to the sides of the chip structure 110. The support layer 210 is made of a different material than the molding compound 220.

[0079] In this way, both the support layer 210 and the molding compound 220 surround the side of the chip structure 110. The support layer 210 can replace part of the material of the molding compound 220, which can reduce the use of the molding compound 220 and thus reduce the packaging cost of the chip package structure 10.

[0080] like Figure 4 As shown in the figure, this application provides a chip packaging structure packaging method, including:

[0081] S1, such as Figure 5A As shown, wafer 100 is provided.

[0082] like Figure 5A As shown, wafer 100 has a plurality of first contacts 101 and a plurality of second contacts 102.

[0083] The wafer 100 may include a first surface a1 and a second surface a2 disposed opposite to each other.

[0084] For example, such as Figure 5AAs shown, the first contact 101 is distributed on the first surface a1 of the wafer 100, and the second contact 102 is distributed inside the wafer 100. The first contact 101 and the second contact 102 are electrically connected.

[0085] The first contact 101 and the second contact 102 can be directly connected, or they can be indirectly connected. This embodiment does not impose any limitations on this; the connection can be reasonably configured according to the actual situation.

[0086] Regarding the first contact 101 and the second contact 102, for example, the first contact 101 and the second contact 102 can be formed on the surface of the wafer using through silicon via (TSV) technology and damascus etching. The damascus etching process involves first etching out the area to be formed of the metal interconnect structure, and then filling it with metal material to achieve multilayer metal interconnects. The aforementioned surface of the wafer is the first surface a1 of the formed wafer 100.

[0087] In this embodiment, the distribution of the first contact 101 and the second contact 102 is not limited. For example, the distribution of the first contact 101 and the second contact 102 can be configured according to the dicing path of the wafer 100. For example, the first contact 101 and the second contact 102 may not be formed on the dicing path.

[0088] The specific structure of wafer 100 is not limited in the embodiments of this application. For example, Figure 5B As shown, the wafer can be an unprocessed wafer obtained from a wafer fab, which is then used to form the first contact 101 and the second contact 102.

[0089] S2, such as Figure 5C As shown, a support layer 210 is formed on the first surface a1 of wafer 100.

[0090] like Figure 5C As shown, the support layer 210 has a through groove 111. The through groove 111 exposes the first contact point 101.

[0091] For example, step S2 may include:

[0092] S21, such as Figure 5C As shown, a support film 210' is formed on the first surface a1 of the wafer 100, and the support film 210' covers a plurality of first contacts 101 of the wafer 100.

[0093] For example, the support film 210' may include a wafer. The material of the support film 210' may include, for example, silicon, silicon oxide, silicon dioxide, metal, or other materials with similar functions and compatible with subsequent packaging processes. The support film 210' may include, for example, a glass layer, a ceramic layer, or a polymer layer.

[0094] Furthermore, the shape of the support film 210' can be a wafer, a square, or any other arbitrary shape. In this embodiment, the material and shape of the support film 210' are not limited; they can be reasonably set according to actual conditions.

[0095] When the support film 210' is a wafer, the material of the support film 210' is the same as that of the wafer 100 mentioned above. This can reduce the difference in the coefficient of thermal expansion (CTE) caused by different materials and alleviate the stress effects caused by thermal expansion and contraction. In addition, using a wafer as the support film 210' can reduce packaging costs.

[0096] For example, the support film 210' and the wafer 100 can be connected by fusion bonding.

[0097] This enables wafer-to-wafer (W2W) bonding, allowing for high-density, small-size packaging structures at a lower cost.

[0098] S22, such as Figure 5C As shown, the support membrane is thinned to 210'.

[0099] In other words, the surface of the support film 210' away from the wafer 100 is thinned. For example, the support film 210' can be thinned by grinding using a chemical mechanical polishing (CMP) process.

[0100] In this embodiment, the thickness of the support film 210' is determined based on the thickness of the subsequent chip structure to be connected. For example, the thickness of the remaining support film 210' is the same as or similar to the thickness of the subsequent chip structure to be connected. For instance, the thickness of the remaining support film 210' can be the same as the thickness of the subsequent chip structure to be connected. Alternatively, the thickness of the remaining support film 210' can be less than the thickness of the subsequent chip structure to be connected. This embodiment does not limit this; it can be reasonably set according to the actual situation.

[0101] In this way, in subsequent packaging process steps, there is no need to grind the support film 210' to make the thickness of the chip structure the same as that of the support film 210', which can avoid damage to the chip structure when the support film 210' is thinned after the chip structure is placed.

[0102] S23, such as Figure 5C As shown, a through groove 111 is formed on the support membrane 210' to form a support layer 210.

[0103] For example, a patterned support membrane 210' is formed to form a support layer 210.

[0104] For example, the through-groove 111 can be formed using photoforming and etching processes. The size of the through-groove 111 along the direction perpendicular to the thickness of the wafer 100 is close to the size of the chip structure to be placed subsequently.

[0105] At this point, at least part of the first contact point 101 is exposed in the through groove 111.

[0106] For example, multiple through grooves 111 are formed on the support film 210', and the remaining support film 210' (i.e. support layer 210) can be located on the dicing path of the wafer 100 for subsequent dicing.

[0107] In this embodiment of the application, after the through groove 111 is opened, the exposed first contact point 101 is also cleaned to remove the residual impurities on the first contact point 101.

[0108] S3, such as Figure 5D As shown, the chip structure 110 is placed in the through slot 111, and the chip structure 110 is connected to the first contact 101 of the wafer 100.

[0109] At this time, such as Figure 5D As shown, the support layer 210 is disposed on at least a portion of the side surface of the chip structure 110.

[0110] It is clarified here that the surface of the chip structure 110 that is in contact with the wafer 100 is called the bottom surface of the chip structure 110, the surface opposite to the bottom surface of the chip structure 110 is called the top surface of the chip structure 110, and the surface that connects the top surface and the bottom surface of the chip structure 110 is called the side surface of the chip structure 110.

[0111] For example, the support layer 210 may be disposed on at least one side of the chip structure 110. For instance, the support layer 210 may be disposed on one side of the chip structure 110. Alternatively, the support layer 210 may be disposed on two sides of the chip structure 110. Alternatively, the support layer 210 may be disposed on three sides of the chip structure 110. Alternatively, the support layer 210 may be disposed on all four sides of the chip structure 110. This application does not limit the scope of the embodiments.

[0112] like Figure 5D As shown, there is a gap between the support layer 210 and the chip structure 110. This is because when the size of the through groove 111 opened on the support layer 210 is larger than the size of the chip structure 110, the chip structure 110 can be placed in the through groove 111.

[0113] When the chip structure 110 is placed in the through groove 111, one side of the chip structure 110 can be in contact with one side wall of the through groove 111, and at this time there is a gap between the opposite side of the chip structure 110 and the opposite side of the through groove 111.

[0114] For example, the chip structure 110 is a quadrilateral, as illustrated below. Figure 5E As shown, the two adjacent sidewalls of chip structure 110-1 are in contact with the two adjacent groove walls of through groove 111, one sidewall of chip structure 110-2 is in contact with one groove wall of through groove 111, and the sidewall of chip structure 110-3 is not in contact with the groove wall of through groove 111.

[0115] At this point, there are gaps between the two adjacent sidewalls of chip structure 110-1 and the support layer 210. There are gaps between the three sidewalls of chip structure 110-2 and the support layer 210, and gaps between all four sidewalls of chip structure 110-3 and the support layer 210. In this embodiment, the relative positions of the chip structure 110 and the support layer 210 are not limited; they can be reasonably set according to actual conditions.

[0116] For example, chip structure 110 can be a bare chip (also called a die or particle). It is understood that a bare chip is obtained by dicing a wafer.

[0117] At this point, the chip structure 110 can select the diced small chips by means of known good die (KGD). For example, known good die chips can be picked up and placed in the through slot 111.

[0118] Alternatively, for example, chip structure 110 can also be a packaged chip obtained by packaging a bare chip.

[0119] The chip structure 110 placed in a through slot 111 can be one or more.

[0120] For example, such as Figure 5F As shown, multiple chip structures 110 can be arranged side by side at intervals on the wafer 100 and located within the through groove 111.

[0121] Or, for example, such as Figure 5F As shown, multiple chip structures 110 can be stacked and disposed on wafer 100, and are located in through slot 111.

[0122] It is understandable that the aforementioned multiple chip structures 110 can all be bare chips, or all be packaged chips. Alternatively, they can be partially bare chips and partially packaged chips.

[0123] In some implementations, the chip structure 110 is connected to the wafer 100 via a first contact 101. For example, such as... Figure 5F As shown, the chip structure 110 and the wafer 100 can be connected via hybrid bonding. The chip structure 110 has multiple third contacts 103 and fourth contacts 104. The third contacts 103 and fourth contacts 104 are electrically connected. Specifically, the connection between the chip structure 110 and the wafer 100 is achieved through the third contacts 103 of the chip structure 110 and the first contacts 101 of the wafer 100.

[0124] This enables hybrid bonding between chip-to-wafer (C2W) structures, avoiding connections through solder balls or other bumps. It removes size limitations on the chip structure 110, allowing for the use of smaller chip structures 110. This results in high-density, small-size chip packaging structures without the need for soldering, leading to lower packaging costs and facilitating the realization of three-dimensional stacked chip packaging structures.

[0125] Or, for example, such as Figure 5G As shown, the chip structure 110 and the wafer 100 can be connected by bumps such as solder balls.

[0126] S4, such as Figure 5H As shown, a molding layer 220 is formed.

[0127] like Figure 5H As shown, the molding compound 220 fills the through-groove 111 and at least partially covers the sidewalls of the chip structure 110. That is, the molding compound 220 fills the gap between the support layer 210 and the chip structure 110.

[0128] It should be noted here that the molding layer 220 and the support layer 210 can be obtained after cutting. Figure 3 The shown chip packaging structure 10 includes a molding layer 220 and a support layer 210.

[0129] This application does not limit the formation process and materials of the molding compound 220. For example, a molding compound 220' is formed in the gap between the support layer 210 and the chip structure 110 on the wafer 100 using an injection molding process. The material of the molding compound 220' may include epoxy resin. For example, the material of the molding compound 220' may include epoxy molding compound (EMC), underfill (UF), adhesive material (AD), and thermal interface material (TIM), etc.

[0130] This application embodiment does not limit the structure of the molding compound 220. The formed molding compound 220 is disposed on the wafer 100 and fills the gap between the support layer 210 and the chip structure 110. For example, the thickness of the molding compound 220 is reasonably set according to the layout of the chip structure 110, so that the molding compound 220 at least covers the side surface of the chip structure 110. Whether the molding compound 220 covers the top surface of the chip structure 110 is not limited.

[0131] The function of the molding layer 220 is to enhance the mechanical strength of the subsequently formed chip package structure 10, protect the chip structure 110, and improve the reliability of the chip package structure.

[0132] In some embodiments, such as Figure 5H As shown, the molding compound 220 encapsulates at least a portion of the side surfaces of the chip structure 110, exposing the top surface of the chip structure 110 (the surface of the chip structure 110 away from the wafer).

[0133] In this way, no molding layer 220 is formed on the top surface of the chip structure 110, which is beneficial for heat dissipation of the chip structure 110 surface.

[0134] Regarding formation Figure 5H The method of molding compound 220 shown is exemplary, such as... Figure 5H As shown, a molding compound 220 is formed directly in the gap between the chip structure 110 and the support layer 210, exposing the top surface of the chip structure 110.

[0135] This method of directly forming the molding layer 220 has fewer process steps, higher preparation efficiency, and is beneficial for heat dissipation on the surface of the chip structure 110.

[0136] Or, for example, such as Figure 5I As shown, a molding compound 220' can be formed on the surface of the chip structure 110 first. The molding compound 220' wraps the side and top surfaces of the chip structure 110. Then, the surface of the molding compound 220' away from the wafer 100 is ground to expose the top surface of the chip structure 110. The remaining molding compound 220' serves as the molding layer 220.

[0137] One method for grinding the plastic sealant 220' is, for example, to use a chemical mechanical polishing process to grind the plastic sealant 220'.

[0138] In other embodiments, such as Figure 5J As shown, the molding compound 220 encapsulates the sides and top of the chip structure 110.

[0139] This eliminates the need for grinding the molding layer 220, reducing the number of process steps.

[0140] This application embodiment does not limit the structure of the molding compound 220. The thickness of the molding compound 220 is reasonably set according to the layout of the chip structure 110 so that the molding compound 220 covers at least part of the side surfaces of the chip structure 110. There is no limitation on whether the molding compound 220 covers the top surface of the chip structure 110.

[0141] S5. A conductive structure is formed on the side of wafer 100 away from chip structure 110.

[0142] In some embodiments, step S5 includes:

[0143] S51, such as Figure 5K As shown, the carrier board 310 is placed on the side of the chip structure 110 away from the wafer 100.

[0144] The carrier substrate 310 may include a wafer. The material of the carrier substrate 310 may include, for example, silicon, silicon oxide, silicon dioxide, metal, or other materials with similar functions and compatible with subsequent packaging processes. The carrier substrate 310 may include, for example, a glass layer, a ceramic layer, or a polymer layer.

[0145] The substrate 310 can be wafer-shaped, square, or any other shape. In this embodiment, the material and shape of the substrate 310 are not limited; they can be reasonably set according to actual conditions.

[0146] When the carrier 310 is a wafer, packaging costs can be reduced.

[0147] For example, such as Figure 5J As shown, the carrier board 310 and the chip structure 110 are connected by a connection layer 320.

[0148] In some embodiments, the connecting layer 320 and the molding layer 220 are separate structures.

[0149] For example, the material of the bonding layer 320 may include an adhesive film layer or an adhesive. For instance, the bonding layer 320 may include a dry film layer or a die attach film (DAF) layer. The material of the bonding layer 320 may be the same as or different from the material of the molding compound layer 220.

[0150] The carrier board 310 and the chip structure 110 are connected using a lamination bonding process. To fix the carrier board 310 onto the chip structure 110, the carrier board 310 and the chip structure 110 are bonded together using a connecting layer 320. In this embodiment, there is no need for a temporary bonding process to connect the carrier board 310 and the chip structure 110, nor is there a need to use temporary bonding adhesive to connect the carrier board 310 and the chip structure 110. Therefore, the lamination bonding process in this embodiment can reduce the packaging cost of the chip packaging structure.

[0151] In other embodiments, the connecting layer 320 and the molding layer 220 are integrally formed.

[0152] For example, such as Figure 5L As shown, during step S4, when the molding compound 220 is formed, the molding compound 220 wraps around the side and top surfaces of the chip structure 110. At this time, the molding compound 220 material on the side of the chip structure 110 serves as the molding compound 220, and the molding compound 220 material on the top surface of the chip structure 110 serves as the interconnecting layer 320. Then, in step S51, the carrier board 310 is placed on the surface of the interconnecting layer 320 away from the wafer 100, so that the carrier board 310 is connected to the chip structure 110 and the wafer 100 through the interconnecting layer 320.

[0153] Or, such as Figure 5M As shown, steps S4 and S51 can be performed in the same process step. For example, using an adhesive material, lamination bonding is used to fill the through-groove 111, that is, to fill the gap between the chip structure 110 and the support layer 210. Adhesive material is also retained on the surface of the chip structure 110 away from the wafer 100 for connection to the carrier 310.

[0154] At this point, the adhesive material on the side of the chip structure 110 serves as the molding layer 220, and the adhesive material on the top surface of the chip structure 110 serves as the connecting layer 320.

[0155] To avoid incomplete filling of the molding compound 220, when the thickness of the chip structure 110 is less than 100μm, the above method can be used to form an integrally molded connection layer 320 and molding compound 220.

[0156] S52, such as Figure 5N As shown, the wafer 100 is thinned to expose the second contact 102.

[0157] At this point, the structure after step S52 is flipped, that is, the carrier board 310 is used to carry the wafer 100 and chip structure 110 and other structures set thereon.

[0158] At this point, the second surface a2 of the wafer 100 is ground to expose the second contact 102.

[0159] S53, such as Figure 5O As shown, a conductive structure 130 is formed on the second contact 102.

[0160] The conductive structure 130 is electrically connected to the second contact 102.

[0161] For example, the conductive structure 130 may include a redistribution layer (RDL) 311 and bumps 312.

[0162] In some embodiments, step S53 may include:

[0163] S531, A redistribution layer 131 is formed on the surface of wafer 100 away from the substrate 310.

[0164] The rewiring layer 131 is electrically connected to the second contact 102.

[0165] S532, A bump 132 is formed on the surface of the redistribution layer 131 on the side away from the carrier board 310.

[0166] For example, bump 132 may include structures made of metal solder such as solder balls, bumps, copper pillars, under-bump metallization (UBM), and controlled-collapse chip connection bumps (C4 bumps). Of course, the material and shape of bump 132 are not limited in this embodiment, and the fabrication process of bump 132 varies depending on its structure.

[0167] For example, when the structure of the bump 132 is a solder ball, it can be prepared by processes such as coating, exposure, development, solder paste printing, and ball placement.

[0168] Alternatively, for example, when the structure of bump 132 is a copper pillar, it can be prepared by processes such as coating, exposure, development, curing, sputtering, electroplating, etching, and reflow. Different preparation processes can be selected as needed to form bumps 132 with different structures.

[0169] In this embodiment, different conductive structures 130 can be formed according to actual needs. For example, only the redistribution layer 131 can be formed, or only the bumps 132 can be formed, or both the redistribution layer 131 and the bumps 132 can be formed.

[0170] S54, such as Figure 5P As shown, remove carrier plate 310.

[0171] In step S54, the structure formed in step S53 is first flipped over and placed on the support plate, and then the support plate 310 is removed.

[0172] For example, the process of removing the carrier 310 can be a grinding process or a thinning process. For instance, mechanical grinding, chemical mechanical planarization, wet etching, or dry etching can be used to remove the carrier 310.

[0173] At this point, the surface of the chip structure 110 away from the wafer 100 may still retain part of the interconnect layer 320 and the interconnect layer 320.

[0174] Alternatively, by way of example, the carrier board 310 can be removed by removing the connection layer 320 between the carrier board 310 and the chip structure 110.

[0175] In this embodiment, the carrier board does not need to be removed through a debonding process, thus reducing the packaging cost of the chip packaging structure.

[0176] S6, such as Figure 5Q As shown, the chip packaging structure 10 is formed by cutting.

[0177] For example, the surface of the molding layer 220 or the support layer 210 is cut to form a chip package structure 10.

[0178] like Figure 5Q As shown, the surface of the chip structure 110 away from the wafer 100 is exposed, which means that the surface of the molding layer 220 or the support layer 210 is cut to form the chip package structure 10.

[0179] At this time, such as Figure 5Q As shown, wafer 100 can be diced to form multiple discrete chip structures 120. Chip structure 110, diced wafer 100 (chip structure 120), diced conductive structure 130, diced interconnect layer 210, and diced molding compound layer 220 form chip package structure 10.

[0180] In this embodiment, cutting can be performed along the molding layer 220, along the support layer 210, or along the interface between the molding layer 220 and the support layer 210. The molding layer 220 has low material hardness, making it easy to cut without damaging the cutting tool.

[0181] Or, for example, such as Figure 5R As shown, the surface of the chip structure 110 away from the wafer 100 is also covered by a connection layer 320 and a carrier plate 310. This means that the surface of the connection layer 320 or the carrier plate 310 is cut to form the chip packaging structure 10.

[0182] At this point, the cutting path is located in the gap between the chip structures 110.

[0183] It should be noted that, in the embodiments of this application, the option to perform cutting can be selected according to actual needs.

[0184] The encapsulation method provided in this application does not impose any restrictions on the order of steps and can be reasonably adjusted as needed.

[0185] Furthermore, steps S1-S6 above can be omitted as needed, and are not required to be included in every step. Steps can also be added as needed, and are not limited to only the steps described above.

[0186] The chip packaging method provided in this application involves placing the chip structure 110 after creating a through groove 111 in the support layer 210 and filling it with molding compound 220 material. This allows the support layer 210 and molding compound 220 to wrap around at least a portion of the side surfaces of the chip structure 110, enhancing the mechanical strength of the chip packaging structure 10, protecting the chip structure 110, and improving the reliability of the chip packaging structure 10. Furthermore, since the support layer 210 is located on the side surface of the chip structure 110, and the material of the support layer 210 has the same or similar coefficient of thermal expansion as the material of the chip structure 110, the expansion and contraction of the support layer 210 and the chip structure 110 are the same or similar during high-temperature expansion and low-temperature cooling. This makes the interaction force between the support layer 210 and the chip structure 110 negligible. The support layer 210 can provide mechanical protection for the chip structure 110, alleviating stress concentration problems caused by thermal expansion and contraction, reducing the risk of warping of the chip structure 110 in the chip packaging structure 10, and reducing the difference in coefficient of thermal expansion caused by different materials. Because the support layer 210 replaces part of the material of the molding compound 220, the amount of material used in the molding compound 220 is reduced, and the packaging cost of the chip packaging structure 10 can also be reduced. For the larger chip structure 110, the material of the support layer 210 has a certain degree of rigidity and can also play a supporting role to prevent the molding compound 220 from collapsing.

[0187] Furthermore, the packaging method provided in this application achieves bonding between the chip structure and the wafer through fusion bonding and hybrid bonding, enabling high-density, small-size packaging structures without the need for soldering, resulting in lower packaging costs and facilitating the realization of three-dimensional stacked chip packaging structures. In the carrier removal process, the carrier is removed by grinding, eliminating the need for debonding processes and temporary bonding adhesives, thus reducing packaging process costs.

[0188] The following embodiments illustrate the chip packaging structure provided in this application. The chip packaging structure can be prepared using the packaging method described above.

[0189] Based on this, such as Figure 6AAs shown, the chip package structure 10 includes a chip structure 110 and a conductive structure 130 stacked and electrically connected to each other, a molding compound 220 disposed on the conductive structure 130 and surrounding the chip structure 110, and a support layer 210 disposed on the conductive structure 130 and covering at least a portion of the sides of the chip structure 110. The molding compound 220 and the support layer 210 together surround the chip structure 110, and at least a portion of the molding compound 220 is attached to the sides of the chip structure 110. The support layer 210 is made of a different material than the molding compound 220.

[0190] Regarding chip structure 110, chip structure 110 may include one chip or multiple chips.

[0191] This application does not limit the chip structure in chip structure 110. In some embodiments, the chip can be a bare chip (also called a die or particle). It is understood that a bare chip is obtained by dicing a wafer.

[0192] In other embodiments, the chip may also be a packaged chip obtained by packaging a bare chip.

[0193] For example, the chip structure 110 may include one or more chips.

[0194] like Figure 6A As shown, chip structure 110 includes a chip.

[0195] Or, for example, such as Figure 6B As shown, the chip structure 110 includes multiple chips. For example, such as Figure 6B As shown, multiple chips are arranged side by side with intervals.

[0196] Or, such as Figure 6C As shown, multiple chips can be stacked and disposed on the wafer structure 120.

[0197] It is understandable that when chip structure 110 includes multiple chips, all of the chips can be bare chips; all of the chips can be packaged chips; or some of the chips can be bare chips and some can be packaged chips.

[0198] In some embodiments, continue to refer to Figure 6A The chip package structure 10 also includes a wafer structure 120. The chip structure 110 and the wafer structure 120 are electrically connected.

[0199] For example, the wafer structure 120 may be formed by wafer dicing.

[0200] Regarding the connection method between chip structure 110 and wafer structure 120, an example is as follows: Figure 6A As shown, chip structure 110 and wafer structure 120 can be connected via hybrid bonding. For example, wafer structure 120 has multiple first contacts 101 and multiple second contacts 102, and chip structure 110 has multiple third contacts 103 and fourth contacts 104. First contacts 101 and second contacts 102 are electrically connected, and third contacts 103 and fourth contacts 104 are electrically connected. Specifically, the connection between chip structure 110 and wafer structure 120 is achieved through the electrical connection of the third contacts 103 of chip structure 110 and the first contacts 101 of wafer structure 120.

[0201] At this point, the connection between chip structure 110 and wafer structure 120 can be viewed as a chip packaging structure for 3D IC packaging.

[0202] This enables hybrid bonding between wafers on the chip, avoiding connections through solder balls or other bumps. It removes size limitations on the chip structure 110, allowing for the use of smaller chip structures 110. This results in high-density, small-size chip packaging structures without the need for soldering, leading to lower packaging costs and facilitating the realization of three-dimensional stacked chip packaging structures.

[0203] Or, for example, such as Figure 7A As shown, the chip structure 110 and the wafer structure 120 can be connected by bumps such as solder balls.

[0204] At this point, the connection between chip structure 110 and wafer structure 120 can be viewed as a chip packaging structure for 2.5D IC packaging.

[0205] In this embodiment, the connection method between chip structure 110 and wafer structure 120 is not limited; it can be set reasonably according to the actual situation.

[0206] Regarding conductive structure 130, such as Figure 7A As shown, the conductive structure 130 may include a redistribution layer 131 and bumps 132.

[0207] like Figure 7A As shown, bump 132 is located on the side of redistribution layer 131 away from chip structure 110, and bump 132 is electrically connected to redistribution layer 131.

[0208] Conductive structure 130 is used to connect chip structure 110 and package board ( Figure 7A (Not shown in the image).

[0209] In this embodiment, different conductive structures 130 can be selected according to actual needs. For example, the conductive structure 130 may include only the redistribution layer 131, or it may include only the bumps 132, or it may include both the redistribution layer 131 and the bumps 132.

[0210] In this embodiment, the conductive structure 130 is not limited, as long as it can realize signal transmission between the chip packaging structure 10 and the packaging board.

[0211] In some embodiments, such as Figure 7B As shown, the chip package structure 10 may also include an adapter board 140.

[0212] The adapter board 140 is disposed between the chip structure 110 and the conductive structure 130, and is electrically connected to the chip structure 110 and the conductive structure 130.

[0213] Regarding the molding layer 220, the molding layer 220 is disposed on the conductive structure 130 and covers at least a portion of the side surfaces of the chip structure 110.

[0214] To clarify, the understanding of the side surface of chip structure 110 can be as follows: the surface of chip structure 110 that is in contact with wafer 100 is called the bottom surface of chip structure 110, the surface opposite to the bottom surface of chip structure 110 is called the top surface of chip structure 110, and the surface that connects the top surface and the bottom surface of chip structure 110 is called the side surface of chip structure 110.

[0215] For example, the molding compound 220 is stacked on top of the conductive structure 130. The molding compound 220 and the chip structure 110 are disposed in the same layer. The molding compound 220 covers at least a portion of the sides of the chip structure 110.

[0216] like Figure 6A As shown, the molding compound 220 covers the side of the chip structure 110. That is, the molding compound 220 is disposed around the side of the chip structure 110. At least a portion of the molding compound 220 is in contact with the side of the chip structure 110. In other words, at least a portion of the molding compound 220 is in direct contact with the chip structure 110.

[0217] For example, the molding compound 220 may cover one or more sides of the chip structure 110, and the molding compound 220 may also cover at least a portion of the sides of the chip structure 110. This embodiment does not impose limitations on this; it can be reasonably configured according to actual circumstances.

[0218] like Figure 6B As shown, when the chip structure 110 includes multiple chips, the molding layer 220 can also fill the gaps between the multiple chips.

[0219] For example, the thickness of the chip structure 110 is greater than or equal to 100 μm, and the material of the molding compound 220 covering the side of the chip structure 110 includes epoxy resin. For example, the material of the molding compound 220 may include epoxy molding compound, chip underfill adhesive, chip adhesive, and thermally conductive medium material, etc.

[0220] The function of the molding layer 220 is to strengthen the mechanical strength of the chip package structure 10, protect the chip structure 110, and improve the reliability of the chip package structure 10.

[0221] Alternatively, for example, the thickness of the chip structure 110 is less than 100 μm, and the molding compound 220 wrapped around the side of the chip structure 110 includes a dry film layer or a chip adhesive film layer.

[0222] Regarding support layer 210, please refer to [reference needed]. Figure 6A The support layer 210 is disposed on the conductive structure 130 and covers at least part of the side surface of the chip structure 110.

[0223] For example, the support layer 210 is stacked with the conductive structure 130. The support layer 210, the molding layer 220, and the chip structure 110 are disposed in the same layer. The support layer 210 covers at least a portion of the side surfaces of the chip structure 110. The support layer 210 may or may not be attached to the chip structure 110.

[0224] In some embodiments, the side of the chip structure 110 may be covered by a support layer 210 and a molding compound 220. In this case, the support layer 210 is located on the side of the molding compound 220 away from the chip structure 110.

[0225] The coefficient of thermal expansion of the support layer 210 material is the same as or similar to that of the chip structure 110 material.

[0226] For example, the material of the support layer 210 may include silicon or silicon dioxide, and the support layer 210 may be formed of glass or a wafer.

[0227] When silicon is used as the material of the support layer 210, it can be formed by photoforming and etching processes on the wafer. This can reduce the cost of the chip packaging structure 10. In addition, the material of the support layer 210 is the same as the material of the chip structure 110, which can reduce the difference in thermal expansion coefficient caused by different materials and alleviate the stress caused by thermal expansion and contraction.

[0228] like Figure 6A As shown, the support layer 210 can be located on the side of the molding layer 220 away from the chip structure 110.

[0229] In other words, the molding layer 220 can be located between the chip structures 110 of the support layer 210.

[0230] Or, such as Figure 8A As shown, one side of the chip structure 110 can be covered only by the support layer 210. Or, as... Figure 8AAs shown, the opposite side of the chip structure 110 may only be covered by the molding compound 220. It should be noted that a support layer 210 may or may not be present in the gaps between the chips in the chip structure 110. The dimensions of the support layer 210 and the molding compound 220 covering the different sides of the chip structure 110 may be the same or different.

[0231] Regarding the positions of the support layer 210 and the molding layer 220, in some embodiments, the molding layer 220 is configured to encapsulate the chip structure 110, and the support layer 210 is configured to encapsulate the chip structure 110.

[0232] For example, such as Figure 8B As shown, the molding compound 220 can cover a portion of the side surface of the chip structure 110, and the support layer 210 can cover another portion of the side surface of the chip structure 110. In step S3 of the above chip packaging method, as... Figure 5E The schematic chip structure 110-1, after forming the molding compound 220, is cut along the junction of the molding compound 220 and the support layer 210 to form a structure as shown. Figure 8B The encapsulation layer 220 and the support layer 210 are shown in the surrounding manner.

[0233] For example, the molding compound 220 can wrap around two adjacent sides of the chip structure 110, and the support layer 210 can wrap around two other adjacent sides of the chip structure 110. Alternatively, the molding compound 220 can wrap around two opposite sides of the chip structure 110, and the support layer 210 can wrap around two other opposite sides of the chip structure 110. Alternatively, the molding compound 220 can wrap around one side of the chip structure 110, and the support layer 210 can wrap around three other sides of the chip structure 110. Alternatively, the molding compound 220 can wrap around three sides of the chip structure 110, and the support layer 210 can wrap around another side of the chip structure 110.

[0234] At this point, the molding layer 220 and the support layer 210 are arranged around the chip structure 110.

[0235] Or, for example, such as Figure 8C As shown, the molding compound 220 can cover part of the side surface of the chip structure 110, and the support layer 210 is arranged around the chip structure 110. In step S3 of the above chip packaging method, as... Figure 5E The schematic chip structure 110-1, after forming the molding layer 220, is cut along the support layer 210 to form a structure as shown. Figure 8C The encapsulation layer 220 and the support layer 210 are shown in the surrounding manner.

[0236] At this point, part of the support layer 210 is located on the side of the molding compound 220 away from the chip structure 110, and part of the support layer 210 is disposed around the chip structure 110. That is to say, part of the support layer 210 is in contact with the molding compound 220, and part of the support layer 210 is in direct contact with the chip structure 110.

[0237] Or, for example, such as Figure 8D As shown, the molding compound 220 can be arranged around the periphery of the chip structure 110, and the support layer 210 is arranged to partially surround the molding compound 220. In step S3 of the above chip packaging method, as... Figure 5E The schematic chip structure 110-3, after forming the molding compound 220, is cut along the support layer 210 or the junction of the support layer 210 and the molding compound 220 to form a structure as shown in the diagram. Figure 8D The encapsulation layer 220 and the support layer 210 are shown in the surrounding manner.

[0238] At this time, such as Figure 8E As shown, the support layer 210 may surround a portion of the periphery of the molding compound 220. Alternatively, as... Figure 8F As shown, the support layer 210 can be arranged around the periphery of the molding layer 220.

[0239] In other embodiments, such as Figure 8E As shown, both the molding compound 220 and the support layer 210 are disposed around the periphery of the chip structure 110, with part of the molding compound 220 surrounding the periphery of the support layer 210 and part of the support layer 210 surrounding the periphery of the molding compound 220.

[0240] In other words, part of the molding compound 220 is disposed on the side of the support layer 210 away from the chip structure 110, and part of the support layer 210 is disposed on the side of the molding compound 220 away from the chip structure 110.

[0241] For example, the surface of the support layer 210 away from the conductive structure 130 is flush with the surface of the chip structure 110 away from the conductive structure 130.

[0242] In this way, the support layer 210 is located on the side of the chip structure 110, which can reduce the risk of warping of the chip structure 110 in the chip packaging structure 10, and at the same time alleviate the stress concentration problem. In addition, for the larger chip structure 110, the support layer 210 wraps around the side of the chip structure 110, and the hardness of the support layer 210 is greater than that of the molding layer 220, which can provide better support for the chip packaging structure 10.

[0243] In some embodiments, such as Figure 9A As shown, the chip packaging structure 10 also includes a connection layer 320 and a carrier board 310.

[0244] like Figure 9AAs shown, the interconnect layer 320 is located on the side of the chip structure 110 away from the conductive structure 130, and the carrier board 310 is located on the side of the interconnect layer 320 away from the chip structure 110.

[0245] In this embodiment, the side of the connection layer 320 away from the chip structure 110 may have a carrier board 310, or it may not have a carrier board 310. This embodiment does not limit this.

[0246] For example, the bonding layer 320 may include a dry film layer or a chip bonding film layer. The material of the bonding layer 320 may be the same as or different from the material of the molding compound layer 220.

[0247] The connecting layer 320 and the molding layer 220 can be integrally molded. That is, the connecting layer 320 and the molding layer 220 can be formed in the same process step.

[0248] This reduces the number of process steps and increases preparation efficiency.

[0249] In some embodiments, such as Figure 9B As shown, the chip packaging structure 10 also includes a packaging board 11.

[0250] All of the above structures are placed on the packaging plate 11.

[0251] The chip packaging structure provided in this application includes a chip structure 110 and a conductive structure 130 stacked and electrically connected to each other, a molding compound 220 disposed on the conductive structure 130 and covering at least a portion of the sides of the chip structure 110, and a support layer 210. The support layer 210 is located on the side of the molding compound 220 away from the chip structure 110. The support layer 210 and the molding compound 220 covering at least a portion of the sides of the chip structure 110 can enhance the mechanical strength of the chip packaging structure 10, protect the chip structure 110, and improve the reliability of the chip packaging structure 10. Furthermore, the support layer 210 is located on the side of the chip structure 110. Since the material of the support layer 210 has the same or similar coefficient of thermal expansion as the material of the chip structure 110, the expansion and contraction of the support layer 210 and the chip structure are the same or similar during high-temperature expansion and low-temperature cooling. This makes the interaction force between the support layer 210 and the chip structure 110 negligible. The support layer 210 can provide mechanical protection for the chip structure 110, alleviate stress concentration problems caused by thermal expansion and contraction, reduce the risk of warping of the chip structure 110 in the chip packaging structure 10, and reduce the difference in the coefficient of thermal expansion caused by different materials. Since the presence of the support layer 210 replaces part of the material of the molding compound 220, the use of molding compound 220 material is reduced, and the packaging cost of the chip packaging structure 10 can also be reduced. For larger chip structures 110, the material of the support layer 210 has a certain degree of rigidity and can also play a supporting role, preventing the molding compound 220 from collapsing.

[0252] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip packaging structure, characterized in that, include: A chip structure and a conductive structure are stacked together, and the chip structure and the conductive structure are electrically connected. A molding layer is disposed on the conductive structure; The molding compound is disposed around the chip structure, and at least a portion of the molding compound is attached to the side of the chip structure; A support layer is disposed on the conductive structure and surrounds at least a portion of the side surface of the chip structure; the molding layer and the support layer together surround the chip structure. The material of the support layer is different from the material of the encapsulation layer.

2. The chip packaging structure according to claim 1, characterized in that, The molding layer is disposed around the chip structure, and the support layer is disposed around the molding layer.

3. The chip packaging structure according to claim 1 or 2, characterized in that, The material of the support layer includes silicon or silicon dioxide.

4. The chip packaging structure according to any one of claims 1-3, characterized in that, The thickness of the chip structure is greater than or equal to 100 μm, and the material of the molding layer includes epoxy molding compound.

5. The chip packaging structure according to any one of claims 1-3, characterized in that, The thickness of the chip structure is less than 100 μm, and the molding layer includes a dry film layer or a chip bonding film layer.

6. The chip packaging structure according to any one of claims 1-5, characterized in that, The chip packaging structure further includes a connection layer and a carrier board; the connection layer is located on the side of the chip structure away from the conductive structure, and the carrier board is located on the side of the connection layer away from the chip structure.

7. The chip packaging structure according to claim 6, characterized in that, The connecting layer and the encapsulation layer are integrally formed.

8. The chip packaging structure according to any one of claims 1-7, characterized in that, The surface of the support layer away from the conductive structure is flush with the surface of the chip structure away from the conductive structure.

9. The chip packaging structure according to any one of claims 1-8, characterized in that, The conductive structure includes a redistribution layer and a bump; the bump is located on the side of the redistribution layer away from the chip structure, and the redistribution layer and the bump are electrically connected.

10. The chip packaging structure according to any one of claims 1-9, characterized in that, The chip packaging structure further includes a wafer structure; the wafer structure is disposed between the chip structure and the conductive structure; the wafer structure has a plurality of first contacts and a plurality of second contacts, and the chip structure has a plurality of third contacts and a plurality of fourth contacts; the first contacts of the wafer structure are electrically connected to the third contacts of the chip structure.

11. The chip packaging structure according to any one of claims 1-9, characterized in that, The chip packaging structure further includes an adapter board; the adapter board is disposed between the chip structure and the conductive structure, and is electrically connected to the chip structure and the conductive structure.

12. A packaging method for a chip packaging structure, characterized in that, include: Form a support layer; The support layer has a through groove; The chip structure is placed within the through groove; the support layer is disposed on at least a portion of the side surface of the chip structure; A molding compound is formed, which fills the through-groove and at least covers the side of the chip structure. A conductive structure is formed, and the conductive structure is electrically connected to the chip structure; The support layer or the molding layer is cut so that the cut chip structure, the conductive structure, the molding layer and the support layer form a chip package structure.

13. The packaging method for the chip packaging structure according to claim 12, characterized in that, Before forming the support layer, the method further includes: A wafer is provided having a plurality of first contacts and second contacts; the first contacts are distributed on a first surface of the wafer, the second contacts are distributed within the wafer, and the first contacts and the second contacts are electrically connected. The formation of the support layer includes: A support layer is formed on the first surface of the wafer; the through groove exposes the first contact.

14. The packaging method for the chip packaging structure according to claim 13, characterized in that, The step of placing the chip structure in the through groove further includes: connecting the chip structure to the first contact point of the wafer.

15. The packaging method for the chip packaging structure according to claim 13 or 14, characterized in that, The formation of the conductive structure includes: forming a conductive structure on the side of the wafer away from the chip structure, wherein the conductive structure is electrically connected to the second contact.

16. The packaging method for the chip packaging structure according to any one of claims 13-15, characterized in that, The formation of a support layer on the first surface of the wafer includes: A support film is formed on the first surface of the wafer, the support film covering the plurality of first contacts of the wafer; A through groove is formed on the support membrane to expose at least a portion of the first contact point, thus forming a support layer.

17. The packaging method for the chip packaging structure according to claim 16, characterized in that, After forming a support film on the first surface of the wafer and before forming a through groove on the support film, the method further includes: thinning the support film.

18. The packaging method for the chip packaging structure according to any one of claims 13-17, characterized in that, The wafer and the support layer are connected by a fusion bonding process.

19. The packaging method for the chip packaging structure according to any one of claims 13-18, characterized in that, The wafer and the chip structure are connected using a hybrid bonding process.

20. The packaging method for the chip packaging structure according to any one of claims 15-19, characterized in that, The formation of a conductive structure on the side of the wafer away from the chip structure includes: A carrier board is placed on the side of the chip structure away from the wafer; the carrier board and the chip structure are connected by a bonding layer; Thin the wafer to expose the second contact; A conductive structure is formed on the second contact; After forming a conductive structure on the second contact and before cutting the support layer or the encapsulation layer, the method further includes removing the carrier plate.

21. The packaging method for the chip packaging structure according to claim 20, characterized in that, The carrier board and the chip structure are connected by a lamination bonding process.

22. The packaging method for the chip packaging structure according to any one of claims 13-21, characterized in that, The formation of the molding compound layer further includes: the molding compound layer is also formed on the surface of the chip structure away from the wafer.

23. An electronic device, characterized in that, Includes the chip packaging structure and printed circuit board as described in any one of claims 1-11; the chip packaging structure and the printed circuit board are electrically connected.

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